TPS22918TDBVTQ1 [TI]
具有可调节上升时间和可调节输出放电功能的单通道、5.5V、2A、52mΩ 汽车负载开关 | DBV | 6 | -40 to 105;型号: | TPS22918TDBVTQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有可调节上升时间和可调节输出放电功能的单通道、5.5V、2A、52mΩ 汽车负载开关 | DBV | 6 | -40 to 105 开关 驱动 光电二极管 接口集成电路 |
文件: | 总30页 (文件大小:1951K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS22918-Q1
ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
TPS22918-Q1 5.5V、2A、导通电阻为 52mΩ 的负载开关
1 特性
2 应用
1
•
•
•
符合 AEC-Q100 标准
•
•
•
•
汽车电子产品
集成式单通道负载开关
信息娱乐系统
符合汽车类 应用的 16 通道 AFE:
仪表组
ADAS(高级驾驶辅助系统)
–
器件温度等级 2:–40°C 至 +105°C 的环境工作
温度范围
3 说明
•
提供功能安全
提供文档以帮助创建功能安全系统设计
输入电压范围:1V 至 5.5V
低导通电阻 (RON
TPS22918-Q1 是一款单通道负载开关,可对上升时间
和快速输出放电进行配置。此器件包括一个 N 沟道金
属氧化物半导体场效应晶体管 (MOSFET),可在 1V 至
5.5V 的输入电压范围内运行并可支持
–
•
•
)
–
–
RON = 52mΩ(VIN = 5V 时的典型值)
RON = 53mΩ(VIN = 3.3V 时的典型值)
2A 的最大持续电流。此开关由一个开关输入控制,能
够直接连接低电压控制信号。
•
•
2A 最大持续开关电流
低静态电流
该器件的可配置上升时间可降低大容量负载电容所产生
的浪涌电流,从而降低或消除电源压降。TPS22918-
Q1 具有 一个可配置的快速输出放电 (QOD) 引脚,用
于控制器件的下降时间,以便针对掉电或排序进行灵活
设计。
–
8.3µA(VIN = 3.3V 时的典型值)
•
•
•
•
低控制输入阈值支持使用 1V 或更高的 GPIO
可配置快速输出放电 (QOD)
通过 CT 引脚可配置上升时间
小型 SOT23-6 封装 (DBV)
TPS22918-Q1 采用小型、带引线的 SOT-23 封装
(DBV),方便对焊接点进行外观检查。该器件在自然通
风环境下的额定运行温度范围为 –40°C 至 +105°C。
–
2.9mm × 2.8mm,间距 0.95mm,
高 1.45mm(带引线)
•
ESD 性能测试符合 AEC Q100 标准
器件信息(1)
–
±2kV 人体模型 (HBM) 和 ±750V 带电器件模型
(CDM)
器件型号
封装
SOT-23 (6)
封装尺寸(标称值)
TPS22918-Q1
2.90mm × 1.60mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
简化原理图
导通电阻与输入电压间的关系
典型值
100
VOUT
VIN
Power
Supply
-40èC
25èC
90
85èC
105èC
QOD
GND
80
CL
RL
CIN
70
60
50
40
30
ON
CT
ON
TPS22918-Q1
GND
OFF
Copyright © 2016, Texas Instruments Incorporated
1
1.5
2
2.5
3 3.5
Input Voltage (V)
4
4.5
5
5.5
D001
IOUT = -200mA
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSCZ8
TPS22918-Q1
ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical DC Characteristics........................................ 7
6.8 Typical AC Characteristics........................................ 9
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
11.3 Thermal Considerations........................................ 20
12 器件和文档支持 ..................................................... 22
12.1 器件支持................................................................ 22
12.2 文档支持................................................................ 22
12.3 接收文档更新通知 ................................................. 22
12.4 社区资源................................................................ 22
12.5 商标....................................................................... 22
12.6 静电放电警告......................................................... 22
12.7 Glossary................................................................ 22
13 机械、封装和可订购信息....................................... 22
7
8
4 修订历史记录
Changes from Revision A (July 2016) to Revision B
Page
•
向特性 部分添加了提供功能安全的链接.................................................................................................................................. 1
Changes from Original (July 2016) to Revision A
Page
•
已将器件状态由“产品预览”更改为“量产数据” .......................................................................................................................... 1
2
Copyright © 2016–2019, Texas Instruments Incorporated
TPS22918-Q1
www.ti.com.cn
ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
VIN
GND
ON
1
2
3
6
5
4
VOUT
QOD
CT
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
Switch input. Place ceramic bypass capacitor(s) between this pin and GND. See the Detailed
Description section for more information
1
VIN
I
2
3
GND
ON
—
I
Device ground
Active high switch control input. Do not leave floating
Switch slew rate control. Can be left floating. See the Feature Description section for more
information
4
CT
O
Quick Output Discharge pin. This functionality can be enabled in one of three ways
•
•
•
Placing an external resistor between VOUT and QOD
Tying QOD directly to VOUT and using the internal resistor value (RPD
Disabling QOD by leaving pin disconnected
5
6
QOD
O
O
)
See the Quick Output Discharge (QOD) section for more information
VOUT
Switch output
Copyright © 2016–2019, Texas Instruments Incorporated
3
TPS22918-Q1
ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
–0.3
–0.3
–0.3
MAX
6
UNIT
V
VIN
Input voltage
VOUT
VON
IMAX
IMAX
IPLS
TJ
Output voltage
6
V
ON voltage
6
V
(3)
(3)
Maximum continuous switch current, TA = 70°C
Maximum continuous switch current, TA = 85°C
2
A
1.5
2.5
150
150
A
Maximum pulsed switch current, pulse < 300 µs, 2% duty cycle
Maximum junction temperature
A
°C
°C
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Assumes 12-K power-on hours at 100% duty cycle. This information is provided solely for your convenience and does not extend or
modify the warranty provided under TI's standard terms and conditions for TI's semiconductor products.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
VIN
Input voltage
1
0
5.5
5.5
VIN
5.5
0.5
105
V
V
VON
ON voltage
VOUT
VIH, ON
VIL, ON
TA
Output voltage
V
High-level input voltage, ON
Low-level input voltage, ON
Operating free-air temperature
Input Capacitor
VIN = 1 V to 5.5 V
VIN = 1 V to 5.5 V
1
0
V
V
(1)
–40
°C
µF
(2)
CIN
1
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(MAX)], the
maximum power dissipation of the device in the application [PD(MAX)], and the junction-to-ambient thermal resistance of the part-package
in the application (θJA), as given by the following equation: TA(MAX) = TJ(MAX) – (θJA × PD(MAX)).
(2) See the Application and Implementation section.
6.4 Thermal Information
TPS22918-Q1
(1)
THERMAL METRIC
DBV (SOT-23)
6 PINS
183.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
151.6
34.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
37.2
ψJB
33.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2016–2019, Texas Instruments Incorporated
TPS22918-Q1
www.ti.com.cn
ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
6.5 Electrical Characteristics
Unless otherwise noted, the specification in the following table applies over the following operating ambient temperature
–40°C ≤ TA ≤ +105°C (full). Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
VIN = 5.5 V
TA
MIN
TYP
9.2
8.7
8.3
10.2
9.3
8.9
0.5
0.5
0.5
0.5
0.4
0.4
MAX
16
16
15
17
16
15
5
UNIT
VIN = 5 V
VIN = 3.3 V
VIN = 1.8 V
VIN = 1.2 V
VIN = 1 V
VON = 5 V, IOUT
= 0 A
IQ, VIN
Quiescent current
–40°C to +105°C
µA
VIN = 5.5 V
VIN = 5 V
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
4.5
3.5
2.5
2
VIN = 3.3 V
VIN = 1.8 V
VIN = 1.2 V
VIN = 1 V
VON = 0 V, VOUT
= 0 V
ISD, VIN
Shutdown current
µA
µA
2
ON pin input leakage
current
ION
VIN = 5.5 V, IOUT = 0 A
–40°C to +105°C
0.1
25°C
–40°C to +105°C
25°C
51
52
52
53
53
55
64
71
59
78
59
79
59
79
59
80
61
80
65
88
77
104
85
116
VIN = 5.5 V, IOUT = –200 mA
VIN = 5 V, IOUT = –200 mA
VIN = 4.2 V, IOUT = –200 mA
VIN = 3.3 V, IOUT = –200 mA
VIN = 2.5 V, IOUT = –200 mA
VIN = 1.8 V, IOUT = –200 mA
VIN = 1.2 V, IOUT = –200 mA
–40°C to +105°C
25°C
–40°C to +105°C
25°C
–40°C to +105°C
25°C
RON
On-Resistance
mΩ
–40°C to +105°C
25°C
–40°C to +105°C
25°C
–40°C to +105°C
25°C
VIN = 1 V, IOUT = –200 mA
VIN = 1 V to 5.5 V
–40°C to +105°C
–40°C to +105°C
25°C
VHYS
ON pin hysteresis
107
24
mV
VIN = 5 V, VON = 0 V
VIN = 3.3 V, VON = 0 V
–40°C to +105°C
25°C
30
35
60
25
45
Output pull down
resistance
RPD
Ω
–40°C to +105°C
25°C
VIN = 1.8 V, VON = 0 V
–40°C to +105°C
Copyright © 2016–2019, Texas Instruments Incorporated
5
TPS22918-Q1
ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
6.6 Switching Characteristics
See timing test circuit in Figure 21 (unless otherwise noted) for references to external components used for the test condition
in the switching characteristics table. Switching characteristics shown below are only valid for the power-up sequence where
VIN is already in steady state condition before the ON pin is asserted high. Test Conditions: VON = 5 V, TA = 25°C.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN = 5 V
tON
tOFF
tR
Turnon time
Turnoff time
VOUT rise time
VOUT fall time
Delay time
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
1950
2
µs
µs
µs
µs
µs
2540
2
tF
tD
690
VIN = 3.3 V
tON
tOFF
tR
Turnon time
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
1430
2
µs
µs
µs
µs
µs
Turnoff time
VOUT rise time
VOUT fall time
Delay time
1680
2
tF
tD
590
VIN = 1.8 V
tON
tOFF
tR
Turnon time
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
965
2
µs
µs
µs
µs
µs
Turnoff time
VOUT rise time
VOUT fall time
Delay time
960
2
tF
tD
480
VIN = 1 V
tON
tOFF
tR
Turnon time
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CIN = 1 µF, COUT = 0.1 µF, CT = 1000 pF
725
3
µs
µs
µs
µs
µs
Turnoff time
VOUT rise time
VOUT fall time
Delay time
560
2
tF
tD
430
6
Copyright © 2016–2019, Texas Instruments Incorporated
TPS22918-Q1
www.ti.com.cn
ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
6.7 Typical DC Characteristics
3
2.5
2
11
10.5
10
-40èC
25èC
85èC
105èC
9.5
9
8.5
8
1.5
1
7.5
-40èC
7
25èC
0.5
0
85èC
105èC
6.5
6
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
D002
D003
VON = 5 V
IOUT = 0 A
VON = 0 V
IOUT = 0 A
Figure 1. Quiescent Current vs Input Voltage
Figure 2. Shutdown Current vs Input Voltage
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
-40èC
25èC
85èC
105èC
VIN= 1 V
VIN = 1.05 V
VIN = 1.2 V
VIN = 1.8 V
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5 V
VIN = 5.5 V
-40
-20
0
20
40
60
80
100
1
1.5
2
2.5
3 3.5
Input Voltage (V)
4
4.5
5
5.5
Temperature (èC)
D004
D001
VON = 5 V
IOUT = –200 mA
VON = 5 V
IOUT = –200 mA
Figure 3. On-Resistance vs Temperature
Figure 4. On-Resistance vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
140
120
100
80
60
40
-40èC
25èC
85èC
105èC
VIN= 1 V
VIN = 1.2 V
VIN = 1.5 V
VIN = 1.8 V
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5 V
VIN = 5.5 V
20
0
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
0.2
0.4
0.6
0.8
1
1.2
Output Current (A)
1.4
1.6
1.8
2
D008
D005
VON = 5 V
TA = 25°C
IOUT = 0 A
Figure 6. Hysteresis Voltage vs Input Voltage
Figure 5. On-Resistance vs Output Current
Copyright © 2016–2019, Texas Instruments Incorporated
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TPS22918-Q1
ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
Typical DC Characteristics (continued)
275
250
225
200
175
150
125
100
75
-40èC
25èC
85èC
105èC
50
25
0
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
D009
VIN = VOUT
VON = 0 V
Figure 7. Output Pull-Down Resistance vs Input Voltage
8
Copyright © 2016–2019, Texas Instruments Incorporated
TPS22918-Q1
www.ti.com.cn
ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
6.8 Typical AC Characteristics
3000
2500
2000
1500
1000
500
800
700
600
500
400
300
-40èC
25èC
85èC
105èC
-40èC
25èC
85èC
105èC
1
1.5
2
2.5
3 3.5
Input Voltage (V)
4
4.5
5
5.5
1
1.5
2
2.5
3 3.5
Input Voltage (V)
4
4.5
5
5.5
D010
D011
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
CT = 1000 pF
Figure 8. Rise Time vs Input Voltage
Figure 9. Delay Time vs Input Voltage
5
4
3
2
1
0
5
4
3
2
1
-40èC
25èC
85èC
105èC
-40èC
25èC
85èC
105èC
0
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
D013
D012
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
QOD = Open
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
Figure 10. Fall Time vs Input Voltage
Figure 11. Turnoff Time vs Input Voltage
2150
1850
1550
1250
950
-40èC
25èC
85èC
105èC
650
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
D014
VIN = 5 V
RL = 10 Ω
CIN = 1 µF
CL = 0.1 µF
CIN = 1 µF
RL = 10 Ω
CL = 0.1 µF
CT =1000 pF
CT = 1000 pF
Figure 13. Rise Time (tR) at VIN = 5 V
Figure 12. Turnon Time vs Input Voltage
Copyright © 2016–2019, Texas Instruments Incorporated
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Typical AC Characteristics (continued)
VIN = 5 V
CIN = 1 µF
CL = 0.1 µF
CL = 0.1 µF
CL = 0.1 µF
VIN = 3.3 V
CIN = 1 µF
CL = 0.1 µF
RL = 10 Ω
QOD = Open
RL = 10 Ω
CT = 1000 pF
Figure 14. Fall Time (tF) at VIN = 5 V
Figure 15. Rise Time (tR) at VIN = 3.3 V
VIN = 3.3 V
RL = 10 Ω
CIN = 1 µF
VIN = 1.8 V
RL = 10 Ω
CIN = 1 µF
CL = 0.1 µF
QOD = Open
CT = 1000 pF
Figure 16. Fall Time (tF) at VIN = 3.3 V
Figure 17. Rise Time (tR) at VIN = 1.8 V
VIN = 1.8 V
RL = 10 Ω
CIN = 1 µF
VIN = 1.0 V
RL = 10 Ω
CIN = 1 µF
CL = 0.1 µF
QOD = Open
CT = 1000 pF
Figure 18. Fall Time (tF) at VIN = 1.8 V
Figure 19. Rise Time (tR) at VIN = 1 V
10
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TPS22918-Q1
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ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
Typical AC Characteristics (continued)
VIN = 1.0 V
CIN = 1 µF
CL = 0.1 µF
RL = 10 Ω
QOD = Open
Figure 20. Fall Time (tF) at VIN = 1 V
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11
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7 Parameter Measurement Information
(1) Rise and fall times of the control signal is 100 ns.
(2) Turnoff times and fall times are dependent on the time constant at the load. For TPS22918-Q1, the internal pull-down
resistance RPD is enabled when the switch is disabled. The time constant is (RQOD || RL) × CL where RQOD equals
RPD + REXT
.
Figure 21. Test Circuit
VON
50%
50%
tF
tOFF
tR
tON
90%
90%
VOUT
VOUT
50%
10%
50%
10%
10%
tD
Figure 22. Timing Waveforms
12
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ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
8 Detailed Description
8.1 Overview
The TPS22918-Q1 is a 5.5-V, 2-A load switch in a 6-pin SOT-23 package. To reduce voltage drop for low
voltage and high current rails, the device implements a low resistance N-channel MOSFET which reduces the
drop out voltage through the device.
The device has a configurable slew rate which helps reduce or eliminate power supply droop because of large
inrush currents. Furthermore, the device features a QOD pin, which allows to configure the discharge rate of
VOUT once the switch is disabled. During shutdown, the device has very low leakage currents, thereby reducing
unnecessary leakages for downstream modules during standby. Integrated control logic, driver, charge pump,
and output discharge FET eliminates the need for any external components, which reduces solution size and bill
of materials (BOM) count.
8.2 Functional Block Diagram
VIN
Charge Pump
Control
Logic
ON
CT
VOUT
QOD
GND
8.3 Feature Description
8.3.1 On and Off Control
The ON pin controls the state of the switch. ON is active high and has a low threshold, making it capable of
interfacing with low-voltage signals. The ON pin is compatible with standard GPIO logic threshold. It can be used
with any microcontroller with 1 V or higher GPIO voltage. This pin cannot be left floating and must be driven
either high or low for proper functionality.
8.3.2 Quick Output Discharge (QOD)
The TPS22918-Q1 includes a QOD feature. The QOD pin can be configured in one of three valid ways:
•
QOD pin shorted to VOUT pin. Using this method, the discharge rate after the switch becomes disabled is
controlled with the value of the internal resistance RPD. The value of this resistance is listed in the Electrical
Characteristics table.
•
QOD pin connected to VOUT pin using an external resistor REXT. After the switch becomes disabled, the
discharge rate is controlled by the value of the total resistance of the QOD. To adjust the total QOD
resistance, Equation 1 can be used.
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Feature Description (continued)
RQOD = RPD + REXT
Where:
•
•
•
RQOD is the total output discharge resistance
RPD is the internal pulldown resistance
REXT is the external resistance placed between the VOUT and QOD pin.
(1)
•
QOD pin is unused and left floating. Using this method, there is no quick output discharge functionality, and
the output remains floating after the switch is disabled.
The fall times of the device depend on many factors including the total resistance of the QOD, VIN, and the
output capacitance. When QOD is shorted to VOUT, the fall time changes over VIN as the internal RPD varies
over VIN. To calculate the approximate fall time of VOUT for a given RQOD, use Equation 2 and Table 1.
VCAP = VIN × e-t/τ
Where:
•
•
•
VCAP is the voltage across the capacitor (V)
t is the time since power supply removal (s)
τ is the time constant equal to RQOD × CL
(2)
The fall times' dependency on VIN becomes minimal as the QOD value increases with additional external
resistance. See Table 1 for QOD fall times.
Table 1. QOD Fall Times
FALL TIME (μs) 90% - 10%, CIN = 1 μF, IOUT = 0 A , VON = 0 V(1)
VIN (V)
TA = 25°C
CL = 10 μF
190
TA = 85°C
CL = 10 μF
210
CL = 1 μF
42
CL = 100 μF
1880
CL = 1 μF
40
CL = 100 μF
2150
5.5
5
43
200
1905
45
220
2200
3.3
2.5
1.8
1.2
1
47
230
2150
50
260
2515
58
300
2790
60
345
3290
75
430
4165
80
490
4950
135
230
955
9910
135
210
1035
10980
19270
1830
19625
1800
(1) Typical values with QOD shorted to VOUT
8.3.2.1 QOD when System Power is Removed
The adjustable QOD can be used to control the power down sequencing of a system even when the system
power supply is removed. When the power is removed, the input capacitor discharges at VIN. Past a certain VIN
level, the strength of the RPD is reduced. If there is still remaining charge on the output capacitor, this results in
longer fall times. For further information regarding this condition, see the Shutdown Sequencing During
Unexpected System Power Loss section.
8.3.2.2 Internal QOD Considerations
Special considerations must be taken when using the internal RPD by shorting the QOD pin to the VOUT pin. The
internal RPD is a pulldown resistance designed to quickly discharge a load after the switch has been disabled.
Care must be used to ensure that excessive current does not flow through RPD during discharge so that the
maximum TJ of 150°C is not exceeded. When using only the internal RPD to discharge a load, the total capacitive
load must not exceed 200 µF. Otherwise, an external resistor, REXT, must be used to ensure the amount of
current flowing through RPD is properly limited and the maximum TJ is not exceeded. To ensure the device is not
damaged, the remaining charge from CL must decay naturally through the internal QOD resistance and must not
be driven.
14
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8.3.3 Adjustable Rise Time (CT)
A capacitor to GND on the CT pin sets the slew rate for each channel. The capacitor to GND on the CT pin must
be rated for 25 V and above. An approximate formula for the relationship between CT and slew rate is shown in
Equation 3.
SR = 0.55 × CT + 30
where
•
•
•
SR is the slew rate (in µs/V)
CT is the capacitance value on the CT pin (in pF)
The units for the constant 30 are µs/V. The units for the constant 0.55 are µs/(V × pF)
(3)
Equation 3 accounts for 10% to 90% measurement on VOUT and does not apply for CT less than 100 pF. Use
Table 2 to determine rise times for when CT is greater or equal to 100 pF.
Rise time can be calculated by multiplying the input voltage by the slew rate. Table 2 contains rise time values
measured on a typical device.
Table 2. Rise Time Table
RISE TIME (µs) 10% - 90%, CL = 0.1 µF, CIN = 1 µF, RL = 10 Ω
Typical values at 25°C with a 25-V X7R 10% ceramic capacitor on CT
CTx (pF)
VIN = 5 V VIN = 3.3 V VIN = 2.5 V VIN = 1.8 V VIN = 1.5 V VIN = 1.2V VIN = 1.0 V
0
135
650
95
455
75
350
60
50
45
40
220
260
220
185
160
470
1260
2540
5435
12050
26550
850
655
480
415
340
300
1000
2200
4700
10000
1680
3580
7980
17505
1300
2760
6135
13460
960
810
660
560
2020
4485
9790
1715
3790
8320
1390
3120
6815
1220
2735
5950
As the voltage across the capacitor approaches the capacitor rated voltage, the effective capacitance reduces.
Depending on the dielectric material used, the voltage coefficient changes. See Table 3 for the recommended
minimum voltage rating for the CT capacitor.
Table 3. Recommended CT Capacitor Voltage Rating
RECOMMENDED CT CAPACITOR VOLTAGE
VIN (V)
RATING (V)(1)
1 V to 1.2 V
1.2 V to 4 V
4 V to 5.5 V
10
16
20
(1) If using VIN = 1.2 V or 4 V, it is recommended to use the higher voltage rating.
8.4 Device Functional Modes
Table 4 describes the connection of the VOUT pin depending on the state of the ON pin.
Table 4. VOUT Connection
ON
L
QOD Configuration
QOD pin connected to VOUT with REXT
QOD pin tied to VOUT directly
QOD pin left open
TPS22918-Q1
GND (via REXT + RPD
)
L
GND (via RPD
Open
)
L
H
Any valid QOD configuration
VIN
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This section highlights some of the design considerations when implementing this device in various applications.
A PSPICE model for this device is also available in the product page of this device on www.ti.com (See the 器件
支持 section for more information).
9.2 Typical Application
This typical application demonstrates how the TPS22918-Q1 can be used to power downstream modules.
VOUT
QOD
VIN
Power
Supply
GND
CL
RL
CIN
ON
CT
ON
TPS22918-Q1
GND
OFF
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the input parameters listed in Table 5.
Table 5. Design Parameter
DESIGN PARAMETER
EXAMPLE VALUE
VIN
5 V
2 A
Load current
CL
22 uF
4 ms
tF
Maximum acceptable inrush current
400 mA
16
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9.2.2 Detailed Design Procedure
9.2.2.1 Input Capacitor (CIN)
To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a
discharged load capacitor or short-circuit, a capacitor must be placed between VIN and GND. A 1 µF ceramic
capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further reduce
the voltage drop during high-current application. When switching heavy loads, it is recommended to have an
input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop.
9.2.2.2 Output Capacitor (CL) (Optional)
Becuase of the integrated body diode in the MOSFET, a CIN greater than CL is highly recommended. A CL
greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current
flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN
dip caused by inrush currents during startup.
9.2.2.3 Shutdown Sequencing During Unexpected System Power Loss
Microcontrollers and processors often have a specific shutdown sequence in which power must be removed.
Using the adjustable Quick Output Discharge function of the TPS22918-Q1, adding a load switch to each power
rail can be used to manage the power down sequencing in the event of an unexpected system power loss
(battery removal). To determine the QOD values for each load switch, first confirm the power down order of the
device this is wished to power sequence. Be sure to check if there are voltage or timing margins that must be
maintained during power down. Next, refer to Table 1 in the Quick Output Discharge (QOD) section to determine
appropriate COUT and RQOD values for each power rail's load switch so that the load switches' fall times
correspond to the order in which they need to be powered down. In the above example, make sure this power
rail's fall time to be 4 ms. Using Equation 2, to determine the appropriate RQOD to achieve our desired fall time.
Because fall times are measured from 90% of VOUT to 10% of VOUT, Equation 2 becomes Equation 4.
.5 V = 4.5 V × e-(4 ms) / (R × (22 µF))
(4)
(5)
RQOD = 83.333 Ω
Refer to Figure 7, RPD at VIN = 5 V is approximately 25 Ω. Using Equation 1, the required external QOD
resistance can be calculated as shown in Equation 6.
83.333 Ω = 25 Ω + REXT
REXT = 58.333 Ω
(6)
(7)
Figure 24 through Figure 29 are scope shots demonstrating an example of the QOD functionality when power is
removed from the device (both ON and VIN are disconnected simultaneously). The input voltage is decaying in
all scope shots below.
•
•
•
•
Initial VIN = 3.3 V
QOD = Open, 500 Ω, or shorted to VOUT
CL = 1 μF, 10 μF
VOUT is left floating
NOTE: VIN may appear constant in some figures. This is because the time scale of the scope shot is too small to
show the decay of CIN.
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VIN = 3.3 V
CIN = 1 µF
CL = 1 µF
VIN = 3.3 V
CIN = 1 µF
CL = 1 µF
QOD = Open
QOD = 500 Ω
Figure 24. Fall Time (tF) at VIN = 3.3 V
Figure 25. Fall Time (tF) at VIN = 3.3 V
VIN = 3.3 V
CIN = 1 µF
CL = 1 µF
VIN = 3.3 V
CIN = 1 µF
CL = 10 µF
QOD = VOUT
QOD = Open
Figure 26. Fall Time (tF) at VIN = 3.3 V
Figure 27. Fall Time (tF) at VIN = 3.3 V
VIN = 3.3 V
CIN = 1 µF
CL = 10 µF
VIN = 3.3 V
CIN = 1 µF
CL = 10 µF
QOD = 500 Ω
QOD = VOUT
Figure 28. Fall Time (tF) at VIN = 3.3 V
Figure 29. Fall Time (tF) at VIN = 3.3 V
9.2.2.4 VIN to VOUT Voltage Drop
The VIN to VOUT voltage drop in the device is determined by the RON of the device and the load current. The
RON of the device depends upon the VIN conditions of the device. Refer to the RON specification of the device in
the Electrical Characteristics table. When the RON of the device is determined based upon the VIN conditions,
use Equation 8 to calculate the VIN to VOUT voltage drop.
18
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∆V is the ILOAD × RON
where
•
•
•
ΔV is the voltage drop from VIN to VOUT
ILOAD is the load current
RON is the On-resistance of the device for a specific VIN
An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.
(8)
9.2.2.5 Inrush Current
Use Equation 9 to determine how much inrush current is caused by the CL capacitor.
dVOUT
I
= CL ´
INRUSH
dt
where
•
•
•
•
IINRUSH is the amount of inrush caused by CL
CL is the capacitance on VOUT
dt is the output voltage rise time during the ramp up of VOUT when the device is enabled
dVOUT is the change in VOUT during the ramp up of VOUT when the device is enabled
(9)
The appropriate rise time can be calculated using the design requirements and the inrush current equation. As
the rise time (measured from 10% to 90% of VOUT) is calculated, this is accounted in the dVOUT parameter (80%
of VOUT = 4 V) as shown in Equation 10.
400 mA = 22 μF × 4 V/dt
dt = 220 μs
(10)
(11)
To ensure an inrush current of less than 400 mA, choose a CT value that yields a rise time of more than 220 μs.
Refering to the Table 2 at VIN = 5 V, CT = 220 μF provides a typical rise time of 650 μs. Adding this rise time and
voltage into Equation 9, yields Equation 12.
IInrush = 22 μF × 4 V / 650 μs
(12)
(13)
IInrush = 135 mA
This inrush current can be seen in the Application Curves section. An appropriate CL value must be placed on
VOUT such that the IMAX and IPLS specifications of the device are not violated.
9.2.3 Application Curves
VIN = 5 V
CL = 22 µF
CT = 0 µF
VIN = 5 V
CL = 22 µF
CT = 220 µF
Figure 30. TPS22918-Q1 Inrush Current
Figure 31. TPS22918-Q1 Inrush Current
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10 Power Supply Recommendations
The TPS22918-Q1 is designed to operate from a VIN range of 1 V to 5.5 V. This supply must be well regulated
and placed as close to the device terminal as possible with the recommended 1-µF bypass capacitor. If the
supply is located more than a few inches from the device terminals, additional bulk capacitance may be required
in addition to the ceramic bypass capacitors. If additional bulk capacitance is required, an electrolytic, tantalum,
or ceramic capacitor of 1 µF may be sufficient.
11 Layout
11.1 Layout Guidelines
•
•
VIN and VOUT traces must be as short and wide as possible to accommodate for high current.
The VIN pin must be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended
bypass capacitance is 1 μF ceramic with X5R or X7R dielectric. This capacitor must be placed as close to the
device pins as possible.
•
The VOUT pin must be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is one-tenth of the VIN bypass capacitor of X5R or X7R dielectric rating.
This capacitor must be placed as close to the device pins as possible.
11.2 Layout Example
1
2
3
6
5
4
VIN VOUT
GND QOD
ON
CT
VIA to Power Ground Plane
Figure 32. Recommended Board Layout
11.3 Thermal Considerations
For best performance, all traces must be as short as possible. To be most effective, the input and output
capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal and short-circuit operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic
electrical effects along with minimizing the case to ambient thermal impedance.
20
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ZHCSF76B –JULY 2016–REVISED DECEMBER 2019
Thermal Considerations (接下页)
The maximum IC junction temperature must be restricted to 150°C under normal operating conditions. To
calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use
Equation 14.
TJ(MAX) - TA
PD(MAX)
=
qJA
(14)
Where:
PD(MAX) is the maximum allowable power dissipation
TJ(MAX) is the maximum allowable junction temperature (150°C for the TPS22918-Q1)
TA is the ambient temperature of the device
θJA is the junction to air thermal impedance. See the Thermal Information table. This parameter is highly
dependent upon board layout.
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www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
关于 TPS22918 PSpice 瞬态模型,请参见 SLVMBI6。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档:
•
•
•
《TPS22918 5.5V、2A、导通电阻为 50mΩ 的负载开关评估模块》,SLVUAP0
《负载开关功耗之静态电流与关断电流》,SLVA757
《负载开关导通电阻基础知识》,SLVA771
12.3 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
22
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS22918TDBVRQ1
TPS22918TDBVTQ1
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
6
6
3000 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
13NW
13NW
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS22918TDBVRQ1
TPS22918TDBVTQ1
SOT-23
SOT-23
DBV
DBV
6
6
3000
250
178.0
178.0
9.0
9.0
3.23
3.23
3.17
3.17
1.37
1.37
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS22918TDBVRQ1
TPS22918TDBVTQ1
SOT-23
SOT-23
DBV
DBV
6
6
3000
250
190.0
190.0
190.0
190.0
30.0
30.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
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EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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