TPS22954 [TI]
具有可调节上升时间、电压监控功能和输出放电功能的 5.7V、5A、14mΩ 负载开关;
| 型号： | TPS22954 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调节上升时间、电压监控功能和输出放电功能的 5.7V、5A、14mΩ 负载开关 开关 监控 |
| 文件： | 总47页 (文件大小：2820K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS22954, TPS22953
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
TPS2295x 5.7V、5A、14mΩ 导通电阻负载开关
1 特性
3 说明
1
•
•
•
集成单通道负载开关
TPS22953/54 是具有受控导通功能的小型单通道负载
开关。 该器件包含一个可在 0.7V 至 5.7V 输入电压范
围内运行的 N 通道 MOSFET，并且可支持最大 5A
的持续电流。
输入电压范围：0.7V 至 5.7V
RON 电阻
–
VIN = 5V (VBIAS = 5V) 时，RON = 14mΩ
•
•
•
5A 最大持续开关电流
可调欠压闭锁 (UVLO) 阈值
带有电源正常 (PG) 指示器的
可调电压监控器
该器件具有可调欠压闭锁 (UVLO) 和可调电源正常
(PG) 阈值，可提供电压监控和可靠的电源排序功能。
器件的可调上升时间控制功能可大幅降低各类大容量负
载电容的浪涌电流，从而降低或消除电源压降。 此开
关可由一个导通/关断输入 (EN) 独立控制，该输入可与
低压控制信号直接对接。 器件集成了一个 15Ω 片上负
载电阻，可在开关被禁用时使输出快速放电。 增强型
快速输出放电 (QOD) 功能可在器件断电后的一小段时
间内继续保持激活状态，以便使输出完成放电。
•
•
可调输出转换率控制
增强型快速输出放电功能，在电源移除后仍能保持
激活状态（仅 TPS22954）
–
15Ω（典型值），可使 100µF 电容在 10ms 内
完全放电
•
•
•
•
•
禁用时提供反向电流保护（仅 TPS22953）
可在监控器检测到故障后自动重启（使能时）
热关断
TPS22953/54 采用小型、节省空间的 10 引脚小外形
尺寸无引线 (SON) 封装，此类封装具有集成散热焊
盘，支持较高功耗。 器件在自然通风环境下的额定运
行温度范围为 –40°C 至 105℃。
低静态电流 ≤ 50µA
带有散热焊盘的小外形尺寸无引线 (SON) 10 引脚
封装
器件信息(1)
•
经测试，静电放电 (ESD) 性能符合 JESD 22 规范
器件编号
封装（引脚）
DSQ (10)
封装尺寸（标称值）
2.00mm x 2.00mm
2.00mm x 3.00mm
–
2kV 人体模型 (HBM) 和 750V 充电器件模型
(CDM)
TPS2295x
DQC (10)
2 应用
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
•
•
•
•
固态硬盘
嵌入式/工业 PC
Ultrabook™/笔记本电脑
台式机
服务器
电信系统
4 简化电路原理图
TPS22953/54
Power
Supply
IN
OUT
OUT
SNS
IN
RSNS1
VBIAS
EN
REN1
RSNS2
CIN
CL = 100 µF
RL
Rpullup
PG
REN2
PG
CT
GND
PAD
CT
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCT5
TPS22954, TPS22953
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
www.ti.com.cn
目录
8.12 Typical Switching Characteristics ......................... 15
Detailed Description ............................................ 21
9.1 Overview ................................................................. 21
9.2 Functional Block Diagram ....................................... 21
9.3 Feature Description................................................. 22
9.4 Device Functional Modes ....................................... 27
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
8.1 Absolute Maximum Ratings ...................................... 4
8.2 ESD Ratings ............................................................ 4
8.3 Recommended Operating Conditions....................... 4
8.4 Thermal Information.................................................. 5
8.5 Electrical Characteristics........................................... 5
8.6 Electrical Characteristics, VBIAS = 5 V ...................... 6
8.7 Electrical Characteristics, VBIAS = 3.3 V ................... 7
8.8 Electrical Characteristics, VBIAS = 2.5 V ................... 8
8.9 Switching Characteristics, CT = 1000 pF.................. 9
8.10 Switching Characteristics, CT = 0 pF.................... 10
8.11 Typical DC Characteristics.................................... 12
9
10 Application and Implementation........................ 28
10.1 Application Information.......................................... 28
10.2 Typical Application ............................................... 31
11 Power Supply Recommendations ..................... 33
12 Layout................................................................... 33
12.1 Layout Guidelines ................................................ 33
12.2 Layout Example .................................................... 34
13 器件和文档支持 ..................................................... 35
13.1 相关链接................................................................ 35
13.2 商标....................................................................... 35
13.3 静电放电警告......................................................... 35
13.4 术语表 ................................................................... 35
14 机械封装和可订购信息 .......................................... 35
5 修订历史记录
Changes from Original (March 2015) to Revision A
Page
•
完整版的最初发布版本。 ....................................................................................................................................................... 1
2
Copyright © 2015, Texas Instruments Incorporated
TPS22954, TPS22953
www.ti.com.cn
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
6 Device Comparison Table
Device
Quick Output
Discharge
Reverse Current
Blocking
Package (Pin)
Body Size
Pin Pitch
DSQ (10)
DQC (10)
DSQ (10)
DQC (10)
2.00 mm x 2.00 mm
2.00 mm x 3.00 mm
2.00 mm x 2.00 mm
2.00 mm x 3.00 mm
0.4 mm
0.5 mm
0.4 mm
0.5 mm
TPS22954
Yes
No
No
TPS22953
Yes
7 Pin Configuration and Functions
1
2
3
10
9
10
1
IN
IN
OUT
OUT
OUT
IN
IN
9
2
3
OUT
GND
GND
8
8
(Exposed
thermal pad)
(Exposed
thermal pad)
BIAS
EN
SNS
PG
SNS
BIAS
EN
4
5
7
6
7
4
5
PG
GND
CT
CT
6
GND
Top View
Bottom View
Pin Functions
PIN(1)
I/O
DESCRIPTION
NAME
NO.
1, 2
3
IN
I
I
Switch input. Bypass this input with a ceramic capacitor to GND.
Bias pin and power supply to the device.
BIAS
Active high switch enable/disable input. Also acts as the input UVLO pin. Use external resistor divider to
adjust the UVLO level. Do not leave floating.
EN
4
5
6
I
GND
CT
–
Device ground.
VOUT slew rate control. Place ceramic cap from CT to GND to change the VOUT slew rate of the device
and limit the inrush current. CT Capacitor should be rated to 25V or higher.
O
Power good. This pin is open drain which will pull low when the voltage on EN and/or SNS is below
their respective VIL level.
PG
7
O
SNS
OUT
8
9, 10
–
I
Sense pin. Use external resistor divider to adjust the power good level. Do not leave floating.
O
–
Switch output.
Thermal Pad
Exposed thermal pad. Tie to GND.
(1) Pinout applies to all package versions.
Copyright © 2015, Texas Instruments Incorporated
3
TPS22954, TPS22953
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
www.ti.com.cn
8 Specifications
8.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
MAX UNIT
VIN
Input voltage range
Bias voltage range
Output voltage range
6
6
6
V
V
V
VBIAS
VOUT
VEN, VSNS
VPG
,
EN, SNS, and PG voltage range
–0.3
6
V
IMAX
IPLS
TJ,MAX
Tstg
Maximum Continuous Switch Current, TA = 70°C
5
7
A
A
Maximum Pulsed Switch Current, pulse <300µs, 2% duty cycle
Maximum junction temperature
(2)
Internally limited
–65 150
Storage temperature range
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See TSD specification in Electrical Characteristics section and Thermal Considerations section.
8.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
8.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
0.7
2.5
0
MAX UNIT
VIN
Input voltage range
VBIAS
5.7
V
V
V
V
VBIAS
VOUT
Bias voltage range
Output voltage range
EN, SNS, and PG voltage range
5.7
VEN, VSNS
,
0
5.7
VPG
(1)
TA
Operating free-air temperature range
Operating Junction Temperature
–40
–40
105
125
°C
°C
TJ
(1) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max)
)
4
Copyright © 2015, Texas Instruments Incorporated
TPS22954, TPS22953
www.ti.com.cn
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
8.4 Thermal Information
TPS22953/54
UNIT
THERMAL METRIC(1)
DQC-10
65.2
73.9
25.5
2
DSQ-10
63.5
81.6
34.1
1.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
RθJC(top)
RθJB
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
25.4
8.5
34.5
7.9
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
8.5 Electrical Characteristics
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40 °C ≤ TA ≤
105 °C and the recommended VBIAS voltage range of 2.5V to 5.7V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN TYP
MAX UNIT
VOLTAGE THRESHOLDS
VIH, Rising threshold
VEN
VIN = 0.7V to VBIAS
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
650 700
560 600
465 515
410 455
750
640
565
500
mV
mV
mV
mV
VIL, Falling threshold
VIN = 0.7V to VBIAS
VIN = 0.7V to VBIAS
VIN = 0.7V to VBIAS
VIH, Rising threshold
VSNS
VIL, Falling threshold
TIMINGS
tBLANK
Blanking time for EN and SNS
EN or SNS Rising
EN or SNS Falling
-40°C to 105°C
-40°C to 105°C
100
5
µs
µs
tDEGLITCH Deglitch time for EN and SNS
Output discharge time
(TPS22954 Only)
tDIS
CL = 100 µF
SNS Falling
-40°C to 105°C
-40°C to 105°C
10
ms
ms
tRESTART Output Restart Time
2
THERMAL CHARACTERISTICS
TSD
Thermal shutdown
Junction Temperature Rising
Junction Temperature Falling
-
-
130 150
20
170
°C
°C
TSDHYS Thermal shutdown hysteresis
Copyright © 2015, Texas Instruments Incorporated
5
TPS22954, TPS22953
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
www.ti.com.cn
8.6 Electrical Characteristics, VBIAS = 5 V
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40 °C ≤ TA ≤
105 °C and VBIAS = 5V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN TYP
34
MAX UNIT
POWER SUPPLIES AND CURRENTS
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
45
50
7
µA
IQ, BIAS
BIAS quiescent current
IOUT = 0, VIN = 0.7V to VBIAS, VEN= 5V
VOUT = 0V, VIN = 0.7V to VBIAS, VEN = 0V
VIN = 5.0V
5
µA
µA
ISD, BIAS BIAS shutdown current
8
0.02
0.01
0.01
0.01
0.01
4
13
3
VIN = 3.3V
10
3
ISD, IN
Input shutdown current
VEN = 0V, VOUT = 0V
VIN = 1.8V
VIN = 1.2V
VIN = 0.7V
µA
10
2
8
2
8
IEN
EN pin input leakage current
SNS pin input leakage current
VEN = 0V to 5.7V
VSNS ≤ VBIAS
0.1
0.1
µA
µA
ISNS
RESISTANCE CHARACTERISTICS
25°C
14
14
14
14
14
14
15
20
23
24
20
23
24
20
23
24
20
23
24
20
23
24
20
23
24
28
30
VIN = 5.0V
VIN = 3.3V
VIN = 1.8V
VIN = 1.5V
VIN = 1.2V
VIN = 0.7V
-40°C to 85°C
-40°C to 105°C
25°C
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
-40°C to 85°C
-40°C to 105°C
25°C
-40°C to 85°C
-40°C to 105°C
25°C
RON
ON-state resistance
IOUT = –200 mA
-40°C to 85°C
-40°C to 105°C
25°C
-40°C to 85°C
-40°C to 105°C
25°C
-40°C to 85°C
-40°C to 105°C
25°C
Ω
Ω
Output pulldown resistance
(TPS22954 Only)
RPD
VIN = VOUT = VBIAS, VEN = 0 V
-40°C to 105°C
6
Copyright © 2015, Texas Instruments Incorporated
TPS22954, TPS22953
www.ti.com.cn
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
8.7 Electrical Characteristics, VBIAS = 3.3 V
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40 °C ≤ TA ≤
105 °C and VBIAS = 3.3V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN TYP
19
MAX UNIT
POWER SUPPLIES AND CURRENTS
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
35
37
6
µA
IQ, BIAS
BIAS quiescent current
IOUT = 0, VIN = 0.7V to VBIAS, VEN= 5V
VOUT = 0V, VIN = 0.7V to VBIAS, VEN = 0V
VIN = 3.3V
4
µA
µA
ISD, BIAS BIAS shutdown current
7
0.01
0.01
0.01
0.01
3
10
3
VIN = 1.8V
10
2
ISD, IN
Input shutdown current
VEN = 0V, VOUT = 0V
µA
VIN = 1.2V
8
2
VIN = 0.7V
8
IEN
EN pin input leakage current
SNS pin input leakage current
VEN = 0V to 5.7V
VSNS = 0V to VBIAS
0.1
0.1
µA
µA
ISNS
RESISTANCE CHARACTERISTICS
25°C
15
14
14
14
14
13
21
24
25
20
23
24
20
23
24
20
23
24
20
23
24
28
30
VIN = 3.3V
VIN = 1.8V
-40°C to 85°C
-40°C to 105°C
25°C
mΩ
mΩ
mΩ
mΩ
mΩ
-40°C to 85°C
-40°C to 105°C
25°C
RON
ON-state resistance
IOUT = –200 mA
VIN = 1.5V
VIN = 1.2V
VIN = 0.7V
-40°C to 85°C
-40°C to 105°C
25°C
-40°C to 85°C
-40°C to 105°C
25°C
-40°C to 85°C
-40°C to 105°C
25°C
Ω
Ω
Output pulldown resistance
(TPS22954 Only)
RPD
VIN = VOUT = VBIAS, VEN = 0 V
-40°C to 105°C
Copyright © 2015, Texas Instruments Incorporated
7
TPS22954, TPS22953
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
www.ti.com.cn
8.8 Electrical Characteristics, VBIAS = 2.5 V
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature –40 °C ≤ TA ≤
105 °C and VBIAS = 2.5V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN TYP
16
MAX UNIT
POWER SUPPLIES AND CURRENTS
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
25
27
5
µA
IQ, BIAS
BIAS quiescent current
IOUT = 0, VIN = 0.7V to VBIAS, VEN= 5V
VOUT = 0V, VIN = 0.7V to VBIAS, VEN = 0V
VIN = 2.5V
4
µA
µA
ISD, BIAS BIAS shutdown current
6
0.01
0.01
0.01
0.01
3
10
3
VIN = 1.8V
10
2
ISD, IN
Input shutdown current
VEN = 0V, VOUT = 0V
µA
VIN = 1.2V
8
2
VIN = 0.7V
8
IEN
EN pin input leakage current
SNS pin input leakage current
VEN = 0V to 5.7V
VSNS = 0V to VBIAS
0.1
0.1
µA
µA
ISNS
RESISTANCE CHARACTERISTICS
25°C
16
15
15
15
14
12
23
26
27
22
25
26
22
25
26
22
24
25
21
24
25
28
30
VIN = 2.5V
VIN = 1.8V
-40°C to 85°C
-40°C to 105°C
25°C
mΩ
mΩ
mΩ
mΩ
mΩ
-40°C to 85°C
-40°C to 105°C
25°C
RON
ON-state resistance
IOUT = –200 mA
VIN = 1.5V
VIN = 1.2V
VIN = 0.7V
-40°C to 85°C
-40°C to 105°C
25°C
-40°C to 85°C
-40°C to 105°C
25°C
-40°C to 85°C
-40°C to 105°C
25°C
Ω
Ω
Output pulldown resistance
(TPS22954 Only)
RPD
VIN = VOUT = VBIAS, VEN = 0 V
-40°C to 105°C
8
Copyright © 2015, Texas Instruments Incorporated
TPS22954, TPS22953
www.ti.com.cn
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
8.9 Switching Characteristics, CT = 1000 pF
Refer to the timing test circuit in Figure 1 (unless otherwise noted) for references to external components used for the test
condition in the switching characteristics table. Switching characteristics shown below are only valid for the power-up
sequence where VIN and VBIAS are already in steady state condition before the EN terminal is asserted high.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN = 5V, VEN = VBIAS = 5V, TA = 25°C
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
ON delay time
1265
6.0
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
1492
2.2
µs
tF
tD
519
VIN = 2.5V, VEN = VBIAS = 5V, TA = 25°C
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
ON delay time
813
6.1
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
765
2.2
µs
µs
µs
µs
tF
tD
430
VIN = 0.7V, VEN = VBIAS = 5V, TA = 25°C
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
ON delay time
476
6.2
245
2.1
tF
tD
353
VIN = 2.5V, VEN = 5V, VBIAS = 2.5V, TA = 25°C
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
ON delay time
813
4.9
765
2.2
tF
tD
430
VIN = 0.7V, VEN = 5V, VBIAS = 2.5V, TA = 25°C
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
ON delay time
476
6.1
245
2.1
tF
tD
353
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8.10 Switching Characteristics, CT = 0 pF
Refer to the timing test circuit in Figure 1 (unless otherwise noted) for references to external components used for the test
condition in the switching characteristics table. Switching characteristics shown below are only valid for the power-up
sequence where VIN and VBIAS are already in steady state condition before the EN terminal is asserted high.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN = 5V, VEN = VBIAS = 5V, TA = 25°C
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
ON delay time
235
6.0
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
140
2.2
µs
tF
tD
165
VIN = 2.5V, VEN = VBIAS = 5V, TA = 25°C
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
ON delay time
200
6
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
79
µs
µs
µs
µs
tF
2.1
160
tD
VIN = 0.7V, VEN = VBIAS = 5V, TA = 25°C
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
ON delay time
170
6
32
2
tF
tD
154
VIN = 2.5V, VEN = 5V, VBIAS = 2.5V, TA = 25°C
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
ON delay time
200
6
79
tF
2.1
160
tD
VIN = 0.7V, VEN = 5V, VBIAS = 2.5V, TA = 25°C
tON
tOFF
tR
Turn-on time
Turn-off time
VOUT rise time
VOUT fall time
ON delay time
170
6
32
2
tF
tD
154
10
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ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
IN
OUT
SNS
CIN = 1µF
ON
(A)
+
-
EN
CL
RL
10kΩ
OFF
BIAS
GND
PG
CT
GND
GND
+
-
TPS22953/54
A. Rise and fall times of the control signal is 100 ns.
Figure 1. Timing Test Circuit
tDEGLITCH
tDEGLITCH
VEN
50%
50%
50%
50%
tON
tOFF
90%
90%
tD
VOUT
50%
50%
10%
10%
tBLANK
tBLANK
tR
tF
Figure 2. Timing Waveforms
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8.11 Typical DC Characteristics
40
36
35
34
33
32
31
30
29
28
27
26
25
24
105°C
85°C
25°C
35
30
25
20
15
10
-40°C
105°C
85°C
25°C
-40°C
2.5
3
3.5
4
4.5
5
5.5
5.5
100
6
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
VBIAS (V)
D001
D002
VIN = 1.8 V
VEN = 5.7V
VOUT = 0V
VBIAS = 5 V
VEN = 5.7V
VOUT = 0V
Figure 3. IQ,BIAS vs VBIAS
Figure 4. IQ,BIAS vs VIN
2.5
2.25
2
6
5.5
5
105°C
85°C
25°C
105°C
85°C
25°C
-40°C
-40°C
1.75
1.5
1.25
1
4.5
4
0.75
0.5
0.25
0
3.5
-0.25
3
2.5
-0.5
3
3.5
4
4.5
5
6
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
VBIAS (V)
D003
D004
VIN = 1.8 V
VEN = 0V
VOUT = 0V
VBIAS = 5 V
VEN = 0V
VOUT = 0V
Figure 5. ISD,BIAS vs VBIAS
Figure 6. ISD,IN vs VIN
22
20
18
16
14
12
10
19
18
17
16
15
14
13
12
11
10
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
VIN = 3.3V
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
-40
-20
0
20
40
60
80
120
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (qC)
Ambient Temperature (qC)
D005
D006
VBIAS = 2.5 V
Iout = –200 mA
VEN = 5V
VBIAS = 3.3 V
Iout = –200 mA
VEN = 5V
Figure 7. RON vs Temperature, VBIAS = 2.5V
Figure 8. RON vs Temperature, VBIAS = 3.3 V
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Typical DC Characteristics (continued)
24
22
20
18
16
14
12
10
105°C
85°C
25°C
-40°C
105°C
85°C
25°C
22
-40°C
20
18
16
14
12
10
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4
VIN (V)
D008
D009
VBIAS = 2.5 V
Iout = –200 mA
VEN = 5V
VBIAS = 3.3 V
Iout = –200 mA
VEN = 5V
Figure 9. RON vs VIN, VBIAS = 2.5 V
Figure 10. RON vs VIN, VBIAS = 3.3 V
22
20
18
16
14
12
10
16
15.75
15.5
15.25
15
105°C
VBIAS = 2.5V
VBIAS = 3.3V
VBIAS = 5V
85°C
25°C
-40°C
VBIAS = 5.7V
14.75
14.5
14.25
14
13.75
13.5
13.25
0.6
1
1.4 1.8 2.2 2.6
3
3.4 3.8 4.2 4.6
5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VIN (V)
VIN (V)
D010
D011
VBIAS = 5 V
Iout = –200 mA
VEN = 5V
TA = 25°C
Iout = –200 mA
VEN = 5V
Figure 11. RON vs VIN, VBIAS = 5 V
Figure 12. RON vs VIN
17.5
17
15.4
15.2
15
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
VIN = 3.3V
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
16.5
16
14.8
14.6
14.4
14.2
14
15.5
15
13.8
13.6
13.4
13.2
14.5
14
13.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
IOUT (A)
IOUT (A)
D032
D033
VBIAS = 2.5 V
VEN = 5V
VBIAS = 3.3 V
VEN = 5V
Figure 13. RON vs IOUT, VBIAS = 2.5 V
Figure 14. RON vs IOUT, VBIAS = 3.3 V
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Typical DC Characteristics (continued)
14.3
22
20
18
16
14
12
10
8
VIN = 5V
VIN = 3.3V
VIN = 2.5V
VIN = 1.8V
105°C
25°C
-40°C
14.2
14.1
14
VIN = 0.7V
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
6
4
2
0
0.5
1
1.5
2
2.5
IOUT (A)
3
3.5
4
4.5
5
0.6 0.8
1
1.2 1.4 1.6 1.8
VOUT (V)
2
2.2 2.4 2.6
D034
D012
VBIAS = 5 V
VEN = 5V
VBIAS = 2.5 V
VIN = VOUT
VEN = 0V
Figure 15. RON vs IOUT, VBIAS = 5 V
Figure 16. RPD vs VOUT, VBIAS = 2.5 V
18
16
14
12
10
8
18
16
14
12
10
8
105°C
25°C
-40°C
105°C
25°C
-40°C
6
6
4
4
2
2
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VOUT (V)
VOUT (V)
D016
D014
VBIAS = 3.3 V
VIN = VOUT
VEN = 0V
VBIAS = 5 V
VIN = VOUT
VEN = 0V
Figure 17. RPD vs VOUT, VBIAS = 3.3 V
Figure 18. RPD vs VOUT, VBIAS = 5 V
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8.12 Typical Switching Characteristics
800
1600
1400
1200
1000
800
105°C
85°C
25°C
-40°C
105°C
85°C
25°C
750
700
650
600
550
500
450
400
350
300
250
200
-40°C
600
400
200
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
D020
D021
VBIAS = 2.5 V
CT = 1000 pF
VEN = low to high
VBIAS = 5 V
CT = 1000 pF
VEN = low to high
Figure 19. tR vs VIN , VBIAS = 2.5 V
Figure 20. tR vs VIN , VBIAS = 5 V
2.2
2.18
2.16
2.14
2.12
2.1
2.25
2.22
2.19
2.16
2.13
2.1
105°C
85°C
25°C
-40°C
2.08
2.06
2.04
2.02
2.07
2.04
2.01
1.98
105°C
85°C
25°C
-40°C
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
D022
D023
VBIAS = 2.5 V
CT = 1000 pF
VEN = high to low
VBIAS = 5 V
CT = 1000 pF
VEN = high to low
Figure 21. tF vs VIN , VBIAS = 2.5 V
Figure 22. tF vs VIN , VBIAS = 5 V
900
850
800
750
700
650
600
550
500
450
400
1400
1300
1200
1100
1000
900
105°C
105°C
85°C
25°C
-40°C
85°C
25°C
-40°C
800
700
600
500
400
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
D024
D025
VBIAS = 2.5 V
CT = 1000 pF
VEN = low to high
VBIAS = 5 V
CT = 1000 pF
VEN = low to high
Figure 23. tON vs VIN , VBIAS = 2.5 V
Figure 24. tON vs VIN , VBIAS = 5 V
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Typical Switching Characteristics (continued)
7.25
6.4
6.35
6.3
105°C
85°C
25°C
-40°C
105°C
85°C
25°C
7
6.75
6.5
-40°C
6.25
6.2
6.25
6
6.15
6.1
5.75
5.5
5.25
5
6.05
6
4.75
5.95
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
D02351
D027
VBIAS = 2.5 V
CT = 1000 pF
VEN = high to low
VBIAS = 5 V
CT = 1000 pF
VEN = high to low
Figure 25. tOFF vs VIN , VBIAS = 2.5 V
Figure 26. tOFF vs VIN , VBIAS = 5 V
480
460
440
420
400
380
360
340
320
300
280
570
540
510
480
450
420
390
360
330
300
270
105°C
105°C
85°C
25°C
-40°C
85°C
25°C
-40°C
0.6 0.8
1
1.2 1.4 1.6 1.8
VIN (V)
2
2.2 2.4 2.6
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
D028
D029
VBIAS = 2.5 V
CT = 1000 pF
VEN = low to high
VBIAS = 5 V
CT = 1000 pF
VEN = low to high
Figure 27. tD vs VIN , VBIAS = 2.5 V
Figure 28. tD vs VIN , VBIAS= 5 V
810
800
790
780
770
760
750
740
730
720
710
700
690
105°C
85°C
25°C
-40°C
2.5
3
3.5
4
4.5
5
5.5
6
VBIAS (V)
D030
VIN = 2.5 V
CT = 1000 pF
VEN = low to
high
Figure 29. tR vs VBIAS
16
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Typical Switching Characteristics (continued)
VIN = 0.7 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
VIN = 0.7 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
RL = 10 Ω
Figure 30. Turn On Waveform, VBIAS = 2.5 V
Figure 31. Turn Off Waveform, VBIAS = 2.5 V
VIN = 0.7 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
VIN = 0.7 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 32. Turn On Waveform, VBIAS = 5 V
Figure 33. Turn Off Waveform, VBIAS = 5 V
VIN = 2.5 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
VIN = 2.5 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 34. Turn On Waveform, VBIAS = 2.5 V
Figure 35. Turn Off Waveform, VBIAS = 2.5 V
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Typical Switching Characteristics (continued)
VIN = 2.5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
VIN = 2.5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
RL = 10 Ω
Figure 36. Turn On Waveform, VBIAS = 5 V
Figure 37. Turn Off Waveform, VBIAS = 5 V
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 38. Turn On Waveform, VBIAS = 5 V
Figure 39. Turn Off Waveform, VBIAS = 5 V
VIN = 5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
VIN = 5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 40. Turn On Waveform, VBIAS = 5 V
Figure 41. Turn Off Waveform, VBIAS = 5 V
18
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Typical Switching Characteristics (continued)
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = Open
VIN = 5 V
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = Open
CIN = 1 µF
Figure 42. Turn On Waveform, No Load
Figure 43. Turn On Waveform, No Load
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 1 Ω
VIN = 5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 1 Ω
Figure 44. Turn On Waveform, Heavy Load
Figure 45. Turn On Waveform, Heavy Load
VIN = 5 V
VBIAS = 5 V
CL = 100 µF
CT = 1000 pF
VIN = 5 V
VBIAS = 5 V
CL = 100 µF
CT = 1000 pF
CIN = 1 µF
RL = 10 Ω
CIN = 1 µF
RL = 10 Ω
Figure 46. PG Response to EN Falling (tDEGLITCH
)
Figure 47. PG Response to SNS Falling with Auto-Restart
(tDEGLITCH and tRESTART
)
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Typical Switching Characteristics (continued)
VIN = 5 V
VBIAS = 5 V
CL = 100 µF
CT = 1000 pF
VIN = 5 V
VBIAS = 5 CT = 1000
V
pF
CIN = 1 µF
RL = 10 Ω
CIN = 1 µF
CL = 100
µF
RL = None
Figure 48. PG Response to SNS Rising (tBLANK
)
Figure 49. Quick Output Discharge of 100µF Load (tDIS
)
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9 Detailed Description
9.1 Overview
The TPS22953/4 are 5.7-V, 5-A load switches in 10-pin SON packages. To reduce voltage drop for low voltage,
high current rails the device implements a low resistance N-channel MOSFET, which reduces the drop out
voltage through the device at high currents. The integrated adjustable undervoltage lockout (UVLO) and
adjustable power good (PG) threshold provides voltage monitoring as well as robust power sequencing.
The adjustable rise time control of the device greatly reduces inrush current for a wide variety of bulk load
capacitances, thereby reducing or eliminating power supply droop. The switch is independently controlled by an
on/off input (EN), which is capable of interfacing directly with low-voltage control signals. A 15 Ω on-chip load
resistor is integrated into the device for output quick discharge when switch is turned off.
During shutdown, the device has very low leakage currents, thereby reducing unneccessary leakages for
downstream modules during standby. Integrated power monitoring functionality, control logic, driver, power
supply, and output discharge FET eliminates the need for any external components, which reduces solution size
and BOM count.
9.2 Functional Block Diagram
Reverse Current
Blocking*
(TPS22953 Only)
IN
Power
supply
module
BIAS
PG
EN
Control
Logic
Driver
VEN
OUT
CT
Thermal
Shutdown
QOD Resistance*
(TPS22954 Only)
SNS
VSNS
GND
(*) Only active when the switch is disabled.
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9.3 Feature Description
9.3.1 On/Off Control (EN pin)
The EN pin controls the state of the switch. When the voltage on EN has exceeded VIH,EN the switch will be
enabled. When EN goes below VIL,EN the switch is disabled.
The EN pin has a blanking time of tBLANK on the rising edge once the VIH,EN threshold has been exceeded. It also
has a deglitch time of tDEGLITCH when the voltage has gone below VIL,EN
.
The EN pin can also be configured via an external resistor divider to monitor a voltage signal for input UVLO.
Refer to the equation and diagram below on how to configure the EN pin for input UVLO.
REN2
V
= V ´
IN
IH,EN
REN1 + REN2
(1)
Where:
VIH,EN = the rising threshold of the EN pin (see Electrical Characteristics table)
VIN = the input voltage being monitored (this could be VIN, VBIAS, or an external power supply)
REN1, REN2 = resistor divider values
VIN or VBIAS
REN1
EN
REN2
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Feature Description (continued)
9.3.2 Voltage Monitoring (SNS pin)
The SNS pin of the device can be used to monitor the output voltage of the device or another voltage rail. The
pin can be configured with an external resistor divider to set the desired trip point for the voltage being monitored
or be tied to OUT directly. If the voltage on the SNS pin exceeds VIH,SNS, the voltage being monitored on the
SNS pin is considered to be valid high. The voltage on the SNS pin must be greater than VIH,SNS for at least
tBLANK before PG is asserted high. If the voltage on the SNS pin goes below VIL,SNS, then the switch will power
cycle (i.e., the switch will be disabled and re-enabled). For proper functionality of the device, this pin must not be
left floating. If a resistor divider is not being used for voltage sensing, this pin can be tied directly to VOUT
.
The SNS pin has a blanking time of tBLANK on the rising edge once the VIH,SNS threshold has been exceeded. It
has a deglitch time of tDEGLITCH when the voltage has gone below VIL,SNS
.
Refer to the equation and diagram below on how to configure the SNS pin for voltage monitoring.
RSNS2
V
= VOUT
´
IH,SNS
R
SNS1 + RSNS2
(2)
Where:
VIH,SNS = the rising threshold of the SNS pin (see Electrical Characteristics table)
VOUT = voltage on the OUTpin
RSNS1, RSNS2 = resistor divider values
VOUT
RSNS1
SNS
RSNS2
Copyright © 2015, Texas Instruments Incorporated
23
TPS22954, TPS22953
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
www.ti.com.cn
Feature Description (continued)
9.3.3 Power Good (PG Pin)
The PG pin is only asserted high when the voltage on EN has exceeded VIH,EN and the voltage on SNS has
exceeded VIH,SNS. There is a tBLANK time, typically 100µs, between the SNS voltage exceeding VIH,SNS and PG
being asserted high. If the voltage on EN goes below VIL,EN or the voltage on SNS goes below VIL,SNS, PG will be
de-asserted. There is a tDEGLITCH time, typically 5µs, between the EN voltage or SNS voltage going below their
respective VIL levels and PG being pulled low.
PG is an open drain pin and must be pulled up with a pull-up resistor. Be sure to never exceed the maximum
operating voltage on this pin. If PG is not being used in the application, tie it to GND for proper device
functionality.
For proper PG operation, the BIAS voltage should be within the recommended operating range. In systems that
are very sensitive to noise or have long PG traces, it is recommended to add a small capacitance from PG to
GND to for decoupling.
9.3.4 Supervisor Fault Detection and Automatic Restart
The falling edge of the SNS pin below VIL,SNS is considered a fault case and will cause the load switch to be
disabled for tRESTART (typically 2ms). After the tRESTART time, the switch will be automatically re-enabled as long
as EN is still above VIH,EN . In the case the SNS pin is being used to monitor VOUT or a downstream voltage, the
restart will help to protect against excessive over-current if there is a quick short to GND.
VIN
IN
0
VBIAS
BIAS
0
VEN
EN
tR
0
tD
VOUT
90%
Voltage
Pulled
Down
OUT
SNS
10%
0
tRESTART
VSNS
0
VIL,SNS
VIH,SNS
tBLANK
tDEGLITCH
VEN
0
PG
Time
Figure 50. Automatic Restart after Quick Short to GND
24
Copyright © 2015, Texas Instruments Incorporated
TPS22954, TPS22953
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ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
Feature Description (continued)
9.3.5 Manual Restart
The falling edge of the SNS pin below VIL,SNS is considered a fault case and will cause the load switch to be
disabled for tRESTART (typically 2ms). The SNS pin can be driven by an MCU to manually reset the load switch.
After the tRESTART time, the switch will be automatically re-enabled as long as EN is still above VIH,EN , even is
SNS is held low. The PG pin will stay low until the switch is re-enabled and the SNS pin rises above VIH,SNS
.
VIN
IN
0
VBIAS
BIAS
0
VEN
EN
tR
0
tD
VOUT
90%
OUT
SNS
10%
0
tRESTART
VSNS
0
VIL,SNS
tDEGLITCH
VEN
0
PG
Time
Figure 51. Manual Restart (SNS Held Low)
If the SNS pin is brought above VIH,SNS within the tRESTART time, the switch will still wait to re-enable. The PG pin
will also stay low until tBLANK after switch is re-enabled. In this case, PG will indicate when the switch is enabled
and capable of being reset again.
VIN
IN
0
VBIAS
BIAS
0
VEN
EN
tR
0
tD
VOUT
90%
OUT
SNS
10%
0
tRESTART
VSNS
0
VIL,SNS
tBLANK
tDEGLITCH
VEN
0
PG
Time
Figure 52. Manual Restart (SNS Toggled Low to High)
Copyright © 2015, Texas Instruments Incorporated
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TPS22954, TPS22953
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
www.ti.com.cn
Feature Description (continued)
9.3.6 Thermal Shutdown
If the junction temperature of the device exceeds TSD, the switch will be disabled. The device will be enabled
once the junction temperature drops by TSDHYS as long as EN is still greater than VIH,EN
.
9.3.7 Quick Output Discharge (QOD) (TPS22954 Only)
The quick output discharge (QOD) transistor is engaged indefinitely whenever the switch is disabled and the
recommended VBIAS voltage is met. During this state, the QOD resistance (RPD) will discharge VOUT to GND. It is
not recommended to apply a continuous DC voltage to OUT when the device is disabled.
The QOD transistor can remain active for a short period of time even after VBIAS looses power. This brief period
of time is defined as tDIS. For best results, it is recommended the device get disabled before VBIAS goes below the
minimum recommended voltage. The waveform below shows the behaviour when power is applied and then
removed in a typical application.
VIN
IN
0
VBIAS
BIAS
0
VEN
EN
EN
tBLANK
VIH,EN
VIL,EN
0
tDEGLITCH
VOUT
OUT
OUT
VOUT < 100mV
0
tDIS
VSNS
VIL,SNS
tDEGLITCH
VIH,SNS
tBLANK
SNS
PG
SNS
PG
0
VEN
0
Time
Figure 53. Power Applied and then Removed in a Typical Application
At the end of the tDIS time, it is not guaranteed that VOUT will be 0V since the final voltage will be dependent upon
the initial voltage and the CL capacitor. The final VOUT can be calculated with the following formula for a given
initial voltage and CL capacitor.
-t
Vƒ = Vo ´ eRC
(3)
Where:
Vf = final VOUT voltage
Vo = initial VOUT voltage
R = the value of the output discharge resistor, RPD (see Electrical Characteristics table)
C = the output bulk capacitance on OUT
9.3.8 VIN and VBIAS Voltage Range
For optimal RON performance, make sure VIN ≤ VBIAS. The device will still be functional if VIN > VBIAS but it will
exhibit RON greater than what is listed in the Electrical Characteristics table. See Figure 50 for an example of a
typical device. Notice the increasing RON as VIN increases. Be sure to never exceed the maximum voltage rating
for VIN and VBIAS
.
26
Copyright © 2015, Texas Instruments Incorporated
TPS22954, TPS22953
www.ti.com.cn
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
Feature Description (continued)
55
50
45
40
35
30
25
20
15
VBIAS = 2.5V
VBIAS = 3.3V
VBIAS = 5V
VBIAS = 5.7V
10
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VIN (V)
D031
Figure 54. RON When VIN > VBIAS
9.3.9 Adjustable Rise Time (CT pin)
A capacitor to GND on the CT pin sets the slew rate for VOUT. An appropriate capacitance value should be
placed on CT such that the IMAX and IPLS specifications of the device are not violated. The capacitor to GND on
the CT pin should be rated for 25 V or higher. An approximate formula for the relationship between CT (except
for CT = open) and the slew rate for any VBIAS is:
SR = 0.35 × CT + 20
where
•
•
•
•
SR = slew rate (in μs/V)
CT = the capacitance value on the CT terminal (in pF)
The units for the constant 20 are μs/V.
The units for the constant 0.35 are μs/(V*pF).
(4)
Rise time can be calculated by multiplying the input voltage (typically 10% to 90%) by the slew rate. The table
below contains rise time values measured on a typical device.
RISE TIME (µs) 10%–90%, CL = 0.1 µF, VBIAS = 2.5V to 5.7V, RL=10Ω LOAD.
TYPICAL VALUES AT 25°C, 25V X7R 10% CERAMIC CAP
CTx (pF)
5V
140
3.3V
98
1.8V
62
1.5V
54
1.2V
46
0.7V
32
Open
220
444
301
175
150
255
474
961
1980
4331
124
210
387
787
1612
3533
81
470
767
518
299
133
245
490
998
2197
1000
2200
4700
10000
1492
3105
6420
14059
994
562
2050
4246
9339
1151
2365
5183
9.4 Device Functional Modes
The following Table describes what the OUT pin will be connected to for a particular device as determined by the
EN pin.
EN
L
TPS22953
OPEN
IN
TPS22954
RPD to GND
IN
H
Copyright © 2015, Texas Instruments Incorporated
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TPS22954, TPS22953
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
www.ti.com.cn
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
This section will highlight some of the design considerations when implementing this device in various
applications. A PSPICE model for this device is also available on www.ti.com for further aid.
10.1.1 Input to OutputVoltage Drop
The input to output voltage drop in the device is determined by the RON of the device and the load current. The
RON of the device depends upon the VIN and VBIAS conditions of the device. Refer to the RON specification of the
device in the Electrical Characteristics table of this datasheet. Once the RON of the device is determined based
upon the VIN and VBIAS voltage conditions, use Equation 5 to calculate the input to output voltage drop:
DV = ILOAD ´RON
(5)
Where:
ΔV = voltage drop from IN to OUT
ILOAD = load current
RON = On-Resistance of the device for a specific VIN and VBIAS
An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.
10.1.2 Thermal Considerations
The maximum IC junction temperature should be restricted to just under the thermal shutdown (TSD) limit of the
device. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient
temperature, use Equation 6.
TJ(max) - TA
PD(max)
=
qJA
(6)
Where:
PD(max) = maximum allowable power dissipation
TJ(max) = maximum allowable junction temperature before hitting thermal shutdown (see Electrical
Characteristics table)
TA = ambient temperature of the device
θJA = junction to air thermal impedance. See Thermal Information section. This parameter is highly
dependent upon board layout.
28
Copyright © 2015, Texas Instruments Incorporated
TPS22954, TPS22953
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ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
Application Information (continued)
10.1.3 Automatic Power Sequencing
The PG pin of the TPS22953/54 allows for automatic sequencing of multiple system rails or loads. The accurate
SNS voltage monitoring will ensure the first rail is up before the next starts to turn on. This approach provides
robust system sequencing and reduces the total inrush current by preventing overlap. The example shows how
two rails can be sequenced. There is no limit to the number of rails that can be sequenced in this way
TPS22953/54
System
Module 1
Power
Supply
IN
OUT
OUT
SNS
IN
RSNS1
VBIAS
EN
REN1
RSNS2
CIN
CL
REN2
PG
CT
GND
PAD
CT
TPS22953/54
Power
Supply
System
Module 2
IN
OUT
OUT
SNS
IN
RSNS1
VBIAS
EN
REN1
RSNS2
CIN
CL
Rpullup
PG
REN2
PG
CT
GND
PAD
CT
Figure 55. Power Sequencing with PG Control
Copyright © 2015, Texas Instruments Incorporated
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TPS22954, TPS22953
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www.ti.com.cn
Application Information (continued)
10.1.4 Monitoring a Downstream Voltage
The SNS pin can be used to monitor other system voltages in addition to VOUT. The status of the monitored
voltage will be indicated by the PG pin which can be pulled up to VOUT or another voltage. The figure below
shows an example of the TPS22953/54 monitoring the output of a downstream DC/DC regulator. In this case, the
switch will turn on when the power supply is above the UVLO, but the PG will not be asserted until the DC/DC
regulator has started up.
TPS22953/54
DC/DC
Regulator
Power
Supply
IN
OUT
CL
IN
OUT
RSNS1
VBIAS
EN
SNS
REN1
RSNS2
CIN
RL
Rpullup
PG
REN2
PG
CT
GND
PAD
CT
Figure 56. Monitoring a Downstream Voltage
In this application, if the DC/DC Regulator is shut down, the supervisor will register this as a fault case and reset
the load switch.
10.1.4.1 Monitoring the Input Voltage
The SNS pin can also be used to monitor VIN in the case a MCU GPIO is being used to control the EN. This will
allow PG to report on the status of the input voltage when the switch is enabled.
TPS22953/54
Power
Supply
IN
OUT
CL
CL
IN
OUT
RSNS1
VBIAS
EN
SNS
RSNS2
GPIO
RL
MCU
Rpullup
PG
PG
CT
GND
PAD
CT
Figure 57. Monitoring Input Voltage
30
Copyright © 2015, Texas Instruments Incorporated
TPS22954, TPS22953
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ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
10.2 Typical Application
This application demonstrates how the TPS22953/54 can use used to limit inrush current to output capacitance.
TPS22953/54
Power
Supply
IN
OUT
OUT
SNS
IN
RSNS1
VBIAS
EN
REN1
RSNS2
CIN
CL = 100 µF
RL
Rpullup
PG
REN2
PG
CT
GND
PAD
CT
Figure 58. Typical Application Schematic for Powering a Downstream Module
10.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
3.3 V
5.0 V
VBIAS
CL
47 µF
150mA
None
Maximum Acceptable Inrush Current
RL
10.2.2 Detailed Design Procedure
To begin the design process, the designer needs to know the following:
•
•
•
•
•
Input voltage
BIAS voltage
Load current
Load capacitance
Maximum acceptable inrush current
10.2.2.1 Inrush Current
To determine how much inrush current will be caused by the CL capacitor, use Equation 7:
dVOUT
I
= CL ´
INRUSH
dt
(7)
Where:
IINRUSH = amount of inrush caused by CL
CL = capacitance on VOUT
dt = VOUT Rise Time (typically 10% to 90%)
dVOUT = Change in VOUT Voltage (typically 10% to 90%)
In this case, a Slew Rate slower than 314μs/V will be required to meet the maximum acceptable inrush
requirement. Equation 4 can be used to estimate the CT capacitance required for this slew rate.
314 μs/V = 0.35 × CT + 20
(8)
(9)
CT = 840 pF
Copyright © 2015, Texas Instruments Incorporated
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TPS22954, TPS22953
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www.ti.com.cn
10.2.3 Application Curves
The following Application Curves show the inrush with multiple different CT values. These curves show only a CT
capacitance greater than 840pF results in the acceptable inrush current of 150mA.
CT = 0 pF
CT = 220 pF
Figure 59. Inrush with CT = 0 pF
Figure 60. Inrush with CT = 220 pF
CT = 470 pF
CT = 1000 pF
Figure 61. Inrush with CT = 470 pF
Figure 62. Inrush with CT = 1000 pF
CT = 2200 pF
Figure 63. Inrush with CT = 2200 pF
32
Copyright © 2015, Texas Instruments Incorporated
TPS22954, TPS22953
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ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
11 Power Supply Recommendations
The device is designed to operate from a VBIAS range of 2.5V to 5.7V and a VIN range of 0.7 V to 5.7 V. The
power supply should be well regulated and placed as close to the device terminals as possible. It must be able to
withstand all transient and load current steps. In most situations, using an input capacitance of 1 µF is sufficient
to prevent the supply voltage from dipping when the switch is turned on. In cases where the power supply is
slow to respond to a large transient current or large load current step, additional bulk capacitance may be
required on the input.
The requirements for larger input capacitance can be mitigated by adding additional capacitance to the CT pin.
This will cause the load switch to turn on more slowly. Not only will this reduce transient inrush current, but it will
also give the power supply more time to respond to the load current step.
12 Layout
12.1 Layout Guidelines
•
•
•
Input and Output traces should be as short and wide as possible to accommodate for high current.
Use vias under the exposed thermal pad for thermal relief for high current operation.
The CT Capacitor should be placed as close as possible to the device to minimize parasitic trace
capacitance. It is also recommended to cutout copper on other layers directly below CT to minimize parasitic
capacitance.
•
•
•
The IN terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is ceramic with X5R or X7R dielectric. This capacitor should be placed as
close to the device pins as possible.
The OUT terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is ceramic with X5R or X7R dielectric. This capacitor should be placed as
close to the device pins as possible.
The BIAS terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is ceramic with X5R or X7R dielectric.
版权 © 2015, Texas Instruments Incorporated
33
TPS22954, TPS22953
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
www.ti.com.cn
12.2 Layout Example
VIA to Power Ground Plane
VIA to PG pin
Input Bypass
Capacitor
Output Bypass
Capacitor
IN
OUT
OUT
SNS
PG
IN
To Bias Supply
BIAS
To µC
EN
GND
CT
To GPIO
control or
resistor
divider
Exposed Thermal
Pad Area
Figure 64. Recommended Board Layout
34
版权 © 2015, Texas Instruments Incorporated
TPS22954, TPS22953
www.ti.com.cn
ZHCSDK9A –MARCH 2015–REVISED APRIL 2015
13 器件和文档支持
13.1 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TPS22953
TPS22954
13.2 商标
All trademarks are the property of their respective owners.
13.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
14 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
35
PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS22953DQCR
TPS22953DSQR
TPS22954DQCR
TPS22954DSQR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
DQC
DSQ
DQC
DSQ
10
10
10
10
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
RB953
3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR
3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
ZFDI
RB954
ZDKI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS22953, TPS22954 :
Automotive : TPS22953-Q1, TPS22954-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS22953DQCR
TPS22953DQCR
TPS22953DSQR
TPS22953DSQR
TPS22954DQCR
TPS22954DSQR
WSON
WSON
WSON
WSON
WSON
WSON
DQC
DQC
DSQ
DSQ
DQC
DSQ
10
10
10
10
10
10
3000
3000
3000
3000
3000
3000
180.0
180.0
180.0
179.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.25
2.3
3.2
3.25
2.3
1.0
1.05
1.15
1.2
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q2
Q2
Q1
Q2
2.2
2.2
2.25
2.3
3.25
2.3
1.05
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS22953DQCR
TPS22953DQCR
TPS22953DSQR
TPS22953DSQR
TPS22954DQCR
TPS22954DSQR
WSON
WSON
WSON
WSON
WSON
WSON
DQC
DQC
DSQ
DSQ
DQC
DSQ
10
10
10
10
10
10
3000
3000
3000
3000
3000
3000
195.0
210.0
210.0
213.0
210.0
210.0
200.0
185.0
185.0
191.0
185.0
185.0
45.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DQC0010A
WSON - 0.8mm max height
S
C
A
L
E
4
.
5
0
0
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.3
0.2
0.35
0.25
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08
0.84 0.1
SYMM
(0.2) TYP
0.05
0.00
5
6
8X 0.5
2X
2
SYMM
11
2.4 0.1
SEE OPTIONAL
TERMINAL
DETAIL
1
10
0.3
10X
0.2
0.1
0.05
PIN 1 ID
(45 X0.2)
C A B
C
0.4
10X
0.2
4218281/C 11/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DQC0010A
WSON - 0.8mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.84)
(
0.2) TYP
10X (0.5)
VIA
1
10
10X (0.25)
(0.95)
11
SYMM
(2.4)
8X (0.5)
6
5
(R0.05) TYP
SYMM
(1.9)
LAND PATTERN EXAMPLE
SCALE: 30X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218281/C 11/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DQC0010A
WSON - 0.8mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.8)
10X (0.5)
10
10X (0.25)
1
(1.08)
11
SYMM
8X (0.5)
(0.64)
METAL
TYP
6
5
(R0.05) TYP
SYMM
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE: 30X
4218281/C 11/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DSQ0010A
WSON - 0.8 mm max height
S
C
A
L
E
5
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
0.9 0.1
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
5
6
SYMM
1.5 0.1
11
2X 1.6
8X 0.4
1
PIN 1 ID
10
0.25
0.15
10X
0.4
0.2
10X
0.1
C A B
0.05
4218906/A 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSQ0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SEE SOLDER MASK
DETAIL
10X (0.5)
10X (0.2)
SYMM
10
1
(1.5)
8X (0.4)
11
SYMM
(0.5)
(R0.05) TYP
5
6
(
0.2) TYP
VIA
(1.9)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218906/A 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSQ0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.5)
10X (0.2)
(0.85)
10
1
8X (0.4)
11
SYMM
(1.38)
(R0.05) TYP
5
6
SYMM
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 11
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4218906/A 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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