TPS22961 [TI]

具有输出放电功能的 3.5V、6A、7mΩ 负载开关;


型号：	TPS22961
厂家：	TEXAS INSTRUMENTS
描述：	具有输出放电功能的 3.5V、6A、7mΩ 负载开关开关
文件：	总29页 (文件大小：1918K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS22961

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

TPS22961 3.5V，6A，超低电阻负载开关

1 特性

3 说明

•

集成单通道负载开关

TPS22961 是一款小型，超低 R_ON，单通道负载开

关，此开关具有受控开启功能。此器件包含一个可在

0.8V 至 3.5V 输入电压范围内运行的 N 通道金属氧化

物半导体场效应晶体管 (MOSFET)，并且支持最大 6A

的持续电流。

VBIAS 电压范围：3V 至 5.5V

输入电压范围：0.8V 至 3.5V

超低 R_ON电阻

–

V_IN= 1.05V (V_BIAS= 5V) 时，R_ON= 4.4mΩ

•

6A 最大持续开关电流

器件的超低 R_ON和高电流处理能力的组合使得此器件

非常适合于驱动具有非常严格压降耐受的处理器电源

轨。器件的快速上升时间使得电源轨可以在器件被启用

时迅速接通，从而减少配电响应时间。此开关可由 ON

端子单独控制，此端子能够与微控制器或低压离散逻辑

电路生成的低压控制信号直接对接。通过集成一个

260Ω 下拉电阻器，在开关关闭时实现快速输出放电

(QOD)，此器件进一步减少总体解决方案尺寸。

低静态电流小于 1µA（最大值）

低控制输入阈值支持使用 1.2V/1.8V/2.5V/3.3V 逻

辑器件

•

受控转换率

–

V_IN= 1.05V 时 (V_BIAS= 5V) ，t_R= 4.2µs

•

快速输出放电 (QOD)

带有散热垫的小外形尺寸无引线 (SON) 8 端子封装

静电放电 (ESD) 性能经测试符合 JESD 22 规范

TPS22961 采用小型，节省空间的 3mm x 3mm 8 端

子小外形尺寸无引线 (SON) 封装 (DNY)，此类封装具

有可实现高功率耗散的集成散热垫。器件在自然通风环

境下的额定运行温度范围为 -40°C 至 85°C。

–

2kV 人体放电模式 (HBM) 和 1kV 器件充电模型

(CDM)

2 应用范围

•

Ultrabook™/笔记本电脑

台式机

器件信息⁽¹⁾

器件型号

TPS22961

封装

WSON (8)

封装尺寸

服务器

3.00mm x 3.00mm

机顶盒

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

电信系统

平板电脑

4 简化电路原理图

VBIAS

(4.5V to 5.5V)

R_ON与 V_IN之间的关系 (V_BIAS= 5V，I_OUT= -200mA)

Processor

(x86, FPGA,

DSP)

VIN

VOUT

Power

Supply

C_IN

C_L

GND

OFF

TPS22961

典型应用：驱动用于处理器的高电流内核电

源轨

-40°C

25°C

85°C

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

V_IN(V)

C007

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSCI4

TPS22961

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram ....................................... 12

8.3 Feature Description................................................. 13

Applications and Implementation ...................... 14

9.1 Application Information............................................ 14

9.2 Typical Application .................................................. 14

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Terminal Configuration and Functions................ 3

Specifications......................................................... 3

7.1 Absolute Maximum Ratings ...................................... 3

7.2 Handling Ratings....................................................... 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics, V_BIAS= 5.0 V ................... 5

7.6 Electrical Characteristics, V_BIAS= 3.0 V ................... 5

7.7 Switching Characteristics.......................................... 6

7.8 Typical Characteristics.............................................. 8

Detailed Description ............................................ 12

10 Power Supply Recommendations ..................... 18

11 Layout................................................................... 19

11.1 Layout Guidelines ................................................. 19

11.2 Layout Example .................................................... 19

12 器件和文档支持 ..................................................... 20

12.1 商标....................................................................... 20

12.2 静电放电警告......................................................... 20

12.3 术语表 ................................................................... 20

13 机械封装和可订购信息 .......................................... 20

5 修订历史记录

Changes from Revision A (February 2014) to Revision B

Page

•

Fixed caption error in Filtered Output curve. ....................................................................................................................... 18

Changes from Original (February 2014) to Revision A

Page

•

完整版的最初发布版本。 ........................................................................................................................................................ 1

TPS22961

www.ti.com.cn

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

6 Terminal Configuration and Functions

DNY PACKAGE

8 TERMINAL

VOUT

VIN

VOUT

VIN

VOUT

VIN

(Exposed thermal

pad)

VIN

(Exposed thermal

pad)

VBIAS

VOUT

GND

VBIAS

VOUT

GND

Top View

Bottom View

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Switch input. Place ceramic bypass capacitor(s) between this terminal and GND. See Detailed

Description section for more information.

VIN

1, 2

Exposed thermal

Pad

Switch input. Place ceramic bypass capacitor(s) between this terminal and GND. See Detailed

Description section for more information.

VIN

VBIAS

Bias voltage. Power supply to the device.

Active high switch control input. Do not leave floating.

Ground.

GND

–

Switch output. Place ceramic bypass capacitor(s) between this terminal and GND. See Detailed

Description section for more information.

VOUT

6, 7, 8

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

V_IN

Input voltage range

V_BIAS

V_OUT

V_ON

I_MAX

I_PLS

T_A

Bias voltage range

Output voltage range

ON pin voltage range

Maximum Continuous Switch Current

Maximum Pulsed Switch Current, pulse < 300 µs, 2% duty cycle

Operating free-air temperature range

Maximum junction temperature

–40

125

°C

T_J

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TPS22961

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

7.2 Handling Ratings

MIN

MAX

UNIT

°C

T_STG

Storage temperature range

–65

150

300

T_LEAD

Maximum lead temperature (10-s soldering time)

Human-Body Model (HBM)⁽²⁾

Charged-Device Model (CDM)⁽³⁾

°C

(1)

V_ESD

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows

safe manufacturing with a standard ESD control process.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

0.8

MAX

UNIT

V_IN

Input voltage range

Bias voltage range

ON voltage range

Output voltage range

V_BIAS– 1.95

V_BIAS

V_ON

V_OUT

5.5

V_IN

5.5

0.5

V_{IH, ON}High-level voltage, ON

V_{IL, ON}Low-level voltage, ON

V_BIAS= 3 V to 5.5 V

1.2

C_IN

Input Capacitor

1⁽¹⁾

µF

(1) Refer to Detailed Description section.

7.4 Thermal Information

TPS22961

THERMAL METRIC⁽¹⁾

DNY

8 PINS

44.6

44.4

17.6

0.4

UNIT

θ_JA

Junction-to-ambient thermal resistance

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

17.4

1.1

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TPS22961

www.ti.com.cn

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

7.5 Electrical Characteristics, V_BIAS= 5.0 V

Unless otherwise noted, the specification in the following table applies over the operating ambient temperature

–40°C ≤ T_A≤ 85°C (full) and V_BIAS= 5.0 V. Typical values are for T_A= 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

POWER SUPPLIES AND CURRENTS

I_OUT= 0, V_IN= 3 V,

V_ON= V_BIAS= 5.0 V

I_{Q, VBIAS}

V_BIASquiescent current

V_BIASshutdown current

Full

0.6

µA

I_{SD, VBIAS}

V_ON= 0 V, V_OUT= 0 V

0.6

0.0009

0.0008

0.0007

0.0006

0.1

V_IN= 3.0 V

V_IN= 2.5 V

V_IN= 2.0 V

V_IN= 1.05 V

V_IN= 0.8 V

V_ON= 0 V,

V_OUT= 0 V

I_{SD, VIN}

V_INshutdown current

Full

µA

ON terminal input leakage

current

I_ON

V_ON= 5.5 V

0.1

RESISTANCE CHARACTERISTICS

25°C

Full

6.5

5.3

4.8

4.4

4.3

260

8.8

6.3

7.2

5.8

6.7

5.3

6.2

5.3

6.1

300

V_IN= 3.0 V

V_IN= 2.5 V

V_IN= 2.0 V

V_IN= 1.05 V

V_IN= 0.8 V

mΩ

25°C

Full

25°C

Full

I_OUT= –200 mA,

V_BIAS= 5.0 V

R_ON

ON-state resistance

25°C

Full

25°C

Full

mΩ

R_PD

Output pulldown resistance

V_IN= 5.0 V, V_ON= 0 V, V_OUT= 1 V

Full

Ω

7.6 Electrical Characteristics, V_BIAS= 3.0 V

Unless otherwise noted, the specification in the following table applies over the operating ambient temperature

–40°C ≤ T_A≤ 85°C (full) and V_BIAS= 3.0 V. Typical values are for T_A= 25°C unless otherwise noted.

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

POWER SUPPLIES AND CURRENTS

I_OUT= 0, V_IN= 1 V,

V_ON= V_BIAS= 3.0 V

I_{Q, VBIAS}

V_BIASquiescent current

V_BIASshutdown current

Full

0.3

µA

I_{SD, VBIAS}

V_ON= 0 V, V_OUT= 0 V

0.3

0.001

0.1

V_IN= 1.05 V

V_IN= 0.8 V

V_ON= 0 V,

V_OUT= 0 V

I_{SD, VIN}

I_ON

V_INshutdown current

Full

µA

0.0008

ON terminal input leakage

current

V_ON= 5.5 V

0.1

RESISTANCE CHARACTERISTICS

25°C

Full

6.7

5.8

8.4

9.2

7.0

7.9

300

V_IN=1.05 V

V_IN= 0.8 V

mΩ

I_OUT= –200 mA,

V_BIAS= 3.0 V

R_ON

ON-state resistance

25°C

Full

mΩ

R_PD

Output pull-down resistance

V_IN= 3V, V_ON= 0 V, V_OUT= 1 V

Full

260

Ω

TPS22961

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

7.7 Switching Characteristics

Refer to the timing test circuit in Figure 1 (unless otherwise noted) for references to external components used for the test

condition in the switching characteristics table.

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNIT

V_IN= 2.5 V, V_ON= V_BIAS= 5 V, T_A= 25ºC (unless otherwise noted)

t_ON

t_OFF

t_R

Turn-on time

Turn-off time

V_OUTrise time

V_OUTfall time

Delay time

10.0

3.5

6.3

2.0

8.1

R_L= 10 Ω, C_L= 0.1 µF

µs

t_F

t_D

V_IN= 1.05 V, V_ON= V_BIAS= 5 V, T_A= 25ºC (unless otherwise noted)

t_ON

t_OFF

t_R

Turn-on time

Turn-off time

V_OUTrise time

V_OUTfall time

Delay time

8.1

11.3

13700

9.5

17.3

L = 2.2 µH (DCR = 0.33 Ω),

C = 2 x 22 µF

(Refer to Typical Application

Powering Rails Sensitive to Ringing

and Overvoltage due to Fast Rise

Time and Figure 31)

12.5

µs

t_F

44200

9.3

t_D

6.7

V_IN= 0.8 V, V_ON= V_BIAS= 5 V, T_A= 25ºC (unless otherwise noted)

t_ON

t_OFF

t_R

Turn-on time

Turn-off time

V_OUTrise time

V_OUTfall time

Delay time

9.7

6.0

3.2

1.8

8.1

R_L= 10 Ω, C_L= 0.1 µF

t_F

t_D

V_IN= 1.05 V, V_ON= 5 V, V_BIAS= 3.0 V, T_A= 25ºC (unless otherwise noted)

t_ON

t_OFF

t_R

Turn-on time

Turn-off time

V_OUTrise time

V_OUTfall time

Delay time

19.1

4.7

R_L= 10 Ω, C_L= 0.1 µF

9.0

t_F

2.0

t_D

15.6

V_IN= 0.8 V, V_ON= 5 V, V_BIAS= 3.0 V, T_A= 25ºC (unless otherwise noted)

t_ON

t_OFF

t_R

Turn-on time

Turn-off time

V_OUTrise time

V_OUTfall time

Delay time

19.0

5.4

R_L= 10 Ω, C_L= 0.1 µF

7.0

t_F

1.9

t_D

15.7

TPS22961

www.ti.com.cn

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

VIN

VOUT

C_IN= 1µF

(A)

C_L

R_L

OFF

VBIAS

GND

TPS22961

GND

Timing Test Circuit

V_ON

50%

t_F

t_OFF

t_R

V_OUT

t_ON

90%

V_OUT

50%

10%

t_D

Timing Waveforms

(A) Rise and fall times of the control signal is 100ns.

Figure 1. Switching Characteristics Measurement Setup and Definitions

TPS22961

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

7.8 Typical Characteristics

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

-40°C

25°C

85°C

-40°C

25°C

85°C

3.25

3.5

3.75

4.25

4.5

4.75

5.25

5.5

3.25

3.5

3.75

4.25

4.5

4.75

5.25

5.5

V_BIAS(V)

C002

C003

V_IN= 1.05 V

V_ON= 5 V

I_OUT= 0 A

V_ON= 0 V

V_OUT= 0 V

Figure 3. I_SD,VBIASvs V_BIAS

Figure 2. I_Q,VBIASvs V_BIAS

0.04

0.035

0.03

0.025

0.02

0.015

0.01

0.005

-40°C

25°C

85°C

VIN = 0.8V

VIN = 0.9V

VIN = 1.05V

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

-40

-15

V_IN(V)

Ambient Temperature (£/)

C001

C004

V_BIAS= 5 V

V_ON= 0 V

Figure 4. I_SD,VINvs V_IN

V_OUT= 0 V

V_BIAS= 3 V

V_ON= 5 V

I_OUT= –200 mA

Figure 5. R_ONvs Ambient Temperature

VIN = 0.8V

VIN = 1.05V

VIN = 1.2V

VIN = 1.5V

VIN = 1.8V

VIN = 2.5V

VIN = 3V

-40°C

25°C

85°C

-40

-15

0.8

0.85

0.9

0.95

1.05

Ambient Temperature (°C)

V_IN(V)

C005

C006

V_BIAS= 5 V

V_ON= 5 V

I_OUT= –200 mA

V_BIAS= 3 V

V_ON= 5 V

Figure 7. R_ONvs V_IN

I_OUT= –200 mA

Figure 6. R_ONvs Ambient Temperature

TPS22961

www.ti.com.cn

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

Typical Characteristics (continued)

-40°C

25°C

85°C

VBIAS = 3V

VBIAS = 5V

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

V_IN(V)

C007

C008

V_BIAS= 5 V

V_ON= 5 V

Figure 8. R_ONvs V_IN

I_OUT= –200 mA

T_A= 25°C

V_ON= 5 V

Figure 9. R_ONvs V_IN

I_OUT= –200 mA

270

268

266

264

262

260

258

256

254

252

-40°C

25°C

85°C

-40°C

25°C

85°C

250

3.5

4.5

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

V_BIAS(V)

V_IN(V)

C009

C012

V_ON= 0 V

V_IN= 1.05 V

V_OUT= 1 V

V_BIAS= 5 V

V_ON= 5 V

I_OUT= –6 A

Figure 10. R_PDvs V_BIAS

Figure 11. R_ONvs V_INat 6A load

0.95

0.9

1.1

1.05

0.95

0.9

0.85

0.8

-40°C

25°C

85°C

0.85

0.8

0.75

25°C

85°C

0.7

3.5

4.5

3.5

4.5

V_BIAS(V)

C011

C010

V_IN= V_BIAS– 2 V

Figure 13. V_IH,ONvs V_BIAS

Figure 12. V_IL,ONvs V_BIAS

TPS22961

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Typical Characteristics (continued)

9.5

8.5

7.5

-40°C

25°C

85°C

-40°C

25°C

85°C

6.5

0.80 0.83 0.85 0.88 0.90 0.93 0.95 0.98 1.00 1.03 1.05

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

V_IN(V)

C015

C020

V_BIAS= 3 V

R_L= 10 Ω

C_L= 0.1 µF

V_BIAS= 5 V

R_L= 10 Ω

Figure 15. t_Dvs V_IN

C_L= 0.1 µF

Figure 14. t_Dvs V_IN

2.2

2.1

2.4

2.3

2.2

2.1

1.9

1.8

1.7

1.6

1.5

1.4

1.9

1.8

1.7

1.6

1.5

1.4

-40°C

25°C

85°C

25°C

85°C

0.80 0.83 0.85 0.88 0.90 0.93 0.95 0.98 1.00 1.03 1.05

0.8

1.4

1.6

1.8

2.2

2.4

2.8

V_IN(V)

C014

C021

V_BIAS= 3 V

R_L= 10 Ω

C_L= 0.1 µF

V_BIAS= 5 V

R_L= 10 Ω

Figure 17. t_Fvs V_IN

C_L= 0.1 µF

Figure 16. t_Fvs V_IN

7.5

6.5

5.5

4.5

-40°C

3.5

-40°C

25°C

85°C

25°C

85°C

2.5

0.8

1.4

1.6

1.8

2.2

2.4

2.8

0.80 0.83 0.85 0.88 0.90 0.93 0.95 0.98 1.00 1.03 1.05

V_IN(V)

C016

C019

V_BIAS= 3 V

R_L= 10 Ω

C_L= 0.1 µF

V_BIAS= 5 V

R_L= 10 Ω

Figure 19. t_OFFvs V_IN

C_L= 0.1 µF

Figure 18. t_OFFvs V_IN

TPS22961

www.ti.com.cn

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

Typical Characteristics (continued)

11.5

10.5

9.5

8.5

-40°C

25°C

85°C

-40°C

25°C

85°C

7.5

0.80 0.83 0.85 0.88 0.90 0.93 0.95 0.98 1.00 1.03 1.05

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

V_IN(V)

C017

C018

V_BIAS= 3 V

R_L= 10 Ω

C_L= 0.1 µF

V_BIAS= 5 V

R_L= 10 Ω

Figure 21. t_ONvs V_IN

C_L= 0.1 µF

Figure 20. t_ONvs V_IN

-40°C

25°C

85°C

-40°C

25°C

85°C

0.80 0.83 0.85 0.88 0.90 0.93 0.95 0.98 1.00 1.03 1.05

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

V_IN(V)

C013

C022

V_BIAS= 3 V

R_L= 10 Ω

C_L= 0.1 µF

V_BIAS= 5 V

R_L= 10 Ω

Figure 23. t_Rvs V_IN

C_L= 0.1 µF

Figure 22. t_Rvs V_IN

VBIAS = 3.0V

VBIAS = 3.3V

VBIAS = 3.6V

VBIAS = 4.2V

VBIAS = 5.0V

VBIAS = 5.5V

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

V_IN(V)

C023

T_A= 25°C

R_L= 10 Ω

C_L= 0.1 µF

Figure 24. t_Rvs V_INfor Various V_BIAS

TPS22961

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

8 Detailed Description

8.1 Overview

The device is a 3.5 V, 6 A load switch in a 8-terminal SON package. To reduce voltage drop for low voltage and

high current rails, the device implements an ultra-low resistance N-channel MOSFET which reduces the drop out

voltage through the device at very high currents.

The device has a controlled, yet quick, fixed slew rate for applications that require quick turn-on response. During

shutdown, the device has very low leakage currents, thereby reducing unnecessary leakages for downstream

modules during standby. Integrated control logic, driver, and output discharge FET eliminates the need for any

external components, which reduces solution size and BOM count.

8.2 Functional Block Diagram

VIN

VBIAS

Control

Logic

Driver

VOUT

GND

TPS22961

www.ti.com.cn

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

8.3 Feature Description

8.3.1 On/off Control

The ON terminal controls the state of the load switch, and asserting the terminal high (active high) enables the

switch. The ON terminal is compatible with standard GPIO logic threshold and can be used with any

microcontroller or discrete logic with 1.2 V or higher GPIO voltage. This terminal cannot be left floating and must

be tied either high or low for proper functionality.

8.3.2 Input Capacitor (C_IN)

To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a

discharged load capacitor or short-circuit, a capacitor needs to be placed between VIN and GND. A 1 µF ceramic

capacitor, C_IN, placed close to the terminals, is usually sufficient. Higher values of C_INcan be used to further

reduce the voltage drop in high-current application. When switching heavy loads, it is recommended to have an

input capacitor 10 times higher than the output capacitor to avoid excessive voltage drop.

8.3.3 Output Capacitor (C_L)

Due to the integrated body diode in the NMOS switch, a C_INgreater than C_Lis highly recommended. A C_L

greater than C_INcan cause V_OUTto exceed V_INwhen the system supply is removed. This could result in current

flow through the body diode from VOUTT to VIN. A C_INto C_Lratio of 10 to 1 is recommended for minimizing V_IN

dip caused by inrush currents during startup, however a 10 to 1 ratio for capacitance is not required for proper

functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) could cause a V_INdip upon turn-on due to

inrush currents.

8.3.4 V_INand V_BIASVoltage Range

For optimal R_ONperformance, make sure V_IN≤ (V_BIAS– 1.95 V). For example, in order to have V_IN= 3.5V, VBIAS

must be 5.5 V. The device will still be functional if V_IN> (V_BIAS– 1.95 V) but it will exhibit R_ONgreater than what is

listed in the Electrical Characteristics, V_BIAS= 5.0 V table. See Figure 25 for an example of a typical device.

Notice the increasing R_ONas V_INincreases. Be sure to never exceed the maximum voltage rating for V_INand

V_BIAS

VBIAS = 3.0V

VBIAS = 3.3V

VBIAS = 3.6V

VBIAS = 4.2V

VBIAS = 5.0V

VBIAS = 5.5V

0.8

1.2

1.6

2.4

2.8

3.2

3.6

4.4

4.8

5.2

V_IN(V)

C023

Figure 25. R_ONvs V_IN(V_IN> V_BIAS

)

TPS22961

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

This section will highlight some of the design considerations when implementing this device in various

applications. A PSPICE model for this device is also available in the product page of this device on www.ti.com

for further aid.

9.2 Typical Application

9.2.1 Typical Application Powering a Downstream Module

This application demonstrates how the TPS22961 can be used to power downstream modules.

VIN

VOUT

VIN

VOUT

C_IN

VIN

(exposed

pad)

C_L= 0.1µF

VBIAS

GND

Figure 26. Typical Application Schematic for Powering a Downstream Module

9.2.1.1 Design Requirements

For this design example, use the following as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_IN

V_BIAS

1.05 V

5.0 V

6 A

Load current

9.2.1.2 Detailed Design Procedure

To begin the design process, the designer needs to know the following:

•

VIN voltage

VBIAS voltage

Load current

TPS22961

www.ti.com.cn

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

9.2.1.2.1 VIN to VOUT Voltage Drop

The VIN to VOUT voltage drop in the device is determined by the R_ONof the device and the load current. The

R_ONof the device depends upon the V_INand V_BIASconditions of the device. Refer to the R_ONspecification of the

device in the Electrical Characteristics table of this datasheet. Once the R_ONof the device is determined based

upon the V_INand V_BIASconditions, use Equation 1 to calculate the VIN to VOUT voltage drop:

DV = I_LOAD´R_ON

(1)

where

•

ΔV = voltage drop from VIN to VOUT

I_LOAD= load current

R_ON= On-resistance of the device for a specific V_INand V_BIAScombination

An appropriate I_LOADmust be chosen such that the I_MAXspecification of the device is not violated.

9.2.1.2.2 Inrush Current

To determine how much inrush current will be caused by the C_Lcapacitor, use Equation 2:

dV_OUT

= C_L´

INRUSH

(2)

where

•

I_INRUSH= amount of inrush caused by C_L

C_L= capacitance on VOUT

dt = time it takes for change in V_OUTduring the ramp up of VOUT when the device is enabled

dV_OUT= change in V_OUTduring the ramp up of VOUT when the device is enabled

An appropriate C_Lvalue should be placed on VOUT such that the I_MAXand I_PLSspecficiations of the device are

not violated.

9.2.1.2.3 Thermal Considerations

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To

calculate the maximum allowable dissipation, P_D(max)for a given output current and ambient temperature, use

Equation 3.

T_J(MAX)- T_A

D(MAX)

R_θJA

(3)

where

•

P_D(max)= maximum allowable power dissipation

T_J(max)= maximum allowable junction temperature (125°C for the TPS22961)

T_A= ambient temperature of the device

Θ_JA= junction to air thermal impedance. See Thermal Information section. This parameter is highly

dependent upon board layout.

TPS22961

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

9.2.1.3 Application Curves

V_BIAS= 5 V

C_L= 0.1 µF

V_IN= 2.5 V

CIN = 1 µF

V_BIAS= 5 V

C_L= 0.1 µF

V_IN= 0.8 V

CIN = 1 µF

Figure 27. t_Rat V_BIAS= 5 V

Figure 28. t_Rat V_BIAS= 5 V

V_BIAS= 5 V

C_L= 0.1 µF

V_IN= 1.05 V

CIN = 1 µF

V_BIAS= 5 V

C_L= 0.1 µF

V_IN= 0.8 V

CIN = 1 µF

Figure 29. t_Rat V_BIAS= 3 V

Figure 30. t_Rat V_BIAS= 3 V

TPS22961

www.ti.com.cn

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

9.2.2 Typical Application Powering Rails Sensitive to Ringing and Overvoltage due to Fast Rise Time

This application demonstrates how the TPS22961 can be used to power rails senstive to ringing and overvoltage

that can often happen due to fast rise times.

L = 2.2µH

VIN

VOUT

VIN

VOUT

C_IN

VIN

(exposed

pad)

C_L= 44µF

VBIAS

GND

Figure 31. Typical Application Schematic for Powering Rails Sensitive to Ringing

9.2.2.1 Design Requirements

For this design example, use the following as the input parameters.

Table 2. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_IN

V_BIAS

1.05 V

5.0 V

3.2%

Acceptable percent overshoot (ρ)

Maximum settling time (t_SETTLE

)

40 µs

9.2.2.2 Detailed Design Procedure

To begin the design process, the designer needs to know the following:

•

VIN voltage

VBIAS voltage

Acceptable percent overshoot

Maximum allowed settling time for the power rail

9.2.2.2.1 Picking Proper Inductor and Capacitor to Meet Voltage Overshoot Requirements

To determine the value of L and C_Lin the circuit, the damping factor associated with the acceptable percent

overshoot must be calculated. To calculate the damping factor (ε), use Equation 4.

- ln ρ

ε =

ln ρ

(

)

(4)

where

•

ε = damping factor of the LC filter

ρ = allowable percent overshoot for the power rail

TPS22961

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Use the damping factor calculated in Equation 4 to determine the inductance (L), the DCR of the inductor (R_DCR),

and capacitance (C_L) to achieve the percent overshoot. This will be an iterative process to determine the optimal

combination of L and C_Lwith standard value components available. Use Equation 5 to determine the

combination of L, R_DCR, and C_Lthat is needed to satisfy damping factor calculated from Equation 4.

R_DCR

C_L

ε =

(5)

where

•

ε = damping factor of the LC filter

R_DCR= DCR of the inductor

C_L= the capacitance of the filter

L = the inductor of the filter

To determine the setting time (within 5% of steady state value) of the filter, use Equation 6.

3´ L ´ C_L

t_SETTLE

(6)

where

•

t_SETTLE= settling time of filter to within 5% of steady state value

ε = damping factor of the LC filter

C_L= the capacitance of the filter

L = the inductor of the filter

The combination of damping factor (ε) and filter settling time (t_SETTLE) will bound the values for L, R_DCR, and C_L

that can be used to meet the design constraints in Table 2.

9.2.2.3 Application Curves

Figure 32. Filtered Output (CH1 = VIN, CH2 = ON, CH3 = Output of LC filter, CH4 = VOUT of TPS22961)

10 Power Supply Recommendations

The device is designed to operate from a V_BIASrange of 3 V to 5.5 V and VIN range of 0.8 V to 3.5 V. This

supply must be well regulated and placed as close to the TPS22961 as possible. If the supply is located more

than a few inches from the device terminals, additional bulk capacitance may be required in addition to the

ceramic bypass capacitors. An electrolytic, tantalum, or ceramic capacitor of 10 µF may be sufficient.

TPS22961

www.ti.com.cn

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

11 Layout

11.1 Layout Guidelines

•

VIN and VOUT traces should be as short and wide as possible to accommodate for high current.

Use vias under the exposed thermal pad for thermal relief for high current operation.

The VIN terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical

recommended bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor should be

placed as close to the device terminals as possible.

•

The VOUT terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical

recommended bypass capacitance is one-tenth of the VIN bypass capacitor of X5R or X7R dielectric rating.

This capacitor should be placed as close to the device terminals as possible.

The VBIAS terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical

recommended bypass capacitance is 0.1-µF ceramic with X5R or X7R dielectric.

11.2 Layout Example

VIA to Power Ground Plane

VIA to VIN Plane

VIN Bypass

VIN

Capacitor

VIN

VOUT Bypass

Capacitor

VIN

To Bias Supply

VBIAS

GND

To GPIO

control

Exposed Thermal

Pad Area

Figure 33. Recommended Board Layout

TPS22961

ZHCSC50B –FEBRUARY 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

12 器件和文档支持

12.1 商标

Ultrabook is a trademark of Intel.

12.2 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.3 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对本

文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧导航栏。

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS22961DNYR

TPS22961DNYT

ACTIVE

WSON

DNY

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

961A1

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

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Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS22961DNYR

TPS22961DNYT

WSON

DNY

3000

250

330.0

180.0

12.4

3.3

1.0

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS22961DNYR

TPS22961DNYT

WSON

DNY

3000

250

367.0

213.0

367.0

191.0

38.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

WSON - 0.8 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

DNY0008A

3.15

2.85

PIN 1 INDEX AREA

3.15

2.85

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

1.6±0.1

SYMM

0.5

0.3

EXPOSED THERMAL

PAD

(0.2) TYP

6X 0.65

SYMM

1.95

2.4±0.1

0.35

0.25

0.1

C A B

0.05

PIN1 ID

(OPTIONAL)

2X (0.2)

0.5

0.3

4221022/E 06/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

WSON - 0.8 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

DNY0008A

(1.6)

5X (0.6)

5X (0.3)

SYMM

(0.6)

3X (0.65)

SYMM

(1.6)

(0.325)

(2.4)

(0.95)

(0.975)

(R0.05) TYP

(0.55)

(2.8)

(Ø0.2) VIA

TYP

LAND PATTERN EXAMPLE

SCALE: 20X

0.07 MAX

0.07 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

EXPOSED METAL

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221022/E 06/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

WSON - 0.8 mm max height

DNY0008A

PLASTIC QUAD FLATPACK- NO LEAD

2X (1.47)

SYMM

5X (0.6)

5X (0.3)

(0.6)

(0.325)

(1.6)

(0.63)

SYMM

(1.06)

(0.975)

3X (0.65)

(R0.05) TYP

METAL

TYP

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

81% PRINTED COVERAGE BY AREA

SCALE: 20X

4221022/E 06/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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