TPS22976NDPUT [TI]

具有可调节上升时间和可选输出放电功能的 2 通道、5.7V、6A、14mΩ 负载开关 | DPU | 14 | -40 to 105;
TPS22976NDPUT
型号: TPS22976NDPUT
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
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具有可调节上升时间和可选输出放电功能的 2 通道、5.7V、6A、14mΩ 负载开关 | DPU | 14 | -40 to 105

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TPS22976  
SLVSDE7B NOVEMBER 2016REVISED SEPTEMBER 2017  
TPS22976 5.7-V, 6-A, 14-mΩ On-Resistance Dual-Channel Load Switch  
1 Features  
3 Description  
The TPS22976 product family consists of two  
devices: TPS22976 and TPS22976N. Each device is  
a dual-channel load switch with controlled turnon. The  
device contains two N-channel MOSFETs that can  
operate over an input voltage range of 0.6 V to 5.7 V,  
and can support a maximum continuous current of 6  
1
Integrated Dual-Channel Load Switch  
Input Voltage Range: 0.6 V to VBIAS  
VBIAS Voltage Range: 2.5 V to 5.7 V  
On-resistance  
RON = 14 m(Typical)  
A
per channel. Each switch is independently  
at VIN = 0.6 V to 5 V, VBIAS = 5 V  
controlled by an on and off input (ON1 and ON2),  
which can interface directly with low-voltage control  
signals. The TPS22976 is capable of thermal  
shutdown when the junction temperature is above the  
threshold, turning the switch off. The switch turns on  
again when the junction temperature stabilizes to a  
safe range. The TPS22976 also offers an optional  
integrated 230-Ω on-chip load resistor for quick  
output discharge when the switch is turned off.  
RON = 18 m(Typical)  
at VIN = 0.6 V to 2.5 V, VBIAS = 2.5 V  
6-A Maximum Continuous Switch Current per  
Channel  
Quiescent Current  
37 µA (Typical, Both Channels)  
at VIN = VBIAS = 5 V  
35 µA (Typical, Single Channel)  
at VIN = VBIAS = 5 V  
The TPS22976 is available in a small, space-saving  
3-mm  
×
2-mm 14-SON package (DPU) with  
integrated thermal pad allowing for high power  
dissipation. The device is characterized for operation  
over the free-air temperature range of –40°C to  
105°C.  
Control Input Threshold Enables Use of  
1.2-, 1.8-, 2.5-, and 3.3-V Logic  
Configurable Rise Time  
Thermal Shutdown  
Device Information(1)  
Quick Output Discharge (QOD) (Optional)  
SON 14-Pin Package with Thermal Pad  
ESD Performance Tested per JESD 22  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
TPS22976  
TPS22976N  
WSON (14)  
3.00 mm × 2.00 mm  
2-kV HBM and 1-kV CDM  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
2 Applications  
Ultrabook™  
Notebooks and Netbooks  
Tablet PCs  
Set-top Boxes and Residential Gateways  
Telecom Systems  
Solid-State Drives (SSD)  
Application Circuit  
VIN1  
VOUT1  
CT1  
ON  
OFF  
Dual  
ON1  
CL  
RL  
CIN  
Power  
Supply  
CT2  
VBIAS  
VIN2  
GND  
or  
VOUT2  
Dual  
DC-DC  
ON  
OFF  
Converter  
ON2  
CL  
RL  
CIN  
GND  
TPS22976  
GND  
Copyright © 2016, Texas Instruments Incorporated  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
TPS22976  
SLVSDE7B NOVEMBER 2016REVISED SEPTEMBER 2017  
www.ti.com  
Table of Contents  
9.3 Feature Description................................................. 16  
9.4 Device Functional Modes........................................ 17  
10 Application and Implementation........................ 18  
10.1 Application Information.......................................... 18  
10.2 Typical Application ................................................ 20  
11 Power Supply Recommendations ..................... 23  
12 Layout................................................................... 23  
12.1 Layout Guidelines ................................................. 23  
12.2 Layout Example .................................................... 23  
12.3 Power Dissipation ................................................. 23  
13 Device and Documentation Support ................. 24  
13.1 Device Support...................................................... 24  
13.2 Documentation Support ........................................ 24  
13.3 Receiving Notification of Documentation Updates 24  
13.4 Community Resources.......................................... 24  
13.5 Trademarks........................................................... 24  
13.6 Electrostatic Discharge Caution............................ 24  
13.7 Glossary................................................................ 24  
1
2
3
4
5
6
7
Features.................................................................. 1  
Applications ........................................................... 1  
Description ............................................................. 1  
Revision History..................................................... 2  
Device Comparison Table..................................... 3  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 4  
7.1 Absolute Maximum Ratings ...................................... 4  
7.2 ESD Ratings.............................................................. 4  
7.3 Recommended Operating Conditions....................... 4  
7.4 Thermal Information.................................................. 4  
7.5 Electrical Characteristics—VBIAS = 5 V..................... 5  
7.6 Electrical Characteristics—VBIAS = 2.5 V.................. 6  
7.7 Switching Characteristics.......................................... 7  
7.8 Typical DC Characteristics........................................ 8  
7.9 Typical AC Characteristics...................................... 11  
Parameter Measurement Information ................ 14  
Detailed Description ............................................ 15  
9.1 Overview ................................................................. 15  
9.2 Functional Block Diagram ....................................... 16  
8
9
14 Mechanical, Packaging, and Orderable  
Information ........................................................... 24  
4 Revision History  
Changes from Revision A (March 2017) to Revision B  
Page  
Updated VIH in Recommended Operating Conditions ............................................................................................................ 4  
Changes from Original (February 2016) to Revision A  
Page  
Updated statement for Equation 4 in Adjustable Rise Time section from "CT = 0 pF" to "CT < 100 pF"............................ 22  
2
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Copyright © 2016–2017, Texas Instruments Incorporated  
Product Folder Links: TPS22976  
 
TPS22976  
www.ti.com  
SLVSDE7B NOVEMBER 2016REVISED SEPTEMBER 2017  
5 Device Comparison Table  
RON AT VIN = VBIAS = 5 V  
QUICK OUTPUT  
DISCHARGE  
MAXIMUM OUTPUT  
ENABLE  
DEVICE  
(TYPICAL)  
CURRENT  
TPS22976  
14 mΩ  
Yes  
No  
6 A  
6 A  
Active high  
Active high  
TPS22976N  
14 mΩ  
6 Pin Configuration and Functions  
DPU Package  
14-Pin WSON with Exposed Thermal Pad  
Top View  
DPU Package  
14-Pin WSON with Exposed Thermal Pad  
Bottom View  
14  
1
1
2
14  
VIN1  
VIN1  
VOUT1  
VOUT1  
VIN1  
VOUT1  
13  
12  
VOUT1  
CT1  
VIN1  
ON1  
3
4
CT1  
ON1  
Thermal  
Pad  
GND  
VBIAS  
11  
10  
GND  
VBIAS  
ON2  
CT2  
5
6
7
ON2  
VIN2  
CT2  
VOUT2  
9
8
VIN2  
VIN2  
VOUT2  
VOUT2  
VIN2  
VOUT2  
Pin Functions  
PIN  
I/O  
DESCRIPTION  
NO.  
NAME  
1
2
3
Switch 1 input. Recommended voltage range for these pins for optimal RON performance is 0.6 V to  
VBIAS. Place an optional decoupling capacitor between these pins and GND to reduce VIN1 dip during  
turnon of the channel. See the Application Information section for more information  
VIN1  
I
ON1  
VBIAS  
ON2  
I
I
I
Active-high switch 1 control input. Do not leave floating  
Bias voltage. Power supply to the device. Recommended voltage range for this pin is 2.5 V to 5.7 V.  
See the Application Information section  
4
5
6
Active-high switch 2 control input. Do not leave floating  
Switch 2 input. Recommended voltage range for these pins for optimal RON performance is 0.6 V to  
VBIAS. Place an optional decoupling capacitor between these pins and GND to reduce VIN2 dip during  
turnon of the channel. See the Application Information section for more information  
VIN2  
I
7
8
9
VOUT2  
O
Switch 2 output  
Switch 2 slew rate control. Can be left floating. Capacitor used on this pin must be rated for a  
minimum of 25 V for desired rise time performance  
10  
11  
12  
CT2  
GND  
CT1  
O
O
Ground  
Switch 1 slew rate control. Can be left floating. Capacitor used on this pin must be rated for a  
minimum of 25 V for desired rise time performance  
13  
14  
VOUT1  
O
Switch 1 output  
Thermal pad (exposed center pad) to alleviate thermal stress. Tie to GND. See the Layout section for  
layout guidelines  
Thermal pad  
Copyright © 2016–2017, Texas Instruments Incorporated  
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TPS22976  
SLVSDE7B NOVEMBER 2016REVISED SEPTEMBER 2017  
www.ti.com  
7 Specifications  
7.1 Absolute Maximum Ratings  
Over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
–0.3  
–0.3  
–0.3  
–0.3  
MAX  
6
UNIT(2)  
VIN1,2  
Input voltage  
V
V
VOUT1,2 Output voltage  
6
VON1,2  
VBIAS  
IMAX  
IPLS  
ON-pin voltage  
6
V
Bias voltage  
6
V
Maximum continuous switch current per channel  
Maximum pulsed switch current per channel, pulse < 300 µs, 3% duty cycle  
Maximum junction temperature  
6
A
8
A
TJ  
125  
150  
°C  
°C  
Tstg  
Storage temperature  
–65  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to network ground terminal.  
7.2 ESD Ratings  
VALUE  
UNIT  
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
±2000  
V(ESD)  
Electrostatic discharge  
V
Charged-device model (CDM), per JEDEC specification JESD22-  
C101(2)  
±1000  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
7.3 Recommended Operating Conditions  
MIN  
MAX  
VBIAS  
5.7  
UNIT  
VIN1,2  
Input voltage  
Bias voltage  
ON voltage  
0.6  
2.5  
0
V
V
V
V
VBIAS  
VON1,2  
VOUT1,2  
5.7  
Output voltage  
VIN  
VBIAS = 2.5 V to 5 V, TA< 85°C  
VBIAS = 2.5 V to 5.7 V, TA< 105°C  
VBIAS = 2.5 V to 5.7 V  
1.05  
1.2  
0
5.7  
VIH  
High-level input voltage, ON  
V
5.7  
VIL  
Low-level input voltage, ON  
Input capacitor  
0.5  
V
CIN1,2  
TA  
1(1)  
µF  
°C  
(2)  
Operating free-air temperature  
–40  
105  
(1) See the Input Capacitor (Optional) section.  
(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may  
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the  
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package  
in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max)  
)
7.4 Thermal Information  
TPS22976  
DPU (WSON)  
14 PINS  
50.8  
THERMAL METRIC(1)  
UNIT  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
Junction-to-top characterization parameter  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
52.3  
18.4  
ψJT  
1.6  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
4
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Product Folder Links: TPS22976  
 
TPS22976  
www.ti.com  
SLVSDE7B NOVEMBER 2016REVISED SEPTEMBER 2017  
Thermal Information (continued)  
TPS22976  
THERMAL METRIC(1)  
DPU (WSON)  
14 PINS  
18.6  
UNIT  
ψJB  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
°C/W  
°C/W  
RθJC(bot)  
6.5  
7.5 Electrical Characteristics—VBIAS = 5 V  
Unless otherwise noted, the specifications in the following table applies where VBIAS = 5 V. Typical values are for TA = 25°C  
PARAMETER  
TEST CONDITIONS  
TA  
MIN TYP MAX UNIT  
POWER SUPPLIES AND CURRENTS  
VBIAS quiescent current (both  
channels)  
IOUT1 = IOUT2 = 0 mA,  
VIN1,2 = VON1,2 = 5 V  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +105°C  
37  
35  
48  
49  
µA  
IQ,VBIAS  
43  
IOUT1 = IOUT2 = 0 mA, VON2 = 0 V  
VIN1,2 = VON1 = 5 V  
VBIAS quiescent current (single  
channel)  
µA  
µA  
44  
ISD,VBIAS  
ISD,VIN  
ION  
VBIAS shutdown current  
VON1,2 = 0 V, VVOUT1,2 = 0 V  
VIN = 5 V  
1.37  
.005  
2.3  
5.5  
11.3  
1.4  
3.4  
0.5  
1.4  
0.3  
0.8  
0.1  
.002  
.002  
.001  
VIN = 3.3 V  
VON = 0 V,  
VOUT = 0 V  
VIN shutdown current (per channel)  
µA  
µA  
VIN = 1.8 V  
VIN = 0.6 V  
ON-pin input leakage current  
VON = 5.5 V  
RESISTANCE CHARACTERISTICS  
25°C  
–40°C to +85°C  
–40°C to +105°C  
25°C  
14  
14  
14  
14  
14  
14  
90  
18  
22  
23  
18  
22  
23  
18  
22  
23  
18  
22  
23  
18  
22  
23  
18  
22  
23  
VIN = 5 V  
VIN = 3.3 V  
VIN = 1.8 V  
VIN = 1.2 V  
VIN = 1.05 V  
VIN = 0.6 V  
–40°C to +85°C  
–40°C to +105°C  
25°C  
–40°C to +85°C  
–40°C to +105°C  
25°C  
RON  
On-state resistance (per channel) IOUT = –200 mA  
m  
–40°C to +85°C  
–40°C to +105°C  
25°C  
–40°C to +85°C  
–40°C to +105°C  
25°C  
–40°C to +85°C  
–40°C to +105°C  
25°C  
VON,HYS  
ON-pin hysteresis  
VIN = 5 V  
mV  
(1)  
RPD  
Output pulldown resistance  
Thermal shutdown  
VIN = VOUT = 5 V, VON = 0 V  
Junction temperature rising  
Junction temperature falling  
–40°C to +105°C  
230 280  
160  
TSD  
ºC  
ºC  
TSD,HYS  
Thermal-shutdown hysteresis  
20  
(1) Not present in TPS22976N  
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TPS22976  
SLVSDE7B NOVEMBER 2016REVISED SEPTEMBER 2017  
www.ti.com  
7.6 Electrical Characteristics—VBIAS = 2.5 V  
Unless otherwise noted, the specifications in the following table applies where VVBIAS = 2.5 V. Typical values are for TA =  
25°C  
PARAMETER  
TEST CONDITIONS  
TA  
MIN TYP MAX UNIT  
POWER SUPPLIES AND CURRENTS  
VBIAS quiescent current (both  
channels)  
IOUT1 = IOUT2 = 0 mA,  
VIN1,2 = VON1,2 = 2.5 V  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +105°C  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +85°C  
–40°C to +105°C  
–40°C to +105°C  
15  
14  
20  
20  
µA  
IQ,VBIAS  
19  
IOUT1 = IOUT2 = 0 mA, VON2 = 0 V  
VIN1,2 = VON1 = 2.5 V  
VBIAS quiescent current (single  
channel)  
µA  
µA  
19  
ISD,VBIAS  
ISD,VIN  
ION  
VBIAS shutdown current  
VON1,2 = 0 V, VVOUT1,2 = 0 V  
VIN = 2.5 V  
.58  
1.1  
0.8  
2.1  
0.5  
1.4  
0.3  
1
.005  
.002  
.002  
.001  
VIN = 1.8 V  
VON = 0 V,  
VOUT = 0 V  
VIN shutdown current (per channel)  
ON-pin input leakage current  
µA  
µA  
VIN = 1.05 V  
0.3  
0.8  
0.1  
VIN = 0.6 V  
VON = 5.5 V  
RESISTANCE CHARACTERISTICS  
25°C  
–40°C to +85°C  
–40°C to +105°C  
25°C  
18  
16  
16  
16  
16  
15  
70  
23  
28  
30  
23  
28  
29  
22  
27  
28  
21  
26  
28  
21  
25  
27  
20  
25  
26  
VIN = 2.5 V  
VIN = 1.8 V  
VIN = 1.5 V  
VIN = 1.2 V  
VIN = 1.05 V  
VIN = 0.6 V  
–40°C to +85°C  
–40°C to +105°C  
25°C  
–40°C to +85°C  
–40°C to +105°C  
25°C  
RON  
On-state resistance (per channel) IOUT = –200 mA  
mΩ  
–40°C to +85°C  
–40°C to +105°C  
25°C  
–40°C to +85°C  
–40°C to +105°C  
25°C  
–40°C to +85°C  
–40°C to +105°C  
25°C  
VON,HYS  
ON-pin hysteresis  
VIN = 2.5 V  
mV  
(1)  
RPD  
Output pulldown resistance  
Thermal shutdown  
VIN = VOUT = 2.5 V, VON = 0 V  
Junction temperature rising  
Junction temperature falling  
–40°C to +105°C  
250 330  
160  
TSD  
ºC  
ºC  
TSD,HYS  
Thermal-shutdown hysteresis  
20  
(1) Not present in TPS22976N  
6
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Product Folder Links: TPS22976  
TPS22976  
www.ti.com  
SLVSDE7B NOVEMBER 2016REVISED SEPTEMBER 2017  
7.7 Switching Characteristics  
PARAMETER  
TEST CONDITION  
MIN  
TYP  
MAX UNIT  
VIN = VON = VBIAS = 5 V, TA = 25ºC (unless otherwise noted)  
tON  
tOFF  
tR  
Turnon time  
Turnoff time  
VOUT rise time  
VOUT fall time  
ON delay time  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
1490  
3
1770  
2
µs  
tF  
tD  
620  
VIN = 0.6 V, VON = VBIAS = 5 V, TA = 25ºC (unless otherwise noted)  
tON  
tOFF  
tR  
Turnon time  
Turnoff time  
VOUT rise time  
VOUT fall time  
ON delay time  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
620  
3
285  
2
µs  
µs  
µs  
tF  
tD  
460  
VIN = 2.5 V, VON = 5 V, VBIAS = 2.5 V, TA = 25ºC (unless otherwise noted)  
tON  
tOFF  
tR  
Turnon time  
Turnoff time  
VOUT rise time  
VOUT fall time  
ON delay time  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
2350  
4
2275  
2
tF  
tD  
1210  
VIN = 0.6 V, VON = 5 V, VBIAS = 2.5 V, TA = 25ºC (unless otherwise noted)  
tON  
tOFF  
tR  
Turnon time  
Turnoff time  
VOUT rise time  
VOUT fall time  
ON delay time  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF  
1410  
5
700  
2
tF  
tD  
1030  
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SLVSDE7B NOVEMBER 2016REVISED SEPTEMBER 2017  
www.ti.com  
7.8 Typical DC Characteristics  
60  
60  
50  
40  
30  
20  
10  
-40èC  
25èC  
-40èC  
25èC  
85èC  
105èC  
85èC  
50  
105èC  
40  
30  
20  
10  
2.5  
3
3.5  
4
4.5  
5
5.5  
2.5  
3
3.5  
4
4.5  
5
5.5  
Bias Voltage (V)  
Bias Voltage (V)  
D001  
D002  
VIN1 = VIN2 = VBIAS  
VON1 = VON2 = 5 V  
VOUT = Open  
VIN1 = VBIAS  
VON1 = 5 V  
VOUT = Open  
Figure 1. VBIAS Quiescent Current vs Bias Voltage  
Both Channels  
Figure 2. VBIAS Quiescent Current vs Bias Voltage  
Single Channel  
0.4  
2.5  
-40èC  
25èC  
85èC  
105èC  
-40èC  
25èC  
85èC  
105èC  
0.35  
0.3  
2
1.5  
1
0.25  
0.2  
0.15  
0.1  
0.05  
0
0.5  
0
-0.05  
2.5  
3
3.5  
4
4.5  
5
5.5  
0.6  
1.1  
1.6  
2.1  
2.6  
3.1  
3.6  
4.1  
4.6  
5
Bias Voltage (V)  
Input Voltage (V)  
D003  
D004  
VIN1 = VIN2 = VBIAS  
VON1 = VON2 = 0 V  
VOUT = 0 V  
VBIAS = 5 V  
VON = 0 V  
VOUT = 0 V  
Note: –40°C and 25°C curves have similar values,  
Figure 3. VBIAS Shutdown Current vs Bias Voltage  
Both Channels  
therefore only one line is visible.  
Figure 4. Off-State VIN Current vs Input Voltage  
Single Channel  
25  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
VIN = 0.6 V  
VIN = 0.8 V  
VIN = 1.05 V  
VIN = 1.2 V  
VIN = 1.8 V  
VIN = 2.5 V  
VIN = 0.6 V  
VIN = 1.05 V  
VIN = 1.8 V  
VIN = 2.5 V  
VIN = 3.3 V  
VIN = 5 V  
20  
15  
10  
-40  
-20  
0
20  
40  
60  
80  
100  
-40  
-20  
0
20  
40  
60  
80  
100  
Ambient Temperature (èC)  
Ambient Temperature (èC)  
D005  
D0056  
VBIAS = 2.5 V  
IOUT = –200 mA  
VON = 5 V  
VBIAS = 5 V  
IOUT = –200 mA  
VON = 5 V  
Note: All RON curves have similar values,  
Figure 5. On-Resistance vs Ambient Temperature  
Single Channel  
therefore only one line is visible.  
Figure 6. On-Resistance vs Ambient Temperature  
Single Channel  
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Typical DC Characteristics (continued)  
25  
26  
24  
22  
20  
18  
16  
14  
12  
10  
-40èC  
25èC  
85èC  
105èC  
-40èC  
25èC  
85èC  
105èC  
20  
15  
10  
0.6  
1
1.4  
1.8  
2.2  
2.5  
0.6  
1.1  
1.6  
2.1  
2.6  
3.1  
3.6  
4.1  
4.6  
5
Input Voltage (V)  
Input Voltage (V)  
D007  
D008  
VBIAS = 2.5 V  
IOUT = –200 mA  
VON = 5 V  
VBIAS = 5 V  
IOUT = –200 mA  
VON = 5 V  
Figure 7. On-Resistance vs Input Voltage  
Figure 8. On-Resistance vs Input Voltage  
Single Channel - Across Ambient Temperatures  
Single Channel - Across Ambient Temperatures  
260  
255  
250  
245  
240  
235  
230  
225  
220  
215  
18  
17  
16  
15  
14  
13  
12  
-40èC  
25èC  
85èC  
105èC  
VBias = 2.5 V  
VBias = 3.3 V  
VBias = 5 V  
VBias = 5.7 V  
0.6 1.1 1.6 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6  
Input Voltage (V)  
2.5  
3
3.5  
4
4.5  
5
5.5  
Bias Voltage (V)  
D011  
D012  
VIN = 2.5 V  
VON = 0 V  
TA = 25°C  
Note: VBIAS = 5 V and 5.7 V curves have similar  
Figure 10. Pulldown Resistance vs Bias Voltage  
Single Channel  
values, therefore only one line is visible.  
Figure 9. On-Resistance vs Input Voltage  
Single Channel - Across VBIAS  
1
0.95  
0.9  
0.9  
-40èC  
25èC  
85èC  
105èC  
-40èC  
25èC  
85èC  
105èC  
0.85  
0.8  
0.85  
0.8  
0.75  
0.7  
0.75  
0.65  
0.7  
0.6  
2.5  
3
3.5  
4
4.5  
5
5.5  
2.5  
3
3.5  
4
4.5  
5
5.5  
Bias Voltage (V)  
Bias Voltage (V)  
D013  
D014  
VIN = VBIAS  
VIN = VBIAS  
Figure 11. High-Level Input Voltage vs Bias Voltage  
Figure 12. Low-Level Input Voltage vs Bias Voltage  
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Typical DC Characteristics (continued)  
140  
120  
100  
80  
60  
40  
20  
0
-40èC  
25èC  
85èC  
105èC  
2.5  
3
3.5  
4
4.5  
5
5.5  
Bias Voltage (V)  
D015  
VIN = VBIAS  
Figure 13. Voltage Input Hysteresis vs Bias Voltage  
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7.9 Typical AC Characteristics  
TA = 25°C, CT = 1000 pF, CIN = 1 µF, CL = 0.1 µF, RL = 10 , VON = 5 V  
800  
700  
600  
500  
400  
300  
200  
100  
0
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
-40èC  
25èC  
85èC  
105èC  
-40èC  
25èC  
85èC  
105èC  
0.6 0.8  
1
1.2 1.4 1.6 1.8  
Input Voltage (V)  
2
2.2 2.4  
0.6  
1.1  
1.6  
2.1  
2.6  
3.1  
3.6  
4.1  
4.6  
5
Input Voltage (V)  
D016  
D017  
VBIAS = 2.5 V  
VBIAS = 5 V  
Figure 14. Delay Time vs Input Voltage  
Figure 15. Delay Time vs Input Voltage  
3
2.5  
2
3
2.5  
2
1.5  
1
1.5  
1
-40èC  
-40èC  
25èC  
85èC  
105èC  
25èC  
85èC  
105èC  
0.5  
0.5  
0
0
0.6  
1
1.4  
1.8  
2.2  
2.5  
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
Input Voltage (V)  
Input Voltage (V)  
D018  
D019  
VBIAS = 2.5 V  
VBIAS = 5 V  
Figure 16. Fall Time vs Input Voltage  
Figure 17. Fall Time vs Input Voltage  
5
4
3
2
1
0
5
4.5  
4
-40èC  
25èC  
85èC  
105èC  
3.5  
3
2.5  
2
1.5  
1
-40èC  
25èC  
85èC  
105èC  
0.5  
0
0.6 0.8  
1
1.2 1.4 1.6 1.8  
Input Voltage (V)  
2
2.2 2.4  
0.6  
1.1  
1.6  
2.1  
2.6  
3.1  
3.6  
4.1  
4.6  
5
Input Voltage (V)  
D020  
D021  
VBIAS = 2.5 V  
VBIAS = 5 V  
Figure 18. Turnoff Time vs Input Voltage  
Figure 19. Turnoff Time vs Input Voltage  
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Typical AC Characteristics (continued)  
TA = 25°C, CT = 1000 pF, CIN = 1 µF, CL = 0.1 µF, RL = 10 , VON = 5 V  
3000  
2500  
2000  
1500  
1000  
500  
1800  
-40èC  
25èC  
85èC  
105èC  
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
-40èC  
25èC  
85èC  
105èC  
0
0.6 0.8  
1
1.2 1.4 1.6 1.8  
Input Voltage (V)  
2
2.2 2.4  
0.6  
1
1.4 1.8 2.2 2.6  
3
3.4 3.8 4.2 4.6  
5
Input Voltage (V)  
D022  
D023  
VBIAS = 2.5 V  
VBIAS = 5 V  
Figure 20. Turnon Time vs Input Voltage  
Figure 21. Turnon Time vs Input Voltage  
3000  
2500  
2000  
1500  
1000  
500  
2500  
2000  
1500  
1000  
500  
-40èC  
25èC  
85èC  
105èC  
-40èC  
25èC  
85èC  
105èC  
0
0
0.6 0.8  
1
1.2 1.4 1.6 1.8  
Input Voltage (V)  
2
2.2 2.4  
0.6  
1
1.4 1.8 2.2 2.6  
3
3.4 3.8 4.2 4.6  
5
Input Voltage (V)  
D024  
D025  
VBIAS = 5 V  
VBIAS = 2.5 V  
Figure 22. Rise Time vs Input Voltage  
Figure 23. Rise Time vs Input Voltage  
VIN = 0.6 V  
VBIAS = 2.5 V  
VIN = 0.6 V  
VBIAS = 5 V  
Figure 24. Turnon Response Time  
Figure 25. Turnon Response Time  
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Typical AC Characteristics (continued)  
TA = 25°C, CT = 1000 pF, CIN = 1 µF, CL = 0.1 µF, RL = 10 , VON = 5 V  
VIN = 2.5 V  
VBIAS = 2.5 V  
VIN = 5 V  
VBIAS = 5 V  
Figure 26. Turnon Response Time  
Figure 27. Turnon Response Time  
VIN = 0.6 V  
VBIAS = 2.5 V  
VIN = 0.6 V  
VBIAS = 5 V  
Figure 28. Turnoff Response Time  
Figure 29. Turnoff Response Time  
VIN = 2.5 V  
VBIAS = 2.5 V  
VIN = 5 V  
VBIAS = 5 V  
Figure 30. Turnoff Response Time  
Figure 31. Turnoff Response Time  
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8 Parameter Measurement Information  
VIN  
VOUT  
CT1, 2  
CIN = 1µF  
VBIAS  
CL  
+
_
RL  
ON  
+
_
ON  
GND  
TPS22976  
GND  
GND  
OFF  
Single Channel Shown for Clarity  
Figure 32. Test Circuit  
VON  
50%  
50%  
tf  
tOFF  
tr  
tON  
90%  
90%  
VOUT  
VOUT  
50%  
10%  
50%  
10%  
10%  
tD  
Figure 33. tON and tOFF Waveforms  
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9 Detailed Description  
9.1 Overview  
The TPS22976 is a 5.7-V, dual-channel, 14-m(typical) RON load switch in a 14-pin WSON package. Each  
channel can support a maximum continuous current of 6 A and is controlled by an on and off GPIO-compatible  
input. To reduce the voltage drop in high current rails, the device implements N-channel MOSFETs. Note that the  
ON pins must be connected and cannot be left floating. The device has a configurable slew rate for applications  
that require specific rise-time, which controls the inrush current. By controlling the inrush current, power supply  
sag can be reduced during turnon. Furthermore, the slew rate is proportional to the capacitor on the CT pin. See  
the Adjustable Rise Time section to determine the correct CT value for a desired rise time.  
The internal circuitry is powered by the VBIAS pin, which supports voltages from 2.5 V to 5.7 V. This circuitry  
includes the charge pump, QOD (optional), and control logic. When a voltage is applied to VBIAS, and the ON1,2  
pins transition to a low state, the QOD functionality is activated. This connects VOUT1 and VOUT2 to ground  
through the on-chip resistor. The typical pulldown resistance (RPD) is 230 .  
During the off state, the device prevents downstream circuits from pulling high standby current from the supply.  
The integrated control logic, driver, power supply, and output discharge FET eliminates the need for any external  
components, reducing solution size and bill of materials (BOM) count.  
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9.2 Functional Block Diagram  
VIN1  
ON1  
CT1  
Control Logic  
VOUT1  
Not Present in  
TPS22976N  
GND  
VBIAS  
Charge Pump  
Not Present in  
TPS22976N  
VOUT2  
CT2  
ON2  
VIN2  
Control Logic  
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Figure 34. TPS22976 Functional Block Diagram  
9.3 Feature Description  
9.3.1 ON and OFF Control  
The ON pins control the state of the switch. Asserting ON high enables the switch. ON is active high with a low  
threshold, making it capable of interfacing with low-voltage signals. The ON pin is compatible with standard GPIO  
logic threshold. It can be used with any microcontroller with 1.2 V or higher GPIO voltage. This pin cannot be left  
floating and must be tied either high or low for proper functionality.  
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Feature Description (continued)  
9.3.2 Input Capacitor (Optional)  
To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a  
discharged load capacitor, a capacitor needs to be placed between VIN and GND. A 1-µF ceramic capacitor, CIN,  
placed close to the pins is usually sufficient. Higher values of CIN can be used to further reduce the voltage drop  
during high-current application. When switching heavy loads, it is recommended to have an input capacitor about  
10 times higher than the output capacitor to avoid excessive voltage drop.  
9.3.3 Output Capacitor (Optional)  
Due to the integrated body diode in the NMOS switch, a CIN greater than CL is highly recommended. A CL  
greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current  
flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN  
dip caused by inrush currents during startup, however a 10 to 1 ratio for capacitance is not required for proper  
functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) could cause slightly more VIN dip upon  
turnon due to inrush currents. This can be mitigated by increasing the capacitance on the CT pin for a longer rise  
time. (See the Adjustable Rise Time section).  
9.3.4 Quick Output Discharge (QOD) (Not Present in TPS22976N)  
The TPS22976 includes a QOD feature. When the switch is disabled, an internal discharge resistance is  
connected between VOUT and GND to remove the remaining charge from the output. This resistance prevents  
the output from floating while the switch is disabled. For best results, it is recommended that the device gets  
disabled before VBIAS falls below the minimum recommended voltage.  
9.3.5 Thermal Shutdown  
Thermal Shutdown protects the part from internally or externally generated excessive temperatures. When the  
device temperature exceeds TSD (typical 160°C), the switch is turned off. The switch automatically turns on again  
if the temperature of the die drops 20 degrees below the TSD threshold.  
9.4 Device Functional Modes  
Table 1 lists the TPS22976 functions.  
Table 1. TPS22976 Functions Table  
ON  
L
VIN to VOUT  
VOUT  
GND  
VIN  
Off  
On  
H
Table 2 lists the TPS22976N functions.  
Table 2. TPS22976N Functions Table  
ON  
VIN to VOUT  
VOUT  
L
Off  
On  
Floating  
VIN  
H
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10 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
10.1 Application Information  
This section highlights some of the design considerations for implementing the device in various applications. A  
PSPICE model for this device is also available on the product page for additional information.  
10.1.1 Parallel Configuration  
To increase current capabilities and to lower RON, both channels can be placed in parallel as seen in Figure 35.  
With this configuration, the CT1 and CT2 pins can be tied together to use one capacitor, CT.  
See the TPS22966 Dual-Channel Load Switch in Parallel Configuration application report and Parallel Load  
Switches for Higher Output Current & Reduced ON-Resistance Design Guide for more information.  
VBIAS  
VOUT1  
CT1  
VIN1  
ON1  
System  
Module  
Power  
Source  
TPS22976  
VOUT2  
CT2  
VIN2  
ON2  
µC GPIO  
GND  
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Figure 35. Parallel Configuration  
10.1.2 Standby Power Reduction  
Battery powered end equipments often have strict power budgets, in which there is a need to reduce current  
consumption. The TPS22976 significantly reduces system current consumption by disabling the supply voltage to  
subsystems in standby states. Alternatively, the TPS22976 reduces the leakage current overhead of the modules  
in standby mode as achieved in Figure 36. Note that standby power reduction can be achieved on either  
channel, as well as dual-channel operation.  
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Application Information (continued)  
Always ON  
Module  
VBIAS  
VIN1  
VOUT1  
Power  
Source  
TPS22976  
GND  
ON1  
CT1  
Standby  
Module  
µC GPIO  
Single channel shown for clarity.  
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Figure 36. Standby Power Reduction  
10.1.3 Power Supply Sequencing without GPIO Input  
Sequential startup of several subsystems is often burdensome and adds complexity for several end equipments.  
The TPS22976 provides a power sequencing solution that reduces the overall system complexity, as seen in  
Figure 37.  
µC GPIO  
VBIAS  
VOUT1  
CT1  
VIN1  
ON1  
Module 1  
Power  
Source  
TPS22976  
VOUT2  
CT2  
VIN2  
ON2  
Power  
Source  
Module 2  
GND  
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Figure 37. Power Sequencing without a GPIO Input  
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Application Information (continued)  
10.1.4 Reverse Current Blocking  
Reverse current blocking is often desired in specific applications, as it prevents current from flowing from the  
output to the input of the load switch when the device is disabled. With the configuration illustrated in Figure 38,  
the TPS22976 can be converted into a single-channel switch with reverse current blocking. VIN1 or VIN2 can be  
used as the input and VIN2 or VIN1 as the output.  
VBIAS  
VOUT1  
CT1  
VIN1  
ON1  
Power  
Source  
TPS22976  
VOUT2  
CT2  
VIN2  
ON2  
System  
Module  
GND  
µC GPIO  
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Figure 38. Reverse Current Blocking  
10.2 Typical Application  
This application demonstrates how the TPS22976 can be used to limit the inrush current when powering on  
downstream modules.  
VIN1  
ON1  
VOUT1  
CT1  
ON  
OFF  
Dual  
CL  
RL  
CIN  
Power  
Supply  
CT2  
VBIAS  
VIN2  
GND  
or  
VOUT2  
Dual  
DC-DC  
ON  
OFF  
Converter  
ON2  
CL  
RL  
CIN  
GND  
TPS22976  
GND  
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Figure 39. Typical Application Circuit  
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Typical Application (continued)  
10.2.1 Design Requirements  
Table 3 shows the TPS22976 design parameters.  
Table 3. Design Parameters  
DESIGN PARAMETER  
Input voltage  
VALUE  
3.3 V  
Bias voltage  
5 V  
Load capacitance (CL)  
Maximum acceptable inrush current  
22 µF  
400 mA  
10.2.2 Detailed Design Procedure  
10.2.2.1 Inrush Current  
When the switch is enabled, the output capacitors must be charged up from 0 V to the set value (3.3 V in this  
example). This charge arrives in the form of inrush current. Inrush current can be calculated using Equation 1.  
Inrush Current = C × dV/dt  
where  
C is the output capacitance  
dV is the output voltage  
dt is the rise time  
(1)  
The TPS22976 offers adjustable rise time for VOUT. This feature allows the user to control the inrush current  
during turnon. The appropriate rise time can be calculated using Table 3 and the inrush current equation. See  
Equation 2 and Equation 3.  
400 mA = 22 μF × 3.3 V/dt  
dt = 181.5 μs  
(2)  
(3)  
To ensure an inrush current of less than 400 mA, choose a CT value that yields a rise time of more than 181.5  
μs. See the oscilloscope captures in the Application Curves section for an example of how the CT capacitor can  
be used to reduce inrush current.  
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10.2.2.2 Adjustable Rise Time  
A capacitor to GND on the CT pins sets the slew rate for each channel. To ensure desired performance, a  
capacitor with a minimum voltage rating of 25 V must be used on either CT pins. An approximate formula for the  
relationship between CT and slew rate is shown in Equation 4.  
Equation 4 accounts for 10% to 90% measurement on VOUT and does not apply for CT < 100 pF. Use Table 4 to  
determine rise times for when CT = 0 pF):  
SR = 0.42 × CT + 66  
where  
SR is the slew rate (in µs/V)  
CT is the capacitance value on the CT pin (in pF)  
The units for the constant 66 is in µs/V.  
(4)  
Rise time can be calculated by multiplying the input voltage by the slew rate. Table 4 shows rise time values  
measured on a typical device. Rise times shown below are only valid for the power-up sequence where VIN and  
VBIAS are already in steady state condition, and the ON pin is asserted high.  
Table 4. Rise Time Values  
RISE TIME (µs) 10% - 90%, CL = 0.1 µF, CIN = 1 µF, RL = 10 Ω(1)  
CT (pF)  
5 V  
149  
3.3 V  
112  
1.8 V  
77  
1.5 V  
70  
1.2 V  
60  
1.05 V  
56  
0.6 V  
42  
0
220  
548  
388  
236  
206  
173  
154  
103  
169  
286  
627  
1249  
2526  
470  
968  
673  
401  
342  
289  
256  
1000  
2200  
4700  
10000  
1768  
3916  
8040  
16520  
1220  
2678  
5477  
11150  
711  
608  
505  
445  
1554  
3179  
6410  
1332  
2691  
5401  
1097  
2240  
4430  
949  
1964  
3933  
(1) TYPICAL VALUES at 25°C, VBIAS = 5 V, 25 V X7R 10% CERAMIC CAP  
10.2.3 Application Curves  
VBIAS = 5 V ; VIN = 3.3 V ; CL = 22 μF  
Figure 40. Inrush Current With CT = 0 pF  
Figure 41. Inrush Current With CT = 220 pF  
22  
Submit Documentation Feedback  
Copyright © 2016–2017, Texas Instruments Incorporated  
Product Folder Links: TPS22976  
 
 
TPS22976  
www.ti.com  
SLVSDE7B NOVEMBER 2016REVISED SEPTEMBER 2017  
11 Power Supply Recommendations  
The device is designed to operate from a VBIAS range of 2.5 V to 5.7 V and a VIN range of 0.6 V to VBIAS  
.
12 Layout  
12.1 Layout Guidelines  
For best performance, all traces must be as short as possible. To be most effective, the input and output  
capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have  
on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects  
along with minimizing the case to ambient thermal impedance.  
12.2 Layout Example  
Notice the thermal vias located under the exposed thermal pad of the device. This allows for thermal diffusion  
away from the device.  
VOUT1 capacitor  
VIN1 capacitor  
CT1 capacitor  
Thermal  
relief vias  
VIN2 capacitor  
CT2 capacitor  
VOUT2 capacitor  
Figure 42. PCB Layout Example  
12.3 Power Dissipation  
The maximum IC junction temperature must be restricted to 125°C under normal operating conditions. To  
calculate the maximum allowable power dissipation, PD(max) for a given output current and ambient temperature,  
use Equation 5.  
TJ(max) - TA  
=
P
D(max)  
θJA  
where  
PD(max) is the maximum allowable power dissipation  
TJ(max) is the maximum allowable junction temperature (125°C for the TPS22976)  
TA is the ambient temperature of the device  
θJA is the junction to air thermal impedance. See the Thermal Information section. This parameter is highly  
dependent upon board layout.  
(5)  
23  
Copyright © 2016–2017, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: TPS22976  
 
TPS22976  
SLVSDE7B NOVEMBER 2016REVISED SEPTEMBER 2017  
www.ti.com  
13 Device and Documentation Support  
13.1 Device Support  
13.1.1 Developmental Support  
For the TPS22976N PSpice Transient Model, see SLVMBV5.  
For the TPS22976 PSpice Transient Model, see SLVMBV6.  
13.2 Documentation Support  
13.2.1 Related Documentation  
For related documentation see the following:  
TPS22976 Evaluation Module User's Guide  
13.3 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper  
right corner, click on Alert me to register and receive a weekly digest of any product information that has  
changed. For change details, review the revision history included in any revised document.  
13.4 Community Resources  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective  
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of  
Use.  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
13.5 Trademarks  
E2E is a trademark of Texas Instruments.  
Ultrabook is a trademark of Intel.  
All other trademarks are the property of their respective owners.  
13.6 Electrostatic Discharge Caution  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
13.7 Glossary  
SLYZ022 TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
14 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most-  
current data available for the designated devices. This data is subject to change without notice and without  
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.  
24  
Submit Documentation Feedback  
Copyright © 2016–2017, Texas Instruments Incorporated  
Product Folder Links: TPS22976  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Sep-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
3000  
3000  
250  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TPS22976ADPUR  
TPS22976DPUR  
TPS22976DPUT  
TPS22976NDPUR  
TPS22976NDPUT  
PREVIEW  
WSON  
WSON  
WSON  
WSON  
WSON  
DPU  
14  
14  
14  
14  
14  
Green (RoHS  
& no Sb/Br)  
NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 105  
-40 to 105  
-40 to 105  
-40 to 105  
-40 to 105  
22976A  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DPU  
Green (RoHS  
& no Sb/Br)  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
22976  
DPU  
Green (RoHS  
& no Sb/Br)  
22976  
DPU  
3000  
250  
Green (RoHS  
& no Sb/Br)  
22976N  
22976N  
DPU  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Sep-2020  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
22-Aug-2020  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS22976DPUR  
TPS22976DPUT  
TPS22976NDPUR  
TPS22976NDPUT  
TPS22976NDPUT  
WSON  
WSON  
WSON  
WSON  
WSON  
DPU  
DPU  
DPU  
DPU  
DPU  
14  
14  
14  
14  
14  
3000  
250  
180.0  
180.0  
180.0  
180.0  
180.0  
8.4  
8.4  
8.4  
8.4  
8.4  
2.25  
2.25  
2.25  
2.25  
2.25  
3.25  
3.25  
3.25  
3.25  
3.25  
1.05  
1.05  
1.05  
1.05  
1.05  
4.0  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
Q1  
Q1  
Q1  
Q1  
Q1  
3000  
250  
250  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
22-Aug-2020  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS22976DPUR  
TPS22976DPUT  
TPS22976NDPUR  
TPS22976NDPUT  
TPS22976NDPUT  
WSON  
WSON  
WSON  
WSON  
WSON  
DPU  
DPU  
DPU  
DPU  
DPU  
14  
14  
14  
14  
14  
3000  
250  
210.0  
210.0  
210.0  
210.0  
210.0  
185.0  
185.0  
185.0  
185.0  
185.0  
35.0  
35.0  
35.0  
35.0  
35.0  
3000  
250  
250  
Pack Materials-Page 2  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you  
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on  
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2020, Texas Instruments Incorporated  

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