TPS2306_10 [TI]
DUAL SEQUENCING HOT SWAP POWER MANAGER;
| 型号： | TPS2306_10 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL SEQUENCING HOT SWAP POWER MANAGER |
| 文件： | 总28页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLVS368 – APRIL 2001
DW PACKAGE
TOP VIEW
D
Wide Input Operating Range (2.75 V to
13.6 V)
D
Controls Ramp-Up Sequence and Slope,
and Ramp-Down Sequence
IMAX1
UP1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC/CS1
DOWN1
GATE1
FAULT
CPUMP
GATE2
DOWN2
CS2
D
Controls Inrush Current
ENBL
IREF
CT
D
Precise Linear Current Amplifier for High
Efficiency and Low Voltage Drop
D
D
D
Programmable Overcurrent Threshold
GND
UP2
Programmable Soft-Start Capability and
Fault Timer
IMAX2
Internal Charge Pump Drives Low-Cost
External NMOS Devices
D
D
D
D
Cascadable for Three or More Supplies
Fault Indicator Output
Direct-drive of Bus Switch
Shutdown Control with Low-Current Sleep
Mode (40 µA)
D
Input Undervoltage Lockout
16-pin SOIC package
D
The TPS2306 Hot Swap Power Manager (HSPM) IC provides hot-swap control, fault handling and power supply
sequencing of two positive voltage supplies. The TPS2306 operates over a wide supply range allowing single
part inventory for a variety of output voltages.
During the transient period of a live insertion or hot-swap event, the TPS2306 actively limits the inrush current
to the plug-in module. An on-chip linear current amplifier (LCA) provides closed-loop control of the current
sourced to the load circuitry on the module. Subsequently, during normal steady-state loading conditions and
in conjunction with an internal high-voltage charge pump, the LCA provides direct gate drive to fully enhance
the external NMOS pass devices. In addition, the < 4-mV input offset voltage of the LCA allows for the use of
low-value sense resistors. Together, these features minimize the insertion loss across the hot-swap interface.
Control inputs allow the designer to program the maximum current level and the inrush current profile (slew rate)
during start-up. Direct programming of the fault time-out also allows the user to establish how long the HSPM
can operate in the current control mode prior to turning off the pass elements. The high degree of user
programmability allows the TPS2306 to be configured for the specific load and bulk capacitance charging
requirements of the target system.
A second level of power bus protection is provided in the form of fast overcurrent comparators monitoring the
load current levels of the two channels. Should a short-circuit event’s edge rate ever exceed the slew rate of
the LCA, the overcurrent comparator immediately latches off the external NMOS devices, overriding the timeout
period. The overcurrent threshold is also user-programmable.
Supply sequencing control is provided via four comparator inputs to independently control the ramp-up and
ramp-down of each supply output (see Figure 1). The TPS2306 also provides a TTL and CMOS compatible
enable input for external control of the supply outputs, and a low-power sleep mode. Also, the open-drain FAULT
output provides single-line fault reporting to the system host for the two monitored supplies.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
QuickSwitch is a registered trademark of Integrated Device Technology, Inc.
Widebust is a trademark of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLVS368 – APRIL 2001
VOUT1 Ramping UP First and DOWN Last
VOUT1 Ramping UP First and DOWN First
VOUT1
VOUT2
t – Time
t – Time
VOUT2 Ramping UP First and DOWN First
VOUT1
VOUT2 Ramping UP First and DOWN Last
VOUT1
VOUT2
VOUT2
t – Time
t – Time
Figure 1. Example Voltage Ramp-up/Ramp-down Sequences
Ĕ
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: VCC/CS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Output voltage range: CPUMP, GATE1, GATE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V
All others . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VCC+0.3 V
Output current range: I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to –1 mA
REF
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Storage temperature range T
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
4.0
MAX
13.6
13.6
–35
UNIT
V
Supply voltage (VCC/CS1)
Input voltage (CS2)
2.75
V
Output current (IREF)
–300
µA
2
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SLVS368 – APRIL 2001
typical application
VCC
VOUT1
UP2
R
SNS1
VIN1
R1A
R1B
VCC/CS1
GATE1
R
IMAX1
VCC
VCC
VPP
LMD1
LMD2
OC1
FAULT
+
FAULT
TIMER
TIME
S
R
Q
Q
LCA
R
OC2
SD
PU
IMAX1
R1 OVLD
SD
ENBL
CT
RAMPOFF
µ
10
A
OC1
VPP
VCC
UVLO
AND
UVLO
CPUMP
CHARGE
PUMP
VS
I
C
T
REF
GND
CS2
UVLO
1.5 V
0.5 V
RAMPOFF
GND
+
REG/REF
GEN
I
REF
IREF
UP1
DOWN1
UP2
DN1
DOWN1
UP1
1.5 V
0.5 V
VPP
R
REF
LMD2
OC2
UP2
IMAX2
CHANNEL 2 LCA, OVLD AND RAMP CONTROL
DOWN2
R
IMAX2
R
VOUT2
DOWN1
CS2
GATE2
R2A
SNS2
VIN2
R2B
UDG–00165
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SLVS368 – APRIL 2001
functional block diagram
VCC/CS1
GATE1 DOWN1
14
15
LMD1
GLD1
UP1
2
ENBL
3
16
VPP
MODE/
STATUS
ENABLE
+1.5V
RAMPOFF
+
LCA
OFF
IMAX1
1
SLP
OFF
SD
GLD1
GLD2
13 FAULT
10 µA
R1
SD
UVLO
OFF
UVLO
UVLO
OC1
OC2
TIMEOUT
RAMPOFF
S
R
Q
Q
VB
OC1
VCC1
OVLD
COMP
DN1
LMD1
LMD2
+0.5V
TIMEOUT
RAMPOFF
FAULT
TIMER
I1
UP1
5
CT
+1.5V
LMD2
GLD2
ENABLE
OFF
GND
6
8
VPP
MODE/
STATUS
CPOK
IMAX2
VCC
UVLO
LCA
+
OFF
UV1
CS2
SLP
10 µA
R2
UV2
SLP
SD
UVLO
OFF
VS
CPOK
CHARGE
PUMP
VB
SLP
VPP
OC2
VCC1
OVLD
COMP
+0.5V
DN2
VCC1
+1.5V
+0.5V
+
REG/REF
GEN
I1 I2
+1.5V
RAMPOFF
I
REF
I2
UP2
4
IREF
OFF
9
11
GATE2
7
10
12
UDG–01004
CS2
UP2
DOWN2 CPUMP
4
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SLVS368 – APRIL 2001
electrical characteristics over recommended operating junction temperature range, V
=
I(VCC/CS1)
12 V, V
= 5 V, –40°C < T < 85°C, all voltages are with respect to GND; T = T . (unless otherwise
I(CS2)
A A J
noted) Currents are positive into and negative out of the specified terminal.
input supply
PARAMETER
TEST CONDITIONS
VCC/CS1 = 4 V, CS2 = 2.75V
MIN
TYP
1
MAX UNIT
I
I
I
Supply current
Supply current
2
CC1
CC2
SLP
mA
4
VCC/CS1 = 13.6 V, CS2 = 13.6 V
ENBL = 0
2
Shutdown current
75
µA
40
undervoltage lockout
PARAMETER
TEST CONDITIONS
CS2 = 3 V
MIN
2.00
1.80
0.05
2.00
1.80
0.05
TYP
2.45
2.25
0.18
2.45
2.25
0.18
MAX UNIT
2.90
VCC/CS1 minimum voltage to start
VCC/CS1 minimum voltage after start
VCC/CS1 hysteresis
CS2 = 3 V
2.60
CS2 = 3 V
0.24
V
CS2 minimum voltage to start
CS2 minimum voltage after start
CS2 hysteresis
VCC/CS1 = 4 V
VCC/CS1 = 4 V
VCC/CS1 = 4 V
2.75
2.60
0.24
reference current
PARAMETER
TEST CONDITIONS
MIN
TYP
1.5
MAX UNIT
V
O
Output voltage
I
= 100 µA
1.4
1.6
V
REF
I
O
Maximum output current
V
REF
= 1.35 V
–300
–150
µA
linear current amplifier 1, linear current amplifier 2
PARAMETER
TEST CONDITIONS
MIN
–4
TYP
MAX UNIT
T
A
= 25_C
4
V
IO
Input offset voltage
Ouput peak current
mV
–40_C ≤ T ≤ 85_C,See Note 1
–5.5
–25
2
5.5
A
I
–5 mA
PK
Ramp-down mode
LCA pulldown
10
25
5
µA
mA
mA
V
I
Output current sink
SINK
0.2
I
Output current sink
Output low voltage
Output high voltage
Overcurrent fault shutdown
100
FAULT
V
OL
Fault shutdown I
SINK
= 10 mA
0.5
V
OH
I
= –4 µA
Note 2
V
SOURCE
overcurrent amplifier 1, overcurrent amplifier 2
PARAMETER
TEST CONDITIONS
(VCC/CS1 – IMAX1), (CS2 – IMAX2)
MIN
TYP
MAX
UNIT
V
IO
Input offset voltage
Internal threshold resistor
Response time
Note 3
Note 4
mV
R
R
INT1,
1.7
2.5
3.3
kΩ
µs
2
INT
t
R
0.5
7
FAULT timer
PARAMETER
TEST CONDITIONS
MIN
–65
TYP
–50
MAX
–35
UNIT
µA
I
CT charge current
CT fault threshold
V
= 1 V
CT
O(CT)
V
TH
1.35
1.50
1.65
V
NOTES: 1. Ensured by design. Not production tested.
2. – 1
V
CPUMP
3. –1.5 × I
4. –0.6 × I
× 2500
× 2500
REF
REF
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SLVS368 – APRIL 2001
ENBL input
PARAMETER
TEST CONDITIONS
MIN
TYP
TYP
MAX
UNIT
V
V
Input low voltage
0.8
V
V
IL
Input high voltage
2
IH
FAULT output
PARAMETER
TEST CONDITIONS
MIN
MAX
1
UNIT
µA
I
Output leakage current
Ouput low voltage
ENBL = 0 V,
ENBL = 5 V,
ENBL = 5 V,
V
= 5 V
LKG
PULLUP
V
OL
I
= 0.1 mA
= 0.5 V
OL
0.5
V
SINK
I
Output current sink
V
1
mA
SINK
charge pump
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
O
Maximum output voltage
Maximum current source
I
= –25 µA
17
25
CPUMP
I
VCC= 5 V
VCC= 5 V,
–50
µA
SOURCE
(
)
17 V * 16 V
Z
O
Charge pump source impedance
50
kΩ
( (
)
(
))
I CP + 17 V * I CP + 16 V
ramp-up comparator 1 and ramp-up comparator 2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
UP
Trip threshold
1.35
1.5
1.65
V
ramp-down comparator 1 and ramp-down comparator 2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
DN
Trip threshold
0.35
0.5
0.65
V
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
CPUMP
CS2
NO.
12
9
O
I
Charge pump output
Channel 2 current sense input
Fault timer capacitor pin
CT
5
I/O
I
DOWN1
DOWN2
ENBL
15
10
3
Ramp-down comparator input for channel 1
Ramp-down comparator input for channel 2
Device enable input
I
I
FAULT
GATE1
GATE2
GND
13
14
11
6
O
O
O
–
I
Active high fault indicator output
Pass FET gate drive (output of LCA1)
Pass FET gate drive (output of LCA2)
Common ground connection for the IC
IMAX1
IMAX2
IREF
1
Maximum sourcing current programming input for channel 1
Maximum sourcing current programming input for channel 2
Reference current programming pin
8
I
4
O
I
UP1
2
Ramp-up comparator input for channel 1
UP2
7
I
Ramp-up comparator input for channel 2
VCC/CS1
16
I
Device supply input and channel 1 current sense input
NOTE: Connecting a scope probe or other metering device to the CT pin alters the fault time.
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SLVS368 – APRIL 2001
detailed pin description
CPUMP — Charge pump output. A capacitor with a value between 0.01 µF and 0.1 µF must be connected
between this pin and ground. The capacitor provides charge storage for driving the gate of the external NMOS
device.
CS2 — Channel 2 current sense input. This pin is used as the current sense for the LCA on the second supply
controller. This pin must be connected to the sense resistor on the input supply having the lower potential.
CT — Fault timer capacitor pin. A capacitor connected from this pin to ground is used to establish the amount
of time that the TPS2306 is allowed to operate in the constant-current mode.
DOWN1, DOWN2 — Ramp-down comparator inputs for Channels 1 and 2, respectively. These inputs are used
to sequence the turn-off of the two supply outputs. Each output starts its turn-off when the voltage on the
corresponding DOWNx input falls below the nominal 0.5 V threshold.
ENBL — Device enable input. Pulling this pin below 0.8 V turns off both external FETs, and puts the IC in
low-current sleep mode. Driving this pin above 2.0 V enables the TPS2306.
FAULT — Active high fault indicator output. This pin becomes a high impedance when a latched fault occurs.
The indication can be the result of a fault time-out or overcurrent condition on either supply. This output can be
used to generate a visual indication of a plug-in card’s status, or as an enable signal for a bus isolation switch.
GATE1, GATE2 — Outputs of the linear current amplifiers. These pins are used to drive the gates of the external
N-channel FETs which act as switches to either turn ON or OFF input supply current to the two loads.
GND — Common ground connection for the IC.
IMAX1, IMAX2 — Programming input to establish the maximum sourcing current level for each of the supplies.
A resistor must be connected between each input supply rail and the corresponding IMAXx input pin of the
device. An internal current sink at each of these pins develops a voltage across the programming resistor,
providing the reference level or threshold at the inverting input of each LCA.
IREF — Reference current programming pin. An external resistor must be connected between this pin and
device ground. Current sourced from this pin determines the precision current sink value at the two IMAXx pins,
thus establishing the constant-current and overcurrent thresholds for the application circuit.
UP1, UP2 — Ramp-up comparator inputs for Channels 1 and 2, respectively. These inputs are used to
sequence the turn-on of the two supply outputs. Each output begins to ramp up when the voltage on the
corresponding UPx input exceeds the nominal +1.5 V threshold.
VCC/CS1 — Supply input for the TPS2306 and channel 1 current sense input. VCC/CS1 is a dual function pin
used for input power to the chip, as well as the current sense input for the channel 1 LCA. For proper device
operation, VCC/CS1 must be connected to the sense resistor of the input supply having the highest voltage
potential.
7
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
detailed description
linear current amplifier
The linear current amplifiers (LCAs) provide closed-loop control over the inrush current during live insertion or
remote turn-on. This closed-loop operation provides direct control of the maximum current that is supplied to
the load, and allows the user to establish the current transient profile.
The current magnitude information is provided as the voltage drop across a low-value sense resistor at the
non-inverting input of the LCA. This voltage is compared to a user-programmable reference at the IMAXx inputs.
When power is applied to the plug-in card and the device is enabled, the LCA output starts to ramp the voltage
of its corresponding MOSFET gate. As the load current increases, the voltage at the CSx pin approaches that
of the IMAXx pin. The LCA servos the GATEx output to maintain equal voltages at its inputs. In this mode, the
external MOSFET acts as a constant current source at this preset current level, herein referred to as IMAX.
Once the bulk capacitance of the load electronics is charged to the input supply level, the inrush current tapers
off to the steady-state load level. With decreasing voltage drop across the sense resistor, the voltage at the
non-inverting input rises. The LCA then saturates, attempting to drive the GATEx output to its supply level. An
internal charge pump supplies this drive voltage (VPP in the block diagram) to fully enhance the external FETs.
LCA operation in the linear mode also starts an internal timer (see Fault Timer section). Should the timer expire
under a continued constant-current condition, the LCA is disabled, and additional gate discharge paths are
turned on to pull the gate low with a nominal 100-mA current. This feature prevents indefinite current sourcing
into a faulty load, such as a short-circuit.
The VCC/CS1 input is a dual function pin used for input power to the chip, as well as the current sense input
for the channel 1 LCA and overcurrent comparator (OVLD COMP in the functional block diagram). CS2 is the
current sense for the LCA and overcurrent comparator on the second (channel 2) supply controller. The CSx
sense inputs are connected to the load side of each of the sense resistors. For proper device operation,
VCC/CS1 must be connected to the sense resistor on the input supply with the highest potential. CS2 is
connected to the sense resistor on the input supply with the lower voltage potential. In typical applications, the
device supply current (4 mA maximum at V
so has negligible impact on the accuracy of the constant current threshold.
= 13.6 V) is small in relation to the monitored output current, and
CC
overcurrent comparator
Each supply is also monitored by an overcurrent (or overload) comparator, whose threshold is set relative to
the maximum sourcing, or IMAX, limit. The overcurrent comparators provide the electronic circuit breaker
function once the LCAs have left the constant-current operating mode and the MOSFET is fully enhanced. The
overcurrent thresholds define catastrophic fault current levels. Should a current overload be detected by the
device, the LCAs are immediately disabled, and the external FETs turned off, bypassing the fault timer.
The overcurrent comparators are required due to the finite response time required to pull the LCAs out of
saturation once the MOSFETs are fully enhanced. If a fault exists when power is initially applied to the board,
the LCA starts up in constant-current mode and limits the load current to IMAX until the fault timer expires. The
overcurrent comparator does not trip under this condition.
8
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
constant-current source level and overcurrent threshold programming
Constant-current source level and fault level programming is accomplished using the IMAXx input pins in
conjunction with the IREF pin. An external resistor connected between the IREF pin and ground is used to
program the internal reference current to a user-selectable value. As shown in the block diagram, the TPS2306
sources current from the IREF pin to maintain a 1.5-V level at this pin. This current is then mirrored to generate
two current sources driving a differential switch on each of the device channels. When the device is enabled,
these sources generate a sink current of magnitude (1.1) × (1.5 V/R
values for the programmed reference current are between 35 µA and 300 µA.
) at each of the IMAXx inputs. Typical
REF
External resistors (R and R in the typical application diagram) connected between the IMAX1 and
IMAX1
IMAX2
IMAX2 pins and the corresponding input voltage rails develop a voltage drop relative to that supply potential.
This drop programs the current level to be sourced to the load. During constant-current operation, the linear amp
slews to limit the voltage across the external sense resistor to the voltage across the corresponding R
resistor, thus limiting the load current.
IMAX
Slew rate control of the start-up inrush current (soft-start), is easily achieved with the addition of a capacitor
across the IMAX programming resistor (C and C in the Figure 2 application diagram). This applies an
SS1
SS2
RC time constant to the ramp-up of the voltage at the IMAX pin, and a corresponding RC characteristic on the
inrush transient during ramp-up of the output voltages. Since the IMAXx pin current sink is off until each channel
is commanded ON by the UPx comparators, the soft-start cap remains discharged until turn-on, regardless of
whether start-up is due to a live insertion event, or remote turn-on of a unit whose supply inputs have been
charged indefinitely. No additional soft-start reset components are required.
The overcurrent comparator thresholds are established in a similar manner, except that an internal fixed resistor
sets the overcurrent threshold (see R1 and R2 in the block diagram). The IMAX programming current also flows
through the overcurrent threshold resistors, generating a reference level that is offset from the corresponding
IMAX reference. These internal resistors have a nominal 2.5-kΩ value, so the comparator thresholds are a
nominal (2500 × I
) V above the fault threshold. Note that since the reference current is programmable, the
REF
user has modest control of the overcurrent threshold for a given sense resistor value.
supply sequencing
Control of both the power up and power down sequence of the two supplies is provided via the four sequencing
inputs, UP1, UP2, DOWN1, and DOWN2. Each channel’s external pass element is ramped on when the ENBL
input is asserted, and the voltage at the corresponding UPx pin exceeds the nominal 1.5-V reference threshold.
The turn-off of the two supplies may also be initiated via the ramp-up comparators; however, for more
autonomous operation, the DOWNx inputs are used. When the device ENBL signal is deasserted, the outputs
of the ramp-down comparators (DN1 and DN2) are gated to the LCA control logic (see block diagram). When
the voltage at either DOWNx input drops below a nominal 0.5 V, that channel’s LCA is disabled, and the pass
element’s gate is subsequently discharged by a 10-µA pull-down current.
9
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
charge pump and housekeeping
The TPS2306 contains an on-chip high-voltage charge pump circuit to step up the supply potential at the VCC
input to provide the gate drive for external N-channel devices. A capacitor with a value between 0.01 µF and
0.1 µF must be connected from the CPUMP pin to ground to provide additional energy storage on the charge
pump output.
During a start-up sequence, undervoltage lockout (UVLO) comparators monitor the supply levels at the
VCC/CS1 and CS2 pins, as well as the charge pump output. The LCAs are inhibited, and the GATEx outputs
pulled low, until input and charge pump levels exceed the UVLO threshold levels. This ensures sufficient supply
potential for the device and LCAs for predictable sequencing control, fault detection, and gate drive prior to
turning the outputs on. The VCC/CS1 input UVLO threshold has a maximum specification of 2.9 V to ensure
start-up, down to the minimum recommended operating supply of 4.0 V. The CS2 input starts with a 2.75-V input
level. There is a nominal amount of hysteresis on the input thresholds to guard against repeated starts in
response to supply droop. The charge pump UVLO threshold is set for a nominal 12.5 V with a V
input of 5 V.
CC
fault timer
The fault timer block contains the control circuitry for generating a time delay, which determines how long the
TPS2306 is allowed to operate in the constant-current, or linear, mode. Without the timer, fault conditions such
as starting up into a shorted load, would cause the TPS2306 to operate in the constant-current mode indefinitely,
at the programmed IMAX sourcing level. Conversely, the HSPM must allow sourcing long enough to charge the
input bulk capacitance. The determination of the time period needed depends on several factors, including:
1) the amount of capacitance to be charged, 2) the load characteristic (constant-current or resistive), and 3) the
soft-start characteristic, if used. Information about estimating the required timeout period is provided in the
Application Information section.
The fault time-out needed is the total ramp-up time of the two channel outputs.
Setting of the user-programmable time-out period is accomplished by connecting a capacitor between the
device CT pin and ground. When either of the linear amplifiers is operating in constant-current mode, circuitry
in the MODE/STATUS block generates the corresponding linear mode detected (LMDx) signal, starting the
timer. The timer operates by sourcing a nominal 50-µA from the CT pin, charging the external capacitor from
0 V. If output charging completes prior to time-out, the LCA’s drive to the rail, and load sourcing continues
uninterrupted. However, if the constant-current mode persists until the timing capacitor voltage exceeds the
1.5-V fault threshold, the TIMEOUT signal is latched as the shutdown signal (SD in the block diagram). Both
FET switches are turned off, and the FAULT output remains asserted.
To restart from a fault timeout, either the ENBL input must be toggled LO then HI, or device power must be
cycled.
enable input
The ENBL input allows host or remote turn-on and turn-off of the controlled supplies. Pulling this pin below 0.8 V
disables both external NMOS devices, and puts the IC in low-power sleep mode. Driving this pin above 2.0 V
enables the supply outputs. Because of the level translation circuitry at the ENBL input, this pin may be pulled
up externally to the V
rail. As seen in the block diagram, assertion of the sleep mode (SLP) signal turns off
CC
much of the peripheral circuitry of the device, including the charge pump, references, LCAs and overcurrent
comparators, reducing supply current to only 40 µA typical with V = 12 V. In order to ensure controlled
CC
shutdown according to the configured sequencing scheme, the gate potential of each output is monitored by
the MODE/STATUS circuitry. Once both gates have discharged below 1 V, the gate low detect (GLDx) signals
allow the part to enter sleep mode.
10
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
fault output logic
The FAULT signal is an open-drain output which is high-impedance under any conditions which cause the
outputs to be switched off, including an overcurrent or fault time-out on either supply, removal of the external
enable signal with subsequent GATEx ramp-down, or an undervoltage condition on either supply input. Refer
to the Application Information section for additional details on using this output.
The circuit diagram of Figure 2 shows a dual hot-swap application in which the TPS2306 is used to hot swap
and sequence 5.0-V and 3.3-V supplies. The total input bulk and filter capacitance associated with the +5.0V
load is represented in the diagram by C
nominal operating currents of each load are represented by the I and I blocks.
. C
represents the load capacitance on the 3.3 V supply. The
LOAD1 LOAD2
L1
L2
VCC
5V_OUT
R
SNS1
Ω
0.04
Q1
5V_IN
D1
C1 0.1
LOAD 1
µF
R1A
10 k
Ω
I
L1
C
C
SS1
LOAD1
R
IMAX1
Ω
TPS2306
IMAX1 VCC/CS1 16
0.33 µ F
365
1
2
3
4
5
6
7
8
R1B
3.57 k
Ω
R1
10 kΩ
UP1
UP1
DOWN1 15
GATE1 14
FAULT 13
CPUMP 12
GATE2 11
DOWN2 10
ENBL
IREF
CT
R
15 k
Ω
REF
C
T
0.1
F
µ
C3
0.01 µF
GND
UP2
IMAX2
CS2
9
C
R
SS2
IMAX2
Ω
0.12 µF
µ
F
274
C2 0.1
R
UP2
D2
1 k
Ω
3.3 V
OUT
R
0.01
Ω
SNS2
LOAD 2
3.3V_IN
Q2
R2A
10 k
UP1
I
Ω
L2
C
LOAD2
R2B
12.1 kΩ
UDG–01002
Figure 2. TPS2306 in a 5-V/3.3-V Dual Hot Swap Application
11
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
Note that the 5.0-V supply, being the higher input potential, is controlled by channel 1 of the device; its current
sense resistor R is tied to the VCC/CS1 input, and the FET switch Q1 gate is driven by the GATE1 output.
SNS1
The 3.3-V supply is controlled by channel 2.
In this application, the TPS2306 is connected such that the 3.3-V supply is ramped up first, followed by the 5.0-V
supply. A pull-up resistor connected to the 3.3-V input (R
applied and the ENBL input is pulled above its 2.0-V ON threshold. A divider on the channel 2 output (R2A and
) enables this supply ramp when 3.3-V power is
UP2
R2B in Figure 2) monitors the 3.3V
is allowed to start ramping up.
node, and establishes the output level at which the channel 1 supply
OUT
+3.3V_OUT
+5V_OUT
I
LOAD2
(1 A / div)
I
LOAD1
(0.5 A / div)
Figure 3. TPS2306 Output Ramp Operation in Figure 2 Circuit.
For ramp-down control, the DOWN1 input has been tied to ground; whereas the DOWN2 input monitors the
5.0-V_OUT status via the R1A/R1B divider net. When the ENBL input is pulled low, channel 1 is turned off first,
and the Q1 gate discharged by a nominal 10-µA pull-down. Once the gate has sufficiently discharged, the
5.0-V_OUT node starts to decay according to the LOAD1 characteristic. When the DOWN2 input eventually
decreases below the 0.5-V threshold of the DN2 comparator, that gate drive is also turned off. The 3.3-V_OUT
node subsequently decays according to the LOAD2 characteristic.
12
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
protecting the TPS2306 from voltage transients
Parasitic inductance associated with the power distribution can cause voltage spikes on the supply inputs if the
load current is suddenly interrupted by the TPS2306. It is important to limit the peak of these spikes to less than
15 V to prevent damage to the TPS2306. These spikes can be minimized by:
D
D
D
Reducing power distribution inductance by locating the supply close to the plug-in module, maximizing the
width of high-current traces and using a PCB ground plane.
Decoupling the VCC/CS1 and CS2 inputs with capacitors (C1 and C2 in Figure 2), located close to the
device. These capacitors are typically valued between 0.1 µF and 1.0 µF in a ceramic dielectric.
Clamping the voltage at the VCC/CS1 and CS2 inputs with Zener diodes (D1 and D2 in Fig.2). The Zener
voltage of these devices can be selected according to the nominal input supply levels; however, the
maximum breakdown in all cases should be less than 15 V to avoid damage to the TPS2306.
D
For applications with high trip currents or significant parasitic inductance, it may be necessary to install
additional bulk capacitance on the backplane side of the plug-in interface. These low-ESR capacitors
should be physically located close to the plug-in slot connector on the power rails. These devices have the
dual benefit of limiting the magnitude of spikes applied to the TPS2306, and limiting supply transients
propagated to other modules in the system if one of the protected outputs is interrupted.
layout considerations
Care should be taken to use good layout practice with the parts placement and etch routing of the plug-in PCB
to optimize the performance of the hot-swap circuit. Some of the key considerations are listed here.
D
Decoupling capacitors should be located close to the device. Keep trace lengths from the capacitor to the
current sense input (CSx), and to the device GND pin to a minimum.
D
D
D
Any protection devices (e.g., D1 and D2 in Figure 2) should be located close to the HSPM IC.
Mount the charge pump reservoir capacitor (C3 in Figure 2) close to the device CPUMP pin.
The reference current programming resistor (R
in Figure 2) should be placed as close as feasible to the
REF
device, with minimized trace length to the pin 4 output.
D
D
To reduce insertion loss across the hot swap interface, use wide traces for the supply and return current
paths. A power plane can be used for the supply return or GND node.
Additional copper placed at the land patterns of the sense resistors and pass FETs can significantly reduce
the thermal impedance of these devices, reducing temperature rise in the module and improving overall
reliability.
D
Because typical values used for current-sense resistors can be so low (between <10 mΩ and approximately
100 mΩ), board trace resistance between elements in the supply current paths becomes significant. To
achieve maximum accuracy of the constant-current thresholds, good Kelvin connections to the resistors
should be used for the IMAX and current sense inputs to the device (see Figure 4). The current sense traces
should connect symmetrically to the sense-resistor land pattern, in close proximity to the element leads,
not upstream or downstream from the device.
13
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ꢖ
SLVS368 – APRIL 2001
APPLICATION INFORMATION
LOAD CURRENT
PATH
LOAD CURRENT
PATH
SENSE
RESISTOR
IMAX
RESISTOR
IMAX
RESISTOR
CS
CS
IMAX
IMAX
TPS2306
TPS2306
UDG–01005
Figure 4. Connecting to the Sense Resistors—SMD Chip
output ramp operation
During a live insertion event, the primary functions of the TPS2306 are to control the inrush current to the two
protected loads, and to control the ramp-up sequence of the supply voltages. Inrush control is achieved via the
two LCAs, as described in the Detailed Description section. To further refine the current limit function, a two-step
gate drive sequence is used to drive the external FETs any time the outputs are ramped up. The plot of Figure 5
demonstrates the TPS2306 operation by showing the typical turn-on characteristic at the IMAX1 input.
14
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ꢋ
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ꢎ
ꢏ
ꢍ
ꢐ
ꢑ
ꢒ
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ꢂ
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
6
5
140
I
= 100 µA
REF
ENABLE
120
100
GATE1
4
80
3
2
60
40
1
Output Voltage
20
0
IMAX1 Current
0
t
t
t
t
t
1
2
3
4
5
t
t
t
0
1
2
t – Time
t – Time
Figure 6. TPS2306 Slow Ramp Operation
Figure 5. TPS2306 Typical IMAX1 Turn–on
Sequence
In Figure 5, the channel 1 ramp-up conditions are met at time t = 0. This means that the ENBL input is asserted,
0
both supply input and charge pump UVLO conditions are met, and the UP1 input voltage exceeds the 1.5-V
threshold. After a nominal delay, the IMAX1 current sink is turned on at t , but only at a level that is approximately
1
5% of the programmed IMAX level. This stage typically lasts approximately 500 µs. After about 500 µs at t , the
2
IMAX1 current ramps to the full programmed level ( I
).
REF
The same two-step characteristic is also used to turn-on the channel 2 FET.
From the load’s perspective, the slow turn-on of the pass elements has the effect shown in Figure 6.
Figure 6 shows the GATE1 and output voltage response to the typical IMAX1 ramp shown in Figure 5. In this
example, the FET is driving an RC-type load. At time t , the IMAX1 input is turned on at a magnitude of I
/20.
1
SNK
The GATE1 output begins to drive the FET gate. However, the FET remains OFF initially, and no current is
allowed to flow. At t the gate voltage exceeds the V threshold of the FET. Between t and t the output
2
GS(on)
2
3
current is limited to the slow turn-on level established by the TPS2306. Accordingly, only slight charging of the
output is obtained during this period. At t , the slow ramp time period expires (the current at IMAX1 steps to the
3
programmed level) and the output now charges at a rate of IMAX/C
. As the output voltage approaches
LOAD1
the input supply level around time t , the charging current begins to taper toward the steady-state load level.
The GATE1 output then drives towards the charge pump voltage, thus fully enhancing the external pass FET.
4
By time t , the output has charged up to 95% of the input dc potential.
5
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
Note that the relative occurrence of time t within the t to t window is influenced by a number of factors. Large
2
1
3
input capacitance and higher ON thresholds of the external FET delay turn-on of the FET, resulting in reduced
output ramp during the first stage. For the TPS2306 parameters, a higher source impedance, smaller slow ramp
current, and a shorter slow ramp period (t to t ) all act to reduce the output ramp during this period. Under some
1
3
conditions, it’s possible that only imperceptible voltage ramping occurs during the slow ramp period, in which
case all significant output charging occurs after time t .
3
determining component values
To demonstrate the process of determining the programming component values for a TPS2306-based hot swap
circuit, a design procedure is detailed here to show the derivation of the values used in the Figure 2 schematic.
For this example, the following system specs were established:
•
•
•
•
V
5.0 Vdc ± 10%
100 µF
V
3.3 Vdc ± 5%
300 µF
LOAD2 =
IN1 =
IN2 =
C
C
I
LOAD1 =
I
0.50 A
1.5 A
L1 =
L2 =
IMAX1 1.0 A
=
IMAX2 3.0 A
=
The IMAX1 and IMAX2 currents are the constant-current mode sourcing levels that are used for fast charging
of the load input capacitance during start-up of the two hot swap channels. To avoid unexpected interruption
of the supply currents during normal loading conditions, the constant-current levels must be set above the
anticipated load current values.
setting the sense resistor values
The sense resistors are used to feed the load current information back to the TPS2306 LCAs and overload
comparators. The values of these resistors can be set by considering the resultant drop under normal
(steady-state) loading conditions. For the Figure 2 application, the drop was limited to 20 mV on each channel.
Given nominal loading conditions, the sense resistors should be set as follows.
V
DROP1
20 mV
0.5 A
R
+
+
+ 40 mW
SNS1
I
(1)
(2)
L1
and
V
DROP2
20 mV
2.0 A
R
+
+
+ 10 mW
SNS2
I
L2
where:
•
•
V
I
V
= the target voltage drop under nominal loading conditions
DROP1, DROP2
I
= the respective load currents of each channel
L1, L2
16
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
setting the reference current magnitude
The reference current level is established by connecting a resistor between the TPS2306 IREF pin and ground
(R in Figure 2). The IMAXx sink currents used to develop the constant-current thresholds are determined
REF
by this reference current value. The TPS2306 can be configured to source from approximately 35 µA to 300 µA.
At 100 µA or greater, the variation in sink currents at the IMAXx inputs is typically ±10% of the programmed
value; however, variation increases with reference current decreasing below the 100-µA level. In addition, the
circuit breaker trip threshold is also established as a resistor drop below the LCA reference (see R1 and R2 in
functional block diagram). It is also then a function of the reference current. Therefore, constant-current mode
accuracy must be balanced against the circuit breaker trip threshold when establishing design values. For a
given sense resistor value, higher values of reference current result in higher overload current thresholds. The
circuit breaker setting can be adjusted downward by decreasing the reference current, or returning to the
previous step and increasing the value of the sense resistor.
For the Figure 2 application, the reference current was set to 100 µA to maintain current source accuracy. The
programming resistor value is then determined from:
V
1.5 V
REF
REF
R
+
+
REF
I
I
(3)
REF
where:
•
•
V
= the IREF pin output voltage
REF
I
= the desired reference current
REF
For I
= 100 µA, the resistor R
was set to the standard 1% value of 15.0 kΩ.
REF
REF
determining the IMAX programming resistor values
During a start-up sequence, the internal LCAs slew the GATEx outputs to maintain the voltage at the CSx pins
equal to the voltage at the corresponding IMAXx input. Therefore, the voltage across the sense resistor R
SNSx
is equal to the drop across the IMAXx programming resistor. Since the sense voltage is the I-R drop of the load
current, the R resistors can be calculated from:
IMAXx
IMAXx R
SNSx
R
+
IMAXx
(
)
1.1 I
REF
(4)
where:
•
IMAXx = the desired constant-current sourcing level
Substituting values from the example application, the following resistor values were calculated.
(
)
(
)
(
)
(
)
1.0 A 0.04W
3.0 A 0.01W
R
+
^ 364 W and R
+
^ 273 W
IMAX1
IMAX2
(
)
(
)
1.1 100 mA
1.1 100 mA
The standard 1% values of R
= 365 Ω and R
= 274 Ω were selected.
IMAX1
IMAX2
Again, the constant current levels must be above the nominal operating current of the load electronics for proper
operation of the hot swap circuit. Once the sense resistor and IMAX resistor values have been established, this
guideline can be verified by testing for the minimum value of the constant-current level, or IMAXx
. The two
(min)
main contributors to device-to-device IMAX variance are the tolerance of the IREF output voltage, and that of
the current sinks at the IMAXx inputs. Assuming the 10% tolerance on IMAX described in the Setting the
Reference Current Magnitude section, the minimum sourcing current during linear operation can be estimated
from equation 5 or 6.
17
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
ǒRIMAXx
Ǔ
(
)
0.9 I
* V
SINK(min)
OS
IMAXx
^
^
(min)
(min)
R
SNSx
(5)
(6)
ǒRIMAXx
Ǔ
I
R
* V
REF(min)
OS
IMAXx
where:
SNSx
•
IMAXx
= the minimum constant-current level
(min)
•
•
V
I
= the maximum input offset of the linear current amplifier, ±4 mV
OS
= the minimum reference current value, determined from I
= 1.4 V/R
REF
REF(min)
REF(min)
Substituting the device and design example values into equation 6, the values of IMAX1
= 0.75 A and
(min)
IMAX2
loads.
= 2.16 A are obtained, which should provide sufficient margin above the nominal 0.5-A and 1.5-A
(min)
Note that in equations 5 and 6 the tolerances of external resistors are ignored; the user can include these if
desired.
circuit breaker trip points
At this point in the design process, sufficient information is known to calculate the circuit breaker trip thresholds.
Referring to the typical application diagram, the current-sense measurement is applied to the inverting input of
the OVLD comparator. It can also be seen from the diagram that the reference voltage for comparison is
developed by sourcing I
Therefore, the nominal trip current threshold, I , can be calculated from equation 7.
through programming resistor R
and the internal resistor R1 (for channel 1).
REF
IMAX
FLT
ǒRIMAXx
Ǔ
ǒRIMAXx
Ǔ
(
)
(
)
) R
1.1 I
SNSx
) 2500W 1.1 I
INT
R
REF
REF
I
+
+
FLTx
R
SNSx
(7)
If the resultant circuit-breaker thresholds are determined to be too high, they can be adjusted by a combination
of decreasing the reference current and/or increasing the sense resistor value.
soft-starting the TPS2306
Inrush current slew rate control, or soft-start, can be programmed into the TPS2306 operation by adding a
capacitor in parallel with the IMAX resistor, as shown by C
output ramp-up is enabled, the IMAXx pin voltage ramps with an RC characteristic. Accordingly, the current
and C
in the Figure 2 schematic. When the
SS1
SS2
supplied during output charging (after the initial slow turn-on period) is of the form:
ȱ
ȧ
ȳ
*t
ǒ Ǔ
R
C
IMAX
SS
ȧ
I
(t) + IMAX Ȳ1 * e
ȴ
SRC
ȧ
ȧ
(8)
where IMAX is the steady-state constant-current level set by R
equation 4) is given by equation 9.
if soft-start were not employed, and (from
IMAX
(
)
R
1.1 I
IMAX
REF
IMAX +
R
SNS
(9)
18
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
If a desired maximum slew rate is known, it can be used to set the value of the soft-start cap, C . Since soft-start
SS
is ∂i/∂t control, the required value of C can be determined by taking the derivative of equation 8 at time t = 0
SS
and solving for C . The result is equation 10 below.
SS
IMAXx
C
+
SSx
ēi
ǒ Ǔ
ǒRIMAXx
Ǔ
ēt
x
(10)
where:
(∂i/∂t) = the desired inrush slew rate of channel x
x
Continuing with the Figure 2 example, if the 5.0-V supply-current ramp is limited to 10 mA per microsecond, but
the 3.3-V input is capable of 100 mA per microsecond, the soft-start caps should be set to:
1.0 A
3.0 A
C
+
C
+
SS1
SS2
0.01
0.1
ǒ Ǔ
ǒ Ǔ
ǒ365 W
Ǔ
ǒ274 W
Ǔ
*6
*6
10
10
C
^ 0.27 mF
C
^ 0.11 mF
SS1
SS2
Generally, selecting the next higher available value helps compensate for variations in the actual IMAX levels,
such that the ∂i/∂t does not exceed the design value, even for a hot swap solution operating at the high end of
its IMAX tolerance band.
programming the supply sequencing
The TPS2306 makes use of four on-chip comparators to control the ramp-up and ramp-down sequencing of
power delivery to the two loads. The UP1 and UP2 inputs are available to configure the ramp-up sequence of
Channels 1 and 2 respectively. The functional block diagram shows that the UPx comparators’ outputs switch
the internal current sources I and I to their respective IMAXx pins. In addition, they release disable inputs to
1
2
the LCAs, enabling LCA drive of the external FET gates.
Output turn-off is programmable via the DOWN1 and DOWN2 inputs. Again referring to the block diagram, when
the external enable signal is removed from the ENBL input, the DNx comparator outputs are gated to the LCA
control logic. When the voltage at either comparator input falls below the 0.5-V reference, that channel’s LCA
is disabled, removing the gate drive. A nominal 10-µA current source pulls the gate toward the GND pin
potential, ultimately turning off the external FET.
19
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
One method of using the UPx and DOWNx inputs to control sequencing is to use resistor dividers across the
loads to sense load status. The dividers scale the output voltages to set the desired value at which controlled
channel should ramp up or turn off. In the Figure 2 application, the pull-up on the UP2 input causes the 3.3-V
supply to ramp up first, when the enable and input conditions are met. Resistors R2A and R2B form a divider
on the 3.3V_OUT node; as this output ramps up, its status is fed back to the UP1 input to control the turn-on
of the 5.0-V output. From the diagram, it can be seen that the voltage at the UP1 pin can be determined from
the simple divider equation; therefore, the value of the R2B resistor (the bottom leg of the divider) can be
selected from:
V
UP
R2B + ǒV
Ǔ
R2A
* V
RAMP
UP
(11)
where:
•
V = the UPx comparator reference voltage
UP
•
V
ramp
= the desired output voltage of the primary channel at which the secondary channel starts to
RAMP
The maximum threshold specification can be used to set the maximum output level at which the second channel
is enabled. In this case, equation 11 becomes:
1.65 V
R2B + ǒV
* 1.65 VǓ
R2A
RAMP
(12)
For the example application, the 5.0-V supply is to be ramped after the 3.3-V supply has nearly attained its
steady-state level. To ensure operation over the supply tolerance window, this voltage was set to a maximum
of 3.0 V. If R2A is set to 10 kΩ, the value R2B = 12.2 kΩ results from equation 12. If the standard value of 12.1 kΩ
is selected, the channel 1 output starts ramping at a nominal voltage of:
22.1 kW
12.1 kW
+ ǒ
Ǔ
V
1.5 V ^ 2.74 V
RAMP
(13)
Similarly, the turn-off threshold for channel 2 is determined by the R1A/R1B divider equation. In this example,
DOWN1 was tied low (to ground) to turn off the 5.0-V supply when the enable is deasserted. As the 5.0V_OUT
node decays, its status is fed back to the DOWN2 input. Therefore, a resistor value for R1B can be found from:
V
DN
R1B + ǒV
Ǔ
R1A
* V
OFF
DN
(14)
where:
•
V = the DNx comparator reference voltage
DN
•
V
= the desired voltage of the turn-off control channel at which the controlled channel gate drive is
OFF
turned off
If R1A is set to 10 kΩ, and channel 2 turn-off should be after the +5.0V_OUT node has decayed to less than
2.50 V, then equation 14 becomes:
20
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
0.65 V
2.5 V * 0.65 V
R1B +
10kW ^ 3.51 kW
(
)
(15)
estimating the output ramp-up time
As described in the Fault Timer section, TPS2306 operation in linear mode is limited to the timeout period
established by the external capacitor on the CT pin. This timeout must be long enough to allow for either the
concurrent or sequential charging of BOTH outputs to the input supply levels. Therefore, an estimate of this
ramp-up time is required to ensure start-up.
The output voltage ramp profiles are influenced by a number of factors, including the amount of load
capacitance, the load current level, the load characteristic (either resistive or constant-current), and the current
ramp profile. Therefore, determination of the charging, or start-up, time is organized into several different load
categories:
1. resistive loads, no soft-start
2. constant-current loads, no soft-start
3. constant-current loads, with soft-start
The case which most closely describes the application characteristics should be selected.
NOTE:In the following discussion, the subscripted “1” and “2” suffixes refer respectively to the first
channel to ramp up (primary or master), and the second (or controlled or slave) channel to ramp,
not necessarily device Channels 1 and 2.
case 1: resistive loads, no soft-start
When the output ramp conditions are met, the pass FET gates are initially only driven to source a current of
approximately 5% of the IMAX current to the loads, as described in the Output Ramp Operation section. This
first step lasts a nominal 500 µs. Subsequently, the output current is ramped to the full IMAX setting. For typical
applications, the extent of capacitance charging during this slow ramp period is relatively small. Therefore, it
can be neglected in estimating total start-up time, simplifying calculations. However, since the HSPM timer is
started as soon as the first output starts ramping, the slow ramp period is included as a component of the total
ramp-up time.
Given these considerations, the start-time calculation approximates the source as making a step change from
0 to IMAX, once enabled. Therefore, the time for either output to charge to a given voltage, v (t), can be found
x
from:
IMAXx ǒR Ǔ
(
)
ȱ
ȧ
ȳ) t
ȧ
Lx
t + R C ȏn
Lx
Lx
SR
ǒIMAXx R Ǔ* n (t)
x
Ȳ
ȴ
Lx
(16)
where:
•
•
•
R
= the load resistance
Lx
C
t
= the load input capacitance (C
or C
in Figure 2)
Lx
LOAD1
LOAD2
= the initial slow turn-on period, approximately 500 µs
SR
21
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APPLICATION INFORMATION
Equation 16 can be used to calculate the time it takes for either of the loads to charge completely by substituting
that channel’s parameters, and solving for t when v (t) = V . However, if the secondary channel ramp
ST
x
DCx
turn-on is initiated by the primary channel’s output voltage level, then the first period of interest is the time when
the primary channel achieves the ramp-up command threshold. This time, designated t
be found from:
in equation 17, can
UP2
IMAX R
1
L1
ƪ
ƫ) t
t
+ R C ȏn
UP2
L1
L1
SR
IMAX R * V
1
L1
RAMP
(17)
where:
•
V
= the programmed ramp-up threshold established using equation 11, and the subscripted “1”
indicates the primary, or controlling channel parameters
RAMP
Once the controlled channel starts to turn on, its voltage ramp follows the same profile as the first channel.
Therefore, the total start-up time for the sequenced outputs is given by equation 18.
IMAX R
2
L2
t
+ R C ȏn
ƪ
ƫ
) t
) t
ST
L2
L2
UP2
SR
IMAX R * V
2
L2
DC2
(18)
where:
•
•
V
= secondary channel supply input voltage
DC2
the subscripted “2” indicates the secondary, or controlled channel parameters
case 2: constant-current loads, no soft-start
Constant-current loads typically employ some type of undervoltage lockout (UVLO), or are achieved by holding
processors and logic in reset until the supply has stabilized. Therefore, the ramp profile has two stages; the first
stage from turn-on until the UVLO threshold (V
in the following equations) is reached, and the remaining
UV
period to ramp from V
to the steady-state level, V . Once the load starts up, the input bulk capacitance is
UV
DC
charged only by the sourcing current in excess of the load current.
Assuming the primary load starts up prior to its voltage attaining the slave channel ramp-up threshold
(V
< V
), the time to reach that threshold can be estimated from:
UV1
RAMP
ǒVRAMP
Ǔ
* V
ȱVUV1
ȳ
UV1
t
+ C
)
) t
ȧ
ȧ
UP2
L1
SR
IMAX
ǒIMAX * I
Ǔ
1
Ȳ
ȴ
1
L1
(19)
where:
•
•
•
V
= the master channel UVLO threshold
UV1
V
= the controlled or slave channel ramp-up threshold
RAMP
I
= the master channel constant-current load
L1
22
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
With this known secondary-channel delay, the total start-up time can now be determined from the time at which
the controlled channel reaches steady-state. This period is given by equation 20.
ǒVDC2
Ǔ
* V
ȱVUV2
ȳ
UV2
t
+ C
)
) t
) t
ȧ
ȧ
ST
L2
UP2
SR
IMAX
ǒIMAX * I
Ǔ
2
Ȳ
ȴ
2
L2
(20)
where:
•
•
V
= the slave channel UVLO threshold
UV2
V
= the slave channel supply input voltage
DC2
case 3: constant-current loads using soft-start
When soft-start is used to bring up a constant-current load, the ramp-up time determination becomes more
complex. Prior to achieving its UVLO threshold, the primary channel’s voltage profile is given by equation 21.
*ǒt*t
Ǔ
ȱ
ȧ
ȳ
ȧ
1
ǒ Ǔ
ǒt * t
Ǔ
t
IMAX
L1
t
1
SS1
1
SS1
Ȳe
ȧ
* 1ȴ
ȧ
n (t) +
)
1
t
C
SS1
(21)
where:
• τSS1 = R
× C
SS1
IMAX1
•
t = t
= the initial slow turn-on period, approximately 500 µs
SR
1
Equation 21 can be plugged into a spreadsheet to solve iterively for different times of interest. Two useful time
points are:
•
•
the time t = t
when (t) = V
, if V
≤ V
(V
is the primary channel UVLO threshold), and
UP2
ν1
RAMP
RAMP
UV1 UV1
the time t = t
when (t) = V
, if V
> V
VUV1
ν1
UV1 RAMP
UV1
Assuming the UVLO threshold is less than the slave channel ramp-up threshold (case 2 above), the effect of
the additional load can be factored into the voltage ramp profile. This better describes the second stage of the
output ramp-up. Since the turn-on event of the second channel occurs during this stage, its point in time can
be found by sampling voltage equation 22 for the time t = t
when ν (t) = V
.
UP2
1
RAMP
n1(t) +ȡ
ȣ
*ǒtVUV1
Ǔ
*ǒt*t
Ǔ
*t
ȱ
1
ȳ
1
1
t
t
) ǒIMAX * I Ǔ ǒ
Ǔ
t
IMAX e
* e
t * t
) V
SS1
SS1
ȧ SS1
ȧ
ȧ
VUV1 ȧ
1
1
L1
UV1
C
L1
Ȳ
ȴ
Ȣ
ꢀ
(22)
where:
•
t
is determined from equation 21
VUV1
Note that for designs where (t
– t ) > 4 × T
, the sourcing current has virtually attained the IMAX level
VUV1
1
SS1 1
sometime prior to t = t
. From inspection of equation 22, it can be seen that the exponential terms become
VUV1
insignificant in this case. Therefore, a good approximation of the voltage waveform can be obtained by
considering it to be the constant-current charging of C at a rate of (IMAX – I ). With this simplification, the
L1
1
L1
time t
can be calculated from equation 23.
UP2
23
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ꢋ
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ꢍ
ꢎ
ꢏ
ꢍ
ꢐ
ꢑ
ꢒ
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
V
* V
RAMP
IMAX * I
UV1
t
^ C
ǒ Ǔ) t
UP2
L1
VUV1
1
L1
(23)
Once the total delay to the secondary channel start-up (t
) is known, substitution of the secondary channel
UP2
parameters into equations 21 and 22 (or 23) can be used to determine the total system start-up time. Substitute
τSS2 for τSS1, IMAX for IMAX , etc. However, for these calculations, the constant t in equations 21 and 22
2
1
1
is now the quantity (t
+ t ). This version of equation 21 is used to determine the time at which the secondary
UP2 SR
channel load starts up, t
the secondary channel parameters into equation 22 (or 23) (including t
output voltage is above the UVLO threshold.
when v (t) = V
. Finally, the system start-up time is calculated by substituting
VUV2
2
UV2
for t
) to model ν (t) when the
VUV2
VUV1 2
setting the linear mode timeout
Once an estimate of the required charging time is obtained, the value of the timing capacitor C can be derived.
T
Since the timeout is obtained via the constant-current charging of the external capacitor, the minimum capacitor
value is given by:
i
t
CT(max)
V
ST
*6
^ ƪ48 10
ƫ
C
+
t
T(min)
ST
F(min)
(24)
where:
•
•
i
(MAX) = the maximum CT charging current, 65 µA
CT
V (MIN) = the minimum fault threshold on the CT pin, 1.35 V
F
For the example application, a total start-up time of about 2.03 ms was obtained. Solving equation 24 using this
timeout value produces a result of C (MIN) = 0.097 µF; a 0.1-µF value is shown in the schematic.
T
using the FAULT output
LED indicator
The TPS2306 FAULT output provides fault reporting capability to the system host. It is an open-drain output
which becomes high-impedance under any conditions which cause either of the GATEx outputs to be turned
off. It can be used to provide a visual indication of a fault by using it as an LED pre-driver, as shown in Figure 7.
24
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
VCC
R
SNS1
Q1
VIN1
VOUT1
C1
µ
0.1 F
TPS2306
R
IMAX1
1
2
3
4
5
6
7
8
VCC/CS1 16
IMAX1
UP1
DOWN1 15
GATE1 14
FAULT 13
CPUMP 12
GATE2 11
DOWN2 10
VCC
ENBL
IREF
CT
R1
R
Ω
10 k
REF
C
T
R2
GND
C3
GND
UP2
D1
FAULT
µ
0.01 F
IMAX2
CS2
9
Q3
C2
R
IMAX2
µ
0.1 F
R
SNS2
VIN2
VOUT2
Q2
UDG–01003
Figure 7. Possible FAULT LED Circuit
QuickSwitch device
Another potential use of the FAULT output is to drive a bus isolation device, such as a Widebust or
QuickSwitch bus switch, as shown in Figure 8. The FAULT output can provide direct-drive of active low bus
enable inputs of the switch device(s).
25
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SLVS368 – APRIL 2001
APPLICATION INFORMATION
VCC
LOAD 1
SYSTEM OR
BACKPLANE
REMOVABLE CARD
ASSEMBLY
R
SNS2
R
SNS1
R
R
IMAX1
IMAX2
VCC/CS1
IMAX1
GATE1
IMAX2
+
+
V2
V1
LOAD 2
CS2
VCC
GATE2
FAULT
VCC
GND
D0:Dx
SLOT D0:Dx
TPS2306
GND OE
Widebus or
QuickSwitch
VCC
VCC
VCC
AD0:ADy
SLOT AD0:ADy
GND OE
Widebus or
QuickSwitch
UDG–01006
Figure 8. Using the TPS2306 with Bus Switches
With outputs disabled, the bus switches provide electrical isolation between the backplane and plug-in card
buses. This is useful for reducing glitches on the system address and data busses during live insertions.
Because of the linear mode detection of the TPS2306, the FAULT output remains asserted throughout the
output voltage ramp period. This pin is not pulled low until a nominal delay after both output supplies have
stabilized at the input voltage levels (see Figure 9). When this occurs, the slot and backplane busses are
connected with a minimal impedance across the bus interface.
26
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SLVS368 – APRIL 2001
ENBL
V
LOAD1
V
LOAD2
OE
Figure 9. TPS2306 FAULT Operation During Ramp-Up
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
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