TPS2330 [TI]
SINGLE HOT SWAP POWER CONTROLLER WITH CIRCUIT BREAKER AND POWER-GOOD REPORTING; 带断路器和电源良好报告单一热插拔电源控制器
| 型号： | TPS2330 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE HOT SWAP POWER CONTROLLER WITH CIRCUIT BREAKER AND POWER-GOOD REPORTING |
| 文件： | 总20页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
D OR PW PACKAGE
(TOP VIEW)
features
Single-Channel High-Side MOSFET Driver
1
2
3
4
5
6
7
14
13
12
11
10
9
GATE
DGND
TIMER
VREG
VSENSE
AGND
ISENSE
DISCH
ENABLE
PWRGD
FAULT
ISET
Input Voltage: 3 V to 13 V
Inrush Current Limiting With dv/dt Control
Circuit-Breaker Control With Programmable
Current Limit and Transient Timer
AGND
IN
Power-Good Reporting With Transient
Filter
8
CMOS- and TTL-Compatible Enable Input
NOTE: Terminal 13 is active high on TPS2331.
Low 5-µA Standby Supply Current . . . Max
typical application
Available in 14-Pin SOIC and TSSOP
Package
V
O
+
VIN
–40°C to 85°C Ambient Temperature Range
3 V – 13 V
DISCH
IN
ISET
GATE
ISENSE
Electrostatic Discharge Protection
VSENSE
VREG
applications
AGND
DGND
Hot-Swap/Plug/Dock Power Management
Hot-Plug PCI, Device Bay
TPS2330
PWRGD
FAULT
TIMER
Electronic Circuit Breaker
ENABLE
description
The TPS2330 and TPS2331 are single-channel hot-swap controllers that use external N-channel MOSFETs
as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP),
inrush-current control, output-power status reporting, and separation of load transients from actual load
increases, are critical requirements for hot-swap applications.
The TPS2330/31 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure
the device is off at start-up and confirm the status of the output voltage rails during operation. An internal charge
pump, capableofdrivingmultipleMOSFETs, providesenoughgate-drivevoltagetofullyenhancetheN-channel
MOSFETs. The charge pump controls both the rise times and fall times (dv/dt) of the MOSFETs, reducing power
transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent
conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during
power-state transitions, to disregard transients for a programmable period.
AVAILABLE OPTIONS
PACKAGES
PIN
COUNT
T
A
HOT-SWAP CONTROLLER DESCRIPTION
ENABLE
ENABLE
Dual-channel with independent OCP and adjustable PG
Dual-channel with interdependent OCP and adjustable PG
20
20
TPS2300IPW
TPS2310IPW
TPS2301IPW
TPS2311IPW
TPS2320ID
TPS2320IPW
TPS2321ID
TPS2321IPW
–40°C to 85°C
Dual-channel with independent OCP
16
14
TPS2330ID
TPS2330IPW
TPS2331ID
TPS2331IPW
Single-channel with OCP and adjustable PG
†
The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2331IPWR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
functional block diagram
IN
PREREG
ISET
ISENSE
GATE
Clamp
DISCH
VREG
dv/dt Rate
Protection
Charge
Pump
Circuit
Breaker
50 µA
Pulldown FET
Circuit Breaker
UVLO and
Power-Up
VSENSE
PWRGD
AGND
DGND
75 µA
20-µs Deglitch
FAULT
TIMER
Logic
ENABLE
50-µs Deglitch
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
AGND
6,9
2
I
I
Analog ground, connects to DGND as close as possible
Digital ground
DGND
DISCH
14
13
11
1
O
I
Discharge transistor
ENABLE/ ENABLE
FAULT
Active low (TPS2330) or active high enable (TPS2331)
Overcurrent fault, open-drain output
Connects to gate of high-side MOSFET
Input voltage
O
O
I
GATE
IN
8
ISENSE
ISET
7
I
Current-sense input
10
12
3
I
Adjusts circuit-breaker threshold with resistor connected to IN
PWRGD
TIMER
O
O
O
I
Open-drain output, asserted low when VSENSE voltage is less than reference.
Adjusts circuit-breaker deglitch time
VREG
4
Connects to bypass capacitor, for stable operation
Power-good sense input
VSENSE
5
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
detailed description
DISCH – DISCH should be connected to the source of the external N-channel MOSFET transistor connected
to GATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve as
reference-voltage connection for internal gate-voltage-clamp circuitry.
ENABLE or ENABLE – ENABLE for TPS2330 is active low. ENABLE for TPS2331 is active high. When the
controller is enabled, GATE voltage will power up to turn on the external MOSFETs. When the ENABLE pin is
pulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50 µs, the gate of the
MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the
output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when
enabled and shuts down PREREG when disabled so that total supply current is much less than 5 µA.
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained long
enough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low.
GATE – GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled,
internal charge-pump circuitry pulls this pin up by sourcing approximately 15 µA. The turnon slew rates depend
upon the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced
by connecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect
the device from false overcurrent triggering during powerup. The charge-pump circuitry will generate
gate-to-source voltages of 9 V–12 V across the external MOSFET transistor.
IN – IN should be connected to the power source driving the external N-channel MOSFET transistor connected
toGATE. TheTPS2330/31drawsitsoperatingcurrentfromIN, andwillremaindisableduntiltheINpowersupply
has been established. The device has been constructed to support 3-V, 5-V, or 12-V operation.
ISENSE, ISET – ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets the
magnitude of the current that generates an overcurrent fault, through a external resistor connected to ISET. An
internalcurrentsourcedraws50µAfromISET. WithasenseresistorfromINtoISENSE, whichisalsoconnected
to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. An overcurrent
condition is assumed to exist if ISENSE is pulled below ISET.
PWRGD – PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drain
output and is pulled low during an undervoltage condition. To minimize erronous PWRGD responses from
transients on the voltage rail, the voltage sense circuit incorporates a 20-µs deglitch filter. When VSENSE is
lower than the reference voltage (about 1.23 V), PWRGD will be active low to indicate an undervoltage condition
on the power-rail voltage.
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled
to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.
VREG – The VREG pin is the output of an internal low-dropout voltage regulator. This regulator draws current
from IN. A 0.1-µF ceramic capacitor should be connected between VREG and ground. VREG can be connected
to IN or to a separated power supply through a low-resistance resistor. However, the voltage on VREG must
be less than 5.5 V.
VSENSE – VSENSE can be used to detect undervoltage conditions on external circuitry. If VSENSE senses
a voltage below approximately 1.23 V, PWRGD is pulled low.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Input voltage range: V
Output voltage range:
, V
, V
,V
, V
. . . . . . . . . . . . . . . –0.3 V to 15 V
I(IN) I(ISENSE) I(VSENSE) I(ISET) I(ENABLE)
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V
O(GATE)
, V
, V
, V
, V
. . . . . . . –0.3 V to 15V
O(DISCH) O(PWRGD) O(FAULT) O(VREG) O(TIMER)
, I
Sink current range:
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 100 mA
, I
GATE DISCH
I
, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 10 mA
PWRGD TIMER FAULT
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are respect to DGND.
DISSIPATION RATING TABLE
DERATING FACTOR
T
≤ 25°C
T
A
= 70°C
T = 85°C
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
PW-14
D-14
755 mW
10.07 mW/°C
8.18 mW/°C
302 mW
245 mW
151 mW
123 mW
613 mW
recommended operating conditions
MIN NOM
MAX
13
UNIT
V
Input voltage, V
V
, V
, V
, V
3
2.95
–40
I
I(IN) I(ISENSE) I(VSENSE) I(ISET)
VREG voltage, V
, when VREG is directly connected to IN
O(VREG)
5.5
V
Operating virtual junction temperature, T
100
°C
J
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < T < 85°C),
A
3 V ≤ V
≤13 V (unless otherwise noted)
I(IN)
general
PARAMETER
TEST CONDITIONS
= 5 V (TPS2331),
MIN
TYP
0.5
75
MAX
1
UNIT
V
V
mA
I(ENABLE)
I
I
Input current, IN
I(IN)
= 0 V (TPS2330)
200
I(ENABLE)
V
V
= 0 V (TPS2331),
= 5 V (TPS2330)
I(ENABLE)
I(ENABLE)
Standby current (sum of currents into IN ISENSE and ISET)
5
µA
I(stby)
GATE
PARAMETER
TEST CONDITIONS
MIN
9
TYP
11.5
14.5
21
MAX
UNIT
V
V
V
V
I(IN)
V
I(IN)
V
I(IN)
= 3 V
G(GATE_3V)
I
= 500 nA,
I(GATE)
DISCH open
Gate voltage
= 4.5 V
= 10.8 V
10.5
16.8
V
G(GATE_4.5V)
G(GATE_10.8V)
Clamping voltage, GATE to
DISCH
V
9
10
50
10
14
75
12
20
V
C(GATE)
S(GATE)
3 V ≤ V
≤ 13.2 V, 3 V ≤ V
≤ 5.5 V,
≤ 5.5 V,
I(IN)
I(IN)
O(VREG)
O(VREG)
I
Source current, GATE
Sink current, GATE
µA
µA
V
= V
+ 6 V
I(GATE)
I(IN)
3 V ≤ V
≤ 13.2 V, 3 V ≤ V
100
V
= V
I(GATE)
I(IN)
V
I(IN)
V
I(IN)
V
I(IN)
V
I(IN)
V
I(IN)
V
I(IN)
= 3 V
0.5
0.6
1
t
t
Rise time, GATE
Fall time, GATE
C
to GND = 1 nF (see Note 2)
to GND = 1 nF (see Note 2)
= 4.5 V
= 10.8 V
= 3 V
ms
ms
r(GATE)
g
g
0.1
0.12
0.2
C
= 4.5 V
= 10.8 V
f(GATE)
NOTE 2: Specified, but not production tested.
TIMER
PARAMETER
TEST CONDITIONS
MIN
0.4
35
1
TYP
0.5
50
MAX
0.6
UNIT
V
V
Threshold voltage, TIMER
Charge current, TIMER
Discharge current, TIMER
OT(TIMER)
V
V
= 0 V
= 1 V
65
µA
I(TIMER)
2.5
mA
I(TIMER)
circuit breaker
PARAMETER
Undervoltage voltage, circuit breaker
Input bias current, I
TEST CONDITIONS
MIN
TYP
50
MAX
60
UNIT
mV
V
R
= 1 kΩ
40
IT(CB)
ISET
I
0.1
5
µA
IB(ISENSE)
SENSE
V
V
= 4 V
= 1 V
400
25
800
150
O(GATE)
Discharge current, GATE
mA
O(GATE)
Propagation (delay) time, comparator inputs to
gate output
C
= 50 pF,
10 mV overdrive,
C = 50 pF
O(timer)
g
t
1.3
µs
pd(CB)
(50% to 10%)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < T < 85°C),
A
3 V ≤ V
≤13 V (unless otherwise noted) (continued)
I(IN)
ENABLE, active low (TPS2330)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level input voltage, ENABLE
Low-level input voltage, ENABLE
2
IH(ENABLE)
0.8
V
IL(ENABLE)
Input pullup resistance,
ENABLE
R
t
See Note 3
100
200
60
300
kΩ
µs
µs
I(ENABLE)
V
increasingabovestopthreshold;100
I(ENABLE)
Turnoff delay time, ENABLE
Turnon delay time, ENABLE
d_off(ENABLE)
ns rise time, 20 mV overdrive (see Note 2)
V
decreasing below start threshold;
I(ENABLE)
t
125
d_on(ENABLE)
100 ns fall time, 20 mV overdrive (see Note 2)
NOTES: 2. Specified, but not production tested.
3. Test I of ENABLE at V
1 V
= 1 V and 0 V, then R =
I(ENABLE)
O
I(ENABLE)
I
I
0V
1V
O_
O_
ENABLE, active high (TPS2331)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level input voltage, ENABLE
2
IH(ENABLE)
Low-level input voltage, ENABLE
0.7
V
IL(ENABLE)
Input pulldown resistance,
ENABLE
R
100
150
85
300
kΩ
µs
µs
I(ENABLE)
V
increasing above start threshold;
I(ENABLE)
100 ns rise time, 20 mV overdrive (see Note 2)
t
t
Turnon delay time, ENABLE
Turnoff delay time, ENABLE
d_on(ENABLE)
V
decreasing below stop threshold;
I(ENABLE)
100
d_off(ENABLE)
100 ns fall time, 20 mV overdrive (see Note 2)
NOTE 2: Specified, but not production tested.
PREREG
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5.5
UNIT
V
VREG
PREREG output voltage
PREREG dropout voltage
4.5 ≤ V
≤ 13 V
3.5
4.1
I(IN)
= 3 V
Vdrop_PREREG
V
I(IN)
0.1
V
VREG UVLO
PARAMETER
TEST CONDITIONS
MIN
2.75
2.65
50
TYP
2.85
2.78
75
MAX
UNIT
V
V
V
V
Output threshold voltage, start
Output threshold voltage, stop
Hysteresis
2.95
OT(UVLOstart)
OT(UVLOstop)
hys(UVLO)
V
mV
mA
UVLO sink current, GATE
V
= 2 V
10
I(GATE)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < T < 85°C),
A
3 V ≤ V
≤13 V, 3 V ≤ V
≤ 5.5 V (unless otherwise noted) (continued)
I(IN1)
I(IN2)
PWRGD
PARAMETER
TEST CONDITIONS
decreasing
I(VSENSE)
MIN
TYP
MAX
UNIT
V
V
Trip threshold, VSENSE
V
1.2 1.225
1.25
V
IT(ISENSE)
Hysteresis voltage, power-good
comparator
20
30
40
mV
hys
V
V
Output saturation voltage PWRGD
I
I
= 2 mA
0.2
0.4
1
V
V
O(sat)(PWRGD)
O
Minimum V
O(VREG)
for valid power-good
= 100 µA, V
= 1 V
O(PWRGD)
O(VREGmin)
O
I
Input bias current, power-good comparator
Leakage current, PWRGD
V
V
V
= 5.5 V
1
µA
µA
IB
I(VSENSE)
O(PWRGD)
I(VSENSE)
I
= 13 V
1
lkg(PWRGD)
increasing,
t
t
Delay time, rising edge, PWRGD
Delay time, falling edge, PWRGD
Overdrive = 20 mV, t = 100 ns,
25
2
µs
µs
dr
r
See Note 2
V
decreasing,
I(VSENSE)
Overdrive = 20 mV, t = 100 ns,
r
df
See Note 2
NOTE 2: Specified, but not production tested.
FAULT output
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.4
1
UNIT
V
V
Output saturation voltage, FAULT
Leakage current, FAULT
I
= 2 mA
O(sat)(FAULT)
O
I
V
= 13 V
µA
lkg(FAULT)
O(FAULT)
DISCH
PARAMETER
TEST CONDITIONS
= 1.5 V, V = 5 V
MIN
5
TYP
MAX
UNIT
mA
V
I
Discharge current, DISCH
V
10
DISCH
I(DISCH)
I(VIN)
V
Discharge on high-level input voltage
Discharge on low-level input voltage
2
IH(DISCH)
IL(DISCH)
V
1
V
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
Load 12 Ω
Load 12 Ω
V
I(ENABLE)
5 V/div
V
I(ENABLE)
5 V/div
V
O(GATE)
10 V/div
V
O(DISCH)
5 V/div
V
O(GATE)
10 V/div
V
O(DISCH)
5 V/div
t – Time – 10 ms/div
t – Time – 10 ms/div
Figure 1. Turnon Voltage Transition
Figure 2. Turnoff Voltage Transition
No Capacitor
on Timer
V
V
I(ENABLE)
I(ENABLE)
5 V/div
5 V/div
No Capacitor
on Timer
V
O(GATE)
10 V/div
V
O(GATE)
10 V/div
V
O(FAULT)
10 V/div
V
O(FAULT)
10 V/div
I
I
O(OUT)
2 A/div
O(OUT)
2 A/div
t – Time – 1 ms/div
t – Time – 5 ms/div
Figure 4. Overcurrent Response: an Overcurrent
Load Plugged Into the Enabled Board
Figure 3. Overcurrent Response: Enabled
Into Overcurrent Load
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
No Capacitor
on Timer
No Capacitor
on Timer
V
I(ENABLE)
5 V/div
V
I(IN)
10 V/div
V
V
O(GATE)
10 V/div
O(GATE)
10 V/div
V
O(FAULT)
10 V/div
V
O(OUT)
10 V/div
I
O(IN)
2 A/div
I
O(OUT)
1 A/div
t – Time – 1 ms/div
t – Time – 5 ms/div
Figure 5. Enabled Into Short Circuit
Figure 6. Hot Plug
V
No Capacitor
on Timer
I(IN)
10 V/div
V
O(GATE)
10 V/div
V
O(OUT)
10 V/div
I
O(OUT)
1 A/div
t – Time – 1 ms/div
Figure 7. Hot Removal
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT (ENABLED)
SUPPLY CURRENT (DISABLED)
vs
vs
VOLTAGE
VOLTAGE
52
51
50
49
15
14
13
12
11
10
9
T
= 85°C
A
IN = 5 V to 13 V
IN = 5 V to 13 V
T
= 85°C
A
T
A
= 25°C
T
A
= 25°C
T
= –40°C
A
T
A
= 0°C
48
47
46
45
T
A
= 0°C
T
A
= –40°C
8
7
44
43
4
5
6
7
8
9
10 11 12 13 14
4
5
6
7
8
9
10 11 12 13 14
V – Input Voltage – V
I
V – Input Voltage – V
I
Figure 9
Figure 8
GATE VOLTAGE
vs
INPUT VOLTAGE
GATE VOLTAGE RISE TIME
vs
GATE LOAD CAPACITANCE
22
20
18
18
C
= 1000 pF
L(GATE)
IN = 12 V
T
= 85°C
A
T
= 25°C
A
T
A
= 25°C
15
12
T
A
= 0°C
T
A
= –40°C
16
14
9
6
12
10
3
0
2
3
4
5
6
7
8
9
10 11 12
0
3
6
9
12
V – Input Voltage – V
I
C
– GATE Load Capacitance – nF
L(GATE)
Figure 10
Figure 11
10
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
TYPICAL CHARACTERISTICS
GATE VOLTAGE FALL TIME
GATE OUTPUT CURRENT
vs
vs
GATE LOAD CAPACITANCE
GATE VOLTAGE
4
3
2
15
14.5
14
IN = 12 V
= 25°C
T
A
T
A
= –40°C
T
= 85°C
A
13.5
13
T
A
= 25°C
T
= 0°C
A
12.5
12
1
0
IN = 13 V
11.5
11
0
3
6
9
12
14 15 16 17 18 19 20 21 22 23 24
V – GATE Voltage
C
– GATE Load Capacitance – nF
L(GATE)
Figure 12
Figure 13
CIRCUIT-BREAKER RESPONSE
LOAD VOLTAGE DISCHARGE TIME
vs
vs
TIMER CAPACITANCE
LOAD CAPACITANCE
12
9
320
280
240
200
160
120
80
IN = 12 V
IN = 12 V
T
A
= 25°C
I
T
= 0 A
= 25°C
O
A
6
3
0
40
0
0
0.2
0.4
0.6
0.8
1
0
100
200
300
400
500
C
– TIMER Capacitance – nF
(timer)
C
– Load Capacitance – µF
L
Figure 14
Figure 15
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
TYPICAL CHARACTERISTICS
UVLO START AND STOP THRESHOLDS
PWRGD THRESHOLD
vs
vs
TEMPERATURE
TEMPERATURE
2.9
2.88
2.86
2.84
2.82
2.8
1.27
1.26
Up
Start
Stop
1.25
1.24
1.23
1.22
Down
2.78
2.76
2.74
1.21
1.20
2.72
2.7
–45–35–25–15 –5
5
15 25 35 45 55 65 75 85 95
–45–35–25 –15 –5 5 15 25 35 45 55 65 75 85 95
T
A
– Temperature – °C
T
A
– Temperature – °C
Figure 17
Figure 16
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
APPLICATION INFORMATION
typical application diagram
This diagram shows a typical dual hot-swap application. The pullup resistors at PWRGD and Fault should be
relatively large (e.g. 100 kΩ) to reduce power loss unless they are required to drive a large load.
System
3 V 13 V IN
Board
R
SENSE
V
O
1 µF 10 µF
+
R
R
VSENSE_TOP
R
ISET
VSENSE_BOTTOM
0.1 µF
VREG IN ISET ISENSE GATE DISCH VSENSE
ENABLE
ENABLE
DGND
FAULT
FAULT
TPS2331
PWRGD
PWRGD
AGND
TIMER
Figure 18. Typical Hot-Swap Application
input capacitor
A 0.1-µF ceramic capacitor in parallel with a 1-µF ceramic capacitor should be placed on the input power
terminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. The
TPS2330/31 does not need to be mounted near the connector or these input capacitors. For applications with
more severe power environments, a 2.2-µF or higher ceramic capacitor is recommended near the input
terminals of the hot-plug board. A bypass capacitor for IN should be placed close to the device.
output capacitor
A 0.1-µF ceramic capacitor is recommended per load on the TPS2330/31; these capacitors should be placed
close to the external FETs and to TPS2330/31. A larger bulk capacitor on the load is also recommended. The
value of the bulk capacitor should be selected based on the power requirements and the transients generated
by the application.
external FET
To deliver power from the input sources to the loads, the controller needs an external N-channel MOSFET. A
few widely used MOSFETs are shown in Table 1. But many other MOSFETs on the market can also be used
with TPS23xx in hot-swap systems.
13
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SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
APPLICATION INFORMATION
Table 1. Some Available N-Channel MOSFETs
CURRENT RANGE
PART NUMBER
DESCRIPTION
MANUFACTURER
(A)
IRF7601
N-channel, r
N-channel, r
= 0.035 Ω, 4.6 A, Micro-8
= 0.040 Ω, 4.6 A, Micro-8
International Rectifier
ON Semiconductor
International Rectifier
ON Semiconductor
International Rectifier
ON Semiconductor
International Rectifier
Vishay Dale
DS(on)
MTSF3N03HDR2
IRF7101
DS(on)
0 to 2
Dual N-channel, r
= 0.1 Ω, 2.3 A, SO-8
= 0.04 Ω, 5 A, SO-8
DS(on)
DS(on)
MMSF5N02HDR2
IRF7401
Dual N-channel, r
N-channel, r
N-channel, r
= 0.022 Ω, 7 A, SO-8
= 0.025 Ω, 5 A, SO-8
DS(on)
MMSF5N02HDR2
IRF7313
DS(on)
2 to 5
Dual N-channel, r
DS(on)
= 0.029 Ω, 5.2 A, SO-8
SI4410
N-channel, r
N-channel, r
N-channel, r
= 0.020 Ω, 8 A, SO-8
= 0.019 Ω, 29 A, d-Pak
= 0.045 Ω, 14 A, d-Pak
DS(on)
DS(on)
DS(on)
IRLR3103
International Rectifier
International Rectifier
5 to 10
IRLR2703
timer
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. This
capacitor should be connected between TIMER and ground. The presence of an overcurrent condition on of
the TPS2330/31 causes a 50-µA current source to begin charging this capacitor. If the overcurrent condition
persists until the capacitor has been charged to approximately 0.5 V, the TPS2330/31 will latch off the transistor
and will pull the FAULT pin low. The timer capacitor can be made as large as desired to provide additional time
delay before registering a fault condition.
output-voltage slew-rate control
When enabled, the TPS2330/TPS2331 controllers supply the gate of an external MOSFET transistor with a
current of approximately 15 µA. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain
capacitance C of the external MOSFET capacitor to a value approximating:
gd
15
C
A
dvs
dt
gd
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external
MOSFET and ground.
VREG capacitor
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-µF
or 0.22-µF ceramic capacitor is recommended.
14
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
APPLICATION INFORMATION
gate drive circuitry
The TPS2330/TPS2331 includes four separate features associated with each gate-drive terminal:
A charging current of approximately 15 µA is applied to enable the external MOSFET transistor. This current
is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH)
of 9 V–12 V. DISCH must be connected to the external MOSFET source terminal to ensure proper operation
of this circuitry.
A discharge current of approximately 75 µA is applied to disable the external MOSFET transistor. Once the
transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO
discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while
ensuring that the gate of the external MOSFET transistor remain at a low voltage.
During a UVLO condition, the gate of the MOSFET transistor is pulled down by an internal PMOS transistor.
This transistor continues to operate even if the voltage at IN is 0 V. This circuitry also helps hold the external
MOSFET transistor off when power is suddenly applied to the system.
During an overcurrent fault condition, the external MOSFET transistor that exhibited an over-current
condition will be rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at
4 V) from the pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and
the UVLO driver is enabled instead.
setting the current-limit circuit-breaker threshold
The current sensing resistor R
the channel, and can be calculated by the following equation:
and the current limit setting resistor R
determine the current limit of
ISENSE
ISET
–6
R
50 10
ISET
I
LMT
R
ISENSE
Typically R
thejunctionofR
is usually very small (0.001 Ω to 0.1 Ω). If the trace and solder-junction resistances between
ISENSE
andISENSEandthejunctionofR
andR
aregreaterthan10%oftheR
value used in the calculation above.
ISENSE
ISENSE
ISET ISENSE
value, then these resistance values should be added to the R
ISENSE
Table 2 shows some of the current sense resistors available in the market.
Table 2. Some Current Sense Resistors
CURRENT RANGE
PART NUMBER
DESCRIPTION
MANUFACTURER
(A)
0 to 1
1 to 2
2 to 4
4 to 6
6 to 8
8 to 10
WSL-1206, 0.05 1%
WSL-1206, 0.025 1%
WSL-1206, 0.015 1%
WSL-2010, 0.010 1%
WSL-2010, 0.007 1%
WSR-2, 0.005 1%
0.05 Ω, 0.25 W, 1% resistor
0.025 Ω, 0.25 W, 1% resistor
0.015 Ω, 0.25 W, 1% resistor
0.010 Ω, 0.5 W, 1% resistor
0.007 Ω, 0.5 W, 1% resistor
0.005 Ω, 0.5 W, 1% resistor
Vishay Dale
15
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
APPLICATION INFORMATION
setting the power-good threshold voltage
The two feedback resistors R
resistor divider setting the voltage at the VSENSE pins. VSENSE voltage equals to
and R
connected between V and ground form a
VSENSE_TOP
VSENSE_BOT O
V
= V × R /(R + R
)
VSENSE_BOT
I(SENSE)
O
VSENSE_BOT VSENSE_TOP
Thisvoltageiscomparedtoaninternalvoltagereference(1.225V±2%)todeterminewhethertheoutputvoltage
level is within a specified tolerance. For example, given a nominal output voltage at V , and defining V
as the minimum required output voltage, then the feedback resistors are defined by:
O
O_min
V
1.225
1.225
Start the process by selecting a large standard resistor value for R
O_min
R
R
VSENSE_TOP
VSENSE_BOT
to reduce power loss. Then
VSENSE_BOT
R
than V
can be calculated by inserting all of the known values into the equation above. When V is lower
, PWRGD will be low as long as the controller is enabled.
VSENSE_TOP
O
O_min
undervoltage lockout (UVLO)
The TPS2330/TPS2331 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on
the VREG pin. This feature will disable the external MOSFET if the voltage on VREG drops below 2.78 V
(nominal) and will re-enable normal operation when it rises above 2.85 V (nominal). Since VREG is fed from
IN through a low-dropout voltage regulator, the voltage on VREG will track the voltage on IN within 50 mV. While
the undervoltage lockout is engaged, GATE is held low by an internal PMOS pulldown transistor, ensuring that
the external MOSFET transistor remain off at the times, even if the power supply has fallen to 0 V.
power-up control
The TPS2330/TPS2331 includes a 500 µs (nominal) startup delay that ensures that internal circuitry has
sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only
upon the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout
circuitry will provide adequate protection against undervoltage operation.
3-channel hot-swap application
Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensing
of the status of the output power on all three of the voltage rails. One such application is device bay, where dv/dt
control of 3.3 V, 5 V, and 12 V is required. By using TPS2330/TPS2331 to drive all three power rails, as is shown
below, TPS2330/31 can deliver three different voltages to three loads while monitoring the status of one of the
loads.
16
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
APPLICATION INFORMATION
System
Board
V
3.3 V IN2
O2
1 µF 10 µF
+
R
g2
R
g3
V
V
5 V IN3
O3
1 µF 10 µF
1 µF 10 µF
+
+
R
SENSE
12 V IN1
O1
R
R
VSENSE_TOP
R
ISET
VSENSE_BOTTOM
R
g1
0.1 µF
V
IN ISET ISENSE GATE DISCH VSENSE
reg
ENABLE
ENABLE
DGND
FAULT
FAULT
PWRGD
PWRGD
TPS2331
AGND
TIMER
Figure 19. Three-Channel Application
Figure 29 shows ramp-up waveforms of the three output voltages.
V
O1
V
V
O3
O2
t – Time – 2.5 ms/div
Figure 20
17
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SINGLE HOT SWAP POWER CONTROLLER WITH
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SLVS277A – MARCH 2000– REVISED APRIL 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
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Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
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