TPS23521PWR [TI]
具有双路电流限制和双路栅极驱动的 -10V 至 -80V 热插拔控制器 | PW | 16 | -40 to 125;
| 型号： | TPS23521PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有双路电流限制和双路栅极驱动的 -10V 至 -80V 热插拔控制器 | PW | 16 | -40 to 125 栅极驱动 控制器 光电二极管 |
| 文件： | 总38页 (文件大小：1842K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS23521
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
TPS23521：–48V 高性能热插拔控制器
1 特性
3 说明
1
•
–10V 至 –80V 直流工作电压，绝对最大电压为
TPS23521 是一款高性能热插拔可使大功率电信系统
–200V
符合严苛的瞬态要求。该器件具有 200V 的绝对最大额
定电压，因此可轻松通过雷击浪涌测试 (IEC61000-4-
5)。借助软启动电容器断开功能，可通过限制浪涌电流
来使用较小的热插拔 FET，而不会影响瞬态响应。双
路热插拔栅极驱动器可以在需要多个热插拔 FET 的 应
用 中节省空间并降低 BOM 成本。400µA 拉电流支持
快速恢复，有助于避免雷击浪涌测试期间的系统复位。
借助双路限流功能，可轻松达到 ATIS 0600315.2013
等标准所规定的掉电和输入阶跃要求。最后，该器件还
可提供带可编程阈值和迟滞的精确欠压和过压保护。
•
•
•
•
软启动电容器断开
双路热插拔栅极驱动器
400µA 栅极拉电流
双路限流（基于 VDS
）
–
–
25mV ±4%（VDS 低时）
3mV ±25%（VDS 高时）
•
可编程过压 (±1.5%) 与欠压 (±2%)
可编程迟滞 (±11%)
–
•
•
超时后重试
16 引脚 TSSOP 封装
器件信息(1)
器件型号
TPS23521
封装
封装尺寸（标称值）
2 应用
TSSOP (16)
5.00mm x 4.40mm
•
•
•
•
•
远程无线电单元
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
基带单元
路由器和切换器
小型基站
–48V 电信基础设施
简化原理图
RTN
To
Load
COUT
VCC
Vref/PG
CSS
1 k
-48 V_OUT
SS
D
R1
TPS23521 PW
RD
UVEN
OV
Q1
Optional
Q2
GATE
GATE2
SNS
R2
R3
TMR
VEE
PROG
CSS,VEE
CTMR
RSNS
-48 V
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDX2
TPS23521
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
目录
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 8
6.7 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 10
9
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 器件和文档支持 ..................................................... 30
12.1 器件支持................................................................ 30
12.2 文档支持 ............................................................... 30
12.3 接收文档更新通知 ................................................. 30
12.4 社区资源................................................................ 30
12.5 商标....................................................................... 30
12.6 静电放电警告......................................................... 30
12.7 Glossary................................................................ 30
13 机械、封装和可订购信息....................................... 30
7
8
7.1 Relationship between Sense Voltage, Gate Current,
and Timer................................................................. 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (September 2017) to Revision A
Page
•
已更改 将“预告信息”更改成了“生产数据” ................................................................................................................................ 1
2
Copyright © 2017, Texas Instruments Incorporated
TPS23521
www.ti.com.cn
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
5 Pin Configuration and Functions
PW Package
16-Pin (TSSOP)
Top View
NC
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Vref/PG
PROG
NC
GATE2
NC
VCC
UVEN
OV
VEE
SNS
GATE
SS
TMR
D
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NC
NO.
1
No connect.
No connect .
NC
2
GATE2
NC
3
O
Gate driver for the 2nd hot swap FET. NC if feature isn’t used.
No connect.
4
This pin corresponds to the IC GND. Kelvin sense to the bottom of RSNS to ensure accurate
current limit.
VEE
5
GND
Sense pin, used to measure current and regulate it. Kelvin Sense to RSNS to ensure accurate
current limits.
SNS
6
7
I
GATE
O
Gate drive for the main hot swap FET.
Pin used for soft starting the output. Connect a capacitor (CSS) between the SS pin and
-48V_OUT. The dv/dt rate on the -48V_OUT pin is proportional to the gate sourcing current
SS
D
8
9
O
I
divided by CSS
.
Pin used to sense the drain of the hot swap FET and to program the threshold where the hot
swap switches from the CL1 and CL2. Connect a resistor from this pin to the drain of the hot
swap FET (also called -48V_OUT) to program the threshold.
Timer pin used to program the duration when the hot swap FET can be in current limit.
Program this time by adding a capacitor between the TMR pin and VEE.
TMR
OV
10
11
12
O
I
Input over voltage comparator. Tie a resistor divider to program the threshold where the
device turns off due to over voltage event.
Input under voltage comparator. Tie a resistor divider to program the threshold where the
device turns on.
UVEN
I
VCC
NC
13
14
S
Clamped supply. Tie to RTN through resistor.
No connect.
Adjust current limit and fast trip threshold by tying to VEE, floating, or tying to VEE through
resistor.
PROG
15
I
5V reference output. Connect to the base of a BJT to generate a rail that can be used to
power current monitors and digital Isolators. It can also be used as a PG for the downstream
DC/DC converters.
Vref/PG
16
O
Copyright © 2017, Texas Instruments Incorporated
3
TPS23521
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX
20
UNIT
V
Supply voltage
Input voltage
VVCC (current into VCC <10 mA)
VSNS, VOV
6.5
V
VUVEN, VD, VSS
30
V
VGATE, VGATE2
VCC
6.5
V
Output voltage
VTMR , VPROG, VVREF/PG
V
Operating junction temperature, TJ
Storage temperature, Tstg
125
150
°C
°C
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX
20
UNIT
V
VVCC
Supply voltage (current into VCC <10 mA)
Input voltage
VSNS, VOV
0
5.5
V
VUVEN, VD, VSS
VGATE, VGATE2
Input voltage
0
18
V
Output voltage
0
VCC
5.5
V
VTMR , VPROG, VVREF/PG Output voltage
0
V
CSS
RSS
RD
Capacitance
Resistance
Resistance
1
200
10
nF
kΩ
kΩ
1
120
2,000
6.4 Thermal Information
TPS23521
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
98.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
31.3
44.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.8
ψJB
43.6
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
TPS23521
www.ti.com.cn
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
6.5 Electrical Characteristics
–40°C ≤ TJ ≤125°C, 1.1 mA < IVCC < 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx = Hi-Z , V(TMR) = 0 V,
VVref,PG = VPROG = Hi-Z; All pin voltages are relative to VEE (unless otherwise noted)
PARAMETER
VCC – Clamped Supply
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(UVLO_VCC)
UVLO on VCC
rising
9
9.5
1
10
V
V
V(UVLO_VCC,hyst)
UVLO hysteresis on VCC
hysteresis
1.1< I(VCC) < 10 mA (current into
VCC)
V(VCC)
VCC regulation
12
14.5
18
V
VVCC = 10 V. Off
1
1
mA
mA
mA
IQ
Quiescent Current
VVCC = 10 V. On
VVCC = 10 V, Gate in regulation
1.1
UVEN – Under Voltage and Enable
V(UVEN_T) Threshold voltage for V(UVEN)
0.985
9
1
1.015
11.2
V
Hysteresis current, sourcing
from UV pin
I(UV_hyst)
VUV = 1.5 V
10
µA
OV – Over Voltage
V(OV_T)
Threshold voltage for VOV
0.98
9
1
1.02
11.2
V
Hysteresis current, sourcing
from OV pin
I(OV_hyst)
TMR – Timer
VTMR
VOV = 1.5 V
10
µA
Voltage on timer when part
times out.
VD = 0 V, TMR ↑, measure VTMR
when VGATE = 0
1.47
0.735
9
1.5
0.75
10
1.53
0.765
11
V
Voltage on timer when part
times out.
VD = 1 V, TMR ↑, measure VTMR
when VGATE = 0
VTMR2
V
VSNS = 0.1 V, VD = 0 V, VTMR = 0 V,
measure I out from TMR
µA
µA
µA
Timer Sourcing current when
in fault condition or when
retrying.
ITMR,SRs
VSNS = 0.1 V, VD = 2 V, VTMR = 0 V,
measure I out from TMR
45
50
55
Timer sinking current when
not in fault condition.
ITMR,SNC
VSNS = 0 V, VD = 0 V, VTMR = 2 V,
1.5
2
2.5
Voltage on timer when the
VSNS = 0 V, VD = 0 V, TMR ↑ = 2 V,
VTMR,RETRY
timer starts going back up in TMR ↓, measure VTMR when I into
0.475
0.5
0.525
V
retry. Retry version only.
TMR change polarity
Number of retry duty cycles.
Retry version only.
NRETRY
DRETRY
64
Retry duty cycle. Retry
version only.
0.4%
Gate Sourcing Current
VG = 5 V, VD = 2 V, VSNS ↑,
IGATE,TIMER
VSNS,TMR1
VSNS,TMR2
Threshold When timer starts measure IGATE when TMR sources
5
1.5
10
2.5
15
µA
mV
mV
to run.
current
VD = 2 V, VTMR = 0 V, VG = 5 V;
Sense Voltage when Timer
starts to run.
VSNS ↑, measure VSNS when TMR
sources current
VD = 0 V, VTMR = 0 V , VG = 5 V;
Sense Voltage when Timer
starts to run.
VSNS ↑, measure VSNS when TMR
23.25
24.5
sources current
SNS – Sense Pin For Current Limit
Leakage current on sense
ISNS,LEAK
-2
2
µA
pin
PROG = Float
PROG = VEE
PROG = FLOAT
PROG = VEE
RPROG = 78.7kΩ
RPROG = 162 kΩ
24
38
25
40
26
42
mV
mV
mV
mV
mV
mV
VTMR = 0 V. VGATE = 5 V. VD = 0 V,
VSNS,CL1
VSNS ↑, measure when IGATE = 0;
45
50
55
VTMR = 0 V. VGATE = 5 V. VD = 0 V,
SNS ↑,measure when IGATE> 100
mA
72
80
88
VSNS,FST
V
110
68
120
75
130
82
Copyright © 2017, Texas Instruments Incorporated
5
TPS23521
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
–40°C ≤ TJ ≤125°C, 1.1 mA < IVCC < 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx = Hi-Z , V(TMR) = 0 V,
VVref,PG = VPROG = Hi-Z; All pin voltages are relative to VEE (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VTMR = 0 V, VGATE = 5 V, VD = 5 V,
VSNS,CL2
Fold Back Current Limit
2.25
3
3.75
mV
V
SNS ↑, measure when IGATE = 0;
VTMR = 0 V, VGATE = 5 V, VD = 5 V,
SNS ↑, Measure when IGATE> 100
mA
PROG – Programing Pin to Set Current Limit (CL) and Fast Trip
VSNS,FST2
Fast Trip during start-up
V
6
9
12
mV
iPROG
PROG pin current
7.9
10.1
12
µA
V
Threshold on VPROG, where the fast
trip setting changes from 80mV to
120mV.
VPROG,LOW
Prog pin voltage
0.48
Threshold on VPROG, where the
current limit setting changes from
25mV to 40mV.
VPROG,MID
Prog pin voltage
Prog pin voltage
0.94
2.4
1.23
1.51
V
V
Threshold on VPROG, where the fast
trip setting changes from 80mV to
120mV.
VPROG,High
GATE – Gate Drive for Main Hot Swap FET
V(VCC-GATE)
Output gate voltage
V(SNS) = 0 V
1
V
Sourcing Current during
normal operation.
V(TMR) = 0 V. V(GATE) = 8 V. VD = 0
V, V(SNS) = 0 V
I(GATE,SRS,NORM)
250
400
µA
Sourcing Current during star- V(TMR) = 0 V. V(GATE) = 5 V. VD = 0
I(GATE,SRS,START)
I(GATE,wkpd)
15
3
20
5
25
7
µA
mA
A
up
V, V(SNS) = 0 V
Weak pull down current
V(SNS) = 0 V. VUVEN = 0 V
Fast Pull down current with
10mV overdrive
I(GATE,FST)
0.4
1
1.5
GATE2 – Gate Drive for Auxiliary Hot Swap FET
V(VCC-GATE2)
I(GATE2,wkpd)
I(GATE2,SRC)
Output gate voltage
weak pull down
V(SNS) = 0 V
VGATE = 0 V
1
V
5
mA
µA
Sourcing Current
50
Fast Pull down current with
10 mV overdrive
IGATE2,FST
VGATE,TH
0.4
1
7.25
0.5
1.5
8
A
V
V
Threshold on VGATE when
GATE2 turns on
Raise VGATE, measure when VGATE2
comes up.
6.25
Hysteresis of threshold on
VGATE when GATE2 turns on
VGATE,TH,hyst
D – Drain Sense
R(D,INT)
hysteresis
Resistance from the drain pin
to GND.
28.5
1.46
30
31.5
1.54
kΩ
Voltage on drain that
switches between two current 20 mV, D↑, measure V when I(GATE)
V(TMR) = 0 V, V(GATE) = 5 V, V(SNS) =
V(D,CL_SW)
1.5
V
limits
= 0
V(TMR) = 1 V, V(GATE) = 5 V, V(SNS)
20 mV, D↑, measure V when I(GATE)
= 0
=
Voltage on drain that
switches the VTMR threshold.
V(D,TMR_SW)
0.73
100
4
0.75
75
0.77
V
V(D,TMR_SW,hyst)
hysteresis for V(D,TMR,SW)
hysteresis
mV
SS (Soft Start)
Pull down current when not in
inrush
I(SS,PD)
VSS = 5 V
mA
Resistance between GATE
and SS in the start-up phase
R(SS,GATE)
80
Ω
Vref/PG
VVref/PG
Reference output
0 < IVref/PG < 800 µA
4.9
5.5
V
6
Copyright © 2017, Texas Instruments Incorporated
TPS23521
www.ti.com.cn
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
Electrical Characteristics (continued)
–40°C ≤ TJ ≤125°C, 1.1 mA < IVCC < 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx = Hi-Z , V(TMR) = 0 V,
VVref,PG = VPROG = Hi-Z; All pin voltages are relative to VEE (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
7.25
2
MAX
UNIT
V
Raise GATE2 until Vref/PG goes
high
VGATE2,PG
IVref/PG
6.5
8
VVref/PG SC current
Vref/PG ON, VVref/PG (shorted)
mA
OTSD (Over Temperature Shut Down)
TSD
Shutdown temperature
Temp Rising
135
155
8
175
°C
°C
Shutdown temperature
Hysteresis
TSD,hyst
Copyright © 2017, Texas Instruments Incorporated
7
TPS23521
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC – Clamped Supply
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVCC: 0 V → 10 V, measure delay
before VGATE
tID
Insertion Delay
32
ms
↑
UVEN
TUV,degl
OV
Deglitch on UVEN
Deglitch on OV
4
4
µs
µs
TOV,degl
SNS
VSNS steps from 0 mV to 60 mV.
Response time to large over current Measure time for GATE and GATE2
to come down.
TSNS,FST,R
ESP
300
ns
Vref/PG
Power Good ↑ (V(GATE) 0 V → 10 V)
Look for Vref/PG ↑
1
ms
ms
Deglitch of Vref/PG. (GATE2 =
unloaded, raise GATE, measure
delay between GATE and Vref/PG)
tVref/PG,DEG
L
Power Good ↓ (V(GATE) 10 V → 0 V)
Look for Vref/PG ↓
32
8
Copyright © 2017, Texas Instruments Incorporated
TPS23521
www.ti.com.cn
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
6.7 Typical Characteristics
Unless otherwise noted: –40°C ≤ TJ ≤125°C, 1.1 mA < IVCC < 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx
= Hi-Z , V(TMR) = 0 V, VVref/PG = VPROG = Hi-Z;
Ivcc injected into VCC pin
Figure 1. VCC Regulation Voltage vs Current and
VVCC = 10 V, Regulation is current limit
Figure 2. Iq vs Temperature and Operating Condition
Temperature
Figure 3. Isns Current Vs Temperature
Figure 4. VVref/PG vs Temperature and IVREF
Figure 5. VVCC-GATE vs Temperature
Copyright © 2017, Texas Instruments Incorporated
9
TPS23521
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
7 Parameter Measurement Information
7.1 Relationship between Sense Voltage, Gate Current, and Timer
The diagram below illustrates the relationship between the VSNS (voltage across RSNS), Gate current, and the
timer operation. The diagram is intended to help explain the various parameters in the electrical characteristic
table and is not drawn to scale.
Note that IGATE reduces as the sense voltage approaches the current limit threshold and it equals zero at the
current limit regulation point. To ensure that the timer always runs when the IC is in regulation the timer starts at
a slightly positive IGATE
.
Figure 6. Relationship Between Timer, Gate Current, and Sense Voltage (VGATE = 5 V)
10
Copyright © 2017, Texas Instruments Incorporated
TPS23521
www.ti.com.cn
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
8 Detailed Description
8.1 Overview
The TPS23521 is a high performance hot swap controller that enables high power telecom systems to comply
with stringent transient requirements. The soft start cap disconnect allows soft start at start-up and disconnects
the soft start cap during normal operation. This allows for the use of smaller hot swap FETs without hurting the
transient response. GATE2 is a second hot swap FET driver, which only turns ON when the main hot swap FET
is fully on. Thus the FETs driven by GATE2 don't need to have strong SOA. This saves space and BOM cost in
high power applications that require multiple hot swap FETs.The 400 µA sourcing current allows fast recovery,
which helps to avoid system resets during lightning surge tests. The dual current limit makes it easier to pass
brown outs and input steps such as required by the ATIS 0600315.2013. Finally, the TPS23521 offers accurate
under voltage and over voltage protection with programmable thresholds and hysteresis.
8.2 Functional Block Diagram
RTN
VCC
Vref/PG
Internal
Regulator
VINT
VINT,GD
& Band Gap
V1V
HS_ON
iHYST
To
Load
R1
R2
DIS_RTN
COUT
UVEN
OV
Logic, Timing, and
Control
Time Out
PROG
V1V
VING
OV_GD
V1.5V
RD
D
R3
VINT
iHYST
30k
CSS
1k
SS
SS
Disconnect
GATE2
Q2
Time
Out
VVCC
Current Limit
& Gate Drive
GATE
SNS
Q1
Timer
Block
in ILIM
HS_ON
IC_GND
RSNS
VEE
TMR
CTMR
-48V
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8.3 Feature Description
8.3.1 Current Limit
The TPS23521 utilizes two current limit thresholds:
•
•
ICL1 – also referred to as high current limit threshold, which is used when the VDS of the hot swap FET is low.
ICL2 – lower current limit threshold, which is used when the VDS of the hot swap FET is high.
This dual level protection scheme ensures that the part has a higher chance of riding out voltage steps and other
transients due to the higher current limit at low VDS, while protecting the MOSFET during start into short and hot-
short events, by setting a lower current limit threshold for conditions with high VDS. The transition threshold is
programmed with a resistor that is connected from the drain of the hot swap FET to the D pin of the TPS23521.
The figure below illustrates an example with a ICL1 set to 25 A and ICL2 set to 3 A. Note that compared to a
traditional SOA protection scheme this approach allows better utilization of the SOA in the 10 V < VDS. < 40-V
range, which is critical in riding through transients and voltage steps.
Note that in both cases the TPS23521 regulated the gate voltage to enforce the current limit. However, this
regulation is not very fast and doesn’t offer the best protection against hot-shorts on the output. To protect in this
scenario a fast comparator is used, which quickly pulls down the gate in case of severe over current events (2x
bigger than VCL1).
Figure 7. Dual Current Limit vs FET Power Limit
8.3.1.1 Programming the CL Switch-Over Threshold
The VDS threshold when the TPS23521 switches over from ICL1 to ICL2 (VD,SW) can be computed using
Equation 1. For example, if a 15-V switch over is desired, RD should be set to 270 kΩ.
1.5 V ì 30 kß + R
(
)
D
VDS,SW
=
30 kß
(1)
8.3.1.2 Setting Up the PROG Pin
The PROG pin can be tied to VEE, left floating, or tied to VEE through a resistor to adjust VSNS,CL1 and the ratio
of fast trip to current limit. The options are set as follows:
●PROG = NC or Float: VSNS,CL1 = 25 mV, VSNS,FST is 2x VSNS,CL1
●RPROG = 196 kΩ (1%): VSNS,CL1 = 25 mV, VSNS,FST is 3x VSNS,CL1
12
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Feature Description (continued)
●RPROG = 66.5 kΩ (1%): VSNS,CL1 = 40 mV, VSNS,FST is 3x VSNS,CL1
●PROG = VEE: VSNS,CL1 = 40 mV, VSNS,FST is 2x VSNS,CL1
8.3.1.3 Programming CL1
The current limit at low VDS (ICL1) of the TPS23521 can be computed using Equation 2 below.
VSNS,CL1
ICL1
=
R SNS
(2)
(3)
To compute ICL1 for a 1-mΩ sense resistor use Equation 3 below.
VSNS,CL1
25 mV
ICL1
=
=
= 25 A
R SNS
1mß
8.3.1.4 Programming CL2
The current limit at high VDS (ICL2) of the TPS23521 can be computed using Equation 4 below.
VSNS,CL2
ICL2
=
R SNS
(4)
(5)
To compute ICL2 for a 1-mΩ sense resistor use Equation 5 below.
VSNS,CL2
3 mV
ICL2
=
=
= 3 A
R SNS
1mß
8.3.2 Soft Start Disconnect
The inrush current into the output capacitor (COUT) can be limited by placing a capacitor between the SS (Soft
Start) pin and the drain of the hot swap MOSFET. In that case the inrush current can be computed using
equation below.
COUT ì IGATE,SRS,START
660 µFì 20 µA
IINR
=
=
= 0.4 A
CSS
33 nF
(6)
Note that with most hot swap the CSS pin is tied simply to the gate pin, but this can interfere with performance
during normal operation if transients or short circuits are encountered. In addition the CSS capacitor tends to pull
up the gate during hot plug and cause shoot through current if it is always tied to the gate. For that reason the
TPS23521 has a disconnect switch between the gate pin and the SS pin as well as a discharge resistor. During
the initial hot plug and during the insertion delay the switch between SS and GATE is open and SS is being
discharged to GND through a resistor. Then during start-up SS and GATE are connected to limit the slew rate.
Once in normal operation the SS pin is not tied to GATE and it is not shorted to GND, which prevents it from
interfering with the operation during transients.
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Feature Description (continued)
CSS
SS 1 k
SS_Dis
CSS,GND
SS_ON
Q1
GATE
Figure 8. Implementation of SS Disconnect
8.3.3 Timer
Timer is a critical feature in the hot swap, which manages the stress level in the MOSFET. The timer will source
and sink current into the timer capacitor as follows:
•
•
Not in current limit: sink 2 µA
If the part is in current limit and VGATE < VGATE,TH, the timer sources current as follows:
–
–
VD < VD,CL_SW: source 10 µA
VD > VD,CL_SW: source 50 µA
The TPS23521 times out and shuts down the hot swap as follows.
•
•
If VD < VD,TMR_SW then the hot swap times out when VTMR reaches 1.5 V.
If VD > VD,TMR_SW then the hot swap times out when VTMR reaches 0.75 V.
The above behavior maximizes the ability of the hot swap to ride out voltage steps, while ensuring that the FET
remains safe even if the part can not ride out a voltage step.
A cool down period follows after the part times out. During this time the timer performs the following:
•
•
•
•
Discharge CTMR with a 2-µA current source until 0.5 V
Charge CTMR with a 10-µA current source until it is back to 1.5 V.
Repeat the above 64 times
Discharge timer to 0 V.
The part attempts to restart after finishing the above. If the UVEN signal is toggled while the 64 cycles are in
progress the part restarts immediately after the 64 cycles are completed.
The timer operates as follows when recovering from POR:
•
If VTMR < 0.5 V:
–
–
Proceed to regular startup
Do not discharge VTMR
•
If VTMR > 0.5 V:
–
–
–
Go through 64 charge/discharge cycles
Discharge VTMR
Proceed to startup
The Time Out (TTO) can be computed using the equations below. Note that the time out depends on the VDS of
the MOSFET.
14
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Feature Description (continued)
C TMR ì VTMR
TTO
=
ITMR,SRS
(7)
(8)
C TMR ì 1.5 V
10 mA
TTO(VD < 0.75 V) =
CTMR ì 0.75 V
10 mA
TTO(0.75 V < VD < 1.5 V) =
(9)
C TMR ì 0.75 V
TTO(VD > 1.5 V) =
50 mA
(10)
8.3.4 Gate 2
The TPS23521 features a second hot swap Gate drive, which can be used to save BOM cost and size in
applications that require multiple hot swap MOSFETs. The 2nd MOSFET is only turned ON when the main FET
is enhanced. As a result the 2nd MOSFET doesn't operate with large current and large voltage across it, thus
reducing the SOA requirements. In many cases a 5x6 QFN FET can replace a D2PACK FET. The following
figures show the operation during start-up and Hot Short event. It can be seen that the second FET is OFF
during stressful operation and turns on during normal operation to improve steady state efficiency and reduce
power losses.
Figure 9. Gate 2 Operation During Start-Up
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Feature Description (continued)
Figure 10. Gate2 Operation During Hot Short
8.4 Device Functional Modes
Figure 11. Simplified Hot Swap State Machine
The Figure above shows a simplified state machine of the hot swap controller. It has 4 distinct operating states
and the controller switches between these states based on the following signals:
•
Ving_rc: This means that both the input voltage is in the right range and the IC has power with Vcc. A 4-µs
delay is added for deglitching. If the input voltage is above the OV threshold, input voltage is below the UV
threshold, or VCC is below its internal UVLO, Ving_rc will be low.
•
TimeOut: This signal comes from the timer block and will be asserted Hi if the IC has timed out due to an
over-current condition. This signal is also Hi while the timer is going through the restart cycles. Once the
cycles are completed this signal will go Low.
16
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Device Functional Modes (continued)
•
•
ins_over: This signal states that the insertion delay has been completed and the hot swap is ready to start-up.
FT: this is the fast trip signal coming from the fast trip comparator. It goes Hi if an extreme over current event
is detected.
•
•
PG: Internal Power good signal. This is high when the hot swap is fully on and the load can draw full power.
For PG to be Hi, the GATE has to be Hi, GATE2 needs to be Hi, and the drain pin needs to be below 0.75 V.
PG_degl: This is a deglitched version of the PG and is the signal used to move between states and controls
the external PGb pin.
8.4.1 OFF State
In this state the hot swap FET is turned off and the controller is waiting to start-up. The controller can be in this
state due to any of these scenarios:
•
•
Input voltage is not in the valid range.
The hot swap is in the cool down state and the timer is going through the retry cycle after a fault condition
such as output hot short or over current.
•
VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.
8.4.2 Insertion Delay State
In this state the hot swap FET is turned off and the controller is waiting for the insertion delay to finish. This
allows the input supply to settle after a Hot Plug. If any of the following occur, the controller will be kicked back to
the OFF state:
•
•
Input voltage is not in the valid range.
VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.
Once the insertion delay is finished, the controller will move to the Start-up state.
8.4.3 Start-up State
In this state the controller is turning on and charging the output cap. The operation is set as follows:
•
•
•
The SS pin is internally connected to the GATE pin to allow for output dv/dt control.
Lower gate sourcing current is applied to the GATE pin to allow for smaller SS caps.
The lower current limit setting of VSNS,CL2 and a lower fast trip setting of VSNS,FST2 is used to minimize the
MOSFET stress in case of a fault condition.
If any of the following occur, the controller will be kicked back to the OFF state:
•
•
•
•
Input voltage is not in the valid range.
The timer times out due to over-current.
VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.
Fast trip is triggered.
Once the PG_degl signal goes Hi, the controller will move to the Normal Operation state.
8.4.4 Normal Operation State
In this state the hot swap is fully on and the operation is set as follows:
•
•
•
The SS pin is disconnected from the GATE pin to improve transient response.
The full gate sourcing current is used to improve transient response.
The current limit and fast trip threshold are a function of the D pin to optimize the transient response while
protecting the MOSFET.
If any of the following occur, the controller will be kicked back to the OFF state:
•
•
•
PG_degl goes low.
The timer times out due to over-current.
VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.
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Device Functional Modes (continued)
Note that if the input voltage is outside the valid range or the fast trip is triggered, the hot swap FET will turn off,
but the controller will not exit the Normal Operation state. In this case the PG signal would go low immediately. If
this condition persists, the PG_degl will go low as well and the controller would move to the OFF state. This
operation prevents the controller from re-starting the system during quick transients.
18
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS23521 is a hot swap controller for –48-V applications and is used to manage inrush current and protect
downstream circuitry and the upstream bus in case of fault conditions. The following key scenarios should be
considered when designing a –48-V hot swap circuit:
•
•
•
•
Start Up.
Output of a hot swap is shorted to ground while the hot swap is on. This is often referred to as a Hot Short.
Powering up a board when the output and ground are shorted. This is usually called a start-into-short.
Input lightning surge. Here it is usually desired to avoid damage to downstream circuitry and to avoid system
restarts.
These scenarios place a lot of stress on the hot swap MOSFET and the board designer should take special care
to ensure that the MOSFET stays within it's Safe Operating Area (SOA) under all of these conditions. A detailed
design example is provided below and the key equations are written out. Note that solving all of these equations
by hand is cumbersome and can result in errors. Instead, TI recommends using the TPS2352X Design
Calculator provided on the product page.
9.2 Typical Application
Figure 12. Application Diagram for Design Example
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Typical Application (continued)
9.2.1 Design Requirements
The table below summarizes the design parameters that must be known before designing a hot swap circuit.
When charging the output capacitor through the hot swap MOSFET, the FET’s total energy dissipation equals
the total energy stored in the output capacitor (1/2CV2). Thus both the input voltage and output capacitance will
determine the stress experienced by the MOSFET. The maximum load power will drive the current limit and
sense resistor selection. In addition, the maximum load current, maximum ambient temperature, and the thermal
properties of the PCB (RθCA) will drive the selection of the MOSFET's RDSON and the number of MOSFETs used.
RθCA is a strong function of the layout and the amount of copper that is connected to the drain of the MOSFET.
Air cooling will also reduce RθCA substantially. Finally, it's important to know what transients the circuit has to
pass in order to size up the input protection accordingly.
Table 1. Design Requirements for a –38 V to –60 V, 400-W Protection Circuit
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
–36 V to –72 V
1200 W
Maximum Load Power
Output Capacitance
4 x 330 µF
After EMI filter.
65°C
Location of Output Cap
Maximum Ambient Temperature
MOSFET RθCA (function of layout)
Pass “Hot-Short” on Output?
Pass a “Start into short”?
Is the load off until PG asserted?
20°C/W
Yes
Yes
Yes
9.2.2 Detailed Design Procedure
9.2.2.1 Selecting RSNS
Before selecting RSNS, first compute the maximum load current. For this example the worst case load current
happens at the minimum input voltage of 36 V. Thus the maximum current is 1200 W/36 V = 33.3 A. To provide
some margin, set the target current limit to 36.6 A (10% higher). Set VSNS,CL1 to 40mV by tying the PROG pin to
VEE and compute RSNS using equation below:
VSNS,CL1
40 mV
36.6A
RSNS,CLC
=
=
= 1.1 mW
ICL1
(11)
Use next available RSNS of 1 mΩ.
9.2.2.2 Selecting Soft Start Setting: CSS and CSS,VEE
First, compute the minimum inrush current where the timer will trip using equation below.
VSNS,TMR2,min
1.5 mV
IINR,TMR.min
=
=
= 1.5 A
RSNS
1 mW
(12)
To avoid running the timer the inrush current needs to be sufficiently low. Target 0.5 A of inrush current to allow
margin, and compute the target CSS using equation below. Note that a 10% total tolerance capacitance was
assumed on Cout.
COUT,MAX ìIGATE,SRS,START
1452 mFì20 mA
CSS
=
=
= 58.08 nF
I
0.5 A
INR,TGT
(13)
Chose CSS close to 58 nF. For this example 55 nF was used, which assumes a 33 nF and 22 nF cap in parallel.
This results in an inrush current of 0.53 A at max COUT (1452 µF) and inrush current of 0.48 A at typical COUT
(1320 µF). Also it is recommended to add a capacitor between the soft start pin and VEE (CSS,VEE) to improve
immunity to input voltage noise during soft start. It's recommended to chose a capacitor that's 3x larger than CSS
.
In this case a 150 nF capacitor was chosen.
20
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Finally the start-up time at maximum input voltage can be computed using the equation below:
CSS ì VIN,MAX
55 nFì72 V
20 mA
TSTART (VIN,MAX ) =
=
= 198 ms
IGATE,SRS,START
(14)
9.2.2.3 Selecting VDS Switch Over Threshold
The VDS threshold where the current limit switches from CL1 to CL2 can be programmed using RD. In general a
higher threshold improves ability to ride through voltage steps, brown outs, and other transients. However, a
larger setting can also expose the MOSFET to more stress, because the larger current limit is now allowed at
higher VDS voltages. If there are no specific voltage step requirements, 20 V is a good starting point. Use the
equation below to compute the target RD.
V
≈
∆
«
’
DS,SW
R = 30 kW ì
- 1 = 370 kW
÷
D
1.5 V
◊
(15)
9.2.2.4 Timer Selection
The timer determines how long the hot swap can be in current limit before timing out and can be programmed
using CTMR. In general a longer time out (TTO) improves ability to ride through voltage steps, brown outs, and
other transients. However, a larger setting can also expose the MOSFET to more stress, because it takes longer
for the FET to shut down during fault conditions. If there are no specific voltage step or transient requirements, 2
ms is a good starting point. Use the equation below to compute the target CTMR. Choose the next available
capacitor value of 15 nF, which results in a 2.25 ms time out.
TTO ìITMR,SRS
2 msì10 mA
CTMR
=
=
= 13.3 nF
VTMR
1.5 V
(16)
9.2.2.5 MOSFET Selection and SOA Checks
When selecting MOSFETs for the –48 V application the three key parameters are: VDS rating, RDSON, and safe
operating area (SOA). For this application the PSMN4R8-100BSE was selected as the Main hot swap FET (Q1)
to provide a 100 V VDS rating, low RDSON, and great SOA. Since this is a high power application 2
CSD19532Q5B FETs were used as auxiliary FETs (Q2) to reduce steady state power dissipation. After selecting
the MOSFET, it is important to double check that it has sufficient SOA to handle the key stress scenarios: start-
up, output Hot Short, and Start into Short. MOSFET's SOA is usually specified at a case temperature of 25°C
and should be derated based on the maximum case temperature expected in the application.
First, compute how much current will flow through Q1 using a current division formula shown below. For this
example the FET RDSON at 100°C was used. RDSON of Q1 (RDSON1) is 4.8 mΩ (PSMNR8-100BSE max RDSON at
25°C) x 1.8 (temperature coefficient), which equals 8.64 mΩ. RDSON of Q2 (RDSON2) is 4.9 mΩ (CSD19532Q5B
max RDSON at 25°C) x 1.6 (temperature coefficient), which equals 7.84 mΩ.
RDSON2
7.84 mW
N2
2
IQ1,MAX = ILOAD,MAX
ì
=
ì 33.3 A = 10.4 A
RDSON2
N2
7.84 mW
+ 8.64mW
+RDSON1
2
(17)
Next the maximum temperature of Q1 can be computed using the equations below.
TC,MAX = TA,MAX + RqCA ì (IQ1,MAX )2 ì RDSON(TJ )
(18)
(19)
C
2
TC,MAX = 65èC + 20è ì 10.4A ì8.64mW = 83.7èC
(
)
W
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Next the stress the MOSFET will experience during operation should be compared to the FETs capability. First,
consider the power up. The inrush current with max COUT will be 0.53 A and the inrush will last for 198 ms. Note
that the power dissipation of the FET will start at VIN,MAX × IINR and reduce to zero as the VDS of the MOSFET is
reduced. The SOA curve of a typical MOSFET assume the same power dissipation for a given time. A
conservative approach is to assume an equivalent power profile where PFET = VIN,MAX × IINR for t = Tstart-up /2. In
this instance, the SOA can be checked by looking at a 72 V, 0.53 A, 99 ms pulse. Based on the SOA of the
PSMN4R8-100BSE, it can handle 72 V, 3 A for 10 ms and it can handle 72 V, 1.3 A for 100 ms. The SOA at TC
= 25°C for 99 ms can be extrapolated by approximating SOA vs time as a power function as shown in equations
below:
ISOA t = a ì t m
( )
(20)
≈
’
ISOA
t
( )
1
≈
’
3A
∆
∆
«
÷
÷
◊
ln
ln
∆
÷
ISOA (t 2 )
1.3A
«
◊
m =
a =
=
= -0.36
≈
’
≈
’
10 ms
t1
t 2
ln
ln
∆
∆
÷
÷
∆
÷
◊
100 ms
«
«
◊
(21)
ISOA (t 2 )
1.3A
=
= 6.82 A ì (ms)0.36
-0.36
tm2
100ms
(22)
(23)
ISOA 99 ms,25èC = 6.82 A ì(ms)0.36 ì(99 ms)-0.36 =1.3 A
Finally, the FET SOA needs to be derated based on the maximum case temperature as shown below. Note that
the FET can handle 0.79 A, while it will have 0.53 A during start-up. Thus there is a lot of margin during this test
condition.
175èC -83.7èC
175C 25C
ISOA 99 ms,T
= 1.3A ì
= 0.79A
C,MAX
(24)
A similar approach should be taken to compute the FETs SOA capability during a Hot Short and start into short.
As shown in the following figure, during a start into short the gate is coming up very slowly due to a large
capacitance tied to the gate through the SS pin. Thus it is more stressful than a Hot Short and should be used for
worst case SOA calculations. To compare the FET stress during start-up into short to the SOA curves the stress
needs to be approximated as a square pulse as showing in the figure below. In this example, the stress is
approximated with a 1.3 ms (Teq), 3 A, 72 V pulse. The FET can handle 18 A, 72 V for 1 ms and 3 A, 72 V for
10 ms. Using approximation and temp derating as shown earlier, the FET's capability can be computed as 8.9 A,
72 V, for 1.3 ms at 83.7°C. 8.9 A is significantly larger than 3 A implying great margin.
22
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Figure 13. Teq During a Start Into a Short
The final operating point to check is the operation with high current and VDS just below the VDS,SW threshold. In
this example, the time out would be 1.1ms (one half of the time out at Vd = 0 V), the current will be 40 A, and the
voltage would be 20 V. Looking up the SOA curve, the FET can handle 100 A, 20 V for 1 ms and 40 A, 20 V for
10 ms. Repeating previously shown approximations and temp derating, the FET's capability is computed to be 58
A, 20 V, for 1.1 ms at 83.7°C. Again this is below the worst case operating point of 40 A and 20 V suggesting
good margin.
9.2.2.6 EMI Filter Consideration
In this example it is assumed that the EMI filter is right after the hot swap and the bulk cap is after the EMI filter.
The EMI filter adds significant inductance and needs to be accounted for. During a Hot Short, the inductor builds
up significant current that needs to go somewhere after the FET opens. For that a free wheeling diode should be
used along with a snubber. For this example a 150 V, SMA diode was used: STPS1150A. The snubber
consisted of a 10-Ω resistor in series with a 1-µF ceramic capacitor. In addition a 0.1-µF ceramic cap was tied
directly on the output.
9.2.2.7 Under Voltage and Over Voltage Settings
Both the threshold and hysteresis can be programmed for under voltage and over voltage protection. In general
the rising UV threshold should be set sufficiently below the minimum input voltage and the falling OV threshold
should be set sufficiently above the maximum input voltage to account for tolerances. For this example a rising
UV threshold of 35 V and a falling UV threshold of 33 V was chosen as the target. First, choose RUV1 based on
the 2 V UV hysteresis as shown below.
VUV,hyst,tgt
2 V
RUV1
=
=
= 200 kßd
iUV,hyst
10 µA
(25)
Once RUV1 is known RUV2 can be computed based on the target rising UV threshold as shown below.
RUV1
200 kW
RUV2
=
=
= 5.88 kW
VUV,TGT,Rising - 1V 35 V -1 V
(26)
23
The OV setting can be programmed in a similar fashion as shown in equations below.
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VOV,hyst,tgt
2 V
ROV1
=
=
= 200 kW
200 kW
iOV,hyst
ROV1
10 mA
(27)
(28)
ROV2
=
=
= 2.67 kW
VOV,TGT,Rising -1 V 76 V -1 V
Optional filtering capacitors can be added to the UV and OV to improve immunity to noise and transients on the
input bus. These should be tuned based on system requirements and input inductance. In this example place
holders were added to the PCB, but the components were not populated.
9.2.2.8 Choosing RVCC and CVCC
The VCC is used as internal supply rail and is a shunt regulator. To ensure stability of internal loop a minimum of
0.1 µF is required for CVCC. To ensure reasonable power on time it is recommended to keep CVCC below 1 µF.
RVCC should be sized in such a way to ensure that sufficient current is supplied to the IC at minimum operating
voltage corresponding to the falling UV threshold. To allow for some margin it is recommended that the current
through RVCC is at least 1.2x of IQ,MAX when RTN = Falling UV threshold and VCC = 10 V (minimum
recommended operating voltage on VCC). For this example RVCC of 16.2 kΩ was used.
9.2.2.9 Power Good Interface to Downstream DC/DC
It is critical to keep the downstream DC/DC off while the hot swap is charging the bulk capacitor. This can be
accomplished through the PGb pin. Note that the VEE of the hot swap and the DC/DC are different and the
Power Good cannot be directly tied to the EN or UV of the DC/DC. The application circuit below provides a
simple way to control the downstream converter with the PGb pin of the hot swap.
Figure 14. Interface to DC/DC
24
Copyright © 2017, Texas Instruments Incorporated
TPS23521
www.ti.com.cn
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
9.2.3 Application Curves
Figure 15. Start Up (Vin = 36 V)
Figure 16. Start Up (Vin = 48 V)
Figure 17. Start Up (Vin = 72 V)
Figure 18. Start Up (Showing GATE2 and Vref/PG)
Zoomed In
Figure 19. Hot Short (Vin = 72 V, no load)
Figure 20. Hot Short (Vin = 72 V, no load)
Copyright © 2017, Texas Instruments Incorporated
25
TPS23521
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
Figure 21. Hot Short (Vin = 72V, 1.2kW load)
Figure 22. Gradual Over Current
Figure 23. Retry Behavior
Figure 24. Start Into Short (Vin =72V)
Figure 25. Start Into Short (Zoomed in)
26
Copyright © 2017, Texas Instruments Incorporated
TPS23521
www.ti.com.cn
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
OR-ing circuit between surge and EVM
OR-ing circuit between surge and EVM
Figure 26. +2kV (2Ω) Lightning Surge
Figure 27. +2kV (2Ω) Lightning Surge (zoomed in)
OR-ing circuit between surge and EVM
Figure 28. -2kV (2Ω) Lightning Surge
OR-ing circuit between surge and EVM
Figure 29. -2kV (2Ω) Lightning Surge (zoomed in)
Copyright © 2017, Texas Instruments Incorporated
27
TPS23521
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
10 Power Supply Recommendations
In general, the TPS23521 is designed to have robust operation from a non-ideal –48 V bus with various
transients such as the lightning surge. The IC is powered through RVCC making it more immune to supply drop
outs and high voltage spikes. Regardless, TI recommends following several key precautions:
•
•
•
Always test the solution with the various transients that can be encountered in the systems. This especially
applies to transients that were not tested with TI’s EVM.
If large input ripple is expected during start-up, increase the ratio of CSS, VEE to CSS to reduce input current
ripple at start-up.
Operating from large input inductance (>40 µH) can cause instability to the current limit loop or oscillations
during start-up. Add a capacitor from Gate to VEE to help stabilize the current limit loop. Add an input
snubber if oscillations are observed at start-up.
28
Copyright © 2017, Texas Instruments Incorporated
TPS23521
www.ti.com.cn
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
11 Layout
11.1 Layout Guidelines
There are several things to keep in mind during layout of the TPS23521 circuit:
● The VEE and SNS pin need to have a Kelvin Sense connection to the sense resistor.
● The VEE trace carries current and needs to be thick and short in order to minimize IR drop and to avoid
introducing current sensing error.
● It is recommended to use a net-tie to separate the power plane coming into the RSNS and the Kelvin connection
to VEE.
● Connect the UVEN resistor divider, OV resistor divider, and TMR cap to the "VEE" to insure maximum
accuracy.
● The filtering caps on SNS should be placed as close to the IC as possible.
11.2 Layout Example
Figure 30. Layout Example
版权 © 2017, Texas Instruments Incorporated
29
TPS23521
ZHCSHW5A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 文档支持
12.2.1 相关文档
如需相关文档，请参阅：
•
《TPS23525EVM-815 评估模块用户指南》(SLVUB36)
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的提醒我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，也
不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航栏。
30
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS23521PWR
TPS23521PWT
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
23521
23521
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS23521PWR
TPS23521PWT
TSSOP
TSSOP
PW
PW
16
16
2000
250
330.0
180.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS23521PWR
TPS23521PWT
TSSOP
TSSOP
PW
PW
16
16
2000
250
356.0
210.0
356.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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