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TPS23525

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

TPS23525：–48V 热插拔and Dual OR-ing控制器

1 特性

3 说明

1

•

–10V 至 –80V 直流工作电压，绝对最大电压为

TPS23525 是一款集成式热插拔双路 OR-ing 控制器，

–200V

可使大功率电信系统符合严苛的瞬态要求。该器件具有

200V 的绝对最大额定电压，因此可轻松通过雷击浪涌

测试 (IEC61000-4-5)。借助软启动电容器断开功能，

可通过限制浪涌电流来使用较小的热插拔 FET，而不

会影响瞬态响应。400µA 拉电流支持快速恢复，有助

于避免雷击浪涌测试期间的系统复位。借助双路限流功

能，可轻松达到 ATIS 0600315.2013 等标准所规定的

掉电和输入阶跃要求。最后，该器件还可提供带可编程

阈值和迟滞的精确欠压和过压保护。

•

软启动电容器断开

400µA 栅极拉电流

双路限流（基于 V_DS

）

–

25mV ±4%（V_DS低时）

3mV ±25%（V_DS高时）

•

可编程过压 (±1.5%) 与欠压 (±2%)

可编程迟滞 (±11%)

集成式双路 OR-ing 控制器

–

调整电压：25mV ±15mV

TPS23525 集成有双路 OR-ing 控制器，因此非常适合

用于由两个冗余电源供电的 –48V 系统。

快速关断电压：–6mV ±4mV

•

超时后重试

器件信息⁽¹⁾

16 引脚 TSSOP 封装

器件型号

TPS23525

封装

封装尺寸（标称值）

2 应用

TSSOP (16)

5.00mm x 4.40mm

•

远程无线电单元

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

基带单元

路由器和切换器

小型基站

–48V 电信基础设施

简化电路原理图

RTN

VCC

R₁

UVEN

OV

PGb

To

Load

C_OUT

R₂

R₃

C_SS

1 k

SS

-48 V_OUT

TPS23525 PW

1 k

Neg48B

Neg48A

GATEA

D

R_D

1 k

Q₁

GATE

SNS

GATEB

TMR

C_TMR

VEE

R_SNS

C_SS,VEE

Q₂

-48 V_A

Q₃

-48 V_B

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSDX0

TPS23525

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

www.ti.com.cn

8.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 15

Application and Implementation ........................ 18

9.1 Application Information............................................ 18

9.2 Typical Application ................................................. 18

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 8

6.7 Typical Characteristics.............................................. 9

Parameter Measurement Information ................ 10

9

10 Power Supply Recommendations ..................... 31

11 Layout................................................................... 32

11.1 Layout Guidelines ................................................. 32

11.2 Layout Example .................................................... 32

12 器件和文档支持 ..................................................... 33

12.1 器件支持................................................................ 33

12.2 文档支持 ............................................................... 33

12.3 接收文档更新通知 ................................................. 33

12.4 社区资源................................................................ 33

12.5 商标....................................................................... 33

12.6 静电放电警告......................................................... 33

12.7 Glossary................................................................ 33

13 机械、封装和可订购信息....................................... 33

7

8

7.1 Relationship between Sense Voltage, Gate Current,

and Timer................................................................. 10

Detailed Description ............................................ 11

8.1 Overview ................................................................. 11

8.2 Functional Block Diagram ....................................... 11

4 修订历史记录

Changes from Revision A (October 2017) to Revision B

Page

•

Changed Input voltage V_Neg48A, V_Neg48BMIN value from -1 V to -0.3 V.................................................................................. 4

Added Input voltage V_Neg48A, V_Neg48Bthrough 1-kΩ resistor ................................................................................................... 4

Changes from Original (October 2017) to Revision A

Page

•

Changed V_{(D,CL_SW)}MIN from 1.47 V to 1.46 V ..................................................................................................................... 6

Changed V_{(D,CL_SW)}MAX from 1.53 V to 1.54 V ..................................................................................................................... 6

2

TPS23525

www.ti.com.cn

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

5 Pin Configuration and Functions

PW Package

16-Pin (TSSOP)

Top View

Neg48A

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Neg48B

NC

GATEB

GATEA

VEE

PGb

VCC

UVEN

OV

SNS

GATE

SS

TMR

D

Not to scale

Pin Functions

TYPE

DESCRIPTION

NAME

NO.

Input to the OR-ing controller for the –48A feed. The TPS23525 will regulate the drop from

VEE to Neg48A to 25 mV to mimic an ideal diode.

Neg48A

1

I

NC

2

3

4

No connect to space high voltage pins.

GATEB

GATEA

O

Gate driver for the OR-ing FET of the -48V_B feed.

Gate driver for the OR-ing FET of the -48V_A feed.

This pin corresponds to the IC GND. Kelvin sense to the bottom of R_SNSto ensure accurate

current limit.

VEE

5

GND

Sense pin, used to measure current and regulate it. Kelvin Sense to R_SNSto ensure accurate

current limits.

SNS

6

7

I

GATE

O

Gate drive for the main hot swap FET.

Pin used for soft starting the output. Connect a capacitor (C_SS) between the SS pin and

-48V_OUT. The dv/dt rate on the -48V_OUT pin is proportional to the gate sourcing current

SS

D

8

9

O

I

divided by C_SS

.

Pin used to sense the drain of the hot swap FET and to program the threshold where the hot

swap switches from the CL1 and CL2. Connect a resistor from this pin to the drain of the hot

swap FET (also called -48V_OUT) to program the threshold.

Timer pin used to program the duration when the hot swap FET can be in current limit.

Program this time by adding a capacitor between the TMR pin and VEE.

TMR

OV

10

11

O

I

Input over voltage comparator. Tie a resistor divider to program the threshold where the

device turns off due to over voltage event.

Input under voltage comparator. Tie a resistor divider to program the threshold where the

device turns on.

UVEN

VCC

12

13

I

S

Clamped supply. Tie to RTN through resistor.

Power Good Bar, which is an open drain output that indicated when the power is good and

the load can start drawing full power. PGb goes low when the hot swap is fully on and the

DC/DC can draw full power.

PGb

14

O

NC

15

16

No connect to space high voltage pins.

Input to the OR-ing controller for the –48B feed. The TPS23525 will regulate the drop from

VEE to Neg48B to 25 mV to mimic an ideal diode.

Neg48B

I

3

TPS23525

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

-0.3

–2

MAX

20

UNIT

V

Supply voltage

Input voltage

V_VCC(current into V_CC<10 mA)

V_SNS, V_OV

6.5

V

V_UVEN, V_D, V_SS

30

V

V_Neg48A, V_Neg48B

V_Neg48A, V_Neg48Bthrough 1-kΩ resistor

V_GATE, V_GATEA, V_GATEB

V_TMR

200

VCC

6.5

V

Input voltage

V

–0.3

–40

–55

V

Output voltage

V

V_PGb

200

125

150

V

Operating junction temperature, T_J

Storage temperature, T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

1000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0

NOM

MAX

20

UNIT

V

V_VCC

Supply voltage (current into V_CC<10 mA)

Input voltage

V_SNS, V_OV

0

5.5

V

V_UVEN, V_D, V_SS

Input voltage

0

18

V

V_Neg48A, V_Neg48B

Input voltage, through 1-kΩ resistor

Output voltage

–0.2

0

150

VCC

5.5

V

V_GATE, V_GATEA, V_GATEB

V

V_TMR

Output voltage

0

V

V_PGb

Output voltage

0

80

V

C_SS

Capacitance

1

200

10

nF

kΩ

R_SS

Resistance

1

R_D

Resistance

120

2,000

R_{NEG48VA ,}R_NEG48VB

Resistance

1

6.4 Thermal Information

TPS23525

THERMAL METRIC⁽¹⁾

PW (TSSOP)

16 PINS

98.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

31.3

44.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

4

TPS23525

www.ti.com.cn

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

Thermal Information (continued)

TPS23525

THERMAL METRIC⁽¹⁾

PW (TSSOP)

16 PINS

1.8

UNIT

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

°C/W

ψ_JB

43.6

R_θJC(bot)

N/A

6.5 Electrical Characteristics

–40°C ≤ T_J≤125°C, 1.1 mA < I_VCC< 10 mA, V_(UVEN)= 2 V, V_(OV)= V_(SNS)= V_(D)= 0 V, V_(SS)= GATEx = Hi-Z , V_(TMR)= 0 V, –1

V < V_NEG48Vx< 150 V, ; All pin voltages are relative to VEE (unless otherwise noted)

PARAMETER

VCC – Clamped Supply

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{(UVLO_VCC)}

UVLO on VCC

rising

9

9.5

1

10

V

V_{(UVLO_VCC,hyst)}

UVLO hysteresis on VCC

hysteresis

1.1< I_(VCC)< 10 mA (current into

VCC)

V_(VCC)

VCC regulation

12

14.5

18

V

V_VCC= 10 V. Off

V_VCC= 10 V. On

1

mA

I_Q

Quiescent Current

V_VCC= 10 V, Gate, GATEA, GATEB

in regulation

1.1

mA

UVEN – Under Voltage and Enable

V_{(UVEN_T)}Threshold voltage for V_(UVEN)

0.985

9

1

1.015

11.2

V

Hysteresis current, sourcing

from UV pin

I_{(UV_hyst)}

V_UV= 1.5 V

10

µA

OV – Over Voltage

V_{(OV_T)}

Threshold voltage for V_OV

0.98

9

1

1.02

11.2

V

Hysteresis current, sourcing

from OV pin

I_{(OV_hyst)}

TMR – Timer

V_TMR

V_OV= 1.5 V

10

µA

Voltage on timer when part

times out.

V_D= 0 V, TMR ↑, measure V_TMR

when V_GATE= 0

1.47

0.735

9

1.5

0.75

10

1.53

0.765

11

V

Voltage on timer when part

times out.

V_D= 1 V, TMR ↑, measure V_TMR

when V_GATE= 0

V_TMR2

V

V_SNS= 0.1 V, V_D= 0 V, V_TMR= 0 V,

measure I out from TMR

µA

Timer Sourcing current when

in fault condition or when

retrying.

I_TMR,SRs

V_SNS= 0.1 V, VD = 2 V, V_TMR= 0 V,

measure I out from TMR

45

50

55

Timer sinking current when

not in fault condition.

I_TMR,SNC

V_SNS= 0 V, V_D= 0 V, V_TMR= 2 V,

1.5

2

2.5

Voltage on timer when the

V_SNS= 0 V, V_D= 0 V, TMR ↑ = 2 V,

V_TMR,RETRY

timer starts going back up in TMR ↓, measure V_TMRwhen I into

0.475

0.5

0.525

V

retry. Retry version only.

TMR change polarity

Number of retry duty cycles.

Retry version only.

N_RETRY

D_RETRY

64

Retry duty cycle. Retry

version only.

0.4%

Gate Sourcing Current

V_G= 5 V, V_D= 2 V, V_SNS↑,

I_GATE,TIMER

Threshold When timer starts measure I_GATEwhen TMR sources

5

10

15

µA

to run.

current

V_D= 2 V, V_TMR= 0 V, V_G= 5 V;

Sense Voltage when Timer

starts to run.

V_SNS,TMR1

V_SNS↑, measure V_SNSwhen TMR

1.5

2.5

mV

sources current

5

TPS23525

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

www.ti.com.cn

Electrical Characteristics (continued)

–40°C ≤ T_J≤125°C, 1.1 mA < I_VCC< 10 mA, V_(UVEN)= 2 V, V_(OV)= V_(SNS)= V_(D)= 0 V, V_(SS)= GATEx = Hi-Z , V_(TMR)= 0 V, –1

V < V_NEG48Vx< 150 V, ; All pin voltages are relative to VEE (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_D= 0 V, V_TMR= 0 V , V_G= 5 V;

Sense Voltage when Timer

starts to run.

V_SNS,TMR2

V_SNS↑, measure V_SNSwhen TMR

23.25

24.5

mV

sources current

SNS – Sense Pin For Current Limit

Leakage current on sense

I_SNS,LEAK

-2

2

µA

V_TMR= 0 V. V_GATE= 5 V. V_D= 0 V

V_SNS,CL1

Current limit

24

25

50

3

26

mV

V

_SNS↑, measure when I_GATE= 0;

V_TMR= 0 V. V_GATE= 5 V. V_D= 0 V.

_SNS↑, measure when I_GATE> 100

V_SNS,FST

V_SNS,CL2

V_SNS,FST2

fast trip current limit

V

45

2.25

6

55

3.75

12

mV

mA

V_TMR= 0 V, V_GATE= 5 V, V_D= 5 V,

Fold Back Current Limit

Fast Trip during start-up

V

_SNS↑, measure when I_GATE= 0;

V_TMR= 0 V, V_GATE= 5 V, V_D= 5 V,

_SNS↑, Measure when I_GATE> 100

V

9

mA

GATE – Gate Drive for Main Hot Swap FET

V_(VCC-GATE)

Output gate voltage

V_(SNS)= 0 V

1

V

Sourcing Current during

normal operation.

V_(TMR)= 0 V. V_(GATE)= 8 V. V_D= 0

V, V_(SNS)= 0 V

I_{(GATE,SRS,NORM)}

250

400

µA

Sourcing Current during star- V_(TMR)= 0 V. V_(GATE)= 5 V. V_D= 0

I_{(GATE,SRS,START)}

I_(GATE,wkpd)

15

3

20

5

25

7

µA

mA

A

up

V, V_(SNS)= 0 V

Weak pull down current

V_(SNS)= 0 V. V_UVEN= 0 V

Fast Pull down current with

10mV overdrive

I_(GATE,FST)

0.4

1

1.5

D – Drain Sense

R_(D,INT)

Resistance from the drain pin

to GND.

28.5

1.46

30

31.5

1.54

kΩ

Voltage on drain that

switches between two current 20 mV, D↑, measure V when I_(GATE)

V_(TMR)= 0 V, V_(GATE)= 5 V, V_(SNS)=

V_{(D,CL_SW)}

1.5

V

limits

= 0

V_(TMR)= 1 V, V_(GATE)= 5 V, V_(SNS)

20 mV, D↑, measure V when I_(GATE)

= 0

=

Voltage on drain that

switches the V_TMRthreshold.

V_{(D,TMR_SW)}

0.73

100

0.75

75

0.77

V

V_{(D,TMR_SW,hyst)}

hysteresis for V_(D,TMR,SW)

hysteresis

mV

SS (Soft Start)

Pull down current when not in

inrush

I_(SS,PD)

V_SS= 5 V

mA

Resistance between GATE

and SS in the start-up phase

R_(SS,GATE)

80

25

Ω

Neg48A, Neg48B

V_Neg48x= –50 mV, GATEx ON

V_Neg48x= –100 mV, GATEx ON

V_Neg48x= 150 V, GATEx off

-2

-7

2

7

µA

I_(lkg,Neg48x)

Leakage current

30

Forward regulation voltage of

V_(FWD)

the OR-ing controller. V_FWD

V_EE– V_(NEG48Vx)

=

10

40

mV

Forward voltage where a fast V_GATEx= 5 V. V_VEE– V_Neg48Vx

↑

V_(FWD,FST)

50

2

80

6

105

10

mV

pull up is activated.

measure when I_GATEx= 100 µA

V_(RV)

Fast reverse trip voltage.

GATEA, GATEB

V_VCC-GATEx

Gate Output Voltage.

0.65

1.1

V

6

TPS23525

www.ti.com.cn

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

Electrical Characteristics (continued)

–40°C ≤ T_J≤125°C, 1.1 mA < I_VCC< 10 mA, V_(UVEN)= 2 V, V_(OV)= V_(SNS)= V_(D)= 0 V, V_(SS)= GATEx = Hi-Z , V_(TMR)= 0 V, –1

V < V_NEG48Vx< 150 V, ; All pin voltages are relative to VEE (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Gate sourcing current in

regulation

I_(GATEx,SRS)

I_(GATEx,SINK)

R_GATE,SRC,FST

I_(GATEx,FST)

V_VEE– V_Neg48Vx= 50 mV

5

µA

Gate sinking current in

regulation

V_VEE– V_Neg48Vx= 0

5

µA

Pull up resistance in fast

sourcing mode.

V_VEE– V_Neg48Vx= 100 mV; Measure

current at V_GATEx= 0 V. R = V_VCC/I

10

1

kΩ

Fast Gate pull down current

V_(VEE)– V_Neg48x= –15 mV

0.4

6.5

1.5

8

A

PGb (Power Good Bar)

Threshold on GATE that

triggers PGb to assert.

V_(GATE,PGb)

Raise V_GATEuntil PGb asserts

PGb sinking 1 mA

7.25

V

V_(PGb,PD)

Pull down strength on PGb

leakage current on PGb pin

1.5

1

V

I_(PGb,LEAK)

µA

OTSD (Over Temperature Shut Down)

T_SD

Shutdown temperature

Temp Rising

135

155

8

175

°C

Shutdown temperature

Hysteresis

T_SD,hyst

7

TPS23525

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

www.ti.com.cn

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

VCC – Clamped Supply

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_VCC: 0 V → 10 V, measure delay

before V_GATE

t_ID

Insertion Delay

32

ms

↑

UVEN

T_UV,degl

OV

Deglitch on UVEN

Deglitch on OV

4

µs

T_OV,degl

SNS

V_SNSsteps from 0 mV to 60 mV.

Response time to large over current Measure time for GATE to come

down.

T_SNS,FST,R

ESP

300

ns

Neg48VA, NEG48VB

V_NEG48Vxsteps from -40 mV to 15

mV. Measure time for GATEx to

come down.

T_Neg48Vx,FSResponse time to large reverse

current

T,RESP

PGb

Power Good ↑ (V_(GATE)0 V → 10 V)

Look for PGb ↓

1

ms

Deglitch of PGb. (raise GATE,

measure delay between GATE and

PGb)

t_PGb,DEGL

Power Good ↓ (V_(GATE)10 V → 0 V)

Look for PGb ↑

32

8

TPS23525

www.ti.com.cn

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

6.7 Typical Characteristics

Unless otherwise noted: –40°C ≤ T_J≤125°C, 1.1 mA < I_VCC< 10 mA, V_(UVEN)= 2 V, V_(OV)= V_(SNS)= V_(D)= 0 V, V_(SS)= GATEx

= Hi-Z , V_(TMR)= 0 V, –1 V < V_NEG48Vx< 150 V , ;

Ivcc injected into VCC pin

Figure 1. VCC Regulation Voltage vs Current and

V_VCC= 10 V, Regulation is current limit

Figure 2. Iq vs Temperature and Operating Condition

Temperature

Figure 3. I_snsCurrent Vs Temperature

Figure 4. I_GATEAvs Temperature

In Power Good

Figure 5. Vpgb vs Temperature

Figure 6. V_VCC-GATEvs Temperature

9

TPS23525

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

www.ti.com.cn

7 Parameter Measurement Information

7.1 Relationship between Sense Voltage, Gate Current, and Timer

The diagram below illustrates the relationship between the V_SNS(voltage across R_SNS), Gate current, and the

timer operation. The diagram is intended to help explain the various parameters in the electrical characteristic

table and is not drawn to scale.

Note that I_GATEreduces as the sense voltage approaches the current limit threshold and it equals zero at the

current limit regulation point. To ensure that the timer always runs when the IC is in regulation the timer starts at

a slightly positive I_GATE

.

Figure 7. Relationship Between Timer, Gate Current, and Sense Voltage (V_GATE= 5 V)

10

TPS23525

www.ti.com.cn

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

8 Detailed Description

8.1 Overview

The TPS23525 is an integrated hot swap and Dual OR-ing controller that enables high power telecom systems to

comply with stringent transient requirements. The soft start cap disconnect allows soft start at start-up and

disconnects the soft start cap during normal operation. This allows for the use of smaller hot swap FETs without

hurting the transient response. The 400 µA sourcing current allows fast recovery, which helps to avoid system

resets during lightning surge tests. The dual current limit makes it easier to pass brown outs and input steps such

as required by the ATIS 0600315.2013. Finally, the TPS23525 offers accurate under voltage and over voltage

protection with programmable thresholds and hysteresis.

The TPS23525 integrates a dual OR-ing controller, making it ideal for –48 V systems fed by two redundant

supplies.The OR-ing controller will turn off if any reverse current is detected.

8.2 Functional Block Diagram

RTN

VCC

Internal

Regulator

& Band Gap

V_INT

V_INT,GD

V_1V

HS_ON

i_HYST

To

Load

R₁

R₂

PGb

DIS_RTN

C_OUT

UVEN

OV

Logic, Timing, and

Control

Time Out

V_1V

VING

OV_GD

V_1.5V

R_D

D

R₃

V_INT

i_HYST

30k

C_SS

1k

SS

Disconnect

Neg48B

Neg48A

ORing

Control

GATEA

GATEB

Time

Out

V_VCC

Current Limit

& Gate Drive

GATE

SNS

Q₁

Timer

Block

in I_LIM

HS_ON

IC_GND

R_SNS

VEE

TMR

Q₃

C_TMR

-48VA

-48VB

Q₃

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8.3 Feature Description

8.3.1 Current Limit

The TPS23525 utilizes two current limit thresholds:

•

I_CL1– also referred to as high current limit threshold, which is used when the V_DSof the hot swap FET is low.

I_CL2– lower current limit threshold, which is used when the V_DSof the hot swap FET is high.

This dual level protection scheme ensures that the part has a higher chance of riding out voltage steps and other

transients due to the higher current limit at low V_DS, while protecting the MOSFET during start into short and hot-

short events, by setting a lower current limit threshold for conditions with high V_DS.The transition threshold is

programmed with a resistor that is connected from the drain of the hot swap FET to the D pin of the TPS23525.

The figure below illustrates an example with a I_CL1set to 25 A and I_CL2set to 3 A. Note that compared to a

traditional SOA protection scheme this approach allows better utilization of the SOA in the 10 V < V_DS.< 40-V

range, which is critical in riding through transients and voltage steps.

Note that in both cases the TPS23525 regulated the gate voltage to enforce the current limit. However, this

regulation is not very fast and doesn’t offer the best protection against hot-shorts on the output. To protect in this

scenario a fast comparator is used, which quickly pulls down the gate in case of severe over current events (2x

bigger than V_CL1).

Figure 8. Dual Current Limit vs FET Power Limit

8.3.1.1 Programming the CL Switch-Over Threshold

The V_DSthreshold when the TPS23525 switches over from I_CL1to I_CL2(V_D,SW) can be computed using

Equation 1. For example, if a 15-V switch over is desired, R_Dshould be set to 270 kΩ.

1.5 V ì 30 kß + R

(

)

D

V_DS,SW

=

30 kß

(1)

8.3.1.2 Programming CL1

The current limit at low V_DS(I_CL1) of the TPS23525 can be computed using Equation 2 below.

V_SNS,CL1

I_CL1

=

R _SNS

(2)

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Feature Description (continued)

To compute I_CL1for a 1-mΩ sense resistor use Equation 3 below.

V_SNS,CL1

25 mV

I_CL1

=

= 25 A

R _SNS

1mß

(3)

8.3.1.3 Programming CL2

The current limit at high V_DS(I_CL2) of the TPS23525 can be computed using Equation 4 below.

V_SNS,CL2

I_CL2

=

R _SNS

(4)

(5)

To compute I_CL2for a 1-mΩ sense resistor use Equation 5 below.

V_SNS,CL2

3 mV

I_CL2

=

= 3 A

R _SNS

1mß

8.3.1.4 Computing the Fast Trip Threshold

The fast trip threshold is set to 2x the I_CL1when operating at low V_DSand its set to 3x the I_CL2when operating at

high V_DS

.

8.3.2 Soft Start Disconnect

The inrush current into the output capacitor (C_OUT) can be limited by placing a capacitor between the SS (Soft

Start) pin and the drain of the hot swap MOSFET. In that case the inrush current can be computed using

equation below.

C_OUTì I_{GATE,SRS,START}

660 µFì 20 µA

I_INR

=

= 0.4 A

C_SS

33 nF

(6)

Note that with most hot swap the C_SSpin is tied simply to the gate pin, but this can interfere with performance

during normal operation if transients or short circuits are encountered. In addition the C_SScapacitor tends to pull

up the gate during hot plug and cause shoot through current if it is always tied to the gate. For that reason the

TPS23525 has a disconnect switch between the gate pin and the SS pin as well as a discharge resistor. During

the initial hot plug and during the insertion delay the switch between SS and GATE is open and SS is being

discharged to GND through a resistor. Then during start-up SS and GATE are connected to limit the slew rate.

Once in normal operation the SS pin is not tied to GATE and it is not shorted to GND, which prevents it from

interfering with the operation during transients.

C_SS

SS 1 k

SS_Dis

C_SS,GND

SS_ON

Q₁

GATE

Figure 9. Implementation of SS Disconnect

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Feature Description (continued)

8.3.3 Timer

Timer is a critical feature in the hot swap, which manages the stress level in the MOSFET. The timer will source

and sink current into the timer capacitor as follows:

•

Not in current limit: sink 2 µA

If the part is in current limit and V_GATE< V_GATE,TH, the timer sources current as follows:

–

V_D< V_{D,CL_SW}: source 10 µA

V_D> V_{D,CL_SW}: source 50 µA

The TPS23525 times out and shuts down the hot swap as follows.

•

If V_D< V_{D,TMR_SW}then the hot swap times out when V_TMRreaches 1.5 V.

If V_D> V_{D,TMR_SW}then the hot swap times out when V_TMRreaches 0.75 V.

The above behavior maximizes the ability of the hot swap to ride out voltage steps, while ensuring that the FET

remains safe even if the part can not ride out a voltage step.

A cool down period follows after the part times out. During this time the timer performs the following:

•

Discharge C_TMRwith a 2-µA current source until 0.5 V

Charge C_TMRwith a 10-µA current source until it is back to 1.5 V.

Repeat the above 64 times

Discharge timer to 0 V.

The part attempts to restart after finishing the above. If the UVEN signal is toggled while the 64 cycles are in

progress the part restarts immediately after the 64 cycles are completed.

The timer operates as follows when recovering from POR:

•

If V_TMR< 0.5 V:

–

Proceed to regular startup

Do not discharge V_TMR

•

If V_TMR> 0.5 V:

–

Go through 64 charge/discharge cycles

Discharge V_TMR

Proceed to startup

The Time Out (T_TO) can be computed using the equations below. Note that the time out depends on the V_DSof

the MOSFET.

C _TMRì V_TMR

T_TO

=

I_TMR,SRS

(7)

(8)

C _TMRì 1.5 V

10 mA

T_TO(V_D< 0.75 V) =

C_TMRì 0.75 V

10 mA

T_TO(0.75 V < V_D< 1.5 V) =

(9)

C _TMRì 0.75 V

T_TO(V_D> 1.5 V) =

50 mA

(10)

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Feature Description (continued)

8.3.4 OR-ing

The TPS23525 features integrated OR-ing that controls the external MOSFET in a way to emulate an ideal

diode. The TPS23525 will regulate the forward drop across the OR-ing FET to 25 mV. This is accomplished by

controlling the V_GSof the MOSFET. As the current decreases the V_GSis also decreased, which effectively

increases the R_DSONof the MOSFET. This process is regulated with a low gain amplifier that is gate (OR-ing

FET) pole compensated. The lower gain helps ensure stability over various operating conditions. The regulating

amplifier ensures that there is no DC reverse current.

However, the amplifier is not very fast and thus it is paired with a fast comparator. This comparator quickly turns

off the FET if there is significant reverse current detected.

Figure 10. Simplified Diagram of OR-ing Block

8.4 Device Functional Modes

Figure 11. Simplified Hot Swap State Machine

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Device Functional Modes (continued)

The Figure above shows a simplified state machine of the hot swap controller. It has 4 distinct operating states

and the controller switches between these states based on the following signals:

•

Ving_rc: This means that both the input voltage is in the right range and the IC has power with Vcc. A 4-µs

delay is added for deglitching. If the input voltage is above the OV threshold, input voltage is below the UV

threshold, or VCC is below its internal UVLO, Ving_rc will be low.

•

TimeOut: This signal comes from the timer block and will be asserted Hi if the IC has timed out due to an

over-current condition. This signal is also Hi while the timer is going through the restart cycles. Once the

cycles are completed this signal will go Low.

•

ins_over: This signal states that the insertion delay has been completed and the hot swap is ready to start-up.

FT: this is the fast trip signal coming from the fast trip comparator. It goes Hi if an extreme over current event

is detected.

•

PG: Internal Power good signal. This is high when the hot swap is fully on and the load can draw full power.

For PG to be Hi, the GATE has to be Hi and the drain pin needs to be below 0.75 V.

PG_degl: This is a deglitched version of the PG and is the signal used to move between states and controls

the external PGb pin.

8.4.1 OFF State

In this state the hot swap FET is turned off and the controller is waiting to start-up. The controller can be in this

state due to any of these scenarios:

•

Input voltage is not in the valid range.

The hot swap is in the cool down state and the timer is going through the retry cycle after a fault condition

such as output hot short or over current.

•

VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.

8.4.2 Insertion Delay State

In this state the hot swap FET is turned off and the controller is waiting for the insertion delay to finish. This

allows the input supply to settle after a Hot Plug. If any of the following occur, the controller will be kicked back to

the OFF state:

•

Input voltage is not in the valid range.

VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.

Once the insertion delay is finished, the controller will move to the Start-up state.

8.4.3 Start-up State

In this state the controller is turning on and charging the output cap. The operation is set as follows:

•

The SS pin is internally connected to the GATE pin to allow for output dv/dt control.

Lower gate sourcing current is applied to the GATE pin to allow for smaller SS caps.

The lower current limit setting of V_SNS,CL2and a lower fast trip setting of V_SNS,FST2is used to minimize the

MOSFET stress in case of a fault condition.

If any of the following occur, the controller will be kicked back to the OFF state:

•

Input voltage is not in the valid range.

The timer times out due to over-current.

VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.

Fast trip is triggered.

Once the PG_degl signal goes Hi, the controller will move to the Normal Operation state.

8.4.4 Normal Operation State

In this state the hot swap is fully on and the operation is set as follows:

•

The SS pin is disconnected from the GATE pin to improve transient response.

The full gate sourcing current is used to improve transient response.

The current limit and fast trip threshold are a function of the D pin to optimize the transient response while

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Device Functional Modes (continued)

protecting the MOSFET.

If any of the following occur, the controller will be kicked back to the OFF state:

•

PG_degl goes low.

The timer times out due to over-current.

VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.

Note that if the input voltage is outside the valid range or the fast trip is triggered, the hot swap FET will turn off,

but the controller will not exit the Normal Operation state. In this case the PG signal would go low immediately. If

this condition persists, the PG_degl will go low as well and the controller would move to the OFF state. This

operation prevents the controller from re-starting the system during quick transients.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS23525 is a hot swap controller for –48-V applications and is used to manage inrush current and protect

downstream circuitry and the upstream bus in case of fault conditions. The following key scenarios should be

considered when designing a –48-V hot swap circuit:

•

Start Up.

Output of a hot swap is shorted to ground while the hot swap is on. This is often referred to as a Hot Short.

Powering up a board when the output and ground are shorted. This is usually called a start-into-short.

Input lightning surge. Here it is usually desired to avoid damage to downstream circuitry and to avoid system

restarts.

These scenarios place a lot of stress on the hot swap MOSFET and the board designer should take special care

to ensure that the MOSFET stays within it's Safe Operating Area (SOA) under all of these conditions. A detailed

design example is provided below and the key equations are written out. Note that solving all of these equations

by hand is cumbersome and can result in errors. Instead, TI recommends using the TPS2352X Design

Calculator provided on the product page.

9.2 Typical Application

Figure 12. Application Diagram for Design Example

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Typical Application (continued)

9.2.1 Design Requirements

The table below summarizes the design parameters that must be known before designing a hot swap circuit.

When charging the output capacitor through the hot swap MOSFET, the FET’s total energy dissipation equals

the total energy stored in the output capacitor (1/2CV²). Thus both the input voltage and output capacitance will

determine the stress experienced by the MOSFET. The maximum load power will drive the current limit and

sense resistor selection. In addition, the maximum load current, maximum ambient temperature, and the thermal

properties of the PCB (R_θCA) will drive the selection of the MOSFET's R_DSONand the number of MOSFETs used.

R_θCAis a strong function of the layout and the amount of copper that is connected to the drain of the MOSFET.

Air cooling will also reduce R_θCAsubstantially. Finally, it's important to know what transients the circuit has to

pass in order to size up the input protection accordingly.

Table 1. Design Requirements for a –38 V to –60 V, 400-W Protection Circuit

DESIGN PARAMETER

Input voltage range

EXAMPLE VALUE

–38 V to –60 V

Maximum Load Power

400 W

Output Capacitance

660 µF

Location of Output Cap

After EMI filter with ~5 µH of inductance.

Maximum Ambient Temperature

MOSFET R_θCA(function of layout)

Pass “Hot-Short” on Output?

Pass a “Start into short”?

Is the load off until PG asserted?

Max Input Inductance

85°C

20°C/W

Yes

10 µH

Level of IEC61000-4-5 to pass

Pass Reverse Hook Up

2-kV Line to Line with 2-Ω series impedance

Yes

9.2.2 Detailed Design Procedure

9.2.2.1 Selecting R_SNS

Before selecting R_SNS, first compute the maximum load current. For this example the worst case load current

happens at the minimum input voltage of 38 V. Thus the maximum current is 400 W/38 V = 10.5 A. To provide

some margin, set the target current limit to 12 A and compute R_SNSusing equation below:

V_SNS,CL1

25 mV

12 A

R_SNS,CLC

=

= 2.08 mW

I_CL1

(11)

Use next available R_SNSof 2 mΩ.

9.2.2.2 Selecting Soft Start Setting: C_SSand C_SS,VEE

First, compute the minimum inrush current where the timer will trip using equation below.

V_SNS,TMR2

1.5 mV

I_INR,TMR

=

= 0.75 A

R_SNS

2 mW

(12)

To avoid running the timer the inrush current needs to be sufficiently low. Target 0.4 A of inrush current to allow

margin, and compute the target C_SSusing equation below.

c _OUT,MAXì I_{GATE,SRS,START}

792 µFì20 µA

c _SS

=

= 39.6 nF

I_INR,TGT

0.4 A

(13)

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Next choose, the next available C_SSgreater than 39.6 nF. For this example 43 nF was used, which assumes a

33 nF and 10 nF cap in parallel. This results in an inrush current of 0.37 A at max C_OUT(792 µF) and inrush

current of 0.31 A at typical C_OUT(660 µF). Also it is recommended to add a capacitor between the soft start pin

and VEE (C_SS,VEE) to improve immunity to input voltage noise during soft start. It's recommended to chose a

capacitor that's 3x larger than C_SS. In this case a 150 nF capacitor was chosen.

Finally the start-up time at maximum input voltage can be computed using the equation below:

c _SSì V_IN,MAX

43nFì 60V

T_START

V

=

= 129 ms

(

)

IN,MAX

I_{GATE,SRS,START}

20µA

(14)

9.2.2.3 Selecting V_DSSwitch Over Threshold

The V_DSthreshold where the current limit switches from CL1 to CL2 can be programmed using R_D. In general a

higher threshold improves ability to ride through voltage steps, brown outs, and other transients. However, a

larger setting can also expose the MOSFET to more stress, because the larger current limit is now allowed at

higher V_DSvoltages. If there are no specific voltage step requirements, 20 V is a good starting point. Use the

equation below to compute the target R_D.

V

≈

∆

«

’

DS,SW

R_D= 30 kß ì

-1 = 370 kß

÷

1.5 V

◊

(15)

9.2.2.4 Timer Selection

The timer determines how long the hot swap can be in current limit before timing out and can be programmed

using C_TMR. In general a longer time out (T_TO) improves ability to ride through voltage steps, brown outs, and

other transients. However, a larger setting can also expose the MOSFET to more stress, because it takes longer

for the FET to shut down during fault conditions. If there are no specific voltage step or transient requirements, 2

ms is a good starting point. Use the equation below to compute the target C_TMR. Choose the next available

capacitor value of 15 nF, which results in a 2.25 ms time out.

T_TOì I_TMR,SRS

2 msì10 mA

C_TMR

=

= 13.3nF

V_TMR

1.5 V

(16)

9.2.2.5 MOSFET Selection and SOA Checks

When selecting MOSFETs for the –48 V application the three key parameters are: V_DSrating, R_DSON, and safe

operating area (SOA). For this application the CSD19535KTT was selected to provide a 100 V V_DSrating, low

R_DSON, and sufficient SOA. After selecting the MOSFET, it is important to double check that it has sufficient SOA

to handle the key stress scenarios: start-up, output Hot Short, and Start into Short. MOSFET's SOA is usually

specified at a case temperature of 25°C and should be derated based on the maximum case temperature

expected in the application. Compute the maximum case temperature using the equation below. Note that the

R_DSONwill vary with temperature and solving the equation below could be a repetitive process. The

CSD19535KTT, has a maximum 3.4 mΩ R_DSONat room temperature and is ~1.5x higher at 100°C. N stands for

the number of MOSFETs used in parallel.

2

I

≈

’

LOAD,MAX

T_C,MAX= T_A,MAX+ R _qCA

ì

ì R_DSONT

J

(

)

∆

÷

N

«

◊

(17)

(18)

C

T_C,MAX= 85 èC + 20è

W

2

ì 10.5 A ì 3.4ì1.5 mW = 96.3 èC

(

)

(

)

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Next the stress the MOSFET will experience during operation should be compared to the FETs capability. First,

consider the power up. The inrush current with max C_OUTwill be 0.37 A and the inrush will last for 129 ms. Note

that the power dissipation of the FET will start at V_IN,MAX× I_INRand reduce to zero as the V_DSof the MOSFET is

reduced. The SOA curve of a typical MOSFET assume the same power dissipation for a given time. A

conservative approach is to assume an equivalent power profile where P_FET= V_IN,MAX× I_INRfor t = Tstart-up /2. In

this instance, the SOA can be checked by looking at a 60 V, 0.4 A, 64.5 ms pulse. Based on the SOA of the

CSD19535KTT, it can handle 60 V, 1.8 A for 10 ms and it can handle 60 V, 1 A for 100 ms. The SOA at T_C

=

25°C for 64.5 ms can be extrapolated by approximating SOA vs time as a power function as shown in equations

below:

I_SOAt = a ì t ^m

( )

(19)

≈

’

1.8 A

1 A

ln

∆

÷

◊

ln (I_SOA

t

/ I

t

)

(

)

(

)

1

SOA

2

«

m =

=

= - 0.25

≈

’

10 ms

ln t / t

(

)

1

2

ln

∆

÷

◊

100 ms

«

(20)

I_SOA

t

2

(

)

1 A

0.25

a =

=

= 3.16A ì ms

(

)

t ^m₂

-0.25

100 ms

(

)

(21)

(22)

-0.25

I_SOA64.5 ms, 25 èC = 3.16 Aì ms ^0.52ì 64.5 ms

= 1.12 A

(

)

(

)

(

)

Finally, the FET SOA needs to be derated based on the maximum case temperature as shown below. Note that

the FET can handle 0.59 A, while it will have 0.37 A during start-up. Thus there is a lot of margin during this test

condition.

175 èC - 96.3 èC

175 èC - 25 èC

I_SOA64.5 ms,T

= 1.12 A ì

= 0.59 A

(

)

C,MAX

(23)

A similar approach should be taken to compute the FETs SOA capability during a Hot Short and start into short.

As shown in the following figure, during a start into short the gate is coming up very slowly due to a large

capacitance tied to the gate through the SS pin. Thus it is more stressful than a Hot Short and should be used for

worst case SOA calculations. To compare the FET stress during start-up into short to the SOA curves the stress

needs to be approximated as a square pulse as showing in the figure below. In this example, the stress is

approximated with a 1.1 ms (Teq), 1.5 A, 60 V pulse. The FET can handle 6 A, 60 V for 1 ms and 1.8 A, 60 V for

10 ms. Using approximation and temp derating as shown earlier, the FET's capability can be computed as 3 A,

60 V, for 1.1 ms at 96°C. 3 A is significantly larger than 1.5 A implying good margin.

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Figure 13. Teq During a Start Into a Short

The final operating point to check is the operation with high current and V_DSjust below the V_DS,SWthreshold. In

this example, the time out would be 1.1ms (one half of the time out at Vd = 0 V), the current will be 12.5 A, and

the voltage would be 20 V. Looking up the SOA curve, the FET can handle 30 A, 20 V for 1 ms and 10 A, 20 V

for 10 ms. Repeating previously shown approximations and temp derating, the FET's capability is computed to be

16 A, 20 V, for 1.1 ms at 96°C. Again this is below the worst case operating point of 12.5 A and 20 V suggesting

good margin.

9.2.2.6 Input Cap, Input TVS, and OR-ing FET selection

This design example is sized for an application that needs to pass a 2 kV, 2Ω lightning strike per IEC61000-4-5.

This equates to almost 1000 A of input current that needs to be clamped. In addition, the design needs to pass

reverse hook up and thus the TVS needs to be bi directional. A ceramic transient voltage suppressor (2x

B72540T6500S162) CT2220K50E2G was used to clamp this huge surge of current. According to it's datasheet it

can clamp 500 A of current to 150 V. Note that the lightning strike can be positive or negative. The worst case

voltage is dropped across the OR-ing FETs when the strike is positive (–48 V line goes above RTN). If the output

of the OR-ing is –48 V and the input goes to +150 V that is a 200 V drop. Thus BSC320N20NS3 was chosen for

the OR-ing FETs. This is a 200 V FET with a 32 mΩ R_DSONat room temperature. 2 of these were used in parallel

to minimize power loss and manage thermal. Finally a 0.1 µF input bypass cap is recommended.

9.2.2.7 EMI Filter Consideration

In this example it is assumed that the EMI filter is right after the hot swap and the bulk cap is after the EMI filter.

The EMI filter adds significant inductance and needs to be accounted for. During a Hot Short, the inductor builds

up significant current that needs to go somewhere after the FET opens. For that a free wheeling diode should be

used along with a snubber. For this example a 150 V, SMA diode was used: STPS1150A. The snubber

consisted of a 10-Ω resistor in series with a 1-µF ceramic capacitor. In addition a 0.1-µF ceramic cap was tied

directly on the output.

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9.2.2.8 Under Voltage and Over Voltage Settings

Both the threshold and hysteresis can be programmed for under voltage and over voltage protection. In general

the rising UV threshold should be set sufficiently below the minimum input voltage and the falling OV threshold

should be set sufficiently above the maximum input voltage to account for tolerances. For this example a rising

UV threshold of 37 V and a falling UV threshold of 35 V was chosen as the target. First, choose R_UV1based on

the 2 V UV hysteresis as shown below.

V_UV,hyst,tgt

2 V

R_UV1

=

= 200 kßd

i_UV,hyst

10 µA

(24)

(25)

Once R_UV1is known R_UV2can be computed based on the target rising UV threshold as shown below.

R_UV1

200 kß

R_UV2

=

= 5.56 kß

V_{UV,TGT,Rising}-1 V

37 V -1 V

The OV setting can be programmed in a similar fashion as shown in equations below.

V_OV,hyst,tgt

3 V

R_OV1

=

= 300 kß

i_OV,hyst

10 µA

(26)

(27)

R_OV1

V_{OV,TGT,Rising}-1 V

300 kß

65 V -1 V

R_OV2

=

= 4.68 kß

(28)

Optional filtering capacitors can be added to the UV and OV to improve immunity to noise and transients on the

input bus. These should be tuned based on system requirements and input inductance. In this example place

holders were added to the PCB, but the components were not populated.

9.2.2.9 Choosing R_VCCand C_VCC

The VCC is used as internal supply rail and is a shunt regulator. To ensure stability of internal loop a minimum of

0.1 µF is required for C_VCC. To ensure reasonable power on time it is recommended to keep C_VCCbelow 1 µF.

R_VCCshould be sized in such a way to ensure that sufficient current is supplied to the IC at minimum operating

voltage corresponding to the falling UV threshold. To allow for some margin it is recommended that the current

through R_VCCis at least 1.2x of I_Q,MAXwhen RTN = Falling UV threshold and VCC = 10 V (minimum

recommended operating voltage on VCC). For this example R_VCCof 16.2 kΩ was used.

9.2.2.10 Power Good Interface to Downstream DC/DC

It's critical to keep the downstream DC/DC off while the hot swap is charging the bulk capacitor. This can be

accomplished through the PGb pin. Note that the VEE of the hot swap and the DC/DC are different and the

Power Good can not be directly tied to the EN or UV of the DC/DC. The application circuit below provides a

simple way to control the downstream converter with the PGb pin of the hot swap.

Figure 14. Interface to DC/DC

23

TPS23525

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

www.ti.com.cn

9.2.3 Application Curves

No Load, Scope GND = -48V_A

Figure 16. Start Up (Vin = 54 V)

Figure 15. Start Up (Vin = 54 V)

No Load, Scope GND = -48V_A

Figure 18. Start Up (Vin = 60 V)

Figure 17. Start Up (Vin = 38 V)

VinA = 54 V, VinB = 54 V, No Load, Scope GND = RTN

VinA = 54.5 V, VinB = 54 V, No Load, Scope GND = RTN

Figure 19. Hot Plug Channel A and B Together

Figure 20. Hot Plug Channel A and B Together

24

TPS23525

www.ti.com.cn

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

VinA = 54 V; VinB = 38 V, Scope GND = RTN, Iload = 5 A

Figure 21. Hot Plug A after B

Figure 22. Hot Plug A after B

VinA = 54 V; VinB = 38 V, Scope GND = RTN, Iload = 5 A

VinA = 54.5 V; VinB = 54 V, Scope GND = RTN, No load

Figure 23. Hot Plug A after B

Figure 24. Hot Plug A after B

Scope GND = -48V_B, No Load, After Inductor

Scope GND = -48V_B, 5-A Load, After Inductor

Figure 25. Output Hot Short (VinB = 54 V)

Figure 26. Output Hot Short (VinB = 54 V)

25

TPS23525

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

www.ti.com.cn

Scope GND = -48V_B, 5A Load, Zoomed in

Scope GND = -48V_B, 5-A Load

Figure 28. Output Hot Short (VinB = 60 V)

Figure 27. Output Hot Short (VinB = 54 V)

Scope GND = -48V_B, 5-A Load, Zoomed In

Scope GND = -48V_A

Figure 30. Gradual Over Current (VinA = 54 V)

Figure 29. Output Hot Short (VinB = 60 V)

Scope GND = -48V_A

Scope Gnd = -48V_A, Vin = 54 V

Figure 32. Start Into Short

Figure 31. Load Step Overcurrent

26

TPS23525

www.ti.com.cn

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

Scope Gnd = -48V_A, Vin = 54 V

Figure 34. Apply Short and Remove Short

Figure 33. Start Into Short

Scope GND = -48V_A, Iload = 5 A

Figure 35. 1-ms Brown Out

Scope GND = -48V_A, Iload = 5 A

Figure 36. 1-ms Brown Out

VinB = 53 V, Iload = 5 A, Scope GND = RTN

Figure 37. Supply Switch Over (Raise VinA)

VinB = 53 V (Raise VinA), Scope GND = RTN, Iload = 5 A

Figure 38. Supply Switch Over (zoomed in)

27

TPS23525

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

www.ti.com.cn

VinA = 54.5 V; VinB = 54 V, Iload = 5 A, Scope GND=RTN

Figure 39. VinA Short

Figure 40. VinA Short

VinA = 54.5 V; VinB = 54 V, Iload = 5 A, Scope GND=RTN

VinB = 60 V

Figure 41. Unplug VinA

Figure 42. Plug in VinA backwards

VinB Floating

Scope GND = -48V_A, No Load

Figure 43. Plug in VinA backwards

Figure 44. Under Voltage and Over Voltage (Rising)

28

TPS23525

www.ti.com.cn

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

Scope GND = -48V_A, No Load

Scope GND = RTN, 5-A load, Per IEC61000-4-5

Figure 45. Under Voltage and Over Voltage (Falling)

Figure 46. -2 kV (2 Ω) Lightning Surge

Scope GND = RTN, 5-A load, Per IEC61000-4-5

Figure 47. -2 kV (2 Ω) Lightning Surge (zoomed in)

Figure 48. +2 kV (2 Ω) Lightning Surge (zoomed in)

Scope GND = RTN, 5-A load, Per IEC61000-4-5

Lin = 20 µH, Scope GND = -48V_A

Figure 49. +2 kV (2 Ω) Lightning Surge (zoomed in)

Figure 50. Start-Up (Vin = 54 V)

29

TPS23525

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

www.ti.com.cn

Lin = 20 µH, Scope GND = -48V_A

Figure 52. Hot Short (Vin = 38 V)

Figure 51. Hot Short (Vin = 54 V)

Lin = 20 µH, Scope GND = -48V_A,

Lin = 20 µH, Scope GND = -48V_A

Figure 54. Load Step Into Overcurrent

Figure 53. Load Step (0 A - 11 A)

Lin = 20 µH, Scope GND = -48V_A

Figure 56. 1-ms Brown Out

Figure 55. Start Into Short

30

TPS23525

www.ti.com.cn

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

10 Power Supply Recommendations

In general, the TPS23525 is designed to have robust operation from a non-ideal –48 V bus with various

transients such as the lightning surge. The IC is powered through RVCC making it more immune to supply drop

outs and high voltage spikes. Regardless, TI recommends following several key precautions:

•

Always test the solution with the various transients that can be encountered in the systems. This especially

applies to transients that were not tested with TI’s EVM.

If large input ripple is expected during start-up, increase the ratio of C_{SS, VEE}to C_SSto reduce input current

ripple at start-up.

Operating from large input inductance (>40 µH) can cause instability to the current limit loop or oscillations

during start-up. Add a capacitor from Gate to VEE to help stabilize the current limit loop. Add an input

snubber if oscillations are observed at start-up.

31

TPS23525

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

There are several things to keep in mind during layout of the TPS23525 circuit:

● The VEE and SNS pin need to have a Kelvin Sense connection to the sense resistor.

● The VEE trace carries current and needs to be thick and short in order to minimize IR drop and to avoid

introducing current sensing error.

● It is recommended to use a net-tie to separate the power plane coming into the R_SNSand the Kelvin connection

to VEE.

● Connect the Neg48Vx filtering caps, UVEN resistor divider, OV resistor divider, and TMR cap to the "VEE" to

insure maximum accuracy.

● The filtering caps on Neg48VB, Neg48VA, and SNS should be placed as close to the IC as possible.

11.2 Layout Example

Figure 57. Layout Example

32

TPS23525

www.ti.com.cn

ZHCSGZ0B –OCTOBER 2017–REVISED NOVEMBER 2017

12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.2 文档支持

12.2.1 相关文档

如需相关文档，请参阅：

•

《TPS23525EVM-815 评估模块用户指南》(SLVUB36)

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的提醒我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，也

不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航栏。

33

PACKAGE OUTLINE

PW0016A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

5

0

SMALL OUTLINE PACKAGE

SEATING

PLANE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX AREA

14X 0.65

16

1

2X

5.1

4.9

4.55

NOTE 3

8

9

0.30

16X

4.5

4.3

NOTE 4

1.2 MAX

0.19

B

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

A

20

0 -8

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

16X (1.5)

(R0.05) TYP

16

1

16X (0.45)

SYMM

14X (0.65)

8

9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

16X (1.5)

SYMM

(R0.05) TYP

16

1

16X (0.45)

SYMM

14X (0.65)

8

9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS23525
厂家：	TEXAS INSTRUMENTS
描述：	具有双路电流限制和双路 ORing 的 -10V 至 -80V 热插拔控制器控制器
文件：	总41页 (文件大小：2667K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS23525 [TI]

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