TPS23755RJJT_技术文档

TPS23755

ZHCSJE2B – DECEMBER 2018 – REVISED NOVEMBER 2020

TPS23755 具有非光电反激式直流/直流控制器的 IEEE 802.3at PoE PD

1 特性

3 说明

•

适用于 1 类 PoE 的完整 IEEE 802.3at PD 解决方

TPS23755 器件结合了以太网供电 (PoE) 供电设备

(PD) 接口、150V 开关功率 FET 和电流模式直流/直流

控制器，并针对反激式拓扑进行了优化。高集成度以及

初级侧调节 (PSR)、展频频率抖动 (SSFD) 和高级启动

使 TPS23755 成为尺寸受限应用的理想之选。PoE 实

现支持 IEEE 802.3at 标准（作为 13W、1 类 PD）。

案

– 提供以太网联盟 (EA) 标识认证设计

– 可靠的 100V、0.36Ω（典型值）热插拔

MOSFET

– 可编程分类等级

具有 0.77Ω（典型值）150V 功率 MOSFET 的集成

PWM 控制器

•

直流/直流控制器的 PSR 功能使用来自辅助绕组的反

馈来控制输出电压，无需外部并联稳压器和光耦合器。

经优化，该器件可与次级侧二极管整流器（通常具有

12V 或更高的输出）一起工作。通常，转换器以

250kHz 的开关频率在连续导通模式 (CCM) 下运行。

– 具有 PSR 的反激式控制器

•

支持 CCM 运行（采用次级侧二极管整流

器）

•

±3%（典型值，12V 输出）负载调节

（5%-100% 范围）

SFFD 和压摆率控制有助于最大限度地减小 EMI 滤波

器的尺寸并降低其成本。高级启动允许使用极小的偏置

电容器，同时可以简化转换器启动和间断设计。

– 支持低侧开关降压拓扑

– 具有同步功能的可调开关频率

– 具有高级启动功能的

– 可编程压摆率和频率抖动，可增强 EMI 降低水

平

次级辅助电源检测功能为次级侧电源适配器提供了优先

级，同时可确保与 PoE 输入电源之间的平稳过渡，无

需效率或热性能折衷。

•

具有平稳过渡功能的次级侧适配器优先级控制

具有 –40°C 至 125°C 结温范围

微型 6mm x 4mm VSON 封装

直流/直流控制器具有内部软启动、斜率补偿和消隐功

能。对于非隔离应用，TPS23755 也支持降压拓扑。

器件信息⁽¹⁾

2 应用

器件型号

TPS23755

封装

封装尺寸（标称值）

•

符合 IEEE 802.3at 标准的受电设备

VSON (24)

6.00mm × 4.00mm

监控摄像头

IP 电话

接入点

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

100

90

80

70

60

50

PoE

DC-DC

40

30

20

10

0

0.2

0.4

0.6

Load Current (A)

0.8

1

1.2

DE0x2ce5

简化版应用

效率与负载电流间的关系，12V 输出

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSDW2

TPS23755

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ZHCSJE2B – DECEMBER 2018 – REVISED NOVEMBER 2020

Table of Contents

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics: DC-DC Controller

Section.......................................................................... 7

6.6 Electrical Characteristics: PoE and Control................ 9

6.7 Typical Characteristics..............................................10

7 Detailed Description......................................................14

7.1 Overview...................................................................14

7.2 Functional Block Diagram.........................................15

7.3 Feature Description...................................................16

7.4 Device Functional Modes..........................................22

8 Application and Implementation..................................30

8.1 Application Information............................................. 30

8.2 Typical Application.................................................... 30

9 Power Supply Recommendations................................38

10 Layout...........................................................................38

10.1 Layout Guidelines................................................... 38

10.2 Layout Example...................................................... 38

11 Device and Documentation Support..........................41

11.1 Related documentation........................................... 41

11.2 支持资源..................................................................41

11.3 Trademarks............................................................. 41

11.4 静电放电警告...........................................................41

11.5 术语表..................................................................... 41

12 Mechanical, Packaging, and Orderable

Information.................................................................... 41

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (January 2019) to Revision B (November 2020)

Page

•

更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1

使用 Dvb 更新了简化版应用 .............................................................................................................................. 1

Added, "...and 6.2-V Zener diode..."...................................................................................................................3

Added paragraph, "VB is the 5-V bias rail..."....................................................................................................17

Updated 图 8-1 and 图 8-2 to include Dvb........................................................................................................30

Added section, "Bias Voltage, CVB and DVB"..................................................................................................32

Changes from Revision * (December 2018) to Revision A (January 2019)

Page

•

将器件状态更改为“量产数据”.............................................................................................................................. 1

2

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ZHCSJE2B – DECEMBER 2018 – REVISED NOVEMBER 2020

5 Pin Configuration and Functions

A1

1

A4

24

DRAIN

NC

RSNS

2

23

CP

GND

SRR

SRF

3

VCC

4

21

20

AUX_V

5

19

18

17

16

15

14

13

VB

AUX_D

CS

6

7

COMP

FB

8

NC

9

DTHR

FRS

CLS

DEN

VPD

VDD

10

11

RTN

VSS

12

A2

A3

图 5-1. RJJ Package 24-Pin VSON Top View

表 5-1. Pin Functions

I/O

DESCRIPTION

NO.

NAME

1

RSNS

O

—

I

Switching Power FET source connection. Connect to the external power current sense resistor.

CP provides the clamp for the primary side regulation loop. Connect this pin to the lower end of the

second primary side winding of the transformer.

2

3

4

CP

GND

SRR

Power ground used by the flyback power FET gate driver and CP. Connect to RTN.

Switching FET Gate sinking current input, used for EMI control. Connect a resistance from SRR to

GND to control the Vds rate of rise.

Switching FET Gate sourcing current input, used for EMI control. Connect a resistance from SRF

to VB to control the Vds rate of fall.

5

6

SRF

VB

I

5-V bias rail for the switching FET gate driver circuit. For internal use only. Bypass with a 0.1-μF

ceramic capacitor and 6.2-V Zener diode to GND pin.

O

Auxiliary supply detect, internally pulled-up to approximately 5 V. Pull this pin low, typically through

an optocoupler from the secondary side, to step down the output voltage of the DC-DC converter

when a secondary side auxiliary supply is connected.

7

AUX_D

I

8

9

CS

I

DC-DC controller current sense input. Connect directly to the external power current sense resistor.

Used for spread spectrum frequency dithering. Connect a capacitor from DTHR to RTN and a

resistor from DTHR to FRS. If dithering is not used, short DTHR to VB pin.

DTHR

O

This pin controls the switching frequency of the DC-DC converter. Tie a resistor from this pin to

RTN to set the frequency.

10

FRS

I/O

11

12

13

RTN

VSS

VDD

—

RTN is the output of the PoE hotswap and the reference ground for the DC-DC controller.

Negative power rail derived from the PoE source.

Source of DC-DC converter start-up current. Connect to VPD for most applications.

Positive input power rail for PoE interface circuit. Derived from the PoE source. Bypass with a 0.1

µF to VSS and protect with a TVS.

14

15

VPD

DEN

—

Connect a 24.9-kΩ resistor from DEN to VPD to provide the PoE detection signature. Pulling this

pin to VSS during powered operation causes the internal hotswap MOSFET to turn off.

I/O

16

17

CLS

NC

O

Connect a resistor from CLS to VSS to program the classification current.

No connect pin. Leave open.

—

Converter error amplifier inverting (feedback) input. It is typically driven by a voltage divider from

the auxiliary winding. Also connect to the COMP compensation network.

18

FB

I

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表 5-1. Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

Compensation output of the DC-DC convertor error amplifier. Connect the compensation networks

from this pin to the FB pin to compensate the converter.

19

COMP

O

AUX_V works with AUX_D to step down the output voltage setting of the DC-DC converter when

an auxiliary supply is detected. Typically connected to FB pin through a resistor which defines the

new voltage setting.

20

21

AUX_V

VCC

O

DC/DC converter bias voltage. The internal startup current source and converter bias winding

output power this pin. Connect a 1-µF minimum ceramic capacitor to RTN.

I/O

23

24

NC

—

O

No connect pin. Leave open.

DRAIN

Drain connection to the internal switching power MOSFET of the DC/DC controller.

The exposed thermal pad must be connected to VSS. A large fill area is required to assist in heat

dissipation.

-

PAD

—

A1-A4

ANCHORS

Should be soldered to PCB for mechanical performance. These pins are not connected internally.

4

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6 Specifications

6.1 Absolute Maximum Ratings

Voltage are with respect to V_VSS(unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

100

6.5

UNIT

VDD, VPD, DEN, GND, RTN⁽²⁾

VDD to RTN

Input voltage

V

AUX_D, FB, CS, all to RTN

SRF to GND

CLS⁽³⁾

6.5

FRS⁽³⁾, COMP⁽³⁾, VB⁽³⁾, SRR⁽³⁾, DTHR⁽³⁾, RSNS⁽³⁾, AUX_V⁽³⁾, all to

RTN

–0.3

6.5

VCC to RTN

–0.3

19

150

60

Voltage

V

DRAIN to GND

CP to GND

GND to RTN

0.3

VB, VCC

Internally limited

35

Internally limited

Sourcing current

CLS

mA

COMP

RTN

DEN

1

Sinking current

AUX_V

5

COMP

Internally limited

Switching DRAIN peak current limit

2

3

I_DRAIN

A

Switching DRAIN peak current limit, Buck topology with 16% duty-

cycle

Peak sourcing

current

CP

1.5

T_J(max)

T_stg

Maximum junction temperature

Storage temperature

Internally Limited

–65 150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) I_RTN= 0 for V_RTN> 80 V.

(3) Do not apply voltage to these pins.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

IEC 61000-4-2 contact discharge⁽³⁾

V_(ESD)

Electrostatic discharge

V

±8000

±15000

IEC 61000-4-2 air-gap discharge⁽³⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) ESD per EN61000-4-2, applied between RJ-45 and output ground of the TPS23755EVM-894 evaluation module. These were the test

levels, not the failure threshold.

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6.3 Recommended Operating Conditions

Voltage with respect to V_VSS(unless otherwise noted)

MIN

0

NOM

MAX

57

UNIT

VDD, VPD, RTN, GND

VCC to RTN

0

16

AUX_D to RTN

Input voltage range

0

VB

2

V

CS to RTN

0

DRAIN to GND

CP to GND

0

125

45

0

Sinking current

RTN

350

1.6

2.5

mA

A

DRAIN, RSNS

Peak current limit

DRAIN, RSNS, Buck topology with 16% duty-cycle

Peak sourcing

current

CP

500

mA

μF

VB⁽¹⁾

0.08

0.8

30

0.1

1

Capacitance

VCC

CLS⁽¹⁾

Resistance

SRF to VB

SRR to GND

100

15

Ω

Synchronization

pulse width input

(when used)

FRS

35

ns

°C

T_J

Operating junction temperature

–40

125

(1) Voltage should not be externally applied to this pin.

6.4 Thermal Information

TPS23755

THERMAL METRIC⁽¹⁾

RJJ (VSON)

24 PINS

34.7

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

24.5

14.5

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

6.4

ψ_JB

14.5

R_θJC(bot)

6.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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ZHCSJE2B – DECEMBER 2018 – REVISED NOVEMBER 2020

6.5 Electrical Characteristics: DC-DC Controller Section

Unless otherwise noted, V_VDD= 48 V; R_DEN= 24.9 kΩ; R_FRS= 60.4 kΩ; CLS, AUX_V, RSNS and DRAIN open; CS, AUX_D,

and GND connected to RTN; SRR connected to GND; SRF, FB and DTHR connected to VB; C_VB= 0.1 μF; C_CC= 1 μF; 8.5 V

≤ V_VCC≤ 16 V; –40°C ≤ T_J≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.

[V_VSS= V_RTNand V_VPD= V_VDD] or [V_VSS= V_RTN= V_VPD], all voltages referred to V_RTNand V_GNDunless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC-DC SUPPLY (VCC)

V_CUVR

V_CUVF

V_CUVH

V_VCCrising

8

5.85

2

8.25

6.1

8.6

6.25

2.5

V

Undervoltage lockout

V_VCCfalling

Hysteresis⁽¹⁾

2.15

Operating current, converter

switching

V_VCC= 10 V, V_FB= V_RTN= V_RSNS

DRAIN with 2-kΩ pull up to 95 V

,

I_RUN

2.0

2.35

mA

V_DD= 10.2 V, V_VCC(0) = 0 V

V_DD= 35 V, V_VCC(0) = 0 V

0.5

1.0

2.5

1.5

ms

t_ST

Start-up time, C_CC= 1 μF

VCC startup voltage

0.80

Measure V_VCCduring startup, I_VCC

0 mA

=

V_{VC_ST}

11

13

15.5

V

DC-DC TIMING (FRS)

V_FB= V_RSNS= V_RTN, Measure at

DRAIN

f_SW

Switching frequency

223

248

273

kHz

V_FB= V_RSNS= V_RTN, Measure at

DRAIN

D_MAX

Duty cycle

75%

2

77.5%

2.2

80%

2.4

V_SYNC

Synchronization

Input threshold

V

FREQUENCY DITHERING RAMP GENERATOR (DTHR)

3 x I_FRS

49.6

µA

V

I_DTRCH

Charging (sourcing) current

Discharging (sinking) current

0.5 V < V_DTHR< 1.38 V

0.6 V < V_DTHR< 1.5 V

47.2

52.1

3 x I_FRS

49.6

I_DTRDC

47.2

1.41

52.1

1.60

V_DTUT

V_DTLT

Dithering upper threshold

Dithering lower threshold

Dithering pk-pk amplitude

V_DTHRrising until I_DTHR> 0

V_DTHRfalling until I_DTHR< 0

1.513

0.487

1.026

0.43

0.54

V

VDTPP

1.005

1.046

V

ERROR AMPLIFIER (FB, COMP)

V_REFC

I_{FB_LK}

G_BW

Feedback regulation voltage

1.723

1.75

1.777

0.5

V

μA

FB leakage current (source or sink) V_FB-RTN= 1.75 V

Small signal unity gain bandwidth

0.9

70

1.2

90

MHz

dB

A_OL

Open loop voltage gain

V_COMPfalling until DRAIN switching

stops

V_ZDC

0% duty-cycle threshold

1.35

1.5

1.65

V

I_COMPH

I_COMPL

COMP source current

COMP sink current

V_FB= V_RTN, V_COMP= 3 V

V_FB= V_VB, V_COMP= 1.25 V

1

mA

2.1

6

V_FB= V_VB, 15 kΩ from COMP to

RTN

V_COMPH

V_COMPL

COMP high voltage

4

5

V

COMP low voltage

COMP to CS gain

V_FB= V_VB, 15 kΩ from COMP to VB

ΔV_CS/ ΔV_COMP, 0 V < V_CS< 0.5 V

1.1

V

0.475

0.5

0.525

V/V

SOFT-START

t_SSSoft-start period

t_CDCool-down period

CURRENT SENSE (CS)

8

16

20

24

26

ms

15

V_CSMAX

Maximum threshold voltage

V_FB= V_RTN, V_CSrising

0.5

0.55

0.6

V

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ZHCSJE2B – DECEMBER 2018 – REVISED NOVEMBER 2020

6.5 Electrical Characteristics: DC-DC Controller Section (continued)

Unless otherwise noted, V_VDD= 48 V; R_DEN= 24.9 kΩ; R_FRS= 60.4 kΩ; CLS, AUX_V, RSNS and DRAIN open; CS, AUX_D,

and GND connected to RTN; SRR connected to GND; SRF, FB and DTHR connected to VB; C_VB= 0.1 μF; C_CC= 1 μF; 8.5 V

≤ V_VCC≤ 16 V; –40°C ≤ T_J≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.

[V_VSS= V_RTNand V_VPD= V_VDD] or [V_VSS= V_RTN= V_VPD], all voltages referred to V_RTNand V_GNDunless otherwise noted.

PARAMETER

t_{OFFDEL_ILM}Current limit turnoff delay

t_{OFFDEL_PW}PWM comparator turnoff delay

Blanking delay

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_CS= 0.65 V

25

41

60

ns

V_CS= 0.4 V

25

41

60

In addtition to t_OFFDEL

56.5

75

93.5

ns

Peak voltage at maximum duty

cycle, referred to CS

V_SLOPE

I_{SL_EX}

Internal slope compensation voltage

120

155

185

mV

V_FB= V_RTN, I_CSat maximum duty

cycle (ac component)

Peak slope compensation current

Bias current

30

42

-5

54

μA

DC component of CS current

-6.7

-3.3

SWITCHING POWER FET (DRAIN, RSNS)

BV_DSS

Power FET break-down voltage

Power FET on resistance

150

0.6

V

R_DS(ON)

0.77

1

1.28

1.1

Ω

Source-to-drain diode forward

voltage

V_SD

I_RSNS= 500 mA

V

SECONDARY SIDE AUXILIARY POWER (AUX_D, AUX_V)

V_AUXEN

V_AUXH

I_pullup

V_{AUX_D}rising

1.7

70

2

0.15

100

2.3

V

AUX_D threshold voltage

Hysteresis ⁽¹⁾

AUX_D pullup current

130

50

µA

V_{AUX_D}= V_VB, 5 KΩ from AUX_V to

VB

V_AVL

AUX_V output low voltage

mV

THERMAL SHUTDOWN

Turnoff temperature

Hysteresis⁽²⁾

145

159

13

165

°C

(1) The hysteresis tolerance tracks the rising threshold for a given device.

(2) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

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6.6 Electrical Characteristics: PoE and Control

Unless otherwise noted, V_VPD= 48 V; R_DEN= 24.9 kΩ; R_FRS= 60.4 kΩ; CLS, AUX_V, RSNS and DRAIN open; CS, AUX_D,

and GND connected to RTN; SRR connected to GND; SRF, FB and DTHR connected to VB; C_VB= 0.1 μF; C_CC= 1 μF;

–40°C ≤ T_J≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.

Unless otherwise noted, V_VPD= V_VDD, V_VCC= V_RTN. All voltages referred to V_VSSunless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

PD DETECTION (DEN)

Detection bias current

DEN leakage current

DEN open, V_VPD= 10 V, Measure I_VPD+ I_VDD+ I_DEN+ I_RTN

V_DEN= V_VPD= 57 V, Measure I_DEN

3.5 8.3

0.1

13.9

5

µA

μA

V

I_lkg

Measure I_VPD+ I_VDD+ I_DEN+ I_RTN, V_VPD= 1.4 V

Measure I_VPD+ I_VDD+ I_DEN+ I_RTN, V_VPD= 10 V

55.5 56.3

60

Detection current

400 407 414.5

V_{PD_DIS}

Hotswap disable threshold

3

4

5

PD CLASSIFICATION (CLS)

R_CLS= 649 Ω

R_CLS= 121 Ω

1.8 2.14

9.9 10.6

17.6 18.6

26.5 27.9

10.7 12.1

0.6 1.1

2.4

11.3

19.4

29.3

13

13 V ≤ V_DD≤ 21 V, Measure

I_VPD+ I_VDD+ I_DEN+ I_RTN

I_CLS

Classification current

mA

R_CLS= 68.1 Ω

R_CLS= 45.3 Ω

V_{CL_ON}

V_{CL_HYS}

V_{CU_OFF}

V_{CU_HYS}

I_lkg

Regulator turns on, V_VPDrising

Hysteresis⁽¹⁾

V

Classification regulator lower

threshold

1.55

23

Regulator turns off, V_VPDrising

Hysteresis⁽¹⁾

21

22

V

Classification regulator upper

threshold

0.5 0.77

1

V

Leakage current

V_VPD= 57 V, V_CLS= 0 V, V_DEN= V_VSS, Measure I_CLS

1

μA

RTN (PASS DEVICE)

ON-resistance

0.36

405 550

100 140

11 12.3

0.68

Ω

Current limit

V_RTN= 1.5 V, pulsed measurement

800 mA

220 mA

Inrush current limit

Foldback voltage threshold

Foldback deglitch time

Leakage current

V_RTN= 2 V, V_VPD: 0 V → 48 V, pulsed measurement

V_RTNrising

13.6

600

40

V

V_RTNrising to when current limit changes to inrush current limit

V_VPD= V_RTN= 100 V, V_DEN= V_VSS

150 387

µs

μA

I_lkg

PD INPUT SUPPLY (VPD, VDD)

UVLO_R

V_VPDrising

34.7 35.5

4.1 4.5

300

36.7

4.7

V

Undervoltage lockout threshold

UVLO_H

Hysteresis ⁽¹⁾

Operating current

Off-state current

VCC open, 40 V ≤ V_VPD= V_VDD≤ 57 V, Startup completed, Measure I_VPD+ I_VDD

RTN, GND and VCC open, V_VPD= 30 V, Measure I_VPD

580

330

I_{VPD_VDD}

µA

THERMAL SHUTDOWN

Turnoff temperature

Hysteresis⁽²⁾

145 159

13

165

°C

(1) The hysteresis tolerance tracks the rising threshold for a given device.

(2) These parameters are provided for reference only.

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6.7 Typical Characteristics

12.5

570

568

566

564

562

560

T_J= -40èC

T_J= 25èC

T_J= 125èC

10

7.5

5

2.5

0

1

2

3

4

VPD-VSS Voltage (V)

5

6

7

8

9

10

-50

-25

0

25

50

75

100

125

Junction Temperature (èC)

D001

D004

图 6-1. Detection Bias Current vs Voltage

图 6-2. PoE Current Limit vs Temperature

160

158

156

154

152

150

148

146

0.6

0.55

0.5

0.45

0.4

0.35

0.3

0.25

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Junction Temperature (èC)

D005

D003

图 6-3. PoE Inrush Current Limit vs Temperature

图 6-4. Pass FET Resistance vs Temperature

650

1.25

1.2

T_J= -40èC

T_J= 25èC

T_J= 125èC

C_CC= 1 mF

V_VDD= 10.2 V

V_VDD= 35 V

600

550

500

450

400

350

300

250

1.15

1.1

1.05

1

0.95

0.9

0.85

0.8

0.75

0.7

25

30

35

40 45

VPD-VSS Voltage (V)

50

55

60

-50

-25

0

25

50

75

100

125

Junction Temperature (èC)

D002

D007

图 6-5. VPD and VDD Supply Current vs Voltage

图 6-6. Converter Startup Time vs Temperature

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6.7 Typical Characteristics (continued)

18

4

3.75

3.5

3.25

3

R_FRS= 37.4 kW

R_FRS= 60.4 kW

R_FRS= 301 kW

17.5

17

2.75

2.5

2.25

2

16.5

16

1.75

1.5

1.25

1

15.5

15

-50

-25

0

25

50

75

100

125

9

10

11 12

VCC Voltage (V)

13

14

Junction Temperature (èC)

D021

D006

图 6-7. Converter Soft-Start Time vs Temperature

图 6-8. Controller Bias Current vs Voltage

400

800

600

400

200

0

350

300

250

200

R_FRS= 37.4 kW

R_FRS= 60.4 kW

R_FRS= 301 kW

150

100

50

0

-50

-25

0

25

50

75

100

125

0

5

10

15

20

25

30

35

40

45

50

Junction Temperature (èC)

Programmable Conductance, 10⁶/R_FRS(W^-1

)

D008

D009

图 6-9. Switching Frequency vs Temperature

图 6-10. Switching Frequency vs Programmed Resistance

51

T_J= 25èC

50.5

50

50.5

50

49.5

49

0.5

0.75

1

DTHR Voltage (V)

1.25

1.5

0.5

0.75

1

DTHR Voltage (V)

1.25

1.5

D015

D016

图 6-11. Frequency Dithering Charging Current

图 6-12. Frequency Dithering Discharging Current

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6.7 Typical Characteristics (continued)

1.022

1.021

1.02

1.76

1.755

1.75

1.019

1.018

1.017

1.016

1.015

1.014

1.745

1.74

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Junction Temperature (èC)

D017

D020

图 6-13. Frequency Dithering Peak-to-Peak Amplitude

图 6-14. Feedback Regulation Voltage vs Temperature

50

80

48

46

44

42

40

38

36

78

76

74

72

70

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Junction Temperature (èC)

D010

D011

图 6-15. Current Slope Compensation Current vs Temperature

图 6-16. Blanking Period vs Temperature

50

48

46

44

42

40

48

46

44

42

40

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Junction Temperature (èC)

D013

D012

图 6-17. Converter PWM Comparator Delay vs Temperature

图 6-18. Converter Current Limit Delay vs Temperature

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6.7 Typical Characteristics (continued)

4

12

10

8

T_J= -40èC

T_J= 25èC

T_J= 125èC

3

2

1

0

6

4

T_J= -40èC

T_J= 25èC

T_J= 125èC

2

0

0.8

1.6

2.4 3.2

COMP Voltage (V)

4

4.8

5.6

0.5

1

1.5

2 2.5

COMP Voltage (V)

3

3.5

4

D018

D019

图 6-19. Error Amplifier Source Current

图 6-20. Error Amplifier Sink Current

100

90

80

70

60

50

40

30

20

10

0

135

120

105

90

75

60

45

30

15

0

T_J= -40èC

T_J= 25èC

T_J= 125èC

-10

-20

100

1k

10k 100k

Frequency (Hz)

1M

100

1k

10k 100k

Frequency (Hz)

1M

D023

D024

图 6-21. Error Amplifier Gain vs Frequency

图 6-22. Error Amplifier Phase vs Frequency

1.4

1.2

1

0.8

0.6

0.4

-50

-25

0

25

50

75

100

125

Junction Temperature (èC)

D014

图 6-23. Switching FET Resistance vs Temperature

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7 Detailed Description

7.1 Overview

The TPS23755 device is a 24-pin integrated circuit that contains all of the features needed to implement an

IEEE802.3at Type-1 powered device (PD), combined with a fully integrated 150-V switching power FET and a

current-mode DC-DC controller optimized for flyback switching regulator designs using primary side control. The

TPS23755 applies to single-output flyback converter applications where a secondary side diode rectifier is used.

Basic PoE PD functionality supported includes detection, hardware classification, and inrush current limit during

startup. DC-DC converter features include startup function and current mode control operation. The TPS23755

device integrates a low 0.36-Ω internal switch to support Type-1 applications.

The TPS23755 features secondary auxiliary power detect (AUX_D) capability, providing priority for a secondary

side power adapter, while ensuring smooth transition (via AUX_V) to and from the PoE power input.

The TPS23755 device contains several protection features such as ƒ, current limit foldback, and a robust 100-V

internal return switch.

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7.2 Functional Block Diagram

VDD

VCC

COMP

FB

Regulator

t

E/A

+

50kꢀ

Vrefc

(1.75V)

disch

t

0.25 V

+

chrg

Converter off

from PD

RTN

uvlo

Control

Soft Start

disch

chrg

VB

Regulator

Reference

Current Ramp

SRF

+

0.75 V

40 ꢁA (pk)

t

CS

DRAIN

3.75k ꢀ

Blanking

Control

1

D

Q

+

CLRB

CLK

RSNS

SRR

0.55 V

t

FRS

Oscillator

CP

DTHR

AUX V

GND

5V

AUX_D

RTN

Detection

Comp.

Class

Comp.

4V

12.1V &

11V

VPD

Class

Comp.

V_SS

DEN

CLS

22V &

21.2V

1.25V

REG.

400µS

800ms

12.3V

& 1V

Converter OFF

S

Q

R

Inrush latch

Inrush limit

threshold

1

0

35.5V &

31V

UVLO

Comp.

1

0

Current limit

threshold

OTSD

I_RTNsense

High if over

temperauture

VSS

RTN

Signals referenced to V_SSunless

otherwise noted

Hotswap

MOSFET

I_RTNsense,1 if < 90% of inrush and current limit

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7.3 Feature Description

See 图 8-1 for component reference designators (R_CSfor example ), and Electrical Characteristics: DC-DC

Controller Section for values denoted by reference (V_CSMAXfor example). Electrical Characteristic values take

precedence over any numerical values used in the following sections.

7.3.1 CLS Classification

An external resistor (R_CLSin 图 8-1) connected between the CLS pin and VSS provides a classification signature

to the PSE. The controller places a voltage of approximately 1.25 V across the external resistor whenever the

voltage differential between VPD and VSS lies from about 11 V to 22 V. The current drawn by this resistor,

combined with the internal current drain of the controller and any leakage through the internal pass MOSFET,

creates the classification current. 表 7-1 lists the external resistor values required for each of the PD power

ranges defined by IEEE802.3at. The maximum average power drawn by the PD, plus the power supplied to the

downstream load, should not exceed the maximum power indicated in Table 7-1. The TPS23755 supports class

0 – 3 power levels.

表 7-1. Class Resistor Selection

POWER AT PD PI

CLASS

RESISTOR (Ω)

MINIMUM (W)

0.44

MAXIMUM (W)

12.95

0

1

2

3

649

121

0.44

3.84

6.49

68.1

45.3

6.49

12.95

7.3.2 DEN Detection and Enable

DEN pin implements two separate functions. A resistor (R_DENin 图 8-1) connected between VPD and DEN

generates a detection signature whenever the voltage differential between VPD and VSS lies from approximately

1.4 to 11 V. Beyond this range, the controller disconnects this resistor to save power. The IEEE 802.3at standard

specifies a detection signature resistance, R_DENfrom 23.75 kΩ to 26.25 kΩ, or 25 kΩ ± 5%. TI recommends a

resistor of 24.9 kΩ ± 1% for R_DEN

.

Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET and class regulator

to turn off. If the resistance connected between VDD and DEN is divided into two roughly equal portions,

then the application circuit can disable the PD by grounding the tap point between the two resistances, while

simultaneously spoiling the detection signature which prevents the PD from properly re-detecting.

7.3.3 Internal Pass MOSFET

RTN pin provides the negative power return path for the load. It is internally connected to the drain of the PoE

hotswap MOSFET, and the DC-DC controller return. RTN must be treated as a local reference plane (ground

plane) for the DC-DC controller and converter primary to maintain signal integrity.

Once V_VPDexceeds the UVLO threshold, the internal pass MOSFET pulls RTN to VSS. Inrush limiting prevents

the RTN current from exceeding a nominal value of about 140 mA until the bulk capacitance (C_BULKin 图 8-1) is

fully charged. Inrush ends when the RTN current drops below about 125 mA. The RTN current is subsequently

limited to about 0.45 A.

If RTN ever exceeds about 12.3 V for longer than 400 μs, then the PD returns to inrush limiting.

7.3.4 DC-DC Controller Features

The TPS23755 device DC-DC controller implements a typical current-mode control as shown in Functional

Block Diagram. Features include oscillator, overcurrent and PWM comparators, current-sense blanker, soft start,

gate driver and switching power FET. In addition, an internal current-compensation ramp generator, frequency

synchronization logic, built-in frequency dithering functionality, thermal shutdown, and start-up current source

with control are provided.

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The TPS23755 is optimized for isolated converters, and it includes an internal error amplifier. The voltage

feedback is from the bias winding. The COMP output of the error amplifier is directly fed to a 2:1 internal resistor

divider and an offset of V_ZDC/2 (approximately 0.75 V) which defines a current-demand control for the pulse

width modulator (PWM). A V_COMPbelow V_ZDCstops converter switching, while voltages above (V_ZDC+ 2 ×

(V_CSMAX+ V_SLOPE)) does not increase the requested peak current in the switching MOSFET.

The internal start-up current source and control logic implement a bootstrap-type startup. The startup current

source charges C_CCfrom VDD and maintain its voltage when the converter is disabled or during the soft-start

period, while operational power must come from a converter (bias winding) output.

The bootstrap source provides reliable start-up from widely varying input voltages, and eliminates the continual

power loss of external resistors.

The peak current limit does not have duty cycle dependency unless R_Sis used as shown in 图 7-2 to increase

slope compensation. This makes it easier to design the current limit to a fixed value.

The DC-DC controller has an OTSD that can be triggered by heat sources including the power switching FET

and GATE driver. The controller OTSD turns off the switching FET and resets the soft-start generator.

7.3.4.1 VCC, VB and Advanced PWM Startup

The VCC pin connects to the auxiliary bias supply for the DC-DC controller. The switching MOSFET gate driver

draws current directly from the VB pin, which is the output of an internal 5-V regulator fed from VCC. A startup

current source from VDD to VCC implements the converter bootstrap startup. VCC must receive power from

an auxiliary source, such as an auxiliary winding on the flyback transformer, to sustain normal operation after

startup.

The startup current source is turned on during the inrush phase, charging C_CCand maintaining its voltage, and it

is turned off only after the DC-DC soft-start cycle has been completed, which occurs when the DC-DC converter

has ramped up its output voltage, as shown in 图 7-1. Internal loading on VCC and VB is initially minimal

while C_CCcharges, to allow the converter to start. Due to the high current capability of the startup source, the

recommended capacitance at VCC is relatively small, typically 1 μF in most applications.

VB is the 5-V bias rail for the switching FET gate driver circuit. A 0.1-μF bypass capacitor between VB and RTN

is required. Additionally, a 6.2-V Zener diode from VB to RTN is required.

Once V_VCCfalls below its UVLO threshold, the converter shuts off and the startup current source is turned back

on, initiating a new PWM startup cycle.

High current startup is ON for the whole soft-start

cycle to allow low VCC capacitance

VCC Startup Source ON

End of Soft-Start, Startup source

turned off

PD + Power Supply Fully

Operational

HSW cap

recharge

Soft Start

图 7-1. Advanced Startup

7.3.4.2 CS, Current Slope Compensation and Blanking

The current-sense input for the DC-DC converter should be connected to the high side of the current-sense

resistor of the switching MOSFET. The current-limit threshold, V_CSMAX, defines the voltage on CS above which

the switching FET ON-time is terminated regardless of the voltage on COMP output.

Routing between the current-sense resistor and the CS pin must be short to minimize cross-talk from noisy

traces such as DRAIN and CP, and to a lower degree to SRR and SRF.

Current-mode control requires addition of a compensation ramp to the sensed inductor (flyback transformer)

current for stability at duty cycles near and over 50%. The TPS23755 has a maximum duty cycle limit of 78.5%,

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permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers.

While the maximum duty cycle is 78.5%, converters may be designed that run at duty cycles well below this for a

narrower, 36-V to 57-V range. The TPS23755 provides a fixed internal compensation ramp that suffices for most

applications. R_S(see 图 7-2) may be used if the internally provided slope compensation is not enough. It works

with ramp current (I_PK= I_SL-EX, approximately 40 μA) that flows out of the CS pin when the MOSFET is on. The

I_PKspecification does not include the approximately 5-μA fixed current that flows out of the CS pin.

Most current-mode control papers and application notes define the slope values in terms of V_PP/T_S(peak ramp

voltage / switching period); however, Electrical Characteristics: DC-DC Controller Section specifies the slope

peak (V_SLOPE) based on the maximum duty cycle. Assuming that the desired slope, V_SLOPE-D(in mV/period),

is based on the full period, compute R_Sper 方程式 1 where V_SLOPE, D_MAX, and I_SL-EXare from Electrical

Characteristics: DC-DC Controller Section with voltages in mV, current in μA, and the duty cycle is unitless (for

example, D_MAX= 0.78).

V_SLOPE(mV)

:

;

BV_{SLOPE _D}mV F @

W

AC

D_MAX

: ;

R_S3 =

× 1000

I

(JA)/D_MAX

SL_EX

(1)

DRAIN

RSNS

CS

R_S

R_CS

C_S

图 7-2. Additional Slope Compensation

Blanking provides an interval between the FET gate drive going high and the current comparator on CS

actively monitoring the input. This delay allows the normal turnon current transient (spike) to subside before the

comparator is active, preventing undesired short duty cycles and premature current limiting.

The TPS23755 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This

avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some

situations or designers that prefer an R-C approach, for example if the presence of R_Scauses increased noise,

due to adjacent noisy signals, to appear at CS pin. The TPS23755 provides a pulldown on CS (approximately

400 Ω) during the GATE OFF-time to improve sensing when an R-C filter must be used, by reducing cycle-to-

cycle carry-over voltage on C_S.

7.3.4.3 COMP, FB, CP and Opto-less Feedback

The TPS23755 DC-DC controller implements current-mode control, using a voltage control loop error amplifier

(pins FB and COMP) to define the input reference voltage of the current mode control comparator which

determines the switching MOSFET peak current. Loop compensation components are connected between

COMP and FB.

V_COMPbelow V_ZDCcauses the converter to stop switching. The maximum (peak) current is requested at

approximately (V_ZDC+ 2 × (V_CSMAX+ V_SLOPE)). The AC gain from COMP to the PWM comparator is 0.5.

The TPS23755 DC-DC controller can operate with feedback from an auxiliary winding of the flyback power

transformer, eliminating the need for external shunt regulator and optocoupler. It also operates with continuously

connected feedback, enabling better optimization of the power supply, and resulting in significantly lower noise

sensitivity.

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The TPS23755 applies to single-output flyback converter applications where a secondary side diode rectifier is

used. In typical 12 V output application and when combined with a correctly designed power transformer, ±5%

load regulation over a wide (5% to 100%) output current range can be achieved.

7.3.4.4 FRS Frequency Setting and Synchronization

The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the

TPS23755 converter to a higher frequency. The internal oscillator sets the maximum duty cycle and controls the

current-compensation ramp circuit, making the ramp height independent of frequency. R_FRSmust be selected

per 方程式 2.

15000

R_FRS(k3) =

f_SW(kHz)

(2)

The TPS23755 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,

or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by

applying a short pulse ( > 35 ns) of magnitude V_SYNCto FRS as shown in 图 7-3. R_FRSmust be chosen so that

the maximum free-running frequency is just below the desired synchronization frequency. The synchronization

pulse terminates the potential ON-time period, and the OFF-time period does not begin until the pulse

terminates. A short pulse is preferred to avoid reducing the potential ON-time.

Figure 7-3 shows examples of nonisolated and transformer-coupled synchronization circuits. R_Treduces noise

susceptibility for the isolation transformer implementation. The FRS node must be protected from noise because

it is high impedance.

Synchronization

Pulse

FRS

Pulse

FRS

47pF

1000pF

T_SYNC

V_SYNC

T_SYNC

1:1

V_SYNC

图 7-3. Synchronization

7.3.4.5 Frequency Dithering for Spread Spectrum Applications

The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted

emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions.

Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit

board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques.

A more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant

PoE Powered Device With Isolated Flyback, SLUA469. Additionally, IEEE 802.3at sections 33.3 and 33.4 have

requirements for noise injected onto the Ethernet cable based on compatibility with data transmission.

A technique referred to as frequency dithering can also be used to provide additional EMI measurement

reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider

bandwidth, thus lowering peak measurements.

Frequency dithering is a built-in feature of the TPS23755. The oscillator frequency can be dithered by connecting

a capacitor from DTHR to RTN and a resistor from DTHR to FRS. An external capacitor, C_DTR(图 8-1), is

selected to define the modulation frequency f_m. This capacitor is being continuously charged and discharged

between slightly less than 0.5 V and slightly above 1.5 V by a current source/sink equivalent to approximately 3x

the current through FRS pin. C_DTRvalue is defined according to:

3

W

R_FRS(3)

C_DTR

=

2.052 × f_m(Hz)

(3)

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f_mshould always be higher than 9 kHz, which is the resolution bandwidth applied during conducted emission

measurement. Typically, f_mshould be set to around 11 kHz to account for component variations.

The resistor R_DTRis used to determine ∆f, which is the amount of dithering, and its value is determined

according to:

0.513 × R_FRS(3)

R_DTR(3) =

%DTHR

(4)

For example, a 13.2% dithering with a nominal switching frequency of 250 kHz results in frequency variation of

±33 kHz.

7.3.4.6 SST and Soft-Start of the Switcher

Converters require a soft-start on the voltage error amplifier to prevent output overshoot on startup. In PoE

applications, the PD also needs soft-start to limit its input current at turnon below the limit allocated by the power

source equipment (PSE).

The TPS23755 provides primary side closed loop controlled soft-start, which applies a slowly rising ramp voltage

to a second control input of the error amplifier. The lower of the reference input and soft-start ramps controls the

error amplifier, allowing the output voltage to rise in a smooth monotonic fashion.

The soft-start period of the TPS23755 is internally set to a nominal value of 16 ms.

7.3.4.7 AUX_V, AUX_D and Secondary Adapter Or'ing

The TPS23755’s unique auxiliary power detect capability provides priority for a secondary side power adapter,

while ensuring smooth transition to and from the PoE power. This can be applied for example in applications

where the auxiliary power is the main power, while the PoE input acts as the backup power. The auxiliary voltage

is “Ore’d” directly at the output of flyback transformer, on secondary side. See 图 7-4 below where the output

voltage is nominally 12 V.

When the auxiliary is present, a signal (AUX_D) tells the PD PWM to lower its output voltage slightly below the

auxiliary voltage to ensure the auxiliary has priority to power the main output. When the auxiliary power goes

away, the DC-DC converter increases back its output voltage, to ensure seamless transition. One significant

advantage of this approach is that the efficiency of the PoE-powered flyback power stage can be optimized

independently of the need for seamless transition. The adjustability of the lower voltage level allows the use of

highly inaccurate auxiliary voltage sources. Such feature eases the thermal design, in particular when secondary

diode rectification is used, since when PoE powered, the flyback stage can deliver power at a higher output

voltage, and hence at a lower output current.

In 图 7-4 below, R_OUT1ensures that the PSE maintains power while the auxiliary is present, ensuring there will

be no power interruption when the auxiliary power is removed.

The lower voltage level is programmable with the R_AUXresistor, which impacts the feedback network division

ratio. Note however that the flyback power transformer design and resistor selection must be such that V_VCCwill

remain above nominally 6.1 V (V_CUVF) while the auxiliary power is present.

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V_OUT

D_OUT

12V

TPS23755

C_OUT

VCC

COMP

C_CC

C_CC2

R₁

R₂

FB

AUX_V

RTN

Vout Flyback

R_OUT1

Secondary

Adapter

(V_ADAPTER

)

AUX_D

Secondary side Aux

Supply Detection

12V

< V_ADAPTER

Vout Flyback

~12V

V_ADAPTER

0V

12V

V_OUT

~12V

图 7-4. Secondary Side Priority Control with Smooth Transition

7.3.5 Internal Switching FET - DRAIN, RSNS, SRF and SRR

The DRAIN and RSNS provide connection to the drain and source of the integrated switching power FET. RSNS

pin is a high current pin and it must have a short connection to the current sense resistor which other end

is directly tied to a plane referenced to the GND pin. Current sensing is done with CS pin, which should be

connected directly to the high side of the current sense resistor.

The internal FET gate driver is powered from VB voltage rail and the return path is through the GND pin. SRF

and SRR pins provide slew rate control of the switching FET. The gate sourcing current is drawn through the

SRF pin which is tied to VB pin through a resistor (0-100 Ω). The gate sinking current circulates through the SRR

pin which is externally tied to the GND pin either via a low-value resistor (0-15 Ω) or a direct connection.

7.3.6 VPD Supply Voltage

VPD pin connects to the positive side of the input supply. It provides operating power to the PD controller and

allows monitoring of the input line voltage. If V_VPDfalls below its UVLO threshold and goes back above it, or if

a thermal shutdown resumes while V_VPDis already above its UVLO threshold, the TPS23755 returns to inrush

limiting.

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7.3.7 VDD Supply Voltage

VDD connects to the source of DC-DC converter startup current. It is connected to VPD for most applications. It

may also be isolated by a diode from VPD to support some PoE priority operation.

7.3.8 GND

GND is the power ground used by the flyback power FET gate driver and CP pin. Connect to the RTN plane. VB

bypassing capacitor should be directly connected to the GND pin.

7.3.9 VSS

VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-

limited hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap

switch. The exposed thermal PAD must be connected to this pin to ensure proper operation.

7.3.10 Exposed Thermal PAD

The exposed thermal PAD is internally connected to VSS pin. It should be tied to a large VSS copper area on

the PCB to provide a low resistance thermal path to the circuit board. TI recommends maintaining a clearance of

0.025” between VSS and high-voltage signals such as VPD and VDD.

7.4 Device Functional Modes

7.4.1 PoE Overview

The following text is intended as an aid in understanding the operation of the TPS23755, but it is not a substitute

for the actual IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33

(PoE), adding high-power options and enhanced classification.

Generally speaking, a device compliant to IEEE 802.3-2008 is referred to as a Type 1 device, and devices with

high power or enhanced classification is referred to as Type 2 devices. The TPS23755 is intended to power Type

1 devices (up to 13 W), and is fully compliant to IEEE 802.3at for hardware classes 0 - 3. Standards change and

must always be referenced when making design decisions.

The IEEE 802.3at standard defines a method of safely powering a PD (powered device) over a cable, and then

removing power if a PD is disconnected. The process proceeds through an idle state and three operational

states of detection, classification, and operation. The PSE leaves the cable unpowered (idle state) while it

periodically looks to see if something has been plugged in; this is referred to as detection. The low power levels

used during detection are unlikely to damage devices not designed for PoE. If a valid PD signature is present,

the PSE may inquire how much power the PD requires; this is referred to as (hardware) classification. Only Type

2 PSEs are required to do hardware classification. The PD may return the default 13-W current-encoded class,

or one of four other choices. The PSE may then power the PD if it has adequate capacity. Once started, the PD

must present the maintain power signature (MPS) to assure the PSE that it is still present. The PSE monitors its

output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle

state. 图 7-5 shows the operational states as a function of PD input voltage.

Shut-

down

Classify

Normal Operation

Detect

0

2.7

10.1 14.5

20.5

30

PI Voltage (V)

36

57

42

3/06/08

图 7-5. Operational States

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The PD input is typically an RJ-45 eight-lead connector which is referred to as the power interface (PI). PD

input requirements differ from PSE output requirements to account for voltage drops in the cable and operating

margin. The IEEE 802.3at standard uses a cable resistance of 20 Ω for Type 1 devices to derive the voltage

limits at the PD based on the PSE output voltage requirements. Although the standard specifies an output power

of 15.4 W at the PSE, only 13 W is available at the PI due to the worst-case power loss in the cable. The PSE

can apply voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT), or between

the two spare pairs (4–5 and 7–8). Power application to the same pin combinations in 1000baseT systems

is recognized in IEEE 802.3at. 1000baseT systems can handle data on all pairs, eliminating the spare pair

terminology. The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges to

accept power from any of the possible PSE configurations. The voltage drops associated with the input bridges

create a difference between the standard limits at the PI and the TPS23755 specifications.

The PSE is permitted to disconnect a PD if it draws more than its maximum class power over a one second

interval. A Type 1 PSE compliant to IEEE 802.3at is required to limit current to between 400 mA and 450 mA

during powered operation, and it must disconnect the PD if it draws this current for more than 75 ms. Class 0

and 3 PDs may draw up to 400-mA peak currents for up to 50 ms. The PSE may set lower output current limits

based on the declared power requirements of the PD.

7.4.2 Threshold Voltages

The TPS23755 has a number of internal comparators with hysteresis for stable switching between the various

states as shown in 图 7-5. 图 7-6 relates the parameters in Electrical Characteristics: DC-DC Controller Section

and Electrical Characteristics: PoE and Control to the PoE states. The mode labeled idle between classification

and operation implies that the DEN, CLS, and RTN pins are all high impedance.

PD Powered

Idle

Classification

V_VPD-V_VSS

Detection

V_{CU_HYS}

V_{CU_OFF}

V_{CL_HYS}

V_{CL_ON}

V_{UVLO_H}

1.4 V

V_{UVLO_R}

Note: Variable names refer to Electrical Characteristic

Table parameters

图 7-6. Threshold Voltages

7.4.3 PoE Start-Up Sequence

The waveforms of 图 7-7 demonstrate detection, classification, and start-up from a Type 1 PSE. The key

waveforms shown are V_VPD-VSS, V_RTN-VSS, and I_PI. IEEE 802.3at requires a minimum of two detection levels;

however, four levels are shown in this example. Four levels guard against misdetection of a device when

plugged in during the detection sequence.

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图 7-7. PoE Start-Up Sequence

7.4.4 Detection

The TPS23755 is in detection mode whenever V_{VPD-V SS}is below the lower classification threshold. When the

input voltage rises above V_{CL_ON}, the DEN pin goes to an open-drain condition to conserve power. While in

detection, RTN is high impedance, almost all the internal circuits are disabled, and the DEN pin is pulled to V_SS

.

An R_DENof 24.9 kΩ (1%), presents the correct signature. It may be a small, low-power resistor because it only

sees a stress of about 5 mW. A valid PD detection signature is an incremental resistance between 23.75 kΩ and

26.25 kΩ at the PI.

The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with

the parallel combination of R_DENand the TPS23755 bias loading. The incremental resistance of the input diode

bridge may be hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge

resistance is partially cancelled by the effective resistance of the TPS23755 during detection.

7.4.5 Hardware Classification

Hardware classification allows a PSE to determine the power requirements of a PD before starting, and helps

with power management once power is applied. The maximum power entries in 表 7-1 determine the class the

PD must advertise. A Type 1 PD may not advertise Class 4. The PSE may disconnect a PD if it draws more than

its stated Class power. The standard permits the PD to draw limited current peaks; however, the average power

requirement always applies.

Voltage from 14.5 V to 20.5 V is applied to the PD for up to 75 ms during hardware classification. A fixed

output voltage is sourced by the CLS pin, causing a fixed current to be drawn from VPD through R_CLS. The total

current drawn from the PSE during classification is the sum of bias and R_CLScurrents. PD current is measured

and decoded by the PSE to determine which of the five available classes is advertised (see Table 7-1). The

TPS23755 disables classification above V_{CU_OFF}to avoid excessive power dissipation. CLS voltage is turned off

during PD thermal limit or when DEN is active. The CLS output is inherently current-limited, but should not be

shorted to VSS for long periods of time.

7.4.6 Maintain Power Signature (MPS)

The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating

voltage is applied. A valid MPS consists of a minimum DC current of 10 mA (at a duty cycle of at least 75 ms on

every 225 ms) and an AC impedance lower than 26.25 kΩ in parallel with 0.05 μF. The AC impedance is usually

accomplished by the minimum C_BULKrequirement of 5 μF. When DEN is used to force the hotswap switch off,

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the DC MPS is not met. A PSE that monitors the DC MPS will remove power from the PD when this occurs. A

PSE that monitors only the AC MPS may remove power from the PD.

7.4.7 Start-Up and Converter Operation

The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides

full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and

classification. The converter circuits discharges C_DD, C_CC, and C_VBwhile the PD is unpowered. Thus V_VDD-RTN

will be a small voltage until just after full voltage is applied to the PD, as seen in 图 7-7.

The PSE drives the PD input voltage to the operating range once it has decided to power up the PD. When V_PD

rises above the UVLO turnon threshold (V_UVLO-R, approximately 35.5 V) with RTN high, the TPS23755 enables

the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of 图 7-8 for an

example. Converter switching is disabled while C_DDcharges and V_RTNfalls from V_VDDto nearly V_VSS; however,

the converter start-up circuit is allowed to charge C_CC. Once the inrush current falls about 10% below the inrush

current limit, the PD control switches to the operational level (approximately 450 mA) and converter switching is

permitted.

Converter switching is allowed if the PD is not in inrush current limit and the VCC under-voltage lockout (V_CUVR

)

circuit permits it. Continuing the start-up sequence shown in Figurer 7-7, V_VCCrises as the start-up current

source charges C_CCand the converter switching is inhibited by the status of the VCC UVLO. The VB regulator

powers the internal converter circuits as V_VCCrises.

Once V_VCCgoes above its UVLO (nominally 8.25 V), the converter switching is enabled following the closed loop

controlled soft-start sequence. Note that the startup current source capability is such that it can fully maintain

V_VCCduring the converter soft-start without requiring any significant C_CCcapacitance, in 48 V input applications.

At the end of the soft-start period, the startup current source is turned off. V_VCCfalls as it powers the internal

circuits including the switching MOSFET gate. If the converter control-bias output rises to support V_VCCbefore it

falls to V_CUVF(nominally 6.1 V), a successful start-up occurs. Figure 7-7 shows a small droop in V_VCCwhile the

output voltage rises smoothly and a successful start-up occurs.

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50V/div

V_VDD-RTN

Converter

starts

PI powered

Inrush

100mA/div

I_PI

V_VCC-RTN

Startup turn off

5V/div

V_OUT

10V/div

OUTPUT VOLTAGE

SOFT START

Time: 10ms/div

图 7-8. Power Up and Start

The converter shuts off when V_VCCfalls below its lower UVLO. This can happen when power is removed from

the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall

including the one that powers VCC. The control circuit discharges VCC until it hits the lower UVLO and turns

off. A restart initiates if the converter turns off and there is sufficient VDD voltage. This type of operation is

sometimes referred to as hiccup mode, which when combined with the soft-start provides robust output short

protection by providing time-average heating reduction of the output rectifier.

图 7-9 illustrates the situation when there is severe overload at the main output which causes VCC hiccup. After

VCC went below its UVLO due to the overload, the startup source is turned back on. Then, a new soft-start cycle

is reinitiated, introducing a short pause before the output voltage is ramped up.

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V_OUToverload

Converter

Turn off then restart

I_PI

100mA/div

Startup turn off

V_VCC-RTN

VCC

UVLO

5V/div

V_OUT

10V/div

OUTPUT VOLTAGE

SOFT START

COOL DOWN

Time: 10ms/div

图 7-9. Restart Following Severe Overload at Main Output of Flyback DC-DC Converter

If V_VPD-VSSdrops below the lower PoE UVLO (UVLO_R – UVLO_H, approximately 31 V), the hotswap MOSFET

is turned off, but the converter still runs. The converter stops if V_VCCfalls below the V_CUVF(nominally 6.1 V),

the hotswap is in inrush current limit, the SST pin is pulled to ground, V_VDD-RTNfalls below typically 7.7 V

(approximately 0.75 V hysteresis) or the converter is in thermal shutdown.

7.4.8 PD Self-Protection

The PD section has the following self-protection functions.

•

Hotswap switch current limit

Hotswap switch foldback

Hotswap thermal protection

The internal hotswap MOSFET is protected against output faults with a current limit and deglitched foldback.

The PSE output cannot be relied on to protect the PD MOSFET against transient conditions, requiring the PD

to provide fault protection. High stress conditions include converter output shorts, shorts from VDD to RTN, or

transients on the input line. An overload on the pass MOSFET engages the current limit, with V_RTN-VSSrising

as a result. If V_RTNrises above approximately 12.3 V for longer than approximately 400 μs, the current limit

reverts to the inrush limit, and turns the converter off. The 400-μs deglitch feature prevents momentary transients

from causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE protection.

图 7-10 shows an example of recovery from a 15-V PSE rising voltage step. The hotswap MOSFET goes into

current limit, overshooting to a relatively low current, recovers to 420 mA, full-current limit, and charges the input

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capacitor while the converter continues to run. The MOSFET did not go into foldback because V_RTN-VSSwas

below 12 V after the 400-μs deglitch.

I_PI

200mA/div

CBULK completes

charge while converter

operates

V_VSS-RTN≈ -15V

10V/div

V_VPD-VSS

20V/div

Time: 200us/div

图 7-10. Response to PSE Step Voltage

The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like start-up or

operation into a VPD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown

(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The PD

restarts in inrush current limit when exiting from a PD overtemperature event.

Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off. This feature

allows a PD with secondary-side adapter ORing to achieve adapter priority. Take care with synchronous

converter topologies that can deliver power in both directions.

The hotswap switch is forced off under the following conditions:

•

V_{DE N}≤ V_{PD_DIS}when V_VPD-VSSis in the operational range

PD over temperature

V_VPD-VSS< PoE UVLO (approximately 31 V)

7.4.9 Adapter ORing

Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power

solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular

installation. While most applications only require that the PD operate when both sources are present, the

TPS23755 device supports forced operation from either of the power sources. 图 7-11 illustrates three options

for diode ORing external power into a PD. Only one option would be used in any particular design. Option 1

applies power to the device input, option 2 applies power between the device PoE section and the power circuit,

and option 3 applies power to the output side of the converter. Each of these options has advantages and

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disadvantages. Many of the basic ORing configurations and much of the discussion contained in the application

note Advanced Adapter ORing Solutions using the TPS23753, (SLVA306), apply to the TPS23755.

Low Voltage

Output

DEN

CLS

Power

Circuit

VSS

RTN

Adapter

Option 2

Adapter

Option 3

Adapter

Option 1

图 7-11. ORing Configurations

Preference of one power source presents a number of challenges. Combinations of adapter output voltage

(nominal and tolerance), power insertion point, and which source is preferred determine solution complexity.

Several factors contributing to the complexity are the natural high-voltage selection of diode ORing (the simplest

method of combining sources), the current limit implicit in the PSE, PD inrush, and protection circuits (necessary

for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for many of the

combinations. However, the TPS23755 device offers several built-in features that simplify some combinations.

Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48-V adapter with PoE

(option 1) presents the problem that either source might be higher. A blocking switch would be required to assure

which source was active. A second example is combining a 12-V adapter with PoE using option 2. The converter

draws approximately four times the current at 12 V from the adapter than it does from PoE at 48 V. Transition

from adapter power to PoE may demand more current than can be supplied by the PSE. The converter must

be turned off while C_BULKcapacitance charges, with a subsequent converter restart at the higher voltage and

lower input current. A third example is use of a 12-V adapter with ORing option 1. The PD hotswap would have

to handle four times the current, and have 1/16 the resistance (be 16 times larger) to dissipate equal power. A

fourth example is that MPS is lost when running from the adapter, causing the PSE to remove power from the

PD. If adapter power is then lost, the PD stops operating until the PSE detects and powers the PD.

The TPS23755 has a unique feature that can be used to achieve seamless transition while applying option

3. It provides adapter priority by reducing the DC-DC output voltage when the adapter voltage is present. An

optocoupler is typically driven from the secondary side of the converter when the adapter voltage is present,

which commands the converter voltage to go down to a predetermined voltage level, by use of pins AUX_D and

AUX_V. This voltage level is lower than the minimum adapter voltage to ensure priority. The DC-DC converter

stays in operation, which with appropriate minimum loading can ensure the PSE power will be maintained, to

ensure there will be no output power interruption next time the adapter voltage goes down.

The IEEE standards require that the PI conductors be electrically isolated from ground and all other system

potentials not part of the PI interface. The adapter must meet a minimum 1500-Vac dielectric withstand test

between the output and all other connections for options 1 and 2. The adapter only needs this isolation for option

3 if it is not provided by the converter.

Adapter ORing diodes are shown for all the options to protect against a reverse-voltage adapter, a short on the

adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in

option 3.

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8 Application and Implementation

Note

以下应用部分的信息不属于 TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适

用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The TPS23755 supports power supply topologies that require a single PWM gate drive with current-mode

control. 图 8-1 provides an example of a simple diode rectified primary-side-regulated flyback converter.

8.2 Typical Application

图 8-1. Basic TPS23755 Implementation

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图 8-2. Simplified Buck Application

8.2.1 Design Requirements

Selecting a converter topology along with a design procedure is beyond the scope of this applications section.

The TPS23755 is optimized for primary-side-regulated diode rectified flyback topologies for 12 V outputs or

higher due to its good balance of high efficiency and output regulation. Typical applications use post regulation

to power the system load's lower voltage rails . The TPS23755 can also be used in non-isolated buck topology

application like shown in Figure 8-1.

Examples to help in programming the TPS23755 in a primary-side regulated flyback are shown below. For more

specific converter design examples refer to the TPS23755EVM-894 EVM: Evaluation Module for TPS23755.

表 8-1. Design Parameters

TEST CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

POWER INTERFACE

Input voltage

Applied to the PoE Input

Applied to the Secondary Input

At device terminals

37

57

V

12

Detection voltage

2.7

14.5

26.5

10.1

20.5

29.3

V

Classification voltage

Classification current

Inrush current-limit

Operating current-limit

DC-TO-DC CONVERTER

Output voltage

At device terminals

V

R_CLASS= 45.3 Ω

mA

140

550

V_IN= 48 V, I_LOAD≤ I_LOAD(max)

12

V

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表 8-1. Design Parameters (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

1

MAX UNIT

Output current

37 V ≤ V_IN≤ 57 V

A

Output ripple voltage peak-to-peak

V_IN= 48 V, I_LOAD= 1 A

V_IN= 48 V, I_LOAD= 100 mA

V_IN= 48 V, I_LOAD= 500 mA

V_IN= 48 V, I_LOAD= 1 A

50

mV

78

Efficiency, end-to-end

86

%

87

Switching frequency

250

kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Input Bridges and Schottky Diodes

Using Schottky diodes instead of PN junction diodes for the PoE input bridges reduces the power dissipation in

these devices by about 30%. There are, however, some things to consider when using them. The IEEE standard

specifies a maximum backfeed voltage of 2.8 V. A 100-kΩ resistor is placed between the unpowered pairs

and the voltage is measured across the resistor. Schottky diodes often have a higher reverse leakage current

than PN diodes, making this a harder requirement to meet. To compensate, use conservative design for diode

operating temperature, select lower-leakage devices where possible, and match leakage and temperatures by

using packaged bridges.

Schottky diode leakage currents and lower dynamic resistances can impact the detection signature. Setting

reasonable expectations for the temperature range over which the detection signature is accurate is the simplest

solution. Increasing RDEN slightly may also help meet the requirement.

Schottky diodes have proven less robust to the stresses of ESD transients than PN junction diodes. After

exposure to ESD, Schottky diodes may become shorted or leak. Care must be taken to provide adequate

protection in line with the exposure levels. This protection may be as simple as ferrite beads and capacitors.

As a general recommendation, use 0.8 A-1 A, 100-V rated discrete or bridge diodes for the input rectifiers.

8.2.2.2 Protection, D₁

A TVS, D₁, across the rectified PoE voltage per 图 8-1 must be used. A SMAJ58A, or equivalent, is

recommended for general indoor applications. Adequate capacitive filtering or a TVS must limit input transient

voltage to within the absolute maximum ratings. Outdoor transient levels or special applications require

additional protection.

8.2.2.3 Capacitor, C₁

The IEEE 802.3at standard specifies an input bypass capacitor (from VDD to VSS) of 0.05 μF to 0.12 μF.

Typically a 0.1-μF, 100-V, 10% ceramic capacitor is used.

8.2.2.4 Detection Resistor, R_DEN

The IEEE 802.3at standard specifies a detection signature resistance, R_DENbetween 23.7 kΩ and 26.3 kΩ, or 25

kΩ ± 5%. Typically a 24.9 kΩ ± 1% is used.

8.2.2.5 Classification Resistor, R_CLS

Connect a resistor from CLS to VSS to program the classification current according to the IEEE 802.3at

standard. The class power assigned should correspond to the maximum average power drawn by the PD during

operation. Select R_CLSaccording to 表 7-1. For Class 3 applications, it is recommended to unpopulate R_CLS. A

compliant PSE will allocate 13 W to either a Class 0 or a Class 3 compliant PD with no difference in PoE system

performance.

8.2.2.6 Bulk Capacitance, C_BULK

The bulk capacitance, C_BULKmust furnish input transients during heavy loads and long cable length conditions.

It also helps with stability on the DC/DC converter. It is recommended to use a minimum 10-uF, electrolytic

capacitor.

32

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8.2.2.7 Output Voltage Feedback Divider, R_AUX, R₁,R₂

R₁, R₂and R_AUXset the output voltage of the bias winding of the converter. For applications that do not use

AUX_D functionality, R_AUXshould not be populated and 方程式 5 should be used.

V_REFCR + R

(

)

1

2

V_VCC

=

R ₂

(5)

For secondary side adapter priority applications, the DC/DC output voltage can be set lower than the adapter

voltage by pulling AUX_D to RTN. 方程式 6 should be used first to determine the lower output voltage when

adapter is present.

V_REFCR + R

(

)

1

2

V_VCC

=

R ₂

(6)

when Aux_D is LOW.

Then R_auxcan be calculated using 方程式 7 to set the nominal output voltage of the bias winding.

V_REFCR R _AUX+ R₁R₂+ R ₂R_Aux

(

)

1

V_VCC

=

R ₂R _AUX

(7)

when Aux_D is HIGH.

When transitioning from the normal operating output voltage to a lower output voltage when Aux_D is pulled

LOW, switching may stop until the VCC voltage can reduce its voltage to the lower VCC voltage. The output

voltage may drop during this time due to the loss of switching. Typically this is not a concern since the adapter

is providing power to the load. A combination of adding a dummy load in parallel with C_CCand increasing the

secondary output capacitance can minimize the time that switching stops.

In applications that use smooth transition between adapter the PoE, circuitry should be added to keep the PSE

connected to the PD and the converter operational while maintaining adapter priority. It is recommended to refer

to the TPS23755EVM-894.

8.2.2.8 Setting Frequency, R_FRS

The converter switching frequency in PWM mode is set by connecting resistor, R_FRSfrom the FRS pin to RTN.

For a converter that requires a 250-kHz switching frequency and using 方程式 8

15000

250 kHz

R_FRSkW =

=

= 60 kW

(

)

f_SWkHz

(

)

(8)

A standard 60.4-kΩ resistor should be used.

8.2.2.9 Frequency Dithering, R_DTRand C_DTR

For optimum EMI performance, C_DTRand R_DTRshould be selected as described in Frequency Dithering for

Spread Spectrum Applications in 方程式 9 and 方程式 10.

3

R_FRS

W

( )

60.4 kW

2.052 ì 11000 Hz

C_DTRnF =

=

= 2.2 nF

(

)

2.052 ì f_mHz

(

)

(9)

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0.513 ì R_FRS

W

( )

0.513 ì60.4kW

R_DTRW =

( )

=

= 235 kW

%DTHR

0.132

(10)

A standard 237-kΩ resistor should be used.

8.2.2.10 Bias Voltage, C_VBand D_VB

VB requires a 0.1 μF capacitor, C_VB, to RTN. D_VB, a 6.2V Zener diode to RTN, is also required.

Note: D_VBon VB is optional in 13W applications when no class resistor is used.

8.2.2.11 Transformer design, T₁

The turns ratio and primary inductance are important parameters to consider in a flyback transformer. The

turns ratio act to limit the max duty cycle and reduce stress on the secondary components while the primary

inductance sets the current ripple. In CCM operation, the higher inductance allows for a reduced current ripple

which can help with EMI performance and noise.

For primary-side regulated flyback converters, the transformer construction is important to maintain good

regulation on the secondary output. It is recommended to use LDT0950 for 12-V applications.

8.2.2.12 Current Sense Resistor, R_CS

R_CSshould be chosen based on the peak primary current at the desired output current limit.

V_CSMAX

R _CS

=

I_{Pk-Pr imary}

(11)

8.2.2.13 Current Slope Compensation, R_S

R_Smay be used if the internally provided slope compensation is not enough. The down slope of the reflected

secondary current through the current sense resistor at each switching period is determined and a percentage

(typically 50%-75%) of it will define V_slope. If necessary, using LDT0950, it is recommended to start with 251 mV

and use 方程式 12.

»

…

ÿ

Ÿ

≈

’

V_SLOPEmV

(

)

»

…

ÿ

Ÿ

⁄

≈

’

155 mV

78.5%

V_SLOPEmV - ∆

÷

◊

(

)

251mV -

D

∆

÷

◊

∆

D_MAX

Ÿ

⁄

«

R _SW =

( )

ì 1000 =

ì 1000 = 1kW

42 mA

78.5%

I_SLmA

(

)

EX

D_MAX

(12)

8.2.2.14 Bias Supply Requirements, C_CC, D_CC

Advanced startup in the TPS23755 allows for relatively low capacitance on the bias circuit. It is recommended

to use a 1-uF, 10%, 25-V ceramic capacitors on C_CC. D_CCcan be a low cost, general-purpose diode. It is

recommended to use MMSD4148 diode (100 V, 200 mA).

8.2.2.15 Switching Transformer Considerations, R_VCCand C_CC2

R_VCChelps to reduce peak charging from the bias winding. Reduced peak charging becomes especially

important when tuning hiccup mode operation during output overload. A typical value for R_VCCin Class 3 PoE

PD applications while maintaining a suitable load regulation is 10 ohms.

8.2.2.16 Primary FET Clamping, R_CL, C_CL, and D_CL

The stored energy in the leakage inductance of the power transformer can cause ringing during the primary FET

turnoff. The snubber must be chosen to mitigate primary FET overshoot and oscillation while maintaining high

overall efficiency.

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It is recommended to use 39 kΩ (125 mW) for R_CLand 0.1 uF (100 V) for C_CL.

D_CLshould be an ultra-fast diode with a short forward recovery time allowing the snubber to turn on quickly. The

200-V / 1-A rated diode with a recovery time approximately 25 ns or better is recommended.

8.2.2.17 Converter Output Capacitance, C_OUT

The output capacitor is considered as part of the overall stability of the converter, the output voltage ripple, and

the load transient response. The output capacitor needs to be selected based on the most stringent of these

criteria. The minimum capacitance is typically determined by the output voltage ripple shown in 方程式 13.

I_OUTA ì D

( )

max

C_OUT

>

V_RippleV ì f

Hz

( )

(

)

SW

(13)

(14)

where D_maxis the calculated operating max duty cycle shown in 方程式 14.

V_OUTì N_PS

D _max

=

V_INmin + V

ì N_PS

(

)

OUT

For strict load transient requirements, the C_OUTcap may need to be increased. The TPS23755EVM-894 uses

two 22 uF ceramic capacitors for an optimized load transient response.

8.2.2.18 Secondary Output Diode Rectifier, D_OUT

The output rectifier diode must provide low forward voltage drop at the secondary peak current. Consideration

must be given to a safe operating area during output overload conditions.

For a 12 V output, PDS360-13 in a high thermal performance package (60 V reverse voltage, 3-A continuous

current max, Vf = 0.62 V max at 3 A ) is used in the TPS23755EVM-894.

8.2.2.19 Slew rate control, R_SRFand R_SRR

R_SRFand R_SRRminimize primary drain-source oscillations and help optimize EMI performance at high

frequencies, the value chosen should be within the recommend operating conditions table in Recommended

Operating Conditions. It is recommended to start with 10 ohms for R_SRFand 10 ohms for R_SRRthen adjust

accordingly during bench and EMI testing.

8.2.2.20 Shutdown at Low Temperatures, D_VDDand C_VDD

For applications operating near –10°C or less, there may be some extra switching cycles during removal of the

PoE input or during shutdown. It is acceptable for most applications; however, for a more monotonic shutdown

of the output voltage during power removal, it is recommended to use D_VDDand C_VDDas shown in 图 8-3. D_VDD

can be MMSD4148 and C_VDDcan be 0.22-uF, 100-V capacitor.

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D_VDD

C_VDD

+

C_BULK

VDD

VPD

C1

D1

TPS23755

VSS

图 8-3. DVDD and CVDD Configuration for Low Temperature Conditions

8.2.3 Application Curves

VDD-VSS

RTN-VSS

IIN

图 8-4. TPS23755 Startup to TPS23861 PSE

图 8-5. TPS23755 PSR Flyback Startup to Full Load

图 8-6. TPS23755 Output Short and Recovery

图 8-7. Slew Rate Adjust SRR = 15 Ω

图 8-8. Slew Rate Adjust SRR = 0 Ω

图 8-9. Slew Rate Adjust SRF = 0 Ω

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12.4

12.3

12.2

12.1

12

IL = 100 mA

IL = 1A

11.9

11.8

11.7

-40

-20

0

20

40

60

80

100

Temperature (èC)

D027

图 8-11. Slew Rate Adjust SRF = 100 Ω

图 8-10. Output Regulation vs. Ambient

Temperature

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9 Power Supply Recommendations

The TPS23755 converter should be designed such that the input voltage of the converter is capable of operating

within the IEEE802.3at recommended input voltage as shown in 图 7-5 and the minimum operating voltage of

the adapter if applicable.

10 Layout

10.1 Layout Guidelines

The TPS23755 IC’s layout footprint shown in the Example Board Layout should be strictly followed. The below

list are key highlights for layout consideration around the TPS23755.

•

Pin 22 of the TPS23755 is omitted from the IC to ensure high voltage clearance from Pin 24 (DRAIN).

Therefore, the Pin 22 footprint should be removed when laying out the TPS23755.

It is recommended having at least 8 vias (VSS) connecting the exposed thermal pad through a top layer

plane (2 oz copper recommended) to a bottom VSS plane (2 oz. copper recommended) to help with thermal

dissipation.

•

The Pin24 of the TPS23755 should be near the power transformer and the current sense resistor should be

close to Pin 1 of the TPS23755 to minimize the primary loop.

The layout of the PoE front end should follow power and EMI or ESD best-practice guidelines. A basic set of

recommendations includes:

•

Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode

bridges, TVS and 0.1-μF capacitor, and TPS23755 converter input bulk capacitor.

Make all leads as short as possible with wide power traces and paired signal and return.

No crossovers of signals from one part of the flow to another are allowed.

Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage

rails and between the input and an isolated converter output.

•

Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay copper

fills in the power path.

The DC-to-DC converter layout benefits from basic rules such as:

•

Having at least 4 vias (VDD) near the power transformer pin connected to VDD through multiple layer planes

to help with thermal dissipation of the power transformer.

Having at least 6 vias (secondary ground) near the power transformer pin connected to secondary ground

through multiple layer planes to help with thermal dissipation of the power transformer.

Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses, which include

the power semiconductors and magnetics.

•

Minimize the trace length of high current power semiconductors and magnetic components.

Where possible, use vertical pairing.

Use the ground plane for the switching currents carefully.

Keep the high-current and high-voltage switching away from low-level sensing circuits including those outside

the power supply.

•

Maintain proper spacing around the high-voltage sections of the converter.

10.2 Layout Example

图 10-1 and 图 10-2 show the top and bottom layer and assemblies of the TPS23755EVM-894 as a reference for

optimum parts placement.

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图 10-1. Top Side and Routing

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图 10-2. Bottom Side Placement and Routing

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11 Device and Documentation Support

11.1 Related documentation

For related documentation, see the following:

•

Texas Instruments, Practical Guidelines to Designing an EMI-Compliant PoE Powered Device With Isolated

Flyback, application report

Texas Instruments, TPS23755EVM-894: Evaluation Module, user's guide

11.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI

的《使用条款》。

11.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.4 静电放电警告

静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

RJJ0023B

VSON - 1 mm max height

S

C

A

L

E

2

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

6.1

5.9

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

4X (0.4)

4X ( 0.25)

1.9 0.1

(0.2) TYP

20X 0.4

A2

A3

13

4X (0.45)

12

EXPOSED

THERMAL PAD

5.5 0.1

2X

SYMM

25

4.4

0.25

0.15

23X

0.1

C B A

24

A4

1

0.05

A1

PIN 1 ID

10X (0.2)

SYMM

0.5

0.3

23X

8X (0.4)

2X (1.6)

4223621/B 06/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RJJ0023B

VSON - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2)

(1.9)

10X (0.2)

SYMM

4X ( 0.25)

23X (0.6)

A1

A4

23X (0.2)

1

24

4X (2.675)

(

0.2) TYP

VIA

20X (0.4)

25

SYMM

(5.5)

(1.32)

TYP

SOLDER MASK

OPENING

(R0.05) TYP

ALL PAD CORNERS

13

12

METAL UNDER

SOLDER MASK

A2

A3

(0.45) TYP

8X

(0.4)

4X (1.725)

(0.6)

TYP

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4223621/B 06/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RJJ0023B

VSON - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

8X (0.85)

4X ( 0.25)

23X (0.6)

A1

A4

1

24

23X (0.2)

8X (1.12)

4X (2.675)

20X (0.4)

SOLDER MASK

OPENING

25

SYMM

(5.94)

(0.66) TYP

(R0.05) TYP

(1.32) TYP

METAL UNDER

SOLDER MASK

12

13

A3

A2

10X (0.46)

(0.525) TYP

4X (1.725)

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

THERMAL PAD 25: 73%

SCALE:20X

4223621B 06/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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PACKAGE MATERIALS INFORMATION

www.ti.com

7-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS23755RJJR

TPS23755RJJT

VSON

RJJ

23

3000

250

330.0

180.0

12.4

4.25

6.25

1.15

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Jan-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS23755RJJR

TPS23755RJJT

VSON

RJJ

23

3000

250

367.0

213.0

367.0

191.0

38.0

35.0

Pack Materials-Page 2

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型号：	TPS23755RJJT
厂家：	TEXAS INSTRUMENTS
描述：	具有非光电反激式直流/直流控制器的 IEEE 802.3at PoE PD \| RJJ \| 23 \| -40 to 125 控制器光电二极管
文件：	总49页 (文件大小：5468K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS23755RJJT [TI]

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