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TPS23861

ZHCSCE7I –MARCH 2014–REVISED JULY 2019

TPS23861 IEEE 802.3at 四端口以太网供电 PSE 控制器

1 特性

3 说明

1

•

IEEE 802.3at 四端口 PSE 控制器

TPS23861 是一款易于使用的灵活 IEEE802.3at PSE

解决方案。该器件在出厂后，无需借助任何外部控制即

可自动管理四个 802.3at 端口。

–

自动检测，分类

自动开启和断开

255mΩ 高效感应电阻器

TPS23861 自动检测具有有效签名的供电器件 (PD)，

根据分类确定供电需求，并施加电源。支持针对类型 2

PD 的两事件分类。TPS23861 支持直流断开和外部场

效应晶体管 (FET) 架构，从而使得设计人员能够在尺

寸、效率和解决方案成本需要之间作出平衡。

•

引脚支持双层 PCB

开尔文电流感应

4 点检测

自动模式（出厂自带）

–

无需设置外部终端

无需进行初始 I²C 通信

独特的引脚分配可通过逻辑分组和 I²C 以及电源引脚的

上下清晰区分来实现 2 层 PCB 设计。这提供了同类产

品中最佳的热性能、Kelvin 精度和低构建成本。

•

半自动模式（由 I²C 命令

–

连续识别和分类

满足 IEEE 400ms T_PON规范

快速端口关断输入

除了自动运行模式外，TPS23861 还可通过 I²C 控制

实现半自动模式，从而实现精确监视和智能电源管理。

无论是在半自动模式还是自动模式下，都能够保证

400ms T_PON规范值。

结合系统参考代码一起使用时的性能最佳http:/

/www.ti.com.cn/product/cn/TPS23861/toolssoft

ware

器件信息⁽¹⁾

•

可选 I²C 控制和监控

器件型号

TPS23861

封装

封装尺寸

温度范围：–40°C 至 125°C

9.8mm x 6.6mm TSSOP 28 封装

TSSOP (28)

9.80mm x 6.60mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用范围

•

以太网交换机和路由器

监控 NVR 和 DVR

住宅网关

PoE 直通系统

无线回程

TOP CONDUCTORS

简化原理图

FETs Uniformly Spread Over Surface

3.3 V

48 V

100 nF

100 V

PORTn

VDD VPWR

47 ꢀ

RESET

DRAINn

SHTDWN

GATEn

22 ꢀ

SENn

TPS23861

BOTTOM GND PLANE

255 mꢀ

Continuous, Robust Backside GND Plane

A3

KSENSx

INT

SCL

SDAI

AIN

SDAO

AOUT

AGND DGND

Note: only port n shown

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSBX9

TPS23861

ZHCSCE7I –MARCH 2014–REVISED JULY 2019

www.ti.com.cn

1

2

3

4

5

6

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 5

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 7

6.6 Timing Requirements.............................................. 11

6.7 Switching Characteristics........................................ 12

6.8 Typical Characteristics............................................ 16

Detailed Description ............................................ 21

7.1 Overview ................................................................. 21

7.2 Functional Block Diagram ....................................... 25

7.3 Feature Description................................................. 25

7.4 Device Functional Modes........................................ 40

7.5 Register Map – I²C-Addressable ............................ 45

8

9

Application and Implementation ........................ 85

8.1 Introduction to PoE ................................................. 85

8.2 Application Information............................................ 85

8.3 Typical Application .................................................. 87

8.4 System Examples ................................................... 93

Power Supply Recommendations...................... 97

9.1 VDD......................................................................... 97

9.2 VPWR ..................................................................... 97

9.3 VPWR-RESET Sequencing .................................... 97

10 Layout................................................................... 98

10.1 Layout Guidelines ................................................. 98

10.2 Layout Example .................................................... 99

11 器件和文档支持 ................................................... 100

11.1 文档支持 ............................................................. 100

11.2 接收文档更新通知 ............................................... 100

11.3 社区资源.............................................................. 100

11.4 商标..................................................................... 100

11.5 静电放电警告....................................................... 100

11.6 Glossary.............................................................. 100

12 机械、封装和可订购信息..................................... 100

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision H (November 2017) to Revision I

Page

•

Added figure titles to the Application Curves........................................................................................................................ 92

Changes from Revision G (October 2016) to Revision H

Page

•

Deleted "or unknown" from Auto subsection ........................................................................................................................ 42

Deleted "and Auto Modes" from TSTART Indicators of Detect and Class Failures subsection........................................... 44

Changed fault conditions for Auto mode in Detect and Class Failure Indicators table ........................................................ 44

Added information to Step 2 in Start/ILIM Event Register subsection ................................................................................. 53

Changes from Revision F (July 2016) to Revision G

Page

•

Deleted the MAX value of 150 mA from I_GO-in the Electrical Characteristics ........................................................................ 8

Changes from Revision E (March 2016) to Revision F

Page

•

Legacy Device Detection, Changed the paragraph, "in general,..." ..................................................................................... 30

Changed section From: Independent Operation when the Bit is Set To: Independent Operation when the AUTO Bit

is Set..................................................................................................................................................................................... 34

•

I²C Slave Address and AUTO Bit Programming, Added NOTE: "When using I²C scan...".................................................. 37

Start/ILIM Event Register, Changed the third list item From: "Detect fault or classification unknown,.." To:

"Overcurrent or class mismatch on second finger in Semi-Auto or Manual Mode." ........................................................... 53

•

Timing Configuration Register, Added new NOTE under TLIM[1:0]: " If ILIM and ICUT are set to same value..." ............ 61

Timing Configuration Register, Added new NOTE under TICUT[1:0]: " If ILIM and ICUT are set to same value...".......... 62

Two-Event Classification Register, Changed the second list item to include: "CLEn is set or a" ....................................... 67

2

TPS23861

www.ti.com.cn

ZHCSCE7I –MARCH 2014–REVISED JULY 2019

•

Replaced Figure 58 .............................................................................................................................................................. 95

Changes from Revision D (September 2015) to Revision E

Page

•

已添加设置）在特性“半自动模式”中添加了说明 .................................................................................................................... 1

Updated Pin Functions table .................................................................................................................................................. 5

Added new Figure 37 .......................................................................................................................................................... 22

Added new Functional Block Diagram.................................................................................................................................. 25

Changed note in A/D Converter and I²C Interface .............................................................................................................. 32

Changed the Note in I²C Slave Address and AUTO Bit Programming ................................................................................ 35

Added note to I²C Slave Address and AUTO Bit Programming .......................................................................................... 35

Changed I²C slave address register note............................................................................................................................. 35

Added new Figure 43 ........................................................................................................................................................... 39

Added a note to Manual about type 2 power 2 event classification..................................................................................... 40

Added content to Semi-Auto................................................................................................................................................. 41

Added "PoEPn" column to Bits Description.......................................................................................................................... 70

Added a note to PoE Plus Register ..................................................................................................................................... 77

Changes from Revision C (June 2015) to Revision D

Page

•

Added reference note to Figure 5 and Figure 6 ................................................................................................................... 15

Changed RESET note to add addition reference link. ........................................................................................................ 23

Added SDAO pin note. ........................................................................................................................................................ 24

Changed I²C Slave Address and AUTO Bit Programming note. ......................................................................................... 35

Added Figure 42, I²C/SMBus Interface Slave Address Programming Protocol. ................................................................. 38

Added note 3 to Table 10..................................................................................................................................................... 45

Changed Connections on Unused Ports section.................................................................................................................. 86

Added reference link to the VPWR-RESET Sequencing note. ............................................................................................ 97

Changes from Revision B (April 2015) to Revision C

Page

•

Added Figure 5 and Figure 6................................................................................................................................................ 15

Changed Figure 36, Disconnected AIN pin from GND......................................................................................................... 22

Added SHTDWN note. ......................................................................................................................................................... 23

Added RESET note. ............................................................................................................................................................ 23

Added Device Power On Initialization section...................................................................................................................... 44

Added note 2 to Table 10..................................................................................................................................................... 45

Added Port n Status Register note....................................................................................................................................... 55

Added Operating Mode Register Command note. .............................................................................................................. 58

Added Operating Mode Register Bit Description note. ........................................................................................................ 58

Added Detect/Class Enable Register Command note. ....................................................................................................... 59

Added Detect/Class Restart Register Command note. ........................................................................................................ 64

Added Power Enable Register Command note.................................................................................................................... 65

Added Power Enable Register Bit Descriptions note. .......................................................................................................... 65

Added Reset Register Command note................................................................................................................................. 66

Added Reset Register Bit Descriptions note. ...................................................................................................................... 66

Changed Figure 46, Disconnected AIN pin from GND......................................................................................................... 85

Changed Figure 48, Disconnected AIN pin from GND......................................................................................................... 87

3

TPS23861

ZHCSCE7I –MARCH 2014–REVISED JULY 2019

www.ti.com.cn

•

Changed Figure 49, Disconnected AIN pin from GND......................................................................................................... 88

Changed Figure 50, Disconnected AIN pin from GND......................................................................................................... 89

Changed Q_Pndescription in Per Port Components ............................................................................................................. 90

Changed maximum VDD supply current from 10 mA to 6 mA in first paragraph and changed wording in second

paragraph of VDD................................................................................................................................................................. 97

•

Added VPWR-RESET Sequencing ...................................................................................................................................... 97

Changes from Revision A (June, 2014) to Revision B

Page

•

Changed VDD current consumption from 10 mA (MAX) to 6.0 mA (MAX)............................................................................ 7

Deleted Processor watchdog trip delay specification. .......................................................................................................... 11

Added When using the I²C interface note. .......................................................................................................................... 32

Added When using the I²C interface note. .......................................................................................................................... 35

Changed FULL SCALE VALUE from 146.2°C to 150°C (typical). ....................................................................................... 71

Changed LSB VALUE from 0.652°C to 7°C......................................................................................................................... 71

Added Temperature sensor performance note..................................................................................................................... 71

Changes from Original (March 2014) to Revision A

Page

•

已添加完整版 TPS23861 IEEE 802.3at 四端口以太网供电 PSE 控制器数据表。 ................................................................ 1

4

TPS23861

www.ti.com.cn

ZHCSCE7I –MARCH 2014–REVISED JULY 2019

5 Pin Configuration and Functions

PW Package

28-Pin TSSOP

Top View

VDD

1

2

28

VPWR

N/C

RESET

27

SCL

SDAI

SDAO

INT

3

4

5

6

26

25

24

23

AOUT

AIN

SHTDWN

A3

DGND

SEN3

7

8

22

21

AGND

GATE2

DRAIN3

GATE3

KSENSB

SEN4

9

20

19

18

17

DRAIN2

SEN2

10

11

12

KSENSA

GATE1

DRAIN4

GATE4

13

14

16

15

DRAIN1

SEN1

Pin Functions

I/O

DESCRIPTION

NAME

A3

NO.

23

22

25

26

7

I

P

I

I²C A3 address line. Internally pulled up to VDD.

Analog ground.

I²C address programming input line; this pin is internally pulled up to VDD.

I²C address programming line; this output is open drain.

Digital ground.

AGND

AIN

AOUT

DGND

DRAIN3

DRAIN4

DRAIN1

DRAIN2

GATE3

GATE4

GATE1

GATE2

O

P

I

9

13

16

20

10

14

17

21

I

Port 1-4 output voltage monitor; connect to output port through a 47-Ω resistor.

I

O

Port 1-4 gate-drive output.

Interrupt; this pin asserts low when a bit in the interrupt register is asserted. This pin is

updated between I²C transactions. This output is open drain.

INT

6

O

KSENSA

KSENSB

N/C

18

11

27

2

I

Kelvin point connection for SEN1 and SEN2.

Kelvin point connection for SEN3 and SEN4.

x

I

Used to effect regulatory voltage-spacing compliance. Leave this pin open.

Reset; when asserted low, the device resets. This pin is internally pulled up to VDD.

Serial clock input for I²C bus.

RESET

SCL

3

I

SDAI

4

I

Serial data input for I²C bus; this pin can be connected to SDAO for non-isolated systems.

Serial data output for I²C bus; this pin can be connected to SDAI for non-isolated systems.

This output is open drain.

SDAO

5

O

SEN3

SEN4

SEN1

SEN2

SHTDWN

VDD

8

I

12

15

19

24

1

Port 1-4 current-sense input; connect to current-sense resistor through a 22-Ω resistor.

I

Low-priority ports shutdown.

P

Digital 3.3-V supply. Bypass VDD to DGND using a 0.1-μF capacitor.

Analog 48-V supply. Bypass VPWR to AGND using a 0.1-μF capacitor.

VPWR

28

5

TPS23861

ZHCSCE7I –MARCH 2014–REVISED JULY 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature, voltages are referenced to DGND and AGND tied together (unless otherwise noted)

(1)

MIN

–0.3

0

MAX

70

4

UNIT

Input voltage

Voltage

VPWR

V

VDD

V

AGND

0.3

4

V

Voltage

SDAI, SDAO⁽²⁾, SCL, AIN, AOUT, SHTDWN, RESET, INT, A3⁽²⁾

V

(3)(4)

Output voltage

Input voltage

Voltage

GATE1-4

13

3

V

SEN1-4⁽⁵⁾, KSENSA, KSENSB

DRAIN1-4⁽²⁾⁽⁶⁾

V

70

20

260

150

V

Voltage

N/C pin

V

Sinking current

INT, SDAO

mA

°C

Lead temperature 1.6 mm (1/16-inch) from case for 10 seconds

Storage temperature range, T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Do not apply external voltage sources directly.

(3) Application of voltage is not implied – these are internally driven pins.

(4) If there is a short between drain and gate, the GATE pin may internally permanently disconnect to prevent cascade damage. The three

other ports will continue to operate.

(5) SEN1-4 will be tolerant to 15-V transients to avoid fault propagation when a MOSFET fails in short-circuit.

(6) Short transients (µs range) up to 80 V are allowed.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature, voltages are referenced to DGND (unless otherwise noted)

MIN

3.0

44

NOM

3.3

MAX

3.6

57

UNIT

V

V_VDD

V_VPWR

48

V

Voltage slew rate on DRAIN1-4

Operating junction temperature

Operating free-air temperature

1

V/µs

°C

T_J

-40

125

85

T_A

°C

6.4 Thermal Information

TPS23861

THERMAL METRIC⁽¹⁾

PW (TSSOP)

28 PINS

70.9

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

16.2

28.2

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.6

ψ_JB

27.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6

TPS23861

www.ti.com.cn

ZHCSCE7I –MARCH 2014–REVISED JULY 2019

6.5 Electrical Characteristics

–40 ≤ T_J≤ +125°C, V_VDD= 3.3 V, V_VPWR= 48 V, V_DGND= V_AGND, DGND, KSENSA and KSENSB connected to AGND, and all

outputs are unloaded, PoEPn = 0, Positive currents are into pins, R_S= 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB

(SEN3 or SEN4), R_SENS= 22 Ω, R_DRAIN= 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating

registers loaded with default values (unless otherwise noted)

PARAMETER

INPUT SUPPLY VPWR

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_VPWR

VPWR current consumption

VPWR UVLO falling threshold

V_VPWR= 57 V

3.5

7

mA

V

V_{UVLOPW_F}

Internal oscillator stops operating

14.5

25

17.5

VPWR Undervoltage falling

threshold

V_{PUV_F}

V_PUVfor port de-assertion

26.5

28

V

V_{UVLOPW_R}

VPWR UVLO rising threshold

15.5

18.5

INPUT SUPPLY VDD

I_VDD

VDD current consumption

5

2.2

2.6

0.4

6

2.4

2.8

mA

V

V_{UVDD_F}

V_{UVDD_R}

V_{UVDD_HYS}

DETECTION

VDD UVLO falling threshold

VDD UVLO rising threshold

Hysteresis VDD UVLO⁽¹⁾

For port turn off

2

2.4

V

First detection point,

V_VPWR– V_DRAINn= 0 V

145

235

490

160

270

540

190

300

585

µA

2nd detection point,

V_VPWR– V_DRAINn= 0 V

I_DET

Detection current

High Current detection point,

V_VPWR– V_DRAINn= 0 V

ΔI_DET

2nd – 1st detection currents

Open circuit detection voltage

Rejected resistance low range

Rejected resistance high range

Accepted resistance range

Shorted port threshold

At V_VPWR– V_DRAINn= 0 V

V_VPWR– V_DRAINn

98

17.5

0.85

33

110

19

118

22

µA

V

V_detect

R_{REJ_LOW}

R_{REJ_HI}

R_ACCEPT

R_SHORT

R_OPEN

15

kΩ

Ω

50

19

25

26.5

350

Open port threshold

55

kΩ

CLASSIFICATION

V_VPWR– V_DRAINn, V_SENn≥ 0 mV ,

V_CLASS

Classification voltage

15.5

18.5

70

20.5

V

I_port≥ 180 µA,

I_{CLASS_Lim}

Classification current limit

V_VPWR– V_DRAINn= 0 V

Class 0-1

90

8

mA

5

13

21

31

45

Class 1-2

16

25

35

51

I_{CLASS_TH}

Classification threshold current

Class 2-3

Class 3-4

Class 4- overcurrent

4 mA ≥ I_port≥ 180 µA, V_VPWR

V_DRAINn

–

V_MARK

Mark voltage

7

10

90

V

I_{MARK_Lim}

Mark sinking current Limit

V_VPWR– V_DRAINn= 0 V

10

70

mA

(1) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product

warranty.

7

TPS23861

ZHCSCE7I –MARCH 2014–REVISED JULY 2019

www.ti.com.cn

Electrical Characteristics (continued)

–40 ≤ T_J≤ +125°C, V_VDD= 3.3 V, V_VPWR= 48 V, V_DGND= V_AGND, DGND, KSENSA and KSENSB connected to AGND, and all

outputs are unloaded, PoEPn = 0, Positive currents are into pins, R_S= 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB

(SEN3 or SEN4), R_SENS= 22 Ω, R_DRAIN= 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating

registers loaded with default values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GATE

V_GOH

Gate drive voltage

V_GATEn, I_GATE= –1 μA

V_GATEn= 5 V

10

80

12.5

V

Gate sinking current with power-on

reset, shutdown detected or port

turn off command

I_GO-

100

mA

Gate sinking current with port short- V_GATEn= 5 V, V_SENn≥ V_SHORT(or

circuit

I_{GO short–}

I_GO+

80

150

mA

V_SHORT2Xif 2x mode)

V_GATEn= 0 V, IGATE = 0

IGATE = 1

39

18

50

25

63

34

µA

Gate sourcing current

DRAIN INPUT

V_PGT

Power good threshold

Shorted FET threshold

Measured at V_DRAINn

1.0

4

2.13

6

3

8

V

V_SHT

Measured at V_DRAINn

Any operating mode except during

R_DRAIN

Resistance from DRAINn to VPWR detection or while the port is ON,

including in device reset state

80

100

190

kΩ

V_DRAINn= 48 V, port OFF (not in

detection)

1

µA

I_DRAIN

DRAINn pin bias current

V_VPWR- V_DRAINn= 30 V, port ON

75

100

A/D CONVERTER

T_CONVConversion time , A/D #1 to 4

All ranges, each port current

0.65

80

0.8

320

100

1

ms

Hz

ms

ADC integration bandwidth (–3

dB)⁽¹⁾

(1)

A_DCBW

T_{INT_CUR}

T_{INT_DET}

Integration (averaging) time, current Each port, port ON current

125

20

Integration (averaging) time,

MAINS bit = 0

detection⁽¹⁾

At V_VPWR– V_DRAINn= 57 V, 0°C to

125°C

15175

11713

15020

11594

15565

12015

15565

12015

15955

12316

16110

12436

Counts

At V_VPWR– V_DRAINn= 44 V, 0°C to

125°C

Powered port voltage conversion

scale factor and accuracy

At V_VPWR– V_DRAINn= 57 V, –40°C

to 125°C

At V_VPWR– V_DRAINn= 44 V, –40°C

to 125°C

At port current = 770 mA

At port current = 7.5 mA

At V_VPWR= 57 V

12300

90

12616

123

12932

156

Counts

Powered port current conversion

scale factor and accuracy

15175

11713

15565

12015

15955

12316

Input voltage conversion scale

factor and accuracy

At V_VPWR= 44 V

Powered port voltage conversion

offset

V_OS

At V_VPWR– V_DRAINn= 0.3 V

0

600

mV

At 44 V to 57 V –40°C to 125°C

At 44 V to 57 V 0°C to 125°C

At 50 mA to 770 mA

–3.5%

–2.5%

3.5%

2.5%

δ_V/V_PORT

δ_I/I_port

Voltage reading accuracy

Current reading accuracy

8

TPS23861

www.ti.com.cn

ZHCSCE7I –MARCH 2014–REVISED JULY 2019

Electrical Characteristics (continued)

–40 ≤ T_J≤ +125°C, V_VDD= 3.3 V, V_VPWR= 48 V, V_DGND= V_AGND, DGND, KSENSA and KSENSB connected to AGND, and all

outputs are unloaded, PoEPn = 0, Positive currents are into pins, R_S= 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB

(SEN3 or SEN4), R_SENS= 22 Ω, R_DRAIN= 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating

registers loaded with default values (unless otherwise noted)

PARAMETER

PORT CURRENT SENSE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_DRAINn= 0 V, I_CUTport n[2:0] =

000, default

90.60

26.65

95.37

28.05

52.02

164.5

234.6

100.14

29.45

mV

V_DRAINn= 0 V, I_CUTport n[2:0] =

001

V_DRAINn= 0 V, I_CUTport n[2:0] =

010

V_CUT

I_CUTlimit

49.42

54.62

V_DRAINn= 0 V, I_CUTport n[2:0] =

110

156.27

172.72

V_DRAINn= 0 V, I_CUTport n[2:0] =

111

222.87

–5%

10

246.33

5%

δ_ICUT/I_CUT

I_CUTtolerance

At port turn on,

V_VPWR– V_DRAINn= 1 V

23

33

31

mV

V_VPWR- V_DRAINn= 10 V

V_VPWR- V_DRAINn= 30 V

V_VPWR– V_DRAINn= 55 V

V_DRAINn= 1 V

20

102

15

46

114.7

31

mV

V_INRUSH

I_Inrushlimit

V_DRAINn= 13 V

V_LIM

ILIM limit with PoEPn = 0

V_DRAINn= 30 V

23

V_DRAINn= 48 V

15

31

V_DRAINn= 1 V

260

127

15

270.3

140

23

285

V_DRAINn= 10 V

153

V_LIM2X

ILIM limit with PoEPn = 1

V_DRAINn= 30 V

31

V_DRAINn= 48 V

15

23

31

Threshold for GATE to be less than

1 V,

V_SHORT

I_SHORTthreshold with PoEPn = 0

140

183

mV

2 μs after application of pulse

V_SHORT2X

I_BIAS

I_SHORTthreshold with PoEPn = 1

Sense pin bias current

357

-2.25

1.275

2.55

5.1

408

0

mV

µA

Port ON or during class

DCTHn = 00, default

DCTHn = 01

2.55

5.1

10.2

17

mV

V_I(min)

Disconnect threshold

DCTHn = 10

DCTHn = 11

8.5

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Electrical Characteristics (continued)

–40 ≤ T_J≤ +125°C, V_VDD= 3.3 V, V_VPWR= 48 V, V_DGND= V_AGND, DGND, KSENSA and KSENSB connected to AGND, and all

outputs are unloaded, PoEPn = 0, Positive currents are into pins, R_S= 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB

(SEN3 or SEN4), R_SENS= 22 Ω, R_DRAIN= 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating

registers loaded with default values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INTERFACE AT V_VDD= 3.3 V

V_IH

V_IL

Digital input high

Digital input low

2.1

V

0.9

Input voltage hysteresis (SCL,

SDAI, AIN, A3, RESET, SHTDWN)

V_{IT_HYS}

V_OL

0.17

30

V

Digital output Low, SDAO

Digital output Low, INT

Pullup resistor to VDD

I_OL= 9 mA

0.4

80

V

I_OL= 3 mA

R_pullup

RESET, AIN, A3, SHTDWN

50

10

kΩ

AOUT OUTPUT

During slave address programming,

I_AOUT= 1 mA

V_{OL_AOUT}

AOUT output low voltage

0.7

V

EEPROM (I²C Slave Address)

n_{EE_cyc}

t_WC

EEPROM endurance

40 V < V_VPWR< 57 V

25

cycles

ms

Write cycle time (byte or page)

100

161

THERMAL SHUTDOWN

T_SDThermal shutdown temperature

Hysteresis⁽¹⁾

Temperature rising

143

154

8

°C

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6.6 Timing Requirements

–40 ≤ T_J≤ +125°C, V_VDD= 3.3 V, V_VPWR= 48 V, V_DGND= V_AGND, DGND, KSENSA and KSENSB connected to AGND, and all

outputs are unloaded, PoEPn = 0, Positive currents are into pins, R_S= 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB

(SEN3 or SEN4), R_SENS= 22 Ω, R_DRAIN= 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating

registers loaded with default values (unless otherwise noted)

MIN

10

TYP

MAX

UNIT

kHz

µs

f_SCL

SCL clock frequency

400

t_LOW

t_HIGH

LOW period of SCL clock

HIGH period of SCL clock

1.3

0.6

µs

SDAO output fall time, SDAO, 2.3 → 0.8 V, C_b= 10 pF, 10-kΩ pullup

to 3.3 V

21

60

250

ns

t_fo

SDAO output fall time, SDAO, 2.3 → 0.8 V, C_b= 400 pF, 1.3-kΩ

pullup to 3.3 V

C_I2C

SCL capacitance

10

6

pF

ns

C_{I2C_SDA}

t_SU,DATW

SDAI, SDAO capacitance

Data set-up time (write operation)

100

600

Data set-up time (read operation), SDAO, 2.3 ↔ 0.8 V, C_b= 400 pF,

1.3-kΩ pull up to 3.3 V

t_SU,DATR

ns

t_HD,DATW

t_HD,DATR

t_fSDA

Data hold time (write operation)

0

150

20

ns

µs

Data hold time (read operation)

600

250

300

200

Input fall times of SDAI, 2.3 → 0.8 V

Input rise times of SDAI, 0.8 → 2.3 V

Input rise time of SCL, 0.8 → 2.3 V

Input fall time of SCL, 2.3 → 0.8 V

Bus free time between a stop and start condition

Hold time after (repeated) start condition

Repeated start condition set-up time

Stop condition set-up time

t_rSDA

20

t_r

20

t_f

20

t_BUF

1.3

0.6

t_HD,STA

t_SU,STA

t_SU,STO

Fault to INT assertion, Time to internally register an interrupt in

response to a fault

(1)

t_{FLT_INT}

150

2.2

µs

t_{ARA_INT}

t_DG

ARA to INT negation

500

ns

µs

s

Suppressed spike pulse width, SDAI and SCL

RESET input minimum pulse width (deglitch time)

I²C Watchdog trip delay

50

t_RDG

5

3.3

t_{WDT_I2C}

t_{STP_AOUT}

1.1

Delay STOP bit to A_OUThigh during I²C address programming

1.25

µs

(1) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product

warranty.

t_rSDA

SDAI/

SDAO

t_fSDA

t_fo

t_BUF

t_SU,DAT

t_f

t_r

t_LOW

SCL

t_HIGH

t_SU,STO

t_HD,DAT

t_SU,STA

t_HD,STA

Stop Condition

Start Condition

Repeated

Start Condition

Figure 1. I²C Timings

11

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6.7 Switching Characteristics

–40 ≤ T_J≤ +125°C, V_VDD= 3.3 V, V_VPWR= 48 V, V_DGND= V_AGND, DGND, KSENSA and KSENSB connected to AGND, and all

outputs are unloaded, PoEPn = 0, Positive currents are into pins, R_S= 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB

(SEN3 or SEN4), R_SENS= 22 Ω, R_DRAIN= 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating

registers loaded with default values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Duty cycle of I_PORTwith current

fault

δIfault

5.5%

6.7%

TICUT = 00, default as supplied

TICUT = 01

50

25

70

35

ms

t_OVLD

I_CUTtime limit

ILIM time limit

TICUT = 10

100

200

50

140

280

70

TICUT = 11

POEPn = 0, default as supplied

POEPn = 1, TLIM = 00

POEPn = 1, TLIM = 01

POEPn = 1, TLIM = 10

POEPn = 1, TLIM = 11

TSTART = 00, default as supplied

TSTART = 01

50

70

t_LIM

28.4

14.7

9.025

50

30

34

15.5

17

11.5

70

Maximum current limit duration in

port start-up

t_START

25

35

TSTART = 10

100

275

300

0

140

500

150

t_DET

Four-point detection duration

Time to complete a detection

V_VPWR– V_DRAINn> 2.5 V

V_VPWR– V_DRAINn< 2.5 V

400

Pause between detection

attempts

t_{DET_BOFF}

1st and 2nd class event, Auto Mode,

Semi-Auto Mode, from detection

complete

t_CLE

Classification duration

6.5

13

ms

1-event physical layer class timing, Auto

Mode and Semi-Auto Mode, from

detection complete

t_pdc

Classification duration

Manual mode, from beginning of

classification

6.5

6

14

12

4

ms

1st and 2nd mark event, from class 4

complete

t_ME

Mark duration

Manual mode, from port turn-on

command to port turn on completed

t_p(on)

Port power-on delay

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Switching Characteristics (continued)

–40 ≤ T_J≤ +125°C, V_VDD= 3.3 V, V_VPWR= 48 V, V_DGND= V_AGND, DGND, KSENSA and KSENSB connected to AGND, and all

outputs are unloaded, PoEPn = 0, Positive currents are into pins, R_S= 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB

(SEN3 or SEN4), R_SENS= 22 Ω, R_DRAIN= 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating

registers loaded with default values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ICUT , ILIM or start fault, Auto Mode,

Semi-Auto Mode,

0.8

1

1.2

s

CLDN = 0X, default as supplied

Fault delay timing. Delay before

next attempt to power a port

following power removal due to

fault condition

ICUT , ILIM or start fault, Auto Mode,

Semi-Auto Mode,

CLDN = 10

t_ed

1.6

3.2

2

4

2.4

4.8

s

ICUT , ILIM or start fault, Auto Mode,

Semi-Auto Mode,

CLDN = 11

TDIS = 00, default as supplied

TDIS = 01

300

75

400

100

200

800

ms

PD maintain power signature

dropout time limit

t_MPDO

TDIS = 10

150

600

TDIS = 11

t_{D_off_SHDW}Gate turn-off time from SHTDWN From SHTDWN to V_GATEn< 1 V, V_SENn

=

1

5

900

5

µs

input

0 V

N

Gate turn-off time from port off

command

From port off command to V_GATEn< 1 V,

V_SENn= 0 V

t_{P_off_CMD}

Gate turn-off time with RESET

From RESET low to, V_GATEn< 1 V, V_SENn

= 0 V

t_{P_off_RST}

POEPn = 0,

V_DRAINn= 1 V , from V_SENnpulsed to

0.425 V

0.9

µs

Gate turn-off time from SENn

input

t_{D_off_SEN}

POEPn = 1,

V_DRAINn= 1 V , from V_SENnpulsed to 0.62

V

t_POR

Device power-on-reset delay

23

5

ms

µs

Reset time duration from RESET

t_RESET

1

V_LIM

V_CUT

SEN

0V

GATE

0V

t_OVLD

Figure 2. Overcurrent Fault Timing

13

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Port Turn-On

Class

V_CLASS

Four-Point Detection

V_PORT

0 V

t_pdc

t_DET

Figure 3. Detection, 1-Event Classification, and Turn On

Port Turn-On

Class

V_CLASS

Four-Point Detection

V_MARK

Mark

V_PORT

0 V

t_CLE

t_ME

t_DET

T_pon

Figure 4. Detection, 2-Event Classification, and Turn On

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V_VDD

3.0V < V_VDD< 3.6V

V_UVDDR

V_UVDDF

t_POR

Time

For more information refer to the application note, TPS23861 Power-On Considerations, SLVA723.

Figure 5. VDD Power-On-Reset

V_VPWR

44V < V_VPWR< 57V

V_{UVLOPW _ F}

V_{UVLOPW_ R}

t_POR

Time

For more information refer to the application note, TPS23861 Power-On Considerations, SLVA723.

Figure 6. VPWR Power-On-Reset

15

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6.8 Typical Characteristics

2.4

17.0

16.5

16.0

15.5

15.0

14.5

14.0

2.3

2.2

2.1

2.0

0

20

40

60

80

100

120

œ40

œ20

0.0

20.0 40.0 60.0 80.0 100.0 120.0

œ40.0 œ20.0

T_J-Junction Temperature-°C

C001

C002

Figure 7. VDD UVLO vs Junction Temperature

Figure 8. VPWR UVLO vs Junction Temperature

7.0

6.5

6.0

5.5

5.0

2.0

1.9

1.8

1.7

1.6

1.5

TJ=-40°C

TJ=25°C

TJ=125°C

2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 3.70

0.0

20.0 40.0 60.0 80.0 100.0 120.0

œ40.0 œ20.0

V_DD-V

T_J-Junction Temperature-°C

C004

C003

Figure 10. VDD Current vs VDD

Figure 9. DC Disconnect vs Junction Temperature

7.00

110

TJ=25°C

TJ=125°C

TJ=-40°C

6.50

6.00

5.50

5.00

4.50

4.00

109

108

107

106

105

20.00

30.00

40.00

50.00

60.00

0

20

40

60

80

100

120

œ40

œ20

VPWR-V

T_J-Junction Temperature-°C

C005

C006

Figure 11. VPWR Current vs VPWR

Figure 12. Current Limit (1x threshold) vs Junction

Temperature

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Typical Characteristics (continued)

300

250

200

150

100

50

120

110

100

90

80

70

60

50

40

30

20

10

0

1x

2x

0

10

20

30

40

50

0

10

20

30

40

50

FET V_DS-V

Port Voltage-V

C008

C007

Figure 14. Current Limit Threshold vs FET Voltage

Figure 13. Inrush Current Limit Threshold vs Port Voltage

22

280

20

18

16

14

12

278

276

274

272

270

TJ=-40°C

TJ=25°C

TJ=125°C

0

10

20

30

40

50

60

70

0

20

40

60

80

100

120

œ40

œ20

Classification Current-mA

T_J-Junction Temperature-°C

C010

C009

Figure 16. Classification Voltage vs Port Classification

Current

Figure 15. Current Limit (2x threshold) vs Junction

Temperature

Figure 17. Valid PD Detection (25 kΩ and 0.1 µF) and CLASS

Figure 18. Valid PD Detection (25 kΩ and 0.1 µF) and CLASS

0 Classification

3 Classification

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Typical Characteristics (continued)

Figure 19. Detection with Invalid PD (15 kΩ and 0.1 µF)

Figure 20. Detection with Invalid PD (open circuit)

Figure 21. Detection with Invalid PD (25 kΩ and 10 µF)

Figure 22. 2-Event Class and Startup with Valid PD

Figure 23. Powering Up Into a 100-µF Load

Figure 24. Semi-Auto Sequenced Turn On

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Typical Characteristics (continued)

Figure 26. Overcurrent (I_CUT) Timeout

Figure 25. All Ports Fast Shutdown

Figure 27. Rapid Response to a 1-Ω Short: 802.3af Mode

Figure 28. Rapid Response to a 1-Ω Short: PoE+ Mode

Figure 29. Response to a 50-Ω Load: 802.3af Mode

Figure 30. Response to a 25-Ω Load: PoE+ Mode

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Typical Characteristics (continued)

Figure 31. Current Limit Timeout: 802.3af Mode, 85-Ω Load

Figure 32. Current Limit 15-ms Timeout: PoE+ Mode, 45-Ω

Load

Figure 33. Inrush Fault Timeout: 100-Ω Load

Figure 34. Current Limit Timeout Restart Delay

Figure 35. Response to 8-mA to 6-mA Load, DC Disconnect Enabled

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7 Detailed Description

7.1 Overview

The TPS23861 is a four-port PSE for power over ethernet applications. Each of the four ports provides fully

automatic detection, classification, protection, and shut down in compliance with the IEEE 802.3at standard.

The schematic of Figure 36 depicts automatic mode operation of the TPS23861, providing turnkey functionality

ready to power PoE loads. No connection to the I²C bus or any type of host control is required. In Figure 36 the

TPS23861 automatically:

1. Performs four-point load detection.

2. Performs classification including type-2 (two-finger) of up to Class 4 loads.

3. Enables power with protective foldback current limiting, and ICUT value based on load class.

4. Shuts down in the event of fault loads and shorts.

5. Performs Maintain Power Signature function to ensure removal of power if load is disconnected.

6. Undervoltage lock out occurs if VPWR falls below V_{PUV_F}(typical 26.5 V).

Following a power-off command, disconnect or shutdown due to a start, ICUT or ILIM fault, the port powers

down. Following port power off due to a power off command or disconnect, the TPS23861 will continue automatic

operation starting with a detection cycle. If the shutdown is due to a start, ICUT or ILIM fault, the TPS23861

enters into a cool-down period. After the end of the cool-down period the TPS23861 continues automatic

operation starting with a detection cycle.

The TPS23861 will not automatically apply power to a port under the following circumstances:

•

The detect status is not Resistance Valid.

If the classification status is overcurrent, class mismatch, or unknown.

21

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Overview (continued)

VPWR

VDD

0.1mF

50V

0.1mF

100V

TPS23861PW

VPWR

1

2

3

4

5

6

7

8

9

VDD

VPWR 28

N/C 27

P2

P3

RESET

SCL

+

RJ45

0.1mF

&

+

RJ45

&

XFMR

0.1mF

100V

-

SMBJ58A-13-F

C1S 1.5

SMBJ58A-13-F

C1S 1.5

100V

XFMR

-

AOUT 26

AIN 25

SDAI

FDMC3612

SDAO

INT

SHTDWN 24

A3 23

10MQ100NTRPBF

(Optional)

0.255W

DGND

SEN3

DRAIN3

AGND 22

GATE2 21

DRAIN2 20

SEN2 19

22.1W

47W

0.255W

22.1W

(Optional)

10 GATE3

11 KSENSB

12 SEN4

10MQ100NTRPBF

KSENSA 18

GATE1 17

DRAIN1 16

SEN1 15

FDMC3612

C1S 1.5

FDMC3612

C1S 1.5

22.1W

P1

P4

47W

-

RJ45

0.1mF

&

-

RJ45

0.1mF

&

13 DRAIN4

14 GATE4

SMBJ58A-13-F

22.1W

100V

XFMR

+

100V

XFMR

+

SMBJ58A-13-F

VPWR

Figure 36. Automatic 4-Port Operation Schematic

VDD

VPWR

PD

Port 2œ4 Analog Control Functions

Port 1 Analog Control Functions

RESET

IDET =

160/270/

540 ꢀA

Load

SHTDWN

DRAINx

Foldback Schedulers

Ilim

Fast Ishort Protection

dv/dt Ramping Control

Rapid Overload Recovery

Class Current Limit

Class Port Voltage Control

GATEx

SENx

Gm

Driver

Processor

0.255

KSENSEA,B

Figure 37. Simplified Block Diagram

22

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Overview (continued)

7.1.1 Detailed Pin Description

The following descriptions refer to the pinout and the functional block diagram.

DRAIN1-DRAIN4: Port 1-4 output voltage monitor and detect sense. Used to measure the port output voltage,

for port voltage monitoring, port-power-good detection and foldback action. Detection probe currents also flow

into this pin. The TPS23861 uses an innovative 4-point technique in order to provide a reliable PD detection.

Detection is performed by sinking two different current levels via the DRAINn pin, while the PD voltage is

measured from VPWR to DRAINn. The 4-point measurement provides the capability to distinguish between an

IEEE-standard-compliant PD and a capacitive or legacy load. If the Port n is not used, DRAINn can be left

floating or tied to AGND.

GATE1-GATE4: Port 1-4 gate drive output used for external N-channel MOSFET gate control. At port turn on, it

is driven positive by a low-current source to turn the MOSFET on. GATEn is pulled low whenever any of the

input supplies are low or if an over-current timeout has occurred. GATEn will also be pulled low if its port is

turned off during fast shutdown. Leave floating if unused. For a robust design, a current-foldback function limits

the power dissipation of the MOSFET during low resistance load or a short-circuit event. The foldback

mechanism measures the port voltage across AGND and DRAINn to reduce the current-limit threshold as shown

in Figure 14, Figure 57, and Figure 58. The fast overload protection is for major faults like a direct short. This

forces down the current within the current limit in less than a microsecond. When ICUT threshold is exceeded

while a port is on, a timer starts. During that time, linear current limiting makes sure the current will not exceed

ILIM combined with current-foldback action. When the timer reaches its t_OVLD(or t_STARTif at port turn on) limit, the

port shuts off. When the port current goes below I_CUT, the counter counts down at a rate 1/16^thof the increment

rate, and it must reach a count of zero before the port can be turned on again.

KSENSA, KSENSB: Kelvin point connection used to perform a differential voltage measurement across the

associated current sense resistors. KSENSA is shared between SEN1 and SEN2, while KSENSB is shared

between SEN3 and SEN4. In order to optimize the accuracy of the measurement, the PCB layout (see

Figure 61) must be done carefully to minimize impact of PCB trace resistance.

SHTDWN: Shutdown, active low. This pin is internally pulled up to VDD, with internal 1-µs to 5-µs deglitch filter.

The Port Power Priority register is used to determine which port(s) is (are) shut down in response to an external

assertion of the SHTDWN pin. The turn-off procedure is similar to a port reset or a reset command (Reset

register).

NOTE

After a SHTDWN cycle occurs, the I²C host should reinitialize the TPS23861 register set

according to the desired user configuration. More detail regarding use of the SHTDWN pin

to power off low priority ports can be obtained by consulting a Texas Instruments technical

representative.

RESET: Reset input, active low. When asserted, the TPS23861 resets, turning off all ports and forcing the

registers to their power-up state. This pin is internally pulled up to VDD, with internal 1-µs to 5-µs deglitch filter.

External RC network can be used to delay the turn-on. There is also an internal power-on-reset which is

independent of the RESET input.

NOTE

After RESET pin de-assertion, there is a delay of approximately 20 ms before TPS23861

can process I²C commands. For more information, refer to the application note TPS23861

Power-On Considerations, SLVA723.

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Overview (continued)

SEN1- SEN4: Port 1-2 current sense input relative to KSENSA, and port 3-4 current sense relative to KSENSB.

A differential measurement is performed using KSENSA and KSENSB Kelvin point connection. It monitors the

external MOSFET current by use of either a 255-mΩ (two 510 mΩ in parallel) or a 250-mΩ (four 1 Ω in parallel)

current-sense resistors connected to AGND. Used by current foldback engine and also during classification. Can

be used to perform load current monitoring via A/D conversion.

NOTE

A classification is done while using the external MOSFET so performing a classification on

more than one port at the same time is possible without exceeding dissipation in the

TPS23861.

For the current limit with foldback function, there is an internal 2-µs analog filter on the SEN1-4 pins to provide

glitch filtering. For measurements through an A/D converter, an anti-aliasing filter is present on the SEN1-4 pins.

This includes the port-powered current monitoring and disconnect. If the port is not used, tie SENn to AGND.

VDD: 3.3-V logic power supply input.

VPWR: High-voltage power supply input. Nominally 48 V.

7.1.2 I²C Detailed Pin Description

AIN: Used to program the I²C slave device address. This pin is internally pulled up to VDD. See I²C Slave

Address and AUTO Bit Programming for more details.

AOUT: Used to program the I²C slave device address for multiple devices. See I²C Slave Address and AUTO Bit

Programming for more details. AOUT is open drain.

A3: I²C A3 address input, used during normal operation and during slave address programming. This pin is

internally pulled up to VDD.

INT: Interrupt output. This pin asserts low when a bit in the interrupt register is asserted. This pin is updated

between I²C transactions. This output is open-drain. Interrupt functional diagram is shown in Figure 43.

SCL: Serial clock input for I²C bus. Requires an external pull-up resistor to VDD.

SDAI: Serial data input for I²C bus. Requires an external pull-up resistor to VDD. This pin can be connected to

SDAO for non-isolated systems. See Figure 50.

SDAO: Open-drain I²C bus output data line. Requires an external resistive pull up. The TPS23861 uses separate

SDAO and SDAI lines to allow optoisolated I²C interface. SDAO can be connected to SDAI for non-isolated

systems.

NOTE

Both VPWR and VDD must be present for proper system level I²C operation.

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7.2 Functional Block Diagram

VDD

VPWR

VDD UVLO

Internal Rails

Good

SHTDWN Direct Shutdown for Ports

PG

VPWR

RESET

RST Block

Port 2-4 Analog Control Functions

Port 1 Analog Control Functions

SHTDWN

IDET =

160/

270/

RST to Blks

PD LOAD

AOUT

AIN

540uA

SHTDWN/POR

Foldback Schedulers

AIN/AOUT Mux

DRAINx

GATEx

SENx

Ilim

Fast Ishort Protection

dv/dt Ramping Control

Rapid Overload Recovery

2X Power

Enable

Gm

Driver

Processor

1 Byte EE NVM

7-Bit Address/Including

State of A3 Pin

18 V

A3

Class Current Limit

Class Port Voltage Control

SDAI

SDAO

SCL

0.255

I2C Interface

IPORT

320-Hz LPF

KSENSEA,B

14-Bit ADC

(Current)

ICLASS

BIT

SCL Watchdog

Register File

Variable Averager

INT

Vdisco

Vport

Vds

V48

PORT DIFF AMP

4:1 MUX

DRAIN1œ4

14-Bit ADC

(Voltage)

SHTDWN

VEE

V48

Temp

BIT

PTAT Diodes

Analog BIT MUX

Variable Averager

Analog Test

AIN

7.3 Feature Description

7.3.1 Detection Resistance Measurement

The detect resistance can be measured and reported in the Port n Detect Resistance Register. Fourteen bits of

resistance information are reported in two bytes. Useful range of measurement is 500 Ω to 55 kΩ. Resolution (1

LSB) is approximately 11 Ω. Measurement repeatability is on the order of ±200 Ω. Additionally, in the MSB of the

resistance register (Port n Resistance: MSByte) the RSn field reports whether a low-resistance circuit, open

circuit or MOSFET short fault is detected.

Before detection begins, the TPS23861 backs-off for up to 400 ms to allow the port voltage to drop below 2.8 V.

This will allow any PD on the port to reset prior to an attempt to detect, classify and apply power to the PD.

Table 1. RSn Field Encoding

RSn1

RSn0

DETECT STATUS

Other

R_STEPBIT WEIGHT

0

1

0

1

0

1

11.0966 Ω/bit

Low (< 2 kΩ)

Open circuit

Additional detect 4.625 Ω/bit

N/A

MOSFET short fault

7.3.2 Physical Layer Classification

Whether one or two classification events will be executed depends on the operating mode and the value of the

TECLENn field in the Two-Event Classification Register. See Device Functional Modes for details.

See Figure 38 and Figure 39 for illustrations of the voltage on the Power Interface (PI) during single-event

(802.3af) and 2-event (802.3at) classification.

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Powered On

802.3 optional

classification

20.5

Free Format

Transition

15.5

Four Point Detection

10

2.8

Figure 38. 802.3af with Classification

Powered On

2^ndClass

1

^stClass

20.5

15.5

10

2.8

1^stMark

2^ndMark

Figure 39. P802.3at with Classification

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7.3.3 Class and Detect Fields

The results of the detection cycle and classification cycle are each stored in a 4-bit field for each port in the

Detect Pn and Class Pn fields of the Port n Status Register. The results of a detection and classification event

are encoded as follows.

Table 2. Detect Pn Field Encoding

DETECT Pn

0000

DETECT STATUS

Unknown (POR value)

Short circuit (<500 Ω)

Reserved

0001

0010

0011

Resistance too low

Resistance valid

Resistance too high

Open circuit

0100

0101

0110

0111

Reserved

1000

MOSFET fault

1001

Legacy detect

1010

Capacitance measurement invalid: Detect measurement beyond

clamp voltage

1011

1100

Capacitance measurement invalid: Insufficient Δv measured

Capacitance measurement is valid, but outside the range of a legacy

device.

Table 3. Class Pn Field Encoding

CLASS Pn

0000

CLASSIFICATION STATUS

Unknown

0001

Class 1

0010

Class 2

0011

Class 3

0100

Class 4

0101

Reserved – read as class 0

Class 0

0110

0111

Overcurrent

1000

Class mismatch

A class mismatch can occur only during two-event classification. If the classification statuses for the first and

second event are different, and the second classification status is not “Overcurrent”, the Classification Status will

be set to Class Mismatch. If the status of the first classification event is “Overcurrent”, the classification status is

set to “Overcurrent” in the Class Pn field, and there will be no second classification event in any case. If in Auto

Mode, the port will not power on automatically, but it still can be powered on through the Power Enable Register.

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7.3.4 Register State Following a Fault

Following an ICUT, ILIM or inrush fault on port n, the port is shut off, and the appropriate fault bit is set in the

Fault Event Register or Start/ILIM Event Register. In addition, the following registers are affected.

•

The PGn and PEn in the Power Status Register are cleared.

The CLSCn and DETCn bits in the Detection Event register are cleared.

The corresponding Port n Status Registers are cleared.

The PGCn and PECn bits in the Power Event Register are set.

The PORT n Voltage Registers is cleared.

7.3.5 Disconnect

The TPS23861 supports DC disconnection. Disconnect threshold and timing are set using the DCTHn field in the

Disconnect Threshold Register and the TDIS field in the Timing Configuration Register respectively. Following a

disconnect event on port n, the following registers are affected.

•

The DISFn bit in the Fault Event Register is set.

The PGn and PEn in the Power Status Register are cleared.

The CLSCn and DETCn status bits in the Detection Event Register are cleared.

The corresponding Port n Status Registers are cleared.

The PGCn and PECn bits in the Power Event Register are set.

The corresponding Port n Voltage Registers are cleared.

7.3.6 Disconnect Threshold

The disconnect current range is selectable through the DCTHn 2-bit fields in the Disconnect Threshold Register.

The encoding of the DCTHn fields is presented in Table 4.

Table 4. DCTHn Field Encoding

DCTHn FIELD

DISCONNECT THRESHOLD, mA

00

01

10

11

7.5

15

30

50

7.3.7 Fast Shutdown Mode

The TPS23861 responds to a low level on the SHTDWN pin by immediately turning off all ports preconfigured as

low priority through the FSEn bits in the Port Power Priority Register. Reaction time is typically 2 µs. If an FSEn

bit is set while the SHTDWN pin is low, the corresponding port is turned off and reset.

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7.3.8 Legacy Device Detection

Legacy PDs which are not compliant with IEEE 802.3at can be identified on port n under control of the LEGMOD

field in the Legacy Detect Mode Register. Two modes of legacy detection are supported. When LEGMODn = 10,

port n is probed for IEEE 802.3at-based compliance (based on resistance measurement) followed by a

capacitance-based detection scheme for legacy devices. When LEGMODn= 01, port n performs a capacitance-

based detection scheme only. This allows the host to probe for a potential legacy PD without pre-charging the

PD capacitance before trying to measure the value of the capacitance.

To measure capacitance, a fixed charge is injected into the Power Interface (PI) and the voltage difference

induced by the charge is measured and reported in the Port n Detect Voltage Difference Registers. The

capacitance is inversely proportional to the voltage difference. The voltage difference is compared against

thresholds to accept capacitance values above 6 µF pursuant to the qualifications which follow.

The Port n Detect Voltage Difference Register consists of two contiguous bytes in the I²C addressable register

space. Together these registers contain a 12-bit unsigned representation of the voltage difference along with a 4-

bit status field named VDSn. When VDSn = 0001 the voltage-difference value represents a valid measurement.

The capacitance measurement may fail due to an excessively small or large capacitance, or an input

capacitance which cannot be discharged because it is behind a diode. These cases are reported in the VDSn

field as well as in the DETECT Pn field in the Port n Status Registers. See Table 5.

Table 5. Capacitance Measurement Characteristics and Capabilities

PARAMETER

CONDITIONS

VALUE

UNIT

Minimum measurable capacitance

Maximum 500-kΩ parallel resistance; maximum

6.1

μF

measurement voltage of 16.5 V at port

Maximum measurable capacitance

Nominal port charging current

Nominal measurement time

Minimum 17-kΩ parallel resistance

Minimum 10-kΩ parallel resistance

100

67

μF

μA

ms

V

540

150

0.4

Minimum voltage at port for commencement of

measurement

Maximum voltage at port for commencement of

measurement

2.4

V

Duration of port-discharge period

First discharge attempt

250

500

16.5

ms

V

Second discharge attempt

Maximum voltage at port at the beginning or end

of measurement

A resistance in parallel with the capacitance at the input of the PD affects the accuracy of the capacitance-

measurement algorithm. A parallel resistance causes the capacitance on the port to appear higher. This fact is

reflected in Table 5 . Capacitance up to 100 μF can be measured with a parallel resistance as low as 17 kΩ,

whereas if the parallel resistance is as low as 10-kΩ, capacitance up to 67 μF can be measured.

The voltage on the port must be in the range of 0.4 V to 2.4 V to begin capacitance measurement. This voltage

as measured at the PSE includes the voltage drops across any diodes in the path of the capacitance. If the

voltage measured is too high (due to charge on the PD capacitance), the TPS23861 makes two attempts to

discharge the port by applying a 100-kΩ load across the port. The first discharge attempt is 250-ms duration; the

second attempt 500 ms.

NOTE

It may not be possible to discharge the PD capacitance rapidly if the capacitance is on the

other side of a diode.

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If the capacitance-measurement algorithm is unable to discharge the port to less than 2.4 V after two attempts,

the algorithm terminates the attempt to measure port capacitance, and report an Unable to achieve 2.4 V to take

first measurement status in the VDSn field of the Port n Detect Voltage Difference Registers. A status of

Capacitance measurement invalid: Insufficient Δv measured is reported in the Port n Status Registers. A status

of Unable to discharge PD input capacitance to 2.4 V before timeout, is reported in the VDSn field of the Port n

Detect Voltage Difference Registers. The host has the option of imposing a longer discharge time and retrying.

Erratic results may be obtained when performing legacy detect in Semi-Auto Mode due to the repeated charging

of the load. If the capacitive load is behind a diode or is in parallel with a high resistance, the capacitor may

eventually charge beyond 2.4 V, and the capacitance measurement fails. Manual Mode is recommended for

legacy detect when there is no information about the load, or if the load input capacitance charges beyond 2.4 V

in Semi-Auto Mode.

If the port is open or a small capacitance is present on the port, the port voltage rises quickly when the

capacitance-measuring current is applied. The voltage on the port is limited to approximately 18 V by an internal

clamp. A status of Capacitance measurement invalid: Detect measurement beyond clamp voltage is reported in

the DETECT Pn field of the Port n Status Registers. Depending on the size of the small capacitance, a status of

First measurement exceeds V_{Det-clamp (min)}or Second measurement exceeds V_{Det-clamp (min)}is reported in the VDSn

field of the PORT n Detect Voltage Difference Registers.

If a large capacitance or short circuit is present on the port, the port voltage will not change sufficiently over the

port charging time to assure a reliable measurement. In this case, a status of Capacitance measurement invalid:

Insufficient Δv measured is reported in the Port n Status Registers, and a status of Δv < 0.5 V (insufficient signal)

or Unable to achieve 0.4V to take first measurement before timeout is reported in the VDSn field of the Port n

Detect Voltage Difference Registers.

Legacy detect is an exceptional condition which warrants special handling by the host system. Consequently,

legacy-detect operation will not be fully supported in Auto Mode. If a legacy device is detected during detection in

any mode of operation, the detect status is reported as Legacy Detect in the Port n Status Register Detect Pn

field. It is up to the host to power on the port. If a port is in Auto Mode, legacy detection is enabled and a legacy

device is detected, the detect status is reported as Legacy Detect in the Port n Status Registers Detect Pn field,

but the port will not power on automatically. In this respect, operation of the port is identical to the Semi-Auto

Mode.

In general, it is expected that a legacy device will not respond to a request for classification. Therefore, if the

portis in Semi-Auto, Auto Mode or Manual Mode and LEGMOD = 01, the PSE will not automatically initiate a

classification cycle even if the CLEn bit is set. On the other hand, if LEGMOD = 10, the TPS23861 is operating in

Semi-Auto or Auto Mode, classification is enabled via the CLEn bit, and a Resistance valid detect status is

returned in response to a standard resistance detection cycle, the TPS23861 follows the standard resistance

detection cycle with a classification cycle. Furthermore, following classification, if in Auto Mode, if the

classification status is not unknown, class mismatch or overcurrent, the port automatically powers up. Additionally

if LEGMOD = 10, it is possible to initiate a classification cycle under manual control using the CLEn bit in the

Detect/Class Enable Register or the RCLn bit in the Detect/Class Restart Register or power on the port under

manual control using the PWONn bit in the Power Enable Register.

If LEGMODn = 10, and a Resistance valid detect status is returned in response to a standard resistance

detection cycle the TPS23861 will not attempt to measure capacitance on the PI.

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7.3.9 VPWR Undervoltage and UVLO Events

This section lists the behavior of VPWR undervoltage and UVLO events when the voltage at the VDD pin is

uninterrupted.

When the voltage at the VPWR pin falls below V_{PUV_F}the following occurs.

•

The VPUV bit in the Supply Event Register is set.

All ports are shut off.

For ports that are shut off the corresponding PGCn and PECn bits in the Power Event Register is set and the

PGn and PEn bits in the Power Status Register are cleared.

•

The following registers are cleared.

–

Detection Event Register

Fault Event Register

Start/ILIM Event Register

Port n Status Register

Detect/Class Enable Register

NOTE

When the voltage at the VPWR pin falls below V_{UVLOPW_F}the following occurs.

•

Both the VPUV and VDUV bits in the Supply Event Register is set

All ports are shut off

All registers are set to their power-on/reset state

7.3.10 Timer-Deferrable Interrupt Support

A programmable timer is provided with range selectable from 10 ms to 150 ms in 10 ms increments. Timer

duration is programmed via the four-bit field TMR [3:0] in the Interrupt Timer Register. Non-critical interrupts will

be deferred from asserting an interrupt on the INT pin until the timer times out. Critical interrupts such as faults

will not be affected by the state of this timer. Critical vs. deferrable interrupts are identified in Table 6. The

behavior of the various interrupt enable bits is not affected by the timer function.

Table 6. Timer-Deferrable Interrupt

INTERRUPT BIT

SUPF

FUNCTION

CRITICAL OR DEFERRABLE

Critical

Supply or thermal fault

Start fault

STRTF

IFAULT

CLASC

DETC

Deferrable

ICUT or ILIM fault

Critical

A classification event occurred

A detection event occurred

A disconnect event occurred

Power good status change

Power enable status change

Deferrable

DISF

Deferrable

PGC

Deferrable

PEC

Deferrable

If the counter is loaded with 0000 (POR state) the counter will not count, and no interrupts will be deferred. That

is, this function will be disabled.

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7.3.11 A/D Converter and I²C Interface

The TPS23861 features five multi-slope integrating converters. Each of the first four converters is dedicated to

current measurement for one port and is operated independently to perform measurements. The converters are

used for current monitoring (100 ms averaged) and disconnect. The fifth converter is shared between all four

ports for detection (conversion time set by MAINS bit), port voltage monitoring, Power Good Status and FET

short detection (1 ms for all). It is also used for general-purpose measurements including input voltage (1 ms)

and temperature.

The A/D converter type used in the TPS23861 differs from other types of converters in that it converts while the

input signal is being sampled by the integrator, resulting in reduced conversion time and providing inherent

filtering over the conversion period. The typical conversion time of the current converters is 800 µs. Digital

averaging is used to provide a port current measurement integrated over a 100-ms time period.

NOTE

An anti-aliasing filter is present for current and voltage monitoring. Port current

conversions are performed continuously.

Powered device (PD) detection is performed by averaging 16 consecutive samples providing significant rejection

of noise at 50/60-Hz line frequency. The total time for the 16 samples can be set to 20 ms or 16.7 ms by the

MAINS bit to correspond to the local mains frequency.

The fifth converter continuously measures drain voltages from one port to the next one, updating internal

registers used for Power Good Status and FET short detection, unless a command is received to perform a

specific measurement.

Also, when the port is powered on, the t_STARTtimer (used during PD power-on inrush) must expire before any

current or voltage A/D conversion can begin for the first four converters.

Figure 40 illustrates read and write operations through I²C interface. The two-data-bytes-read operation is

applicable to A/D conversion results.

It is also possible to perform an I²C write operation to many TPS23861 devices at same time. The slave address

during this broadcast access is 0x30.

The TPS23861, using the INT pin, supports the SMBALERT protocol. When INT is asserted low, if the bus

master controller sends the alert response address, the TPS23861 responds providing its device address on the

SDA line and releases the INT line. If there is a collision between two TPS23861 devices responding

simultaneously, then the device with the lower address wins arbitration and responds first, by use of SDAI and

SDAO lines.

An I²C watchdog timer is also available on the TPS23861, which monitors the I²C clock line in order to prevent

hung software situations that could leave ports in a hazardous state. The timer can be reset by either edge on

the SCL line. When enabled, if the watchdog timer expires, all ports are turned off and WDS bit is set. The

nominal watchdog time-out period is 2 seconds. See I²C Watchdog Register for more details on the subject.

NOTE

When a stop condition is detected on the I²C bus after having at least received the

command byte, the TPS23861 stores the command byte in an internal register.

NOTE

When using the I²C interface the host software should wait 22 ms minimum after a reset to

ensure valid I²C transactions.

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This content can be later used as a register address pointer during next quick read cycle register access. See

Figure 40. This internal register is cleared at power on or through the RESET pin.

R/W

Bit

R/W

Bit

1 Data Byte

Read Cycle

SDAI

A6 A5 A4 A3 A2 A1 A0 R/W

C5 C4 C3 C2

A6 A5 A4 A3 A2 A1 A0 ^R/W

D7 D6 D5 D4 D3 D2 D1 D0

C0

C1

C6

C7

Command Code

Slave Address

R/W=0

Slave Address

R/W=1

Data from

Slave to Host

SDAO

D7 D6 D5 D4 D3 D2 D1 D0

R/W

Bit

R/W

Bit

2 Data Byte

Read Cycle

C0

C1

R/W

D7 D6 D5 D4 D3 D2 D1 D0

A6 A5 A4 A3 A2 A1 A0 R/W

C5 C4 C3 C2

A6 A5 A4 A3 A2 A1 A0

C6

C7

SDAI

Command Code

Slave Address

R/W=0

Slave Address

R/W=1

LSByte Data from

Slave to Host

MSByte Data from

Slave to Host

D7 D6 D5 D4 D3 D2 D1 D0

SDAO

R/W

Bit

Write Cycle

C0

C1

A6 A5 A4 A3 A2 A1 A0 R/W

C4

C2

C3

D7 D6 D5 D4 D3 D2 D1 D0

C5

C6

C7

SDAI

Slave Address

R/W=0

Data from

Host to Slave

Command Code

SDAO

Quick Read Cycle

(latest addressed register)

R/W

Bit

SDAI

R/W

D7 D6 D5 D4 D3 D2 D1 D0

A6 A5 A4 A3 A2 A1 A0

Data from

Slave Address

R/W=1

Slave to Host

SDAO

D7 D6 D5 D4 D3 D2 D1 D0

Alert Response

R/W

Bit

SDAI

R/W

A6 A5 A4 A3 A2 A1 A0

Slave Address from

Slave to Host

ARA Slave Address

R/W=1

SDAO

A6 A5 A4 A3 A2 A1 A0

Figure 40. I²C/SMBus Interface Read and Write Protocol

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7.3.12 Independent Operation when the AUTO Bit is Set

The TPS23861 operates as a fully automatic PSE in compliance with IEEE 802.3at when the AUTO bit is set as

described in I²C Slave Address and AUTO Bit Programming section. Fully automatic operation means that the

TPS23861 operates as a power-over-ethernet four-port PSE without any connection to a host system via the I²C

bus. Generally speaking, when the bit is set, most specialized features of the TPS23861 are disabled.

NOTE

The state of the AUTO bit is read only following power on, hardware reset (RESET pin) or

writing a 1 to the RESAL bit in the Reset Register.

If the AUTO bit is set and the TPS23861 is connected to a host over the I²C bus, the host may change the

register settings any time after power up, including changing operating mode. When the AUTO bit is set, the

state of TPS23861 following power up is summarized below.

•

The CLEn and DETn bits in the Detect/Class Enable Register is set. Consequently, detect and classification

is performed before any power on.

•

The DCDEn bit in the Disconnect Enable Register is set, enabling automatic disconnection.

The TECLENn bits in the Two-Event Classification Register is set to 0b01. Consequently, if a Class 4 PD is

recognized during the classification cycle,

–

The TPS23861 initiates a second physical-layer classification event.

The PoEPn bit in the PoE Plus register is set, employing the 2x curve for I_LIM

The ICUT Port n fields in the ICUTnm CONFIG registers will be set to 0b110 corresponding to 645 mA.

.

•

If a Class 0, 1, 2 or 3 PD is recognized during the classification cycle,

–

There is no second physical-layer classification event.

The POEPn bit is cleared so the TPS23861 employs the 1x foldback curve for I_LIM

A value of 374 mA is used for ICUT.

.

The Port n Mode field in the Operating Mode Register is set to Auto (0×11) for all four ports. Consequently,

–

Detection, classification and power up occurs in sequence, automatically and independently for each port.

Following a valid one- or two-event physical layer classification, the TPS23861 applies power to a port

subject to the inrush-current foldback protection curve in Figure 57.

.

•

The FSEn bits in the Port Power Priority Register is set. Consequently, all ports are shut down in response to

a low level on the SHTDWN pin.

The LEGMODn fields in the Legacy Detect Mode Register is set to 00. Consequently, legacy PD devices not

compliant with IEEE 802.3at will not be detected.

The General Mask 1 Register is set to its standard power-on-reset value 0x80. Consequently,

–

Interrupts are enabled.

During detection A/D conversions of the detect voltage occurs at a rate of 800 per second.

Classification levels are determined as if a 255-mΩ resistor is used for the current-sense resistor.

NOTE

If a 250-mΩ resistor is used, the classification thresholds shifts slightly, but remains

compliant with IEEE 802.3at.

•

The Interrupt Enable Register is set to 0xE4, enabling the following interrupts

–

SUPEN – Supply event fault enable bit.

STRTEN – Start fault enable bit.

IFEN – ICUT or ILIM fault enable bit.

DISEN – Disconnect event interrupt enable bit.

•

Any register not explicitly referenced above is set to its default power-on-reset value according to Table 10.

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7.3.13 I²C Slave Address and AUTO Bit Programming

NOTE

When using the I²C interface the host software should wait 22 ms minimum after a reset to

ensure valid I²C transactions.

NOTE

Please note EEPROM endurance of 25 write cycles. Writing to the EEPROM more than

this may result in erratic behavior.

The TPS23861 includes a means to program in EEPROM the following two fields:

•

A seven bit I²C slave address for operation with a host processor.

AUTO bit which allows the TPS23861 to operate independently without a host processor.

The benefits this approach include:

•

Up to 125 similar devices become addressable.

Provides a high level of flexibility.

–

Helps to resolve conflicts with other peripherals on same I²C bus.

The I²C address can be programmed at production subassembly module level or motherboard level.

Allows a simple approach to field-installed upgrades or expansions to PSE systems.

•

No physical address line required, no bank selection required.

Smaller package. No address line pins and no AUTO pin.

NOTE

For compatibility with legacy systems, the module A3 bank addressing is provided by use

of the A3 input pin.

As shown in Figure 41, the initial I²C address programming access is established by a local daisy chain chip

select connection between multiple TPS23861 devices. The AIN pin plays the role of a “moving chip select”

during address programming.

NOTE

Global write command including an unlock code (AAh) is required in order to write to the

I²C slave address register.

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AIN-AOUT daisy-chain connection allows the I²C

address of each device to be programmed separately

All devices respond to global address 30h

regardless of the state of the A3 pin.

SCL

SDAI

1

2

3

4

5

6

7

8

9

VDD

VPWR 28

N/C 27

1

2

3

4

5

6

7

8

9

VDD

VPWR 28

N/C 27

1

2

3

4

5

6

7

8

9

VDD

VPWR 28

N/C 27

1

2

3

4

5

6

7

8

9

VDD

VPWR 28

RESET

SCL

RESET

SCL

RESET

SCL

RESET

SCL

N/C 27

AOUT 26

AIN 25

AOUT 26

AIN 25

AOUT 26

AIN 25

AOUT 26

AIN 25

SDAI

SDAO SHTDWN 24

V_DD

INT

A3 23

AGND 22

GATE2 21

INT

A3 23

AGND 22

GATE2 21

INT

A3 23

AGND 22

GATE2 21

INT

A3 23

AGND 22

GATE2 21

DGND

SEN3

DGND

SEN3

DGND

SEN3

U2

U1

Un-1

Un

SEN3

DRAIN3 DRAIN2 20

10 GATE3 SEN2 19

11 KSENSB KSENSA 18

12 SEN4 GATE1 17

13 DRAIN4 DRAIN1 16

14 GATE4 SEN1 15

DRAIN3 DRAIN2 20

10 GATE3 SEN2 19

11 KSENSB KSENSA 18

12 SEN4 GATE1 17

13 DRAIN4 DRAIN1 16

14 GATE4 SEN1 15

DRAIN3 DRAIN2 20

10 GATE3 SEN2 19

11 KSENSB KSENSA 18

12 SEN4 GATE1 17

13 DRAIN4 DRAIN1 16

14 GATE4 SEN1 15

DRAIN3 DRAIN2 20

10 GATE3 SEN2 19

11 KSENSB KSENSA 18

12 SEN4 GATE1 17

13 DRAIN4 DRAIN1 16

14 GATE4 SEN1 15

If U1 or U2 is programmed with

If Un-1 or Un is programmed with

I²C address [a₇a₆a₅a₄a₃a₂a₁a₀] the device will

respond to the I²C address [a₇a₆a₅a₄1a₂a₁a₀]

because the A3 pin is tied high.

I²C address [a₇a₆a₅a₄a₃a₂a₁a₀] the device will

respond to the I²C address [a₇a₆a₅a₄0a₂a₁a₀]

because the A3 pin is tied low.

Figure 41. I²C Slave Address and AUTO Bit Programming Circuit

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The sequence during address programming is as follows:

•

Global write command including an unlock code (AAh) and a temporary common slave address (any address

other than 30h) is sent to all I²C devices through the broadcast address, 30h.

•

All TPS23861 devices respond to the broadcast address 30h regardless of the state of the A3 pin. When the

three-byte sequence is correctly decoded,

1. Each TPS23861 has a new I²C address determined by the programmed temporary slave address with bit

3 equal to the state of the A3 pin.

2. All TPS23861 devices force low the AOUT output.

For example, if a temporary common slave address of 20h is written to one device with A3 low and one with

A3 high, the device with A3 low will respond to I²C address 20h and the device with A3 high responds to I²C

address 28h.

•

The first TPS23861 device being selected is the only one having its AIN pin at logic high level (U1 in

Figure 41).

Using the temporary slave address, write the new 7-bit device address in the I²C slave address register. See

data format below.

NOTE

The SLA3 slave address bit follows the logic level of A3 input pin, as detailed for I²C Slave

Address register.

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

AUTO

7-bit I²C Address

•

The first slave accepts the new address, then forces its AOUT output pin to high level and automatically locks

the access to its slave address register. It also stores permanently its new slave address into EEPROM.

The same procedure is repeated for the next slave device, which has just detected that its AIN input has

become high.

•

This is repeated until all slaves have been reprogrammed.

The host can then interrogate each slave, one by one, in order to validate their new address.

NOTE

During the address programming procedure if the slave has not received its new address

within a timeout period (around 100 ms), it goes back to the initial slave address (before

the address programming sequence was initiated); it locks its address register and

releases its AOUT output.

•

Bit 7 of the 8-bit transfer (AUTO) defines if the controller operates independently (no host processor) as an

automatic PSE. The state of this bit is monitored only immediately following a power-on reset, writing a 1 to

the RESAL bit of the RESET register, or after the RESET input has been activated. The impact of that bit

state on registers after reset is reflected in the Table 10 (Reset State column) and is referred to as “A”.

NOTE

After programming a new I²C slave address to register 0×11, a 100 ms delay is

recommended before trying to perform a read check.

NOTE

When using I²C scan for device discovery, it is recommended to add at least a 100 ms

delay between writing commands to address 0x30 (Broadcast address) and 0x31. This

prevents receiving unnecessary extra ACK. Skipping writing command to address 0x30

can also avoid the extra ACK.

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Slave #1 I²C address programming

Global Write Cycle: Unlock the Address register

R/W

Bit

R/W

Bit

C1 C0

SA6 SA5 SA4 SA3 SA2 SA1 SA0

0

1

0

1

0

W

C4 C3 C2

0

D6 D5 D4 D3 D2 D1 D0

W

1

0

D7 D6 D5 D4 D3 D2 D1 D0

New slave address

C5

0

C7 C6

0

SDAI

...

Temporary common

slave Address

R/W=0

Temporary common

slave address

7-bit Global Address

R/W=0

Unlock Code

Slave address

command

SDAO

AOUT U1

.

t_{STP_AOUT}

AOUT Un-1

AOUT Un

Slave #n I²C Address Programming

R/W

Bit

0

1

SA6 SA5 SA4 SA3 SA2 SA1 SA0

W

0

1

0

D7 D6 D5 D4 D3 D2 D1 D0

0

SDAI

...

Temporary common

slave Address

R/W=0

Slave address

command

New slave address

SDAO

AOUT U1

.

AOUT Un-1

AOUT Un

Figure 42. I²C/SMBus Interface Slave Address Programming Protocol

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CoR 0x03h

CLRAIN

(Clear All Interrupts)

(0x1Ah)

CLRAIN

(Clear All Interrupts)

(0x1Ah)

CLINP

(Clear Interrupt Pin)

(0x1Ah)

R

Q3

Q2

Q1

Q0

PEC

Interrupt Bit 0

(0x00h)

Port Power Enable Status

Change

PWR Enable

Event

R

CK

D

Q

PESEN

Interrupt Enable

(0x01h)

Q7

Q6

Q5

Q4

PGC

Interrupt Bit 1

(0x00h)

Port Power Good Status

Change

PWR Good

Event

R

CK

Logic Hi

Q

INTEN

(Interrupt Pin Enable

(0x17h)

PGSEN

Interrupt Enable (0x01h)

INT

Port Disconnect Event

Detection Cycle

Classification Cycle

ICUT or ILIM Fault

CoR 0x09h

CLRAIN

(Clear All Interrupts)

(0x1Ah)

CLRAIN

(Clear All Interrupts)

(0x1Ah)

CLINP

(Clear Interrupt Pin)

(0x1Ah)

R

Q3

Q2

Q1

Q0

STRTF

Interrupt Bit 6

(0x00h)

Port Start Fault

Start Event

R

CK

D

Q

STRTEN

Interrupt Enable

(0x01h)

CoR 0x0Bh

CLRAIN

(Clear All Interrupts)

(0x1Ah)

CLRAIN

(Clear All Interrupts)

(0x1Ah)

CLINP

(Clear Interrupt Pin)

(0x1Ah)

R

Q7

Q6

Q5

Q4

SUPF

Interrupt Bit 7

(0x00h)

Supply Event

R

CK

D

Q

SUPEN

Interrupt Enable

(0x01h)

Figure 43. Interrupt Logic Functional Diagram

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7.4 Device Functional Modes

Four operating modes are defined as follows. Operating mode is controlled for each port through the Port n

Mode field in the Operating Mode Register. Operating mode codes appear in Operating Mode Register.

7.4.1 Off

Port n will not detect, classify or power on. When the operating mode of port n is set to Off the following takes

place.

•

Port voltage and current are monitored continuously. The results are reported in the Port n Voltage and Port n

Current Registers.

•

The CLSCn and the DETCn bits in the Detection Event register are cleared.

The Port n Status register is cleared.

The CLEn and the DETEn bits in the Detect/Class Enable register are cleared.

The DISFn and the ICUTn bits in the Fault Event Register are cleared.

The ILIMn and STRTn bits in the Start/ILIM Event register are cleared.

If the port was powered on when the operating mode is set to Off, the port is shut off, and the following

occurs.

–

The PGCn and the PECn bits in the Power Event Register are set.

The PGn and PEn bits in the Power Status register are cleared.

7.4.2 Manual

NOTE

In order to meet the IEEE 802.3at standard, PWONn bit should be set within 22 ms after

classification is completed if two-event classification is applied.

There is no automatic change of state. A single detection or classification event may be initiated by writing to the

appropriate bit of the Detect/Class Restart Register which is a pushbutton register. Furthermore, setting the

DETEn bit initiates one detect cycle for Port n; setting the CLEn bit initiates one classify cycle for Port n. The

number of classification events depend on the classification status of the first classification event and the setting

of the TECLENn field as shown in Table 7.

Table 7. Number of Classification Events in Manual Mode

CLASSIFICATION STATUS

OF FIRST CLASSIFICATION EVENT

TOTAL NUMBER

OF CLASSIFICATION EVENTS

VALUE OF TECLENn

Class 0, Class 1, Class 2 or Class 3

XX

X0

X1

One

Two

Class 4

In manual mode, writing to the pushbutton PWONn bit powers on Port n immediately.

NOTE

In Manual mode, the ICUTn and PoEPn fields are not set automatically. They must be set

by the host. Furthermore, there is no cool-down period in manual mode.

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7.4.3 Semi-Auto

No activity takes place on the port until the DETEn bit in the Detect/Class Enable register is set. When DETEn is

set, port n automatically performs detection. If a valid PD is detected and CLEn is set, the port initiates a

classification cycle. The classification cycle is single-event if a class 0, 1, 2 or 3 PD is recognized. If the first

classification event returns a class 4 signature, a second classification event is initiated depending on the setting

of the TECLENn field in the Two-Event Classification Register. The cycle of detect, then classification repeats

continuously.

Powering on the port requires writing to the pushbutton PWONn bit in the Power Enable Register. The port

powers on meeting the IEEE T_P(on)requirement to power on within 400 ms of the end of a valid detection.

Depending on the timing of the PWONn command, the controller may initiate a new detect and (if CLEn is set)

classification sequence before powering on the port if required to meet the T_P(on)requirement. If the final detect is

invalid, or if the final classification returns overcurrent or class mismatch, the port will not power on and the

STRTn bit is set in the Start/ILIM Event Register. For Turn-On sequencing see Push-Button Power On

Response.

NOTE

In Semi-Auto Mode, the ICUTn and PoEPn fields are not set automatically. They must be

set by the host.

Following a power-off command, disconnect or shutdown due to a Start, ICUT or ILIM fault, the port powers off.

Following a shutdown due to a start, ILIM or ICUT fault, the TPS23861 enters into a cool-down period. During the

cool-down period any port power on command using Power Enable Command is ignored. The length of the cool-

down period is set in the CLDN field of the Cool Down/Gate Drive Register. After the end of the cool-down period

the TPS23861 initiates a detect cycle and continues semi-automatic operation.

NOTE

TI recommends using this reference code to develop your software

http://www.ti.com/product/TPS23861/toolssoftware

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7.4.4 Auto

In Auto Mode the TPS23861 automatically cycles the port through detection, classification and power on. The

ICUT and PoEP fields are set automatically based on the classification status. If a class 0, 1, 2 or 3 PD is

recognized, ICUTn is set to 000 (374 mA) and the PoEPn bit is cleared. If a class 4 PD is recognized, ICUTn is

set to 110 (645 mA) and the PoEPn bit is set. Auto Mode and the AUTO bit are related, but are not identical.

When the Bit is set, all ports are placed in Auto Mode; additionally, several other registers are set. See

Independent Operation when the AUTO Bit is Set section.

Following a power-off command, disconnect or shutdown due to a Start, ICUT or ILIM fault, the port powers off.

Following port power off due to a power off command or disconnect, the TPS23861 continues automatic

operation starting with a detection cycle (if DETEn is set). If the shutdown is due to a Start, ICUT or ILIM fault,

the TPS23861 enters into a cool-down period. During the cool-down period any port power-on command using

Power Enable Command is ignored. The length of the cool-down period is set in the CLDN field of the Cool

Down/Gate Drive Register. After the end of the cool-down period the TPS23861 continues automatic operation

starting with a detection cycle, assuming DETEn is set.

The TPS23861 will not automatically apply power to a port, even if Operating Mode is set to Auto, under the

following circumstances.

•

The detect status is not Resistance Valid. This means that the DETEn bit must be set in order to power on in

Auto Mode.

NOTE

A write to the DETEn bit or CLEn bit will not stick if the port is in Off Mode.

•

If the classification status is overcurrent or, class mismatch.

The TPS23861 starts in Auto Mode after a power-on reset or when the RESET pin is de-asserted. When a valid

PD is connected as TPS23861 comes out of reset, then the ports will sequence through detection, classification,

and power on as shown in Figure 44. Staggered port power on prevents the sudden inrush of current from the

VPWR supply when multiple PDs are already connected.

Figure 44. Port Sequencing after RESET Pin De-Assertion

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7.4.5 Push-Button Power On Response

The port behavior of the TPS23861 to a commanded power on from the push-button register varies depending

upon both the detect and class enable registers.

Table 8. Summarized Response⁽¹⁾

OPERATING MODE

DETECT EN BIT

CLASS EN BIT

PORT BEHAVIOR

Port does not power on

Off

x

0

1

0

x

0

1

Manual

Port immediately powers on

Port does not power on

Port powers on after completion of next good detect

Port does not power on

Semi-Auto

Port powers on after completion of next good detect and

classification

1

x

1

x

Pushbutton power on ignored. Port follows Auto Mode

rules

Auto

(1) Response to a push-button power on.

Figure 45. Semi-Auto Sequenced Turn On

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7.4.6 TSTART Indicators of Detect and Class Failures

The start fault indicator reports additional problems in Semi-Auto to the host. This notifies the host that the PSE

encountered a problem and was unable to turn the port on. The interrupt pin activates when the TSTART mask is

enabled and one of these fault conditions occur. The conditions are described in Table 9.

(1)

Table 9. Detect and Class Failure Indicators

OPERATING MODE

FAULT CONDITION

None

Off

Manual

Overcurrent condition at the end of t_STARTtime period

Detect not valid

Semi-Auto

Auto

Class unknown

Class mismatch

Class overcurrent

Overcurrent condition at the end of t_STARTtime period

(1) Conditions that set start fault.

7.4.7 Device Power On Initialization

At device power on and after VDD and VPWR exceed V_UVDDRand V_{UVLOPW_R}respectively, TPS23861 initializes

for t_POR. During this time TPS23861 will not respond to I²C commands. Wait approximately 20 ms after t_POR

before sending I²C commands.

,

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7.5 Register Map – I²C-Addressable

(1)(2)

Table 10. I²C-Addressable Register Set Summary

REGISTER OR

COMMAND

NAME

CMD

CODE

I²C

R/W

DATA

BYTE

RST STATE

FIELD DESCRIPTION

00

01

Interrupt

RO

1

1000,0000

SUPF

STRTF IFAULT CLASC DETC

STRTE

DISF

PGC

PEC

Interrupt Enable

R/W

1AA0,0A00 SUPEN

IFEN

CLCEN DEEN

DISEN PGSEN PESEN

N

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

RO

CoR

RO

1

Power Good status change

PGC4 PGC3 PGC2 PGC1

Classification

CLSC4 CLSC3 CLSC2 CLSC1 DETC4 DETC3 DETC2 DETC1

Disconnect occurred ICUT fault occurred

DISF3 DISF2 ICUT3 ICUT2

ILIM fault occurred Start fault occurred

STRT4 STRT3 STRT2 STRT1

Power Enable status change

Power Event

Detection Event

Fault Event

0000,0000

0011,0000

PEC4

PEC3

PEC2

PEC1

Detection

CoR

RO

CoR

RO

DISF4

DISF1

ICUT4

ICUT1

Start/ILIM Event

Supply Event

CoR

RO

ILIM4

TSD

ILIM3

-

ILIM2

ILIM1

VPUV

VDUV

-

CoR

RO

Port 1 Status

Port 2 Status

Port 3 Status

Port 4 Status

Power Status

0000,0000

CLASS P1

DETECT P1

DETECT P2

DETECT P3

DETECT P4

RO

CLASS P2

CLASS P3

CLASS P4

RO

PG4

PG3

PG2

PG1

PE4

PE3

PE2

PE1

I²C Slave

Address

11

12

13

RO⁽³⁾

R/W

1

1010,0000

AUTO

SLA6

SLA5

SLA4

SLA3

SLA2

SLA1

SLA0

AAAA,AAA

A

Operating Mode

Port 4 Mode

Port 3 Mode

Port 2 Mode

Port 1 Mode

Disconnect

Enable

0000,AAAA

-

DCDE4 DCDE3 DCDE2 DCDE1

DETE4 DETE3 DETE2 DETE1

Detect/Class

ENABLE

AAAA,AAA

A

14

15

16

17

18

R/W

WO

1

CLE4

FSE4

CLE3

FSE3

CLE2

FSE2

CLE1

FSE1

Port PWR Priority

AAAA,0000

0000,0000

1000,0000

-

Timing

Configuration

TLIM

TSTART

TICUT

TDIS

M250

General Mask

INTEN

RCL4

-

MAINS

RCL1

-

R

Detect/Class

Restart

RCL3

RCL2

RDET4 RDET3 RDET2 RDET1

19

1A

Power Enable

Reset

WO

1

-

POFF4 POFF3 POFF2 POFF1 PWON4 PWON3 PWON2 POWN1

CLRAIN CLINP

-

RESAL RESP4 RESP3 RESP2 RESP1

Legacy Detect

Mode

20

R/W

1

0000,0000

LEGMOD4

LEGMOD3

TECLEN3

LEGMOD2

TECLEN2

LEGMOD1

TECLEN1

Two-Event

Classification

21

27

29

R/W

1

0A0A,0A0A

0000,0000

TECLEN4

Interrupt Timer

R

TMR 3-0

Disconnect

Threshold

DCTH4

DCTH3

DCTH2

DCTH1

2A

2B

2C

ICUT21 CONFIG

ICUT43 CONFIG

Temperature

R/W

RO

1

0000,0000

-

ICUT Port 2

ICUT Port 4

-

ICUT Port 1

ICUT Port 3

Temperature (bits 7 to 0)

(1) Bits labeled "R" are reserved. Undesirable behavior may result if the value of these bits are changed from the reset value.

(2) Bits labeled “A” assume the state of the bit programmed into register 0x11 after POR.

(3) This register is Read/Write during slave address programming when preceded by the unlock code.

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Register Map – I²C-Addressable (continued)

Table 10. I²C-Addressable Register Set Summary ⁽¹⁾⁽²⁾(continued)

REGISTER OR

COMMAND

NAME

CMD

CODE

I²C

R/W

DATA

BYTE

RST STATE

FIELD DESCRIPTION

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

RO

R/W

0000,0000

0000,----

Input voltage: LSByte

Input Voltage

Port 1 Current

Port 1 Voltage

Port 2 Current

Port 2 Voltage

Port 3 Current

Port 3 Voltage

Port 4 Current

2

-

Input voltage: MSByte (bits 13 to 8)

Port 1 current: LSByte

Port 1 current: MSByte (bits 13 to 8)

Port 1 voltage: LSByte

Port 1 voltage: MSByte (bits 13 to 8)

Port 2 current: LSByte

Port 2 current: MSByte (bits 13 to 8)

Port 2 voltage: LSByte

Port 2 voltage: MSByte (bits 13 to 8)

Port 3 current: LSByte

Port 3 current: MSByte (bits 13 to 8)

Port 3 voltage: LSByte

Port 3 voltage: MSByte (bits 13 to 8)

Port 4 current: LSByte

Port 4 current: MSByte (bits 13 to 8)

Port 4 voltage: LSByte

Port 4 Voltage

PoE Plus

Port 4 voltage: MSByte (bits 13 to 8)

1

POEP4 POEP3 POEP2 POEP1

-

Firmware

Revision

RRRR,RRR

R

41

RO

Firmware revision

42

43

I²C Watchdog

R/W

1

0001,0110

111,sr[4:0]

-

Watchdog disable

Silicon revision number

WDS

-

Device ID

Device ID number

Cool Down/Gate

Drive

45

R/W

1

2

0000,0000

CLDN

IGATE

-

60

61

62

63

64

65

66

67

68

RO

0000,0000

Port 1 resistance: LSByte

Port 1 Detect

Resistance

RS1

RS2

RS3

RS4

Port 1 resistance: MSByte (bits 13 to 8)

Port 2 resistance: LSByte

Port 2 Detect

Resistance

2

Port 2 resistance: MSByte (bits 13 to 8)

Port 3 resistance: LSByte

Port 3 Detect

Resistance

Port 3 resistance: MSByte (bits 13 to 8)

Port 4 resistance: LSByte

Port 4 Detect

Resistance

Port 4 resistance: MSByte (bits 13 to 8)

Port 1 voltage difference (bits 7 to 0)

Port 1 Detect

Voltage

Difference

2

Port 1 voltage difference: MSByte

(bits 11 to 8)

69

6A

6B

6C

6D

6E

6F

RO

0000,0000

VDS1

VDS2

VDS3

VDS4

Port 2 voltage difference (bits 7 to 0)

Port 2 Detect

Voltage

Difference

Port 2 voltage difference: MSByte

(bits 11 to 8)

Port 3 voltage difference (bits 7 to 0)

Port 3 Detect

Voltage

Difference

Port 3 voltage difference: MSByte

(bits 11 to 8)

Port 4 voltage difference (bits 7 to 0)

Port 4 Detect

Voltage

Difference

Port 4 voltage difference: MSByte

(bits 11 to 8)

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7.5.1 Interrupt Register

Command = 00h with 1 Data Byte, Read Only

BITS

D7

SUPF

1

D6

STRTF

0

D5

IFAULT

0

D4

CLASC

0

D3

DETC

0

D2

DISF

0

D1

PGC

0

D0

PEC

0

BIT NAME

RESET OR POR VALUE

Active high, each bit corresponds to a particular event that occurred.

Each bit can be individually reset by doing a read at the corresponding event register address, or by setting bit 7

of Reset Register.

Any active bit of the Interrupt register activates the INT output if its corresponding enable bit in the Interrupt

Enable Register is set, as well as the INTEN bit in the General Mask Register.

Bit Descriptions

SUPF: Indicates that a supply event fault occurred.

SUPF = TSD || VDUV || VPUV

1 = At least one supply event fault occurred.

0 = No such event occurred.

STRTF: Indicates that a start fault occurred on at least one port.

STRTF = STRT1 || STRT2 || STRT3 || STRT4

1 = Start fault occurred for at least one port.

0 = No start fault occurred.

IFAULT: Indicates that an ICUT or ILIM fault occurred on at least one port.

IFAULT = ICUT1 || ICUT2 || ICUT3 || ICUT4 || ILIM1 || ILIM2 || ILIM3 || ILIM4

1 = ICUT or ILIM Fault occurred for at least one port.

0 = No ICUT or ILIM Fault occurred.

CLASC: Indicates that at least one classification cycle occurred on at least one port.

CLASC = CLSC1 || CLSC2 || CLSC3 || CLSC4

1 = At least one classification cycle occurred for at least one port.

0 = No classification cycle occurred.

DETC: Indicates that at least one detection cycle occurred on at least one port.

DETC = DETC1 || DETC2 || DETC3 || DETC4

1 = At least one detection cycle occurred for at least one port.

0 = No detection cycle occurred.

DISF: Indicates that a disconnect event occurred on at least one port.

DISF = DISF1 || DISF2 || DISF3 || DISF4

1 = Disconnect event occurred for at least one port.

0 = No disconnect event occurred.

PGC: Indicates that a power good status change occurred on at least one port.

PGC = PGC1 || PGC2 || PGC3 || PGC4

1 = Power good status change occurred on at least one port.

0 = No power good status change occurred.

PEC: Indicates that a power enable status change occurred on at least one port.

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PEC = PEC1 || PEC2 || PEC3 || PEC4

1 = Power enable status change occurred on at least one port.

0 = No power enable status change occurred.

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7.5.2 Interrupt Enable Register

Command = 01h with 1 Data Byte, Read/Write

BITS

D7

SUPEN

1

D6

STRTEN

A

D5

IFEN

A

D4

CLCEN

0

D3

DEEN

0

D2

DISEN

A

D1

PGSEN

0

D0

PESEN

0

BIT NAME

RESET or POR VALUE

Each bit corresponds to a particular event or fault as defined in the Interrupt Register.

Writing a 1 into a bit allows the corresponding event to generate an interrupt on the INT pin.

Writing a 0 into a bit masks the corresponding event/fault from activating the INT pin.

NOTE

The bits of the Interrupt Register always change state according to events or faults,

regardless of the state of the Interrupt Enable Register. The INTEN bit of the General

Mask 1 Register must also be set in order to allow an event to activate the INT output.

Bit Descriptions

SUPEN: Supply event fault enable bit.

1 = Supply event fault activates the INT output.

0 = Supply event fault has no impact on INT output.

STRTEN: Start fault enable bit.

1 = Start fault activates the INT output.

0 = Start fault has no impact on INT output.

IFEN: IFAULT enable bit.

1 = ICUT or ILIM Fault occurrence activates the INT output.

0 = ICUT or ILIM Fault occurrence has no impact on INT output.

CLCEN: Classification cycle interrupt enable bit.

1 = Classification cycle occurrence activates the INT output.

0 = Classification cycle occurrence has no impact on INT output.

DEEN: Detection cycle interrupt enable bit.

1 = Detection cycle occurrence activates the INT output.

0 = Detection cycle occurrence has no impact on INT output.

DISEN: Disconnect event interrupt enable bit.

1 = Disconnect event occurrence activates the INT output.

0 = Disconnect event occurrence has no impact on INT output.

PGSEN: Power good status change interrupt enable bit.

1 = Power good status change activates the INT output.

0 = Power good status change has no impact on INT output.

PESEN: Power enable status change interrupt enable bit.

1 = Power enable status change activates the INT output.

0 = Power enable status change has no impact on INT output.

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7.5.3 Power Event Register

Command = 02h with 1 Data Byte, Read Only

Command = 03h with 1 Data Byte, Clear on Read

BITS

D7

PGC4

0

D6

PGC3

0

D5

PGC2

0

D4

PGC1

0

D3

PEC4

0

D2

PEC3

0

D1

PEC2

0

D0

PEC1

0

BIT NAME

RESET or POR VALUE

Active high, each bit corresponds to a particular event that occurred.

Each bit PGCn, PECn represents an individual port.

A read at each location (02h or 03h) returns the same register data with the exception that the Clear-on-Read

command clears all bits of the register.

If this register is causing the INT pin to be activated, this Clear-on-Read command releases the INT pin.

Any active bit will have an impact on the Interrupt Register as indicated in the Interrupt Register description.

Bit Descriptions

PGC4-PGC1: Indicates that a power good status change occurred.

1 = Power good status change occurred.

0 = No power good status change occurred.

PEC4-PEC1: Indicates that a power enable status change occurred.

1 = Power enable status change occurred.

0 = No power enable status change occurred.

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7.5.4 Detection Event Register

Command = 04h with 1 Data Byte, Read Only

Command = 05h with 1 Data Byte, Clear on Read

BITS

D7

CLSC4

0

D6

CLSC3

0

D5

CLSC2

0

D4

CLSC1

0

D3

DETC4

0

D2

DETC3

0

D1

DETC2

0

D0

DETC1

0

BIT NAME

RESET or POR VALUE

Active high, each bit corresponds to a particular event that occurred.

Each bit CLSCn, DETCn represents an individual port.

A read at each location (04h or 05h) returns the same register data with the exception that the Clear-on-Read

command clears all bits of the register. These bits are cleared when port n is turned off.

If this register is causing the INT pin to be activated, this Clear-on-Read command releases the INT pin.

Any active bit will have an impact on the Interrupt Register as indicated in the Interrupt Register description.

Bit Descriptions

CLSC4-CLSC1: Indicates that at least one classification cycle occurred.

1 = At least one classification cycle occurred.

0 = No classification cycle occurred.

DETC4-DETC1: Indicates that at least one detection cycle occurred.

1 = At least one detection cycle occurred.

0 = No detection cycle occurred.

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7.5.5 Fault Event Register

Command = 06h with 1 Data Byte, Read Only

Command = 07h with 1 Data Byte, Clear on Read

BITS

D7

DISF4

0

D6

DISF3

0

D5

DISF2

0

D4

DISF1

0

D3

ICUT4

0

D2

ICUT3

0

D1

ICUT2

0

D0

ICUT1

0

BIT NAME

RESET or POR VALUE

Active high, each bit corresponds to a particular event that occurred.

Each bit DISFn, ICUTn represents an individual port.

A read at each location (06h or 07h) returns the same register data with the exception that the Clear-on-Read

command clears all bits of the register. These bits are cleared by I²C power-off command (POFFn) or port-reset

command (RESPn).

If this register is causing the INT pin to be activated, this Clear-on-Read releases the INT pin.

Any active bit will have an impact on the Interrupt Register as indicated in the Interrupt Register description.

Bit Descriptions

DISF4-DISF1: Indicates that a disconnect event occurred.

1 = Disconnect event occurred.

0 = No disconnect event occurred.

ICUT4-ICUT1: Indicates that an ICUT Fault occurred.

1 = ICUT fault occurred.

0 = No ICUT fault occurred.

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7.5.6 Start/ILIM Event Register

Command = 08h with 1 Data Byte, Read Only

Command = 09h with 1 Data Byte, Clear on Read

BITS

D7

ILIM4

0

D6

ILIM3

0

D5

ILIM2

0

D4

ILIM1

0

D3

STRT4

0

D2

STRT3

0

D1

STRT2

0

D0

STRT1

0

BIT NAME

RESET or POR VALUE

Active high, each bit corresponds to a particular event that occurred.

Each bit ILIMn, STRTn represents an individual port.

A read at each location (08h or 09h) returns the same register data with the exception that the Clear-on-Read

command clears all bits of the register. These bits are cleared by I²C power-off command (POFFn) or port-reset

command (RESPn).

If this register is causing the INT pin to be activated, this Clear-on-Read command releases the INT pin.

Any active bit has an impact on the Interrupt Register as indicated in the Interrupt Register description.

Bit Descriptions

STRT4-STRT1: Indicates that a start fault occurred at port turn on. This may be caused by:

1. Overcurrent (foldback) condition at the end of t_START

.

2. Detect or classification fault following a pushbutton PWON command in Semi-Auto or Manual Mode.

3. Overcurrent or class mismatch on second finger in Semi-Auto or Manual Mode.

1 = Inrush fault or class/detect error occurred.

0 = No inrush fault or class/detect error occurred.

ILIM4-ILIM1: Indicates that an ILIM fault occurred, which means the port has limited its output current to ILIM or

the folded back ILIM for more than t_LIM

.

1 = ILIM fault occurred.

0 = No ILIM fault occurred.

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7.5.7 Supply Event Register

Command = 0Ah with 1 Data Byte, Read Only

Command = 0Bh with 1 Data Byte, Clear on Read

BITS

D7

TSD

0

D6

-

D5

VDUV

1

D4

VPUV

1

D3

-

D2

-

D1

-

D0

-

BIT NAME

POR VALUE

0

Active high, each bit corresponds to a particular event that occurred.

A read at each location (0Ah or 0Bh) returns the same register data with the exception that the Clear-on-Read

command clears all bits of the register.

If this register is causing the INT pin to be activated, this Clear-on-Read releases the INT pin.

Any active bit has an impact on Interrupt Register as indicated in the Interrupt Register description.

Bit Descriptions

TSD: Indicates that a thermal shutdown occurred. When there is thermal shutdown, all ports are powered off and

are put in Off Mode. The TPS23861 internal circuitry continues to operate however, including the A/D converters.

Note that at as soon as the internal temperature has decreased below the low threshold, the ports can be

powered on regardless of the status of the TSD bit.

1 = Thermal shutdown occurred.

0 = No thermal shutdown occurred.

VDUV: Indicates that a VDD UVLO occurred. VDUV is set following a power-on reset or if the voltage at the VDD

pin falls below V_{UVDD_F}

1 = VDD UVLO occurred.

0 = No VDD UVLO occurred.

VPUV: Indicates that a VPWR UVLO occurred. VPUV is set following a power-on reset or if the voltage at the

VPWR pin falls below V_{PUV_F}

.

1 = VPWR undervoltage occurred.

0 = No VPWR undervoltage occurred.

NOTE

If the RESET input is pulled low during normal operation, VPUV is set if VPWR is below

its UVLO threshold. There is no impact on VDUV since VDD is maintained.

When VPWR drops below V_{PUV_F}but not as low as V_{UVLOPW_F}all ports are powered off as if a push-button off

was executed. (Same as writing 1 to POFFn in Power Enable Register.) When VPWR undervoltage (below

V_{UVLOPW_F}) occurs, all ports are powered off, and there is a power-on reset.

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7.5.8 Port n Status Register

7.5.8.1 Port 1 Status Register

Command = 0Ch with 1 Data Byte, Read Only

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

CLASS P1

DETECT P1

RESET or POR VALUE

0

7.5.8.2 Port 2 Status Register

Command = 0Dh with 1 Data Byte, Read Only

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

CLASS P2

DETECT P2

RESET or POR VALUE

0

7.5.8.3 Port 3 Status Register

Command = 0Eh with 1 Data Byte, Read Only

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

CLASS P3

DETECT P3

RESET or POR VALUE

0

7.5.8.4 Port 4 Status Register

Command = 0Fh with 1 Data Byte, Read Only

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

CLASS P4

DETECT P4

RESET or POR VALUE

0

Represents the most recent classification and detection results for port n. These bits are cleared when port n is

turned off.

NOTE

In order to disable detection for any port with unknown, short circuit, open circuit, or

MOSFET fault detection status (0x0C-0x0F), clear the corresponding port DETEx bits in

0x14 instead of writing the port off command to 0x12, 0x19, or 0x1A.

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Bit Descriptions

CLASS Pn[3:0]: CLASS Pn is a 4-bit field for each port. The value of CLASS Pn is the most recent classification

result on port n. The selection is as following:

CLASS Pn

0000

CLASSIFICATION STATUS

Unknown

0001

Class 1

0010

Class 2

0011

Class 3

0100

Class 4

0101

Reserved – read as Class 0

Class 0

0110

0111

Overcurrent

1000

Class mismatch

A class mismatch can occur only during two-event classification. If the classification status for the first and

second event are different, and the second classification status is not Overcurrent, the Classification Status is set

to Class mismatch. If the status of the first classification event is “Overcurrent”, the classification status will be set

to “Overcurrent” in the CLASS Pn, and there will be no second classification event in any case. In Auto Mode,

port will not power on automatically, but still can be powered on through the Power Enable Register. The

appropriate STRTn bit is set in the Start/ILIM Event Register following these sorts of faults during classification.

DETECT Pn[3:0]: DETECT Pn is a 4-bit field for each port. The value of DETECT Pn is the most recent

detection result on port n.

NOTE

Bit states 1001 – 1100 apply to legacy detection only.

The selection is as following:

DETECT Pn

0000

DETECT STATUS

Unknown (POR value)

Short circuit (<500 Ω)

Reserved

0001

0010

0011

Resistance too low

Resistance valid

Resistance too high

Open circuit

0100

0101

0110

0111

Reserved

1000

MOSFET fault

1001

Legacy detect

1010

Capacitance measurement invalid: Detect measurement beyond

clamp voltage

1011

1100

Capacitance measurement invalid: Insufficient Δv measured

Capacitance measurement is valid, but outside the range of a legacy

device.

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7.5.9 Power Status Register

Command = 10h with 1 Data Byte, Read Only

BITS

D7

PG4

0

D6

PG3

0

D5

PG2

0

D4

PG1

0

D3

PE4

0

D2

PE3

0

D1

PE2

0

D0

PE1

0

BIT NAME

RESET or POR VALUE

Each bit represents the actual power status of a port.

Each bit PGn, PEn represents an individual port.

These bits are cleared when port n is turned off, including if the turn off is caused by a fault condition.

Bit Descriptions

PG4-PG1: Each bit, when at 1, indicates that the port is on and that the voltage at DRAINn has gone below

VPGT while the port is powered on. These bits are latched high once the turn on is complete and can only be

cleared when the port is turned off or following a reset or power-on reset.

1 = Power is good.

0 = Power is not good.

PE4-PE1: Each bit indicates the on/off state of the corresponding port.

1 = Port is on.

0 = Port is off.

7.5.10 I²C Slave Address Register

Command = 11h with 1 Data Byte, Read Only

BITS

D7

AUTO

1

D6

SLA6

0

D5

SLA5

1

D4

SLA4

0

D3

SLA3

0

D2

SLA2

0

D1

SLA1

0

D0

SLA0

0

BIT NAME

Initial EEPROM VALUE

Bit Descriptions

SLA6-SLA0: I²C device address, stored in EEPROM . This address can be changed by following the I²C slave

address programming protocol. For more details, see the I²C Slave Address and AUTO Bit Programming.

NOTE

The programmed device address should not be any of 0x00, 0x30, 0x0C.

AUTO: Defines whether the controller operates automatically in Auto Mode even in the absence of a host

controller. Automatic operation is described in Independent Operation when the AUTO Bit is Set section. The

state of this bit is monitored only immediately following a Power-on Reset or after the RESET input has been

activated. The impact of that bit state on registers after reset is reflected in Table 10 and is referred to “A”.

DESCRIPTION

BINARY DEVICE ADDRESS

6

0

5

1

4

1

0

3

0

1

2

0

1

0

BROADCAST ACCESS

ALERT RESPONSE

SLAVE NUMBER

0

1

0

SLA6

SLA5

SLA4

A3 pin

SLA2

SLA1

SLA0

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7.5.11 Operating Mode Register

Command = 12h with 1 Data Byte, R/W

BITS

D7

Port 4 Mode

AA

D6

D5

D4

D3

Port 2 Mode

AA

D2

D1

Port 1 Mode

AA

D0

BIT NAME

Port 3 Mode

RESET or POR VALUE

AA

Each field configures the operating mode per port.

NOTE

An Operating Mode write command to 0x12 with a transition from Off Mode to Auto Mode

or from Off Mode to Semi-Auto Mode requires an I²C bus processing delay of 1.2 ms

when followed by a Detect/Class Enable (0x14) write command. This delay applies from

the end of the Operating Mode command (stop pulse) to the end of the Detect/Class

Enable command (stop pulse).

Bit Descriptions

Port n Mode[1:0]: The selection is as following:

PORT n MODE [1:0]

OPERATING MODE

00

01

10

11

Off

Manual

Semi-Auto

Auto

In Off Mode, the port is off and there is neither detection nor classification. In Manual Mode, there is no

automatic state change. In Semi-Auto Mode, detection and classification are automated but not the port power

on, while in Auto Mode all three are automated. See Device Functional Modes for a detailed description of each

of the four operating modes.

NOTE

For any port with power enable set (PEx=1 in 0x10), ensure that port power good status in

0x10 is also set (PGx=1) prior to changing the mode to Off in the Operating Mode register

(0x12).

7.5.12 Disconnect Enable Register

Command = 13h with 1 Data Byte, R/W

BITS

D7

D6

D5

D4

D3

DCDE4

A

D2

DCDE3

A

D1

DCDE2

A

D0

DCDE1

A

BIT NAME

-

RESET or POR VALUE

-

Enables the disconnect detection mechanism for each port.

Bit Descriptions

DCDE4-DCDE1: DC disconnect enable for each port. Disconnect consists of measuring the port current at SENn

pin, starting the TDIS timer if this current is below a threshold and turning the port off if a time out occurs. Also,

the corresponding disconnect bit (DISFn) in the Fault Event Register is set accordingly. The TDIS timer is reset

each time the current goes higher than the disconnect threshold for 13% of T_MPDO. The counter does not

decrement below zero. Look at the Timing Configuration Register for more details on how to set T_MPDOby writing

to the TDIS field.

7.5.13 Detect/Class Enable Register

Command = 14h with 1 Data Byte, R/W

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BITS

D7

CLE4

A

D6

CLE3

A

D5

CLE2

A

D4

CLE1

A

D3

DETE4

A

D2

DETE3

A

D1

DETE2

A

D0

DETE1

A

BIT NAME

RESET or POR VALUE

Detection and classification enable for each port.

When in Manual mode, setting a bit means that only one cycle (detection or classification) is performed for the

corresponding port. The bit is automatically cleared when the cycle has been completed.

NOTE

The same result can be obtained by writing to the Detect/Class Restart Register.

NOTE

Write commands to either 0x12, 0x18, 0x19, or 0x1A require an I²C bus processing delay

of 1.2 ms when followed by a Detect/Class Enable (0x14) write command. This delay

applies from the end of the 0x12, 0x18, 0x19, or 0x1A command (stop pulse) to the end of

the Detect/Class Enable command (stop pulse).

It is also cleared if a port turn off (Power Enable Register) is issued.

In Semi-Auto Mode, while the port is not powered up, detection and classification are performed continuously, as

long as the CLEn and DETEn bits are kept set. First, detection is performed. If a Resistance valid status is

returned, classification follows. After, the detect-class sequence repeats. If a valid status is not returned by the

detection event, classification is skipped, and detection is repeated.

In Auto Mode, if the port is not powered up and the DETEn and CLEn bits are set, classification follows a valid

detect, and power-on follows classification unless classification returns Unknown, Overcurrent or Class Mismatch

Status.

During the cool-down cycle following a Start, ICUT or ILIM, any Detect/Class Enable command for that port are

delayed until the end of the cool-down period.

NOTE

At the end of the cool-down period, one or more detection/class cycles are automatically

restarted as described previously if the detect enable bit is set.

Bit Descriptions

CLE4-CLE1: Classification enable bits.

1 = Enabled.

0 = Disabled.

DETE4-DETE1: Detection enable bits.

1 = Enabled.

0 = Disabled.

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7.5.14 Port Power Priority Register

Command = 15h with 1 Data Byte, R/W

BITS

D7

FSE4

A

D6

FSE3

A

D5

FSE2

A

D4

FSE1

A

D3

R15[3]

0

D2

R15[2]

0

D1

R15[1]

0

D0

R15[0]

0

BIT NAME

RESET or POR VALUE

Bit Descriptions

FSE4-FSE1: Port power priority bits to support Fast Shutdown; one bit per port. It is used to specify which port or

ports is/are shut down in response to an external assertion of the SHTDWN pin fast shutdown signal. The turn-

off procedure is similar to a port reset using Reset command (Reset register). If one of these bits is set while the

SHTDWN pin is low, that port is shut down as well.

1 = When the SHTDWN is forced to a low level, the corresponding port is powered off.

0 = SHTDWN signal has no impact on the port.

Reserved: Bits R15[3:0] are reserved for future use. Undesirable behavior may result if the value of these bits

are changed from their reset value.

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7.5.15 Timing Configuration Register

Command = 16h with 1 Data Byte, R/W

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

TLIM

TSTART

TICUT

TDIS

RESET or POR VALUE

0

These bits define the timing configuration for all four ports.

NOTE

The PGn and PEn bits in the Power Status Register are cleared when there is a Start,

ICUT or ILIM condition.

Bit Descriptions

TLIM[1:0]: ILIM fault timing, which is the foldback current limit time duration before port turn off. This timer is

loaded with its maximum count corresponding to t_LIMafter expiration of the t_STARTperiod; the timer counts down

when the port is limiting its output current to ILIM. If the ILIM timer counts down to zero, the port is powered off.

After the port is powered off the cool-down period commences. The cool-down period is selected by the CLDN

field in the Cool Down/Gate Drive register. During the cool-down period the port will not engage in detection,

classification, or powered-up operation. When the port is powered up and while the port current is below ILIM,

the same counter increments at a rate 1/16^thof the count-down rate (independent of the setting in the CLDN

field). The counter does not increment past the maximum count corresponding to the programmed TLIM value.

NOTE

At the end of the cool-down period, when in Semi-Auto or Auto Mode, a detection cycle is

automatically restarted if the detect enable bit is set.

NOTE

If ILIM and ICUT are set to same value, it is a race condition between ILIM and ICUT in

TPS23861 and it depends on the firmware as to the winner.

When a POEPn bit in the PoE Plus Register is cleared, the t_LIMused for the associated port is always the

nominal value (~60 ms). If the POEPn bit is set, then t_LIMfor associated port is programmable with the following

selection:

TLIM[1:0]

NOMINAL t_LIM(ms) WHEN PoEPn BIT IS SET

00

01

10

11

60

30

15

10

TSTART[1:0]: This 2-bit field sets the length of the t_STARTperiod, which is the maximum allowed overcurrent time

during inrush. If at the end of the t_STARTperiod the current is still limited to I_INRUSH, the port is powered off. This is

followed by a cool-down period, set with the CLDN field in the Cool Down/Gate Drive Register, during which the

port cannot be turned on if in Semi-Auto or Auto Mode.

NOTE

At the end of cool-down cycle, when in Semi-Auto or Auto Mode, a detection cycle is

automatically restarted if the class and detect enable bits are set.

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The selection is as following:

TSTART [1:0]

NOMINAL t_START(ms)

00

01

10

11

60

30

120

Reserved

TICUT[1:0]: ICUT fault timing, which is the overcurrent time duration before port turn off (t_OVLD).

This timer is loaded with its maximum count corresponding to t_OVLDafter expiration of the t_STARTperiod; the timer

counts down when the port current exceeds ICUT. If the ICUT timer counts down to zero, the port is powered off.

After the port is powered off the cool-down period commences. The cool-down period is set with the CLDN field

in the Cool Down/Gate Drive Register. During the cool-down period the port will not engage in detection,

classification, or powered-up operation. When the port is powered up and while the port current is below ICUT,

the same counter increments at a rate 1/16^thof the count-down rate (independent of the setting in the CLDN

field). The counter does not increment past the maximum count corresponding to the programmed TICUT value.

NOTE

At the end of cool-down cycle, when in Semi-Auto or Auto Mode, a detection cycle is

automatically restarted if the detect enable bit is set.

NOTE

If ILIM and ICUT are set to same value, it is a race condition between ILIM and ICUT in

TPS23861 and it depends on the firmware as to the winner.

The selection is as following:

TICUT[1:0]

NOMINAL t_OVLD(ms)

00

01

10

11

60

30

120

240

TDIS[1:0]: Disconnect delay, which is the time to turn off a port once there is a disconnect condition.

After port power on and the completion of the t_STARTperiod the TDIS counter is started when the port current

drops below the disconnect threshold established in the DCTHn fields, and the counter is reset each time the

current goes continuously higher than the disconnect threshold for 13% of t_MPDO. The counter does not

decrement below zero. The selection is as following:

TDIS[1:0]

NOMINAL t_MPDO(ms)

0

1

0

1

0

1

360

90

180

720

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7.5.16 General Mask 1 Register

Command = 17h with 1 Data Byte, Read/Write

BITS

D7

INTEN

1

D6

D5

D4

MAINS

0

D3

D2

D1

D0

M250

0

BIT NAME

R17[3]

R17[2]

R17[1]

RESET or POR VALUE

0

Reserved

Bit Descriptions

INTEN: INT pin enable bit. Writing a 1 permits any bit of the Interrupt Register to activate the INT output.

NOTE

Activating INTEN has no impact on the Event Registers.

1 = Any enabled bit of the Interrupt register can activate the INT output.

0 = INT output cannot be activated.

Reserved: Bits R17[3], R17[2] and R17[1] are reserved for future use. Undesirable behavior may result if the

value of these bits are changed from the reset value.

MAINS: Detection Voltage Measurement Duration Bit. Set or clear this bit to correspond to the mains frequency

local to where the TPS23861 is being used in a system. The A/D converter will perform 16 conversions during

the detection cycle. The results of these 16 conversions are averaged resulting in a total acquisition time equal to

one cycle of the mains frequency. This technique greatly reduces mains-induced interference in the detection

cycle measurement.

1 = Convert port voltage during detection at a rate of 960 A/D conversions per second. This corresponds to 16

conversions during one period of 60-Hz mains frequency.

0 = Convert port voltage during detection at a rate of 800 A/D conversions per second. This corresponds to 16

conversions during one period of 50-Hz mains frequency.

M250: Current-sense-resistor-selection bit. Setting this bit directs the TPS23861 to use ICUT and classification

look-up tables corresponding to a 250-mΩ current-sense resistor.

1 = Set this bit if a 250-mΩ current-sense resistor is used as a current-sense resistor.

0 = Clear this bit if a 255-mΩ current-sense resistor is used as a current-sense resistor.

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7.5.17 Detect/Class Restart Register

Command = 18h with 1 Data Byte, Write Only

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

RCL4

RCL3

RCL2

RCL1

RDET4

RDET3

RDET2

RDET1

Push button register.

Each bit corresponds to a particular cycle (detect or class restart) per port.

Each cycle can be individually triggered by writing a “1” at that bit location, while writing a “0” does not change

anything for that event.

In Manual Mode, a single cycle (detect or class restart) is initiated. In Semi-Auto and Auto Mode, the

corresponding bit in the Detect/Class Enable register is set, and the TPS23861 operates as prescribed in Device

Functional Modes section.

During the cool-down cycle following a Start, ICUT or ILIM, any Detect/Class Restart Command for that port is

accepted, but the corresponding action is delayed until end of cool-down period.

NOTE

A Detect/Class Restart write command to 0x18 requires an I²C bus processing delay of

1.2 ms when followed by a Detect/Class Enable (0x14) write command. This delay applies

from the end of the Detect/Class Restart command (stop pulse) to the end of the

Detect/Class Enable command (stop pulse).

Bit Descriptions

RCL4-RCL1: Restart classification bits.

RDET4-RDET1: Restart detection bits.

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7.5.18 Power Enable Register

Command = 19h with 1 Data Byte, Write Only

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

POFF4

POFF3

POFF2

POFF1

PWON4

PWON3

PWON2

PWON1

Push button register. Setting a bit in this register directs the TPS23861 to turn a port on or off.

Used to force a port(s) power on or power off in any mode except Off Mode or during a port shutdown condition

via the SHTDWN pin.

NOTE

A power off write command to 0x19 requires an I²C bus processing delay of 1.2 ms when

followed by a Detect/Class Enable (0x14) write command. This delay applies from the end

of the power off command (stop pulse) to the end of the Detect/Class Enable command

(stop pulse).

NOTE

In Semi-Auto or in Auto Mode, as long as the port is kept off, detection and classification

are performed continuously if the corresponding class and detect enable bits are set.

The details of a power-on operation depends on the operating mode. See Device Functional Modes section for

details.

Writing a “1” at POFFn location powers off the associated port.

NOTE

Writing a “1” at POFFn and PWONn of same port during the same write operation powers

off the port.

During the cool-down cycle following a Start, ICUT or ILIM, when in Semi-Auto or Auto Mode, any port turn on

using Power Enable Command is ignored. The port can be turned on at the end of the cool-down cycle. When in

Manual Mode, the port powers on immediately in response to a power on command even when in cool-down.

Bit Descriptions

POFF4-POFF1: Port power off bits. When POFFn is written, the following takes place:

•

The corresponding Port n Voltage Registers are cleared.

The corresponding Port n Detect Resistance Register are cleared.

The CLSCn and the DETCn bits in the Detection Event Register are cleared.

The corresponding Port n Status Register are cleared.

The CLEn and the DETEn bits in the Detect/Class Enable Register are cleared.

The DISFn and ICUTn bits in the Fault Event Register are cleared.

The ILIMn and the STRTN bits in the Start/ILIM Event Register are cleared.

If the port was powered on when POFFn is set, the port is powered off, and the following occurs.

–

The PGCn and the PECn bits in the Power Event Register are set.

The PGn and PEn bits in the Power Status Register are cleared.

PWON4-PWON1: Port power on bits.

NOTE

For any port with power enable set (PEx=1 in 0x10), ensure that port power good status in

0x10 is also set (PGx=1) prior to writing a power off command to the Power Enable

register (0x19).

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7.5.19 Reset Register

Command = 1Ah with 1 Data Byte, Write Only

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

CLRAIN

CLINP

RESAL

RESP4

RESP3

RESP2

RESP1

Push button register.

Writing a “1” at a bit location triggers an event while a “0” has no impact.

NOTE

A reset port write command to 0x1A requires an I²C bus processing delay of 1.2 ms when

followed by a Detect/Class Enable (0x14) write command. This delay applies from the end

of the reset port command (stop pulse) to the end of the Detect/Class Enable command

(stop pulse).

Bit Descriptions

CLRAIN: Clear all interrupts bit. Writing a “1” to CLRAIN clears all event registers and all bits in the Interrupt

Register. It also releases the INT pin.

CLINP: When a “1” is written to this register, the TPS23861 releases the INT pin without any impact on either the

event registers nor on the Interrupt Register.

RESAL: Reset register bits when a “1” is written to this location. Writing a “1” to this location results in a state

equivalent to a power-up reset.

NOTE

For any port with power enable set (PEx=1 in 0x10), ensure that port power good status in

0x10 is also set (PGx=1) prior to writing a reset port command to the Reset register

(0x1A).

NOTE

The VDUV and VPUV bits (Supply Event Register) follow the state of VDD and VPWR

supply rails.

RESP4-RESP1: Reset port bits. Used to force an immediate port(s) turn off in any mode, by writing a “1” at the

corresponding RESPn bit location(s). When port n is reset, the following takes place.

•

The corresponding Port n Voltage Register are cleared.

The CLCSn and the DETCn bits in the Detection Event Register are cleared.

The corresponding Port n Status Register are cleared.

The CLEn and the DETEn bits in the Detect/Class Enable Register are cleared.

The DISFn and ICUTn bits in the Fault Event Register are cleared.

The ILIMn and STRTn bits in the Start/ILIM Event Register are cleared.

If in cool-down, the lockout functionality of the cool-down timer is cancelled.

If the port was powered on when RESPn is set, the port is shut off, and the following occurs.

–

The PGCn and the PECn bits in the Power Event Register are set.

The PGn and PEn bits in the Power Status Register are cleared.

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7.5.20 Legacy Detect Mode Register

Command = 20h with 1 Data Byte, Read/Write

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

LEGMOD4

LEGMOD3

LEGMOD2

LEGMOD1

RESET or POR VALUE

00

Legacy-detect operation is described in Legacy Device Detection. The TPS23861 can perform a legacy-detect

operation only or a standard detection followed by a legacy-detect operation when directed by the RDETn push-

button command in the Detect/Class Restart Register, or in Semi-Auto or Auto Mode when the DETEn bit in the

Detect/Class Enable Register is set. Note that in Semi-Auto or in Auto Mode, the port will not automatically

power up if a legacy device is detected. In these cases, the port must be powered on by the host.

Bit Descriptions

LEGMODn[1:0]: Legacy-detection-mode field. This field defines the Legacy-Detect Mode of Port n as follows.

LEGMODn[1:0]

LEGACY DETECT MODE

00

Legacy detect disabled; if DETEn bit in Detect/Class Enable Register is set, a standard

(resistance only) detection sequence will be performed.

01

10

11

Legacy detect sequence only; if DETEn bit in Detect/Class Enable Register is set, a legacy

detect sequence will be performed

Standard + legacy detect sequence; if DETEn bit in Detect/Class Enable Register is set, a

standard detection followed by legacy detect sequence will be performed

Reserved

7.5.21 Two-Event Classification Register

Command = 21h with 1 Data Byte, Read/Write

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

TECLEN4

TECLEN3

TECLEN2

TECLEN1

RESET or POR VALUE

0A

The Two-Event Classification Register controls whether a second physical-layer classification event occurs after

a class 4 PD is classified under the following circumstances:

•

In Manual Mode, when CLEn is set or a pushbutton RCLn bit is written.

In Semi-Auto Mode, when CLEn is set or a PWONn pushbutton command is written.

In Auto Mode

Bit Descriptions

TECLENn[1:0]: The TECLENn field sets the conditions for PSE-initiated two-event physical layer classification

as follows. The details of these conditions depend on the operating mode as outlined in the preceding paragraph

and the Device Functional Modes section.

Table 11. TECLENn Field Encoding

TECLENn[1:0]

CONDITIONS FOR TWO-EVENT PHYSICAL-LAYER CLASSIFICATION

Two-event physical-layer classification is disabled

00

01

10

11

A second classification event is initiated if a class 4 classification event occurs

Reserved

A second classification event is initiated if a class 4 classification event occurs

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7.5.22 Interrupt Timer Register

Command = 27h with 1 Data Byte, Read/Write

BITS

D7

R27[7]

0

D6

R27[6]

0

D5

R27[5]

0

D4

R27[4]

0

D3

TMR[3]

0

D2

TMR[2]

0

D1

TMR[1]

0

D0

TMR[0]

0

BIT NAME

RESET OR

POR VALUE

Bit Descriptions

TMR[3:0]: Non-critical interrupts may be deferred using an internal timer. Once loaded with a non-zero value, the

internal timer counts continuously with period calculated as follows:

t = Nì t_STEP

where

•

t = Timer period, ms

N = 4-bit value in TMR[3:0] field

t_STEP= 10 ms

(1)

Non-critical interrupts generated within the TPS23861 will be passed to the interrupt-handling hardware

whenever the timer counts down to 0. (The timer then reloads and continues to count.)

NOTE

‘interrupt-handling hardware’ includes all interrupt-enabling functionality as well.

Critical and non-critical interrupts are defined in Table 6. When the TMR[3:0] field is read, the contents will be the

contents last written by firmware.

When TMR[3:0] = 0 all interrupts will be handled as they are generated. In other words, this function is disabled

when TMR[3:0] = 0000.

Reserved: Bits R27[7:4] are reserved for future use. Undesirable behavior may result if the value of these bits

are changed from the reset value.

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7.5.23 Disconnect Threshold Register

Command = 29h with 1 Data Byte, Read/Write

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

DCTH4

DCTH3

DCTH2

DCTH1

RESET or POR VALUE

00

Disconnect current thresholds may be programmed individually for each port.

7.5.23.1 Bits Description

DCTHn[1:0]: A 2-bit field used to set the current threshold for disconnect. If the port is powered on and the

current goes below the disconnect threshold set by DCTHn, the TDIS counter is started. If the TDIS timer times

out the port is powered down.

DCTHn FIELD

DISCONNECT THRESHOLD, mA

00

01

10

11

7.5

15

30

50

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7.5.24 ICUTnm CONFIG Register

7.5.24.1 ICUT21 CONFIG Register

Command = 2Ah with 1 Data Byte, Read/Write

BITS

D7

D6

D5

ICUT Port 2

0

D4

D3

D2

D1

ICUT Port 1

0

D0

BIT NAME

RESET or POR VALUE

0

7.5.24.2 ICUT43 CONFIG Register

Command = 2Bh with 1 Data Byte, Read/Write

BITS

D7

D6

D5

ICUT Port 4

0

D4

D3

D2

D1

ICUT Port 3

0

D0

BIT NAME

RESET or POR VALUE

0

7.5.24.3 Bits Description

ICUT Port n[2:0]: is a 3-bit field used to set the ICUT current threshold. If the current threshold set by ICUT Port

n is exceeded, the TICUT timer begins to count. When the terminal count (0) is reached, an ICUT fault is

declared, and the port is shut down.

NOTE

The current values in the following table are nominal values.

ICUT PORT n FIELD

I_CUT(mA)

374

PoEPn⁽¹⁾

000

001

010

011

100

101

110

111

0

1

110

204

374

754

592

645

920

(1) PoEPn bit should be set according to ICUT value for host to ensure the ICUT and ILIM relationship.

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7.5.25 Temperature Register

Command = 2Ch with 1 Data Byte, Read Only

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Temp[7:0]

RESET or POR VALUE

0

Die temperature register.

Bit Descriptions

Temp[7:0]: 8-bit data conversion result of temperature. The equation defining the temperature measured is:

T = -20 + Nì T_STEP

where

•

T = temperature, °C

TSTEP = LSB value

N = 8-bit value in Temp[7:0]

(2)

MODE

FULL SCALE VALUE

LSB VALUE

Any

150°C (typical)

0.7°C

NOTE

Temperature sensor performance is only typical, not production tested and not ensured.

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7.5.26 Input Voltage Register

Command = 2Eh with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 2Eh

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Input Voltage[7:0]

RESET or POR VALUE

0

MSB: 2Fh

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Input Voltage[13:8]

RESET or POR VALUE

0

Bit Descriptions

Data conversion result. The I²C data transmission is a 2-byte transfer.

Input Voltage[13:0]: 14-bit Data conversion result of input voltage. The update rate is approximately 1 per

second.

The equation defining the voltage measured is:

V = Nì V_STEP

where

•

V = input voltage, V

N = 14 bit value in input voltage register

V_STEP= LSB value

(3)

MODE

FULL SCALE VALUE

LSB VALUE

Any

60 V

3.662 mV

NOTE

The measurement is made between VPWR and AGND.

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7.5.27 Port n Current Register

7.5.27.1 Port 1 Current Register

Command = 30h with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 30h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 1 Current[7:0]

RESET or POR VALUE

0

MSB: 31h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 1 Current[13:8]

RESET or POR VALUE

0

7.5.27.2 Port 2 Current Register

Command = 34h with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 34h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 2 Current[7:0]

RESET or POR VALUE

0

MSB: 35h

BITS

D7

-

D6

-

D5

D4

D3

D2

D1

D0

BIT NAME

Port 2 Current[13:8]

RESET or POR VALUE

0

7.5.27.3 Port 3 Current Register

Command = 38h with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 38h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 3 Current[7:0]

RESET or POR VALUE

0

MSB: 39h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 3 Current[13:8]

RESET or POR VALUE

0

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7.5.27.4 Port 4 Current Register

Command = 3Ch with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 3Ch

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 4 Current[7:0]

RESET or POR VALUE

0

MSB: 3Dh

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 4 Current[13:8]

RESET or POR VALUE

0

Port current is monitored continuously when:

•

The port is powered on.

The port is in Off Mode. Data conversion result.

The I²C data transmission is a 2-byte transfer.

NOTE

The conversion is done using a TI-proprietary multi-slope integrating converter.

Bit Descriptions

Port n Current[13:0]: 14-bit data conversion result of current for Port n. The result depends on whether the

current-sense resistor is 250 mΩ or 255 mΩ.

The equation defining the current measured is:

I = NìI_STEP

where

•

I = Port n Current, A

N = 14-bit value in Port n Current Register

I_STEP= LSB value

(4)

R_S= 255 mΩ

R_SENSE= 250 mΩ

FULL SCALE

LSB VALUE

FULL SCALE

LSB VALUE

1 A

61.039 µA

1.02 A

62.260 µA

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7.5.28 Port n Voltage Register

7.5.28.1 Port 1 Voltage Register

Command = 32h with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 32h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 1 Voltage[7:0]

RESET or POR VALUE

0

MSB: 33h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 1 Voltage[13:8]

RESET or POR VALUE

0

7.5.28.2 Port 2 Voltage Register

Command = 36h with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 36h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 2 Voltage[7:0]

RESET or POR VALUE

0

MSB: 37h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 2 Voltage[13:8]

RESET or POR VALUE

0

7.5.28.3 Port 3 Voltage Register

Command = 3Ah with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 3Ah

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 3 Voltage[7:0]

RESET or POR VALUE

0

MSB: 3Bh

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 3 Voltage[13:8]

RESET or POR VALUE

0

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7.5.28.4 Port 4 Voltage Register

Command = 3Eh with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 3Eh

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 4 Voltage[7:0]

RESET or POR VALUE

0

MSB: 3Fh

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 4 Voltage[13:8]

RESET or POR VALUE

0

Port voltage is monitored continuously when

•

The port is powered on.

The port is in Off Mode.

Data conversion result. The I²C data transmission is a 2-byte transfer.

Bit Descriptions

Port n Voltage[13:0]: 14-bit Data conversion result of voltage for port n. The equation defining the voltage

measured is:

V = Nì V_STEP

where

•

V = Port n Voltage, V

N = 14-bit value in Port n Voltage Register

V_STEP= LSB Value

(5)

FULL SCALE VALUE

LSB VALUE

60 V

3.662 mV

NOTE

The port voltage measurement is made between VPWR and DRAINn.

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7.5.29 PoE Plus Register

Command = 40h with 1 Data Byte, R/W

BITS

D7

PoEP4

0

D6

PoEP3

0

D5

PoEP2

0

D4

PoEP1

0

D3

D2

D1

D0

BIT NAME

RESET or POR VALUE

The POEPn bit can be set or cleared by the host processor over the I²C interface. Additionally, the bit is set

when in Auto Mode before the port is powered on following the recognition of a valid Class 4 PD. Likewise, the

POEPn bit is cleared before the port is powered on when in Auto Mode and a Class 0, 1, 2 or 3 PD is

recognized.

One POEPn bit supports each port. When the POEPn bit for a port is set:

•

2 x I_LIMfoldback curve is applied to a port when the port is powered on. See Figure 58.

The short-circuit protection threshold (I_LIM) for the FET is increased by a factor of 2.5 with respect to the

POEPn-bit-cleared value.

•

The t_LIMvalue is selectable via the TLIM timer field in the Timing Configuration Register.

Likewise, when the POEPn bit for a port is cleared:

•

1 x I_LIMfoldback curve is applied to a port when the port is powered on. See Figure 58.

The short-circuit protection threshold (I_LIM) for the FET is reduced to a value of 40% of the POEPn-bit-set

value.

•

The t_LIMvalue is set to 60 ms.

The inrush-foldback behavior is not affected by the setting of the POEPn bit. See Figure 57.

Bit Descriptions

PoEPn: PoE+ bits. Setting this bit causes the 2 x I_LIMfoldback curve to be applied to Port n.

1 = Use 2 x I_LIMfoldback curve on Port n.

0 = Use 1 x I_LIMfoldback curve on Port n.

NOTE

PoEPn bit should be set according to ICUT value for host to ensure the ICUT and ILIM

relationship. See Table 15

7.5.30 Firmware Revision Register

Command = 41h with 1 Data Byte, Read Only

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

FRV

RRR

RESET or POR VALUE

R

Bit Descriptions

FRV[2:0]: Firmware revision number.

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7.5.31 I²C Watchdog Register

Command = 42h with 1 Data Byte, R/W

BITS

D7

D6

D5

D4

D3

D2

D1

D0

WDS

0

BIT NAME

IWD[3:0]

RESET or POR VALUE

1

0

1

The I²C watchdog timer monitors the I²C clock line in order to prevent hung software situations that could leave

ports in a hazardous state. The timer can be reset by either edge on SCL input. If the watchdog timer times out,

the WDS bit is set. Depending on the value of IWD, all ports may be powered down. The nominal watchdog time-

out period is 2 seconds.

When the ports are powered down due to a watchdog event, the corresponding bits are cleared in the Detection

Event Register (CLSCn, DETn), Fault Event register (DISFn, ICUTn), Start/ILIM Event Register (STRTn), Port n

Status Registers (Class Pn, Detect Pn) and Detect/Class Enable Register (CLEn, DETEn).

The corresponding PEn and PGn bits of the Power Status Register are also updated accordingly.

Bit Descriptions

IWD3 - IWD0: I²C Watchdog disable. When equal to 1011, the watchdog is masked. Otherwise, it is umasked

and the watchdog is operational.

WDS: I²C Watchdog timer status, valid even if the watchdog is masked. When set, it means that the watchdog

timer has expired without any activity on I²C clock line. Writing 0 at WDS location clears it.

NOTE

when the watchdog timer expires and if the watchdog is unmasked, all ports are also

turned off.

When the ports are turned OFF due to I²C watchdog, the corresponding bits in Detection Event Register

(CLSCn, DETCn), Fault Event Register (DISFn, ICUTn), Start Event Register (STRTn), Port n Status register

(Class Pn, Detect Pn), Detect/Class Enable Register (CLEn, DETEn) and Power-On Fault Register (PFn) are

also cleared. The corresponding PGCn and PECn bits of Power Event register is set if there is a change. The

corresponding PEn and PGn bits of Power Status Register are updated accordingly.

7.5.32 Device ID Register

Command = 43h with 1 Data Byte, R/W

BITS

D7

D6

DID

1

D5

D4

D3

D2

SR

D1

D0

BIT NAME

RESET or POR VALUE

1

SR[4:0]

Bit Descriptions

DID: Device ID number (111).

SR: Silicon Revision number.

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7.5.33 Cool Down/Gate Drive Register

Command = 45h with 1 Data Byte, R/W

BITS

D7

D6

D5

IGATE

0

D4

D3

D2

D1

D0

BIT NAME

CLDN

RESET or POR VALUE

0

These bits are applicable to all four ports.

Bit Descriptions

CLDN: Fault Cool-Down Timer Programming Field. Following a Start, ICUT or ILIM, a port shuts down, and the

cool-down timer counts down. Until the timer counts down to 0, the port will not be allowed to be powered on if

the port is in Semi-Auto or Auto Mode. If in Manual Mode, the port can be powered on immediately with a push-

button command by writing to PWONn in the Power Enable Register. The cool-down timer is cancelled by power-

on reset, device reset or port reset (see Reset Register).

The field programming is:

CLDN[1:0]

NOMINAL COOL-DOWN TIMER PERIOD

0X

10

11

1 s

2 s

4 s

IGATE: GATE Pull-Up Current Bit. IGATE sets the gate pull-up current.

IGATE

NOMINAL GATE PULLUP CURRENT (µA)

0

1

50

25

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7.5.34 Port n Detect Resistance Register

7.5.34.1 Port 1 Detect Resistance Register

Command = 60h with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 60h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 1 Resistance[7:0]

RESET or POR VALUE

0

MSB: 61h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

RS1[1:0]

Port 1 Resistance[13:8]

RESET or POR VALUE

0

7.5.34.1.1 Port 2 Detect Resistance Register

Command = 62h with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 62h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 2 Resistance[7:0]

RESET or POR VALUE

0

MSB: 63h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

RS2[1:0]

Port 2 Resistance[13:8]

RESET or POR VALUE

0

7.5.34.1.2 Port 3 Detect Resistance Register

Command = 64h with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 64h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 3 Resistance[7:0]

RESET or POR VALUE

0

MSB: 65h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

RS3[1:0]

Port 3 Resistance[13:8]

RESET or POR VALUE

0

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7.5.34.1.3 Port 4 Detect Resistance Register

Command = 66h with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 66h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 4 Resistance[7:0]

RESET or POR VALUE

0

MSB: 67h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

RS4[1:0]

Port 4 Resistance[13:8]

RESET or POR VALUE

0

Bit Descriptions

Most recent 2 point detection resistance measurement. The resistance value shown is usable only if RSn[1:0] are

at 00 or 01. The I²C data transmission is a 2 byte transfer.

Port n Resistance[13:0]: 14-bit data conversion result of detection resistance for port n. The equation defining

the resistance measured is:

R = NìR_STEP

where

•

R = Detection resistance, Ω

N = 14-bit value in Port n Resistance Register

R_STEP= LSB value

(6)

USEABLE RESISTANCE RANGE

LSB VALUE

500 Ω to 55 kΩ

11.0966 Ω

RSn[1:0]: Most recent detection result status on port n. If the state is 00, the 14-bit resistance value is calculated

with a bit weight of 11.0966 Ω/bit. If the state is 01, two additional detection fingers have been performed at

higher detection currents (270 µA and 540 µA) in order to better measure the lower port impedance. The 14-bit

resistance value is calculated with a bit weight of 4.625 Ω/bit in this case. The detection result is maintained in

the register in any operating mode following the detection.

R_Sn1

R_Sn0

DETECT STATUS

Other

R_STEPBIT WEIGHT

0

1

0

1

0

1

11.0966 Ω/bit

Low (< 2 kΩ)

Open circuit

Additional detect 4.625 Ω/bit

N/A

MOSFET short fault

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7.5.35 Port n Detect Voltage Difference Register

7.5.35.1 Port 1 Detect Voltage Difference Register

Command = 68h with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 68h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 1 Voltage Difference [7:0]

RESET or POR VALUE

0

MSB: 69h

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

VDS1[3:0]

Port 1 Voltage Difference [11:8]

RESET or POR VALUE

0

7.5.35.2 Port 2 Detect Voltage Difference Register

Command = 6Ah with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 6Ah

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 2 Voltage Difference [7:0]

RESET or POR VALUE

0

MSB: 6Bh

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

VDS2[3:0]

Port 2 Voltage Difference [11:8]

RESET or POR VALUE

0

7.5.35.3 Port 3 Detect Voltage Difference Register

Command = 6Ch with 2 Data Byte (LSByte first, MSByte second), Read Only

LSB: 6Ch

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 3 Voltage Difference [7:0]

RESET or POR VALUE

0

MSB: 6Dh

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

VDS3[3:0]

Port 3 Voltage Difference [11:8]

RESET or POR VALUE

0

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7.5.35.4 Port 4 Detect Voltage Difference Register

Command = 6Eh with 2 Data Byte (LSByte first, MSByte second), Read

LSB: 6Eh

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

Port 4 Voltage Difference [7:0]

RESET or POR VALUE

0

MSB: 6Fh

BITS

D7

D6

D5

D4

D3

D2

D1

D0

BIT NAME

VDS4[3:0]

Port 4 Voltage Difference [11:8]

RESET or POR VALUE

0

This register is used to determine the presence of a legacy PD by measuring the PD input capacitance on the PI.

A charge is injected into the PI, and the resulting Δv is reported. The Δv value shown is useable only if VDSn[3:0]

= 0001.

The I²C data transmission is a 2-byte transfer.

Bit Descriptions

Port n Voltage Difference[11:0]: 12-bit data conversion result of the difference in voltage on the port as a result

of a fixed charge injected into the port. The equation defining the resistance measured is:

k

C @

Nì V_STEP

where

•

C = Port capacitance, F

k = 81 x 10-6 coulomb

N = 12-bit value in Port n Detect Voltage Difference Register

V_STEP= LSB Value

(7)

NOTE

The expression for port capacitance ignores the effect of any conductance in parallel with

the capacitance being measured. The effect of parallel conductance is to give a higher

value than the actual value of any capacitance present.

USEABLE CAPACITANCE RANGE

VOLTAGE DIFFERENCE LSB VALUE

10 to 100 µF

4.884 mV

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VDSn[3:0]: Most recent detect voltage difference result status on Port n. If “0001” state, the 12-bit Δv value is

useable.

This measurement is made on a port if legacy detect is enabled using the Legacy Detect Mode Register.

VDSn is set to the Power-On Reset State (0000b) when legacy detection is enabled until a Δv measurement is

made.

The detection result is maintained in the register in any operating mode following the measurement.

The selection is as following:

VDSn[3:0]

0000

VOLTAGE-DIFFERENCE MEASUREMENT STATUS

Power-on reset

0001

Valid measurement

0010

Unable to discharge PD input capacitance to 2.4 V before timeout

Unable to achieve 0.4V to take first measurement before timeout

First measurement exceeds VDet-clamp (min)

Second measurement exceeds VDet-clamp (min)

ΔV < 0.5 V (insufficient signal)

0011

0100

0101

0110

7.5.36 Reserved Registers

•

Register 0x1B

Register 0x1D

Register 0x1E

Register 0x1F

Register 0x22

Register 0x23

Register 0x24

Register 0x25

Register 0x59

Reserved: These registers are reserved for manufacturing or future use. Undesirable behavior may result if

these registers are written to.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Introduction to PoE

Power-over-Ethernet (PoE) is a means of distributing power to Ethernet devices over the Ethernet cable using

either data or spare pairs. PoE eliminates the need for power supplies at the Ethernet device. Common

applications of PoE are security cameras, IP Phones and PDA chargers. The host or mid-span equipment that

supplies power is the Power Source Equipment (PSE). The load at the Ethernet connector is the Powered device

(PD). PoE protocol between PSE and PD controlling power to the load is specified by IEEE Std 802.3at-2009.

Transformers are used at Ethernet host ports, mid-spans and hubs, to interface data to the cable. A DC voltage

can be applied to the center tap of the transformer with no effect on the data signals. As in any power

transmission line, a relatively high 48 V is used to keep current low, minimize the effect of IR drops in the line

and preserve power to the load. Standard POE delivers approximately 13 W to a type 1 PD, and 25.5 W to a

type 2 PD. Figure 46 shows the overview schematic of a POE port.

8.2 Application Information

The TPS23861 is a four port, IEEE 802.3at PoE PSE controller and can be used in very simple, low port count,

automatic or high port count micro-controller managed applications.

Subsequent sections describe detailed design procedures for applications with different requirements including

host control.

VPWR

VDD

0.1mF

50V

0.1mF

100V

TPS23861PW

VPWR

1

2

3

4

5

6

7

8

9

VDD

VPWR 28

N/C 27

P2

P3

RESET

SCL

+

0.1mF

100V

-

+

RJ45

&

XFMR

RJ45

&

XFMR

0.1mF

100V

-

SMBJ58A-13-F

C1S 1.5

SMBJ58A-13-F

C1S 1.5

AOUT 26

AIN 25

SDAI

FDMC3612

SDAO

INT

SHTDWN 24

A3 23

10MQ100NTRPBF

(Optional)

0.255W

DGND

SEN3

DRAIN3

AGND 22

GATE2 21

DRAIN2 20

SEN2 19

22.1W

47W

0.255W

22.1W

(Optional)

10 GATE3

11 KSENSB

12 SEN4

10MQ100NTRPBF

KSENSA 18

GATE1 17

DRAIN1 16

SEN1 15

FDMC3612

C1S 1.5

FDMC3612

C1S 1.5

22.1W

P1

P4

47W

-

RJ45

0.1mF

&

-

RJ45

0.1mF

&

13 DRAIN4

14 GATE4

SMBJ58A-13-F

22.1W

100V

XFMR

+

100V

XFMR

+

SMBJ58A-13-F

VPWR

Figure 46. Automatic 4-Port Operation Schematic

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Application Information (continued)

The schematic of Figure 46 depicts automatic mode operation of the TPS23861, providing turnkey functionality

ready to power PoE loads. No connection to the I²C bus or any type of host control is required. In Figure 46 the

TPS23861 automatically:

1. Performs load detection.

2. Performs classification including type-2 (two-finger) of up to Class 4 loads.

3. Enables power with protective foldback current limiting, and ICUT value based on load class.

4. Shuts down in the event of fault loads and shorts.

5. Performs Maintain Power Signature function to ensure removal of power if load is disconnected.

6. Undervoltage lock out occurs if VPWR falls below V_{PUV_F}(typical 26.5 V).

Following a power-off command, disconnect or shutdown due to a start, ICUT or ILIM fault, the port powers

down. Following port power off due to a power off command or disconnect, the TPS23861 continues automatic

operation starting with a detection cycle. If the shutdown is due to a start, ICUT or ILIM fault, the TPS23861

enters into a cool-down period. After the end of the cool-down period the TPS23861 continues automatic

operation starting with a detection cycle.

The TPS23861 will not automatically apply power to a port under the following circumstances:

•

The detect status is not Resistance Valid.

If the classification status is overcurrent, class mismatch, or unknown.

8.2.1 Kelvin Current Sensing Resistor

Load current in each PSE port is sensed as the voltage across a low-end current-sense resistor with a value of

255 mΩ. For more accurate current sensing, kelvin sensing of the low end of the current-sense resistor is

provided through pins KSENSA for ports 1 and 2, and KSENSB for ports 3 and 4.

8.2.2 Connections on Unused Ports

The TPS23861 can be used on applications needing only 1 to 4 ports. On unused ports ground the SENx pin

and leave the GATEx pin floating. DRAINx pins can be grounded or left open (leaving open may slightly reduce

power consumption). One example of an unused PORT4 is shown in Figure 47. For detailed design and

component selection information, see System Examples.

This schematic shows connections for an unused PORT4.

11 KSENSB KSENSA 18

47 W

12 SEN4

GATE1 17

DRAIN1 16

SEN1 15

13 DRAIN4

14 GATE4

255 mꢀ/

250 mꢀ

22 W

Port 4

Not Used

Figure 47. Unused PORT4 Connections

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8.3 Typical Application

Typical applications are shown for several port counts. The TPS23861 is an effective choice for port counts less

than the 4 ports provided, and these applications clearly show the connections for unused ports.

Applications are shown for both Auto Mode as well as Semi-Auto Mode. Operation in any mode except Auto

Mode require I²C host support. The TPS23861 provides useful telemetry in multi port applications to aid in

implementing port power management.

8.3.1 Two Port, Auto Mode Application with External Port Reset

VPWR

VDD

TPS23861PW

C_VDD

C_VPWR

R_RST

VPWR

1

2

3

4

5

6

7

8

9

VDD

VPWR 28

N/C 27

P2

RESET

SCL

+

-

RJ45

&

XFMR

D_P2A

C_P2

AOUT 26

AIN 25

PORT RESET

F_P2

SDAI

Q_P2

SDAO

INT

SHTDWN 24

A3 23

D_P2B

(Optional)

R_S2A

R_S2B

DGND

SEN3

DRAIN3

AGND 22

GATE2 21

DRAIN2 20

SEN2 19

R_DRN2

R_S1A

R_S1B

R_SEN2

(Optional)

10 GATE3

11 KSENSB

12 SEN4

D_P1B

KSENSA 18

GATE1 17

DRAIN1 16

SEN1 15

Q_P1

P1

R_DRN1

R_SEN1

-

F_P1

RJ45

&

13 DRAIN4

14 GATE4

C_P1

D_P1A

XFMR

+

VPWR

Figure 48. Two Port Auto Mode Application With Port Reset

8.3.1.1 Design Requirements

Table 12. Design Parameters

DESIGN PARAMETER

VALUE

Auto Mode

Operating mode

Number/type of ports

Other requirements

Two type 2 ports

Push button port reset

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8.3.2 Four Port, Auto Mode Application

VPWR

VDD

TPS23861PW

C_VDD

C_VPWR

VPWR

1

2

3

4

5

6

7

8

9

VDD

VPWR 28

N/C 27

P2

P3

RESET

SCL

+

-

RJ45

&

XFMR

RJ45

&

XFMR

D_P2A

D_P3A

C_P2

C_P3

AOUT 26

AIN 25

F_P2

F_P3

-

SDAI

Q_P2

Q_P3

SDAO

INT

SHTDWN 24

A3 23

D_P2B

D_P3B

(Optional)

R_S2A

R_S2B

R_S3B

R_S3A

DGND

SEN3

DRAIN3

AGND 22

GATE2 21

DRAIN2 20

SEN2 19

R_SEN3

R_DRN3

R_DRN2

R_S1A

R_S1B

R_S4B

R_S4A

R_SEN2

(Optional)

10 GATE3

11 KSENSB

12 SEN4

D_P1B

D_P4B

KSENSA 18

GATE1 17

DRAIN1 16

SEN1 15

Q_P1

Q_P4

R_SEN4

R_DRN4

P1

P4

R_DRN1

R_SEN1

-

F_P1

F_P4

RJ45

&

RJ45

&

13 DRAIN4

14 GATE4

C_P1

C_P4

D_P1A

D_P4A

XFMR

+

VPWR

Figure 49. Four Port Auto Mode Application

8.3.2.1 Design Requirements

The design for the four port Auto Mode application is the same as for the two port design scaled up by two. In

addition, the four port application does not require port reset so the RESET pin may be connected directly to

VDD.

Table 13. Design Parameters

DESIGN PARAMETER

Operating mode

VALUE

Auto Mode

Number/type of ports

Four type 2 ports

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8.3.3 Eight Port, Semi-Auto Mode Application Using MSP430 Micro-Controller

VPWR

VDD

TPS23861PW

C_VDD

C_VPWR

VPWR

1

2

3

4

5

6

7

8

9

VDD

VPWR 28

N/C 27

P2

P3

RESET

SCL

+

-

+

-

RJ45

&

XFMR

RJ45

&

XFMR

D_P2A

D_P3A

C_P2

C_P3

AOUT 26

AIN 25

F_P2

F_P3

SDAI

Q_P2

Q_P3

SDAO

INT

SHTDWN 24

A3 23

D_P2B

D_P3B

(Optional)

R_S2A

R_S2B

R_S3B

R_S3A

DGND

SEN3

DRAIN3

AGND 22

GATE2 21

DRAIN2 20

SEN2 19

R_SEN3

R_DRN3

R_DRN2

R_S1A

R_S1B

R_S4B

R_S4A

R_SEN2

(Optional)

10 GATE3

11 KSENSB

12 SEN4

D_P1B

D_P4B

KSENSA 18

GATE1 17

DRAIN1 16

SEN1 15

Q_P1

Q_P4

R_SEN4

R_DRN4

P1

P4

R_DRN1

R_SEN1

-

F_P1

F_P4

RJ45

&

RJ45

&

13 DRAIN4

14 GATE4

C_P1

C_P4

D_P1A

D_P4A

XFMR

+

VDD

ADDR=0x20

VPWR

R_SCL

R_SDA

I2C Host

Device

VPWR

VDD

TPS23861PW

C_VPWR

C_VDD

VPWR

1

2

3

4

5

6

7

8

9

VDD

VPWR 28

N/C 27

P6

P7

RESET

SCL

+

-

+

-

RJ45

&

XFMR

RJ45

&

XFMR

D_P6A

D_P7A

C_P6

C_P7

AOUT 26

AIN 25

F_P6

F_P7

SDAI

Q_P6

Q_P7

SDAO

INT

SHTDWN 24

A3 23

D_P6B

D_P7B

(Optional)

R_S6A

R_S6B

R_S7B

R_S7A

DGND

SEN3

DRAIN3

AGND 22

GATE2 21

DRAIN2 20

SEN2 19

R_SEN7

R_DRN7

R_DRN6

R_SEN6

R_S5A

R_S5B

R_S8B

R_S8A

(Optional)

10 GATE3

11 KSENSB

12 SEN4

D_P5B

D_P8B

KSENSA 18

GATE1 17

DRAIN1 16

SEN1 15

Q_P5

Q_P8

R_SEN8

R_DRN8

P5

P8

R_DRN5

R_SEN5

-

F_P5

F_P8

RJ45

&

RJ45

&

13 DRAIN4

14 GATE4

C_P5

C_P8

D_P5A

D_P8A

XFMR

+

ADDR=0x28

VPWR

Figure 50. Eight Port Semi-Auto Mode Application

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8.3.3.1 Design Requirements

The design for the eight port Semi-Auto Mode application is the same as for the two port design scaled up by

four. In addition, the eight port application does not require port reset so the RESET pin may be connected

directly to VDD. Two TPS23861 devices are used in the eight port configuration and are managed by the I²C

host device. The factory default I²C address for each TPS23861 is 0x20 when the A3 pin is low and 0x28 when

the A3 pin is left open or tied to VDD.

Table 14. Design Parameters

DESIGN PARAMETER

Operating mode

VALUE

Semi-Auto Mode

Number/type of ports

Other requirements

Eight type 2 ports

Micro-controller managed

8.3.4 Detailed Design Procedure

8.3.4.1 Power Pin Bypass Capacitors

•

C_VPWR: 0.1 µF, 100 V, X7R ceramic at pin 28 (VPWR)

C_VDD: 0.1 µF, 50 V, X7R ceramic at pin 1 (VDD)

8.3.4.2 Per Port Components

•

R_DRNn: R_DRNnshould be a 47-Ω, 5%, 0.1-W resistor in an 0603 SMT package.

R_SENn: R_SENnshould be a 22.1-Ω, 1%, 0.1-W resistor in an 0603 SMT package.

C_Pn: 0.1-µF, 100-V, X7R ceramic between VPWR and Pn-

R_SnA/ R_SnB: The port current sense resistors can be either a combination of two 0.51-Ω, 1% resistors in

parallel (0.255 Ω) or four 1.00-Ω, 1% resistors in parallel (0.250 Ω). The most common usage employs dual

0.51-Ω, 1%, 0.25-W resistors in an 0805 SMT package. Power dissipation for the resistor pair at maximum

I_CUTis approximately 117 mW (~58 mW each).

•

Q_Pn: The port MOSFET can be a small, inexpensive device with average performance characteristics.

–

BVDSS should be 100 V minimum for high voltage surge environment considerations.

R_DS(on)(V_GS= 10 V) should be between 50 mΩ and 150 mΩ for power dissipation considerations.

–

The power dissipation for Q_Pnwith R_DS(on)= 100 mΩ at maximum I_CUTis approximately 46 mW.

–

Input capacitance (C_ISS) should be less than 2000 pF.

Gate Charge (Q_G) at V_GATEn= 12.5 V should be less than 50 nC (see NOTE below).

NOTE

For applications requiring faster response times under soft overload conditions (1 to

1.5 x ILIM), Q_G@ V_GATEn= 12.5 V may be required to be << 50 nC.

•

F_Pn: The port fuse should be a slow blow type rated for at least 60 VDC and above ~2 x I_CUT(max). The cold

resistance should be below 200 mΩ to reduce the DC losses. The power dissipation for F_Pnwith a cold

resistance of 180 mΩ at maximum I_CUTis approximately 83 mW.

D_PnA: The port TVS should be rated for the expected port surge environment. D_PnAshould have a minimum

reverse standoff voltage of 58 V and a maximum clamping voltage of 95 V at the expected peak surge

current.

D_PnB: The negative clamp diode is optional for extreme surge environments. D_PnBshould be rated for V_R

=

100 V minimum and be able to survive the expected surge current. Low forward voltage drop at the rated

current is beneficial.

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8.3.4.3 System Level Components (not shown in the schematic diagrams)

•

TVS: The system TVS should have a minimum reverse standoff voltage of 58 V and a maximum clamping

voltage of 95 V at the expected peak-surge current.

Bulk Capacitor: The system bulk capacitor(s) should be rated for 100 V and can be an aluminum electrolytic

type. Lower values can be paralleled to achieve at least 47 µF per four ports.

Digital I/O Pull-Up Resistors: RESET, AIN, A3, and SHTDWN are internally pulled up to VDD with a 50-kΩ

(typical) resistor. A stronger pull-up resistor can be added externally such as a 10 kΩ, 1%, 0.063 W type in a

SMT package. SCL, SDAI, SDAO, and INT require external pull-up resistors within a range of 1 kΩ to 10 kΩ

depending on the total number of devices on the bus. The AOUT pin is either connected to an upstream

device (to the AIN pin) or left unconnected and as such requires no external pull-up resistor.

•

Ethernet Data Transformer (per port): The Ethernet data transformer must be rated to operate within the

IEEE802.3at standard in the presence of the DC port current conditions. The transformer is also chosen to be

compatible with the Ethernet PHY. The transformer may also be integrated into the RJ45 connector and cable

terminations.

RJ45 Connector (per port): The majority of the RJ45 connector requirements are mechanical in nature and

include tab orientation, housing type (shielded or unshielded), or highly integrated. An integrated RJ45

consists of the Ethernet data transformer and cable terminations at a minimum. The integrated type may also

contain the port TVS and common mode EMI filtering.

Cable Terminations (per port): The cable terminations typically consist of series resistor (usually 75 Ω) and

capacitor (usually 10 nF) circuits from each data transformer center tap to a common node which is then

bypassed to a chassis ground (or system earth ground) with a high-voltage capacitor (usually 1000 pF to

4700 pF at 2 kV).

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8.3.5 Application Curves

Searching for PD

PD classified

PD detected

Figure 52. Power on Sequence After PD is Connected

Figure 51. Open Circuit Detection

PD detected (four point)

One-event class (class 0 current)

One-event class (class 3 current)

Figure 53. Four Point Detection, One-event Classification

(Class 0) and Power On

Figure 54. Four Point Detection, One-event Classification

(Class 3) and Power On

Load

current

Inrush

current

CLS1 MRK1 CLS2 MRK2

Two-event class

(class 4 current)

Figure 55. Two-event Classification

(Class 4) and Power On

Figure 56. Inrush and Load On

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8.4 System Examples

8.4.1 Overcurrent and Overload Protection

The TPS23861 provides three levels of overcurrent protection. During the t_STARTperiod immediately following

power up, inrush current protection is provided as described in Inrush Protection. This protection allows the input

capacitance of the PD to charge to the full input voltage on the power interface while ensuring the pass FET

remains within its safe operating area.

Following the end of the t_STARTperiod a two-tiered current-limit protection scheme is applied to the ports. The first

level (i.e., lower current) is the ICUT current limit. The ICUT current-limit threshold is set using the ICUTnm

CONFIG registers and includes a timeout, t_OVLD, set using TICUT field in the TIMING CONFIGURATION register.

When the TICUT timer times out because the ICUT current threshold is exceeded, the port is powered off, and

the ICUTn bit in the FAULT EVENT register is set with the option of asserting an interrupt. This delay in powering

down the port provides protection against spurious power downs during moderate load transients. See ICUT

Current Limit.

The second level of powered-on current-limiting protection is the ILIM current limit. The ILIM current limit is a

hard limit. That is, hardware protection including voltage foldback is imposed when the ILIM current threshold is

reached. This second level of protection is invoked in the event of extreme overload or short circuit. The ILIM

current-limit value is set using the POEPn bits in the PoE Plus register. Also, when the ILIM value is reached, the

ILIM timer is started. When the ILIM timer times out, the port is powered off and the ILIMn bit in the Start/ILIM

Event Register is set with the option of asserting an interrupt. See Foldback Protection (ILIM).

8.4.2 Inrush Protection

Inrush-current limiting is provided by the TPS23861 according to the curve in Figure 57. When the port is first

powered on, the TSTART timer is started. While the TSTART timer is counting, the port current is limited to

I_INRUSH, as shown in Figure 57. If at the end of t_STARTperiod the current is still limiting at I_INRUSH, the port is

powered off and the STRTn bit in the Start/ILIM Event Register is set with the option of asserting an interrupt.

500

450

400

350

300

250

200

150

100

50

0

10

20

30

40

50

60

70

Port Voltage -V

C002

Figure 57. Foldback During Inrush (at port turn on)

I_Inrushvs V_PORT

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System Examples (continued)

8.4.3 ICUT Current Limit

In addition to the absolute current limit imposed by the ILIM foldback curve (Figure 58) the TPS23861 supports

an additional level of current-limit protection.

When the ICUT current-limit threshold is reached, the TICUT timer starts counting down. When it reaches zero

the port is powered down. If the port current drops below the ICUT current-limit threshold while the TICUT timer

is counting, the TICUT timer counts up, albeit at a slower rate, without exceeding the maximum count

corresponding to the setting in the TICUT field.

The ICUT current-limit threshold is meant to be applied such that its setting is below the setting of the ILIM

current limit. That is, the ICUT threshold should be reached before the TPS23861 asserts foldback control over

the port current via an ILIM current limit. To this end, the ICUT threshold should be set lower than the ILIM

current limit. This must be accomplished by the host except when in Auto Mode (or the AUTO bit is set). In that

case, the settings for ICUT and ILIM is properly set based on classification results before the port is powered on.

The ICUT current limit threshold (ICUT) is programmable on a per-port basis in the 3-bit ICUT Port n fields in the

ICUTnm CONFIG registers. The encoding of the ICUT Port n fields is shown in Table 15. The current values in

Table 15 are nominal values.

Table 15. ICUT Current Limit Encoding

ICUT PORT n Field

ICUT (mA)

374

PoEPn⁽¹⁾

000

001

010

011

100

101

110

111

0

1

110

204

374

754

592

645

920

(1) PoEPn bit should be set according to ICUT value for host to ensure the ICUT and ILIM relationship.

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8.4.4 Foldback Protection (ILIM)

The TPS23861 features two types of foldback protection mechanisms for complete MOSFET protection. During

inrush at port power on, the foldback is based on the port voltage as shown in Figure .

NOTE

The inrush-current profile remains the same no matter what the state is of the PoEPn bit in

the PoE Plus Register.

After the port has been powered on and Power Good is valid, a dual-slope foldback current limit is applied,

providing protection against partial and total short-circuit at port output, while still being able to maintain the port

powered during normal transients in the TPS23861 input voltage or load current. Refer to Figure 58. Note that

setting the POEPn bit selects the 2x curve while clearing it selects the 1x curve.

The TLIM timer starts counting down when the current-limit threshold in Figure 57 and Figure 58 is reached.

When it reaches zero the port is powered down. If the ILIM current-limit condition is cleared while the TLIM timer

is counting, the TLIM timer counts up, at a slower rate, without exceeding the maximum count corresponding to

the setting in the TLIM field which is located in the Timing Configuration Register.

If the port experiences a short circuit, the TPS23861 forces zero volts on the gate of the external FET to protect it

from destruction. Within microseconds the foldback circuit engages, and until the ILIM timeout is reached, the

port current is controlled according to the foldback schedule.

The ILIM current limit is to be applied such that its setting is greater than the setting of the ICUT current

threshold. That is, an ICUT current-limit condition should occur before the TPS23861 asserts foldback control

over the port current via an ILIM current limit. To this end, the ILIM current limit must be set greater than the

ICUT current threshold. This must be accomplished by the host except when in Auto Mode (or the AUTO bit is

set). In that case, the settings for ICUT and ILIM will be properly set based on classification results before the

port is powered on.

1.2

1X

2X

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

5

10

15

20

25

30

35

MOSFET Drain Voltage (V)

40

45

50

D001

Figure 58. Foldback Port On (ILIM vs V_DRAIN

)

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8.4.5 Kelvin Current Sensing Resistor

Load current in each PSE port is sensed as the voltage across a low-end current-sense resistor with a value of

255 mΩ. Alternatively, a 250-mΩ resistor may be used. If a 250-mΩ sense resistor is used the M250 bit in the

General Mask 1 Register must be set. For more accurate current sensing, kelvin sensing of the low end of the

current-sense resistor is provided through pins KSENSA for ports 1 and 2, and KSENSB for ports 3 and 4.

Figure 59 illustrates the kelvin-sensing scheme.

3.3 V

48 V

100 nF

100 V

PORTn

VDD VPWR

47 ꢀ

22 ꢀ

SCL

DRAINn

GATEn

SENn

SDAO

SDAI

INT

TPS23861

255 mꢀ/

250 mW

KSENSx

AGND DGND

Note: only port n shown

Figure 59. Kelvin Current-Sense Connection

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9 Power Supply Recommendations

9.1 VDD

The recommended VDD supply voltage requirement is 3.3 V, ±0.3 V. Each TPS23861 requires approximately 5

mA typical and 6 mA maximum from the VDD supply. The VDD supply can be generated from VPWR with a

linear regulator (TPS7A4001) for single TPS23861/Auto Mode based PSE or a buck-type regulator (LM5007 or

LM5019 based) for a higher port count PSE using multiple TPS23861 devices operating in Auto or Semi-Auto

Modes.

The power supply design must ensure the VDD rail rises monotonically through V_UVDDRwithout any droop below

V_UVDDFas the loads are turned on. This is accomplished with proper bulk capacitance across the VDD rail for the

expected load current steps over worst case design corners. Furthermore, the combination of decoupling

capacitance and bulk storage capacitance must hold the VDD rail above the UVLO_fall threshold during any

expected transient outages once power is applied.

9.2 VPWR

The recommended VPWR supply voltage requirement is 44 V to 57 V. A power supply with a nominal 48-V or

54-V output can support both type 1 and type 2 PD requirements. The output current required from the VPWR

supply depends on the number and type of ports required in the system. The TPS23861 can be configured for

type 1 and type 2 ports and the current limit is set proportionally. ICUT for a type 1 port is 374 mA , ±5%, and for

a type 2 port is 645 mA, ± 5%. Size the VPWR supply accordingly for the number and type of ports to be

supported. As an example, the VPWR power supply rating should be greater than 3.2 A for eight type 1 ports or

greater than 5.5 A for eight type 2 ports, assuming maximum port and standby currents.

9.3 VPWR-RESET Sequencing

The voltage on the RESET pin (V_RESET) should be kept below 0.9 V until V_VPWRexceeds V_{UVLOPW_R}. If VDD is

turned ON after V_VPWRexceeds V_{UVLOPW_R}then no delay for RESET is required. If VDD is ON before V_VPWR

exceeds V_{UVLOPW_R}then a delay for RESET is required. This delay can be provided by the system host or with a

capacitor (C_RST) connected to the RESET pin using the internal (50 kΩ typical) or external pullup resistor.

NOTE

For the schematic diagrams shown in Figure 36, Figure 46, Figure 48, Figure 49, and

Figure 50, the VDD power supply is turned on after the VPWR power supply exceeds

V_{UVLOPW_R}. More detail regarding TPS23861 power-on sequencing can be obtained by

referring to the application note, TPS23861 Power-On Considerations, SLVA723.

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10 Layout

10.1 Layout Guidelines

10.1.1 Port Current Kelvin Sensing

KSENSA is shared between SEN1 and SEN2, while KSENSB is shared between SEN3 and SEN4. In order to

optimize the accuracy of the measurement, the PCB layout must be done carefully to minimize impact of PCB

trace resistance. Refer to Figure 60 as an example.

Shape connecting R_S1A/B

and R_S2A/Bto KSENSA

R_S1A/B

R_S2A/B

KSENSA route

to SN1902071

To R_SEN1

Vias connecting

shape to GND layer

To R_SEN2

Figure 60. Kelvin Sense Layout Example

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10.2 Layout Example

BOTTOM SIDE (not mirrored)

TOP SIDE

TPS23861PW

KSENSB

R_DRN3

R_SEN3

R_S3A

R_S3B

R_SEN2

R_S1A

KSENSA

R_S4A

Q_P2

R_S2A

R_S2B

Q_P3

R_S4B

R_S1B

R_DRN2

GND

Q_P1

Q_P4

F_P4

F_P2

F_P3

D_P1A

D_P4A

D_P3A

D_P2A

C_P4

C_P1

P1

C_P2

P2

C_P3

P4

P3

GND

J_IO

VPWR

Figure 61. Four Port Layout Example

10.2.1 Component Placement and Routing Guidelines

10.2.1.1 Power Pin Bypass Capacitors

C_VPWR: Place close to pin 28 (VPWR) and connect with low inductance traces and vias according to Figure 61.

C_VDD: Place close to pin 1 (VDD) and connect with low inductance traces and vias according to Figure 61.

10.2.1.2 Per-Port Components

R_SnA/ R_SnB: Place according to Figure 60 in a manner that facilitates a clean Kelvin connection with

KSENSEA/B.

Q_Pn: Place Q_Pnaround the TPS23861 as illustrated in Figure 61. Provide sufficient copper from Q_Pn-Dto F_Pn.

R_DRNn: Place R_DRNnnear to Q_Pn-D. Connect to DRAINn pins as illustrated in Figure 61.

R_SENn: Place R_SENnnear to Q_Pn-S. Connect to SENn pins as illustrated in Figure 61.

F_Pn, C_Pn, D_PnA, D_PnB: Place this circuit group near the RJ45 port connector (or port power interface if a daughter

board type of interface is used as illustrated in Figure 61). Connect this circuit group to Q_Pn-D/ GND (TPS23861-

AGND) using low inductance traces.

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11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

应用报告《IC 封装热指标》，SPRA953.

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

100

重要声明和免责声明

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS23861PW
厂家：	TEXAS INSTRUMENTS
描述：	具有自主模式的 2 线对、2 类、4 通道 PoE PSE \| PW \| 28 \| -40 to 125 光电二极管
文件：	总108页 (文件大小：1940K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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