TPS2394PWR [TI]

用于 -48V 冗余电源的 -12V 至 80V 热插拔控制器 | PW | 14 | -40 to 85;


型号：	TPS2394PWR
厂家：	TEXAS INSTRUMENTS
描述：	用于 -48V 冗余电源的 -12V 至 80V 热插拔控制器 \| PW \| 14 \| -40 to 85 控制器光电二极管电源管理电路电源电路
文件：	总18页 (文件大小：339K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS2394

www.ti.com

SLVSAA9 –AUGUST 2010

–48-V Hot Swap Power Manager

Check for Samples: TPS2394

FEATURES

DESCRIPTION

•

Operating Supply Range of –12 V to –80 V

Withstands Transients to –100 V

Programmable Current Limit

The TPS2394 is a hot swap power manager which

can provide inrush limit, over current protection, short

circuit protection. The TPS2394 operates with supply

voltages from −12 V to −80 V, and withstands input

transient to −100 V.

Programmable Linear Inrush Slew Rate

Programmable UV/OV Thresholds

Programmable UV and OV Hysteresis

Fault Timer to Eliminate Nuisance Trips

Power Good and Fault Outputs

14-Pin TSSOP Package

The TPS2394 uses a power FET to provide load

current slew rate control and peak current limiting that

is programmed by one resistor and one capacitor.

The device also provides a power good output to

enable down-stream power converters and a fault

output to indicate load problems.

APPLICATIONS

•

–48-V Distributed Power Systems

Central Office Switching

ATCA Systems

Base Stations

TYPICAL APPLICATION DIAGRAM

R_LOAD

RTN

(1)

C_LOAD

RTN

FLT

R_SENSE

GAT

Power Good

Fault

TPS2394

SENSE

SOURCE

FLTTIM RAMP

C_FLT

C_RAMP

-Vin

(1) D1 optional per application requirements.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS2394

SLVSAA9 –AUGUST 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)⁽²⁾

PARAMETERS

VALUE

–0.3 to 100

–0.3 to 15

–0.3 to 100

UNIT

RTN

Input voltage range

FLTTIM, RAMP, SENSE, OV, UV

(3)

Output voltage range

FLT, PG

Continuous output current

FLT, PG

°C

Operating junction temperature range, T_J

ESD - Human body model (HBM)

ESD - Charged device model (CDM)

–55 to 125

1.5

(1) All voltages are with respect to SOURCE (unless otherwise noted).

(2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(3) With 10 kΩ minimum series resistance. Range limited to –0.3V to 80V from low impedance source.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

–80

–40

NOM

MAX

–12

UNIT

Input supply, SOURCE to RTN

–48

Operating junction temperature range

°C

TSSOP-14 PACKAGE

(TOP VIEW)

RTN

FLT

GAT

SENSE

FLTTIM

RAMP

SOURCE

PRODUCT INFORMATIONS⁽¹⁾

T_A

PACKAGE

PART NUMBER

−40°C to 85°C

TSSOP-14

TPS2394PW

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at wwww.ti.com.

THERMAL INFORMATION

TPS2394

THERMAL METRIC⁽¹⁾

UNITS

PW (14 (PINS)

q_JA

q_JB

y_JT

y_JB

Junction-to-ambient thermal resistance

120.8

62.8

Junction-to-board thermal resistance

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

56.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Product Folder Link(s): TPS2394

TPS2394

www.ti.com

SLVSAA9 –AUGUST 2010

ELECTRICAL CHARACTERISTICS

SOURCE = -48 V, UV = 2.5 V, OV = 0.5 V, SENSE = 0 V, RAMP = 0 V, T_A= −40°C to 85°C (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY

I_CC1

Supply current

SOURCE = -48 V

1000

1500

2000

–8

µA

I_CC2

SOURCE = -80 V

To GAT pull up

V_{UVLO_I}

V_HYST

Internal UVLO threshold voltage

Internal UVLO hysteresis voltage

–11.8

–10

240

500

OVERVOLTAGE AND UNDERVOLTAGE INPUTS (OV AND UV)

To GAT pull up, 25°C

To GAT pull up, 0 to 70°C

To GAT pull up, –40 to 85°C

UV = −45.5 V

1.391

1.387

1.384

–11

1.400

–10

1.409

1.413

1.419

–9

V_THUV

UV threshold voltage, UV rising, to SOURCE

I_HYSUV

I_ILUV

UV hysteresis

µA

UV low−level input current

OV threshold voltage, OV rising, to SOURCE

OV hysteresis

UV = −47 V

–1

V_THOV

I_HYSOV

I_ILOV

To GAT pull up

1.376

–11.1

–1

1.400

–10

1.426

–8.6

OV = −45.5 V

µA

OV low−level input current

OV = −47 V

LINEAR CURENT AMPLIFIER (LCA)

V_OH

High level output, GAT−SOURCE

SENSE = SOURCE

SENSE – SOURCE = 80 mV,

GAT = –43 V, FLTTIME = 5 V

I_{SINK_f}

GAT sink current in fault

SENSE – SOURCE = 80 mV,

GAT = –43 V, FLTTIME = 2 V

I_{SINK_l}

GAT sink current in linear mode

I_IN

SENSE input current

0 V < SENSE – SOURCE < 0.2 V

RAMP – SOURCE = 6 V

–1

–7

µA

V_{REF_K}

V_IO

Reference clamp voltage, SENSE – SOURCE

Input offset voltage, SENSE – SOURCE

RAMP – SOURCE = 0 V

(1) All voltages are with respect to RTN unless otherwise stated.

(2) Currents are positive into and negative out of the specified terminal.

Product Folder Link(s): TPS2394

TPS2394

SLVSAA9 –AUGUST 2010

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ELECTRICAL CHARACTERISTICS (continued)

SOURCE = -48 V, UV = 2.5 V, OV = 0.5 V, SENSE = 0 V, RAMP = 0 V, T_A= −40°C to 85°C (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RAMP GENERATOR

I_SRC1

I_SRC2

V_OL

RAMP source current, slow turn-on rate

RAMP source current, normal rate

Low-level output voltage

RAMP – SOURCE = 0.25 V

–800

–550

–10

–300

–8.5

µA

RAMP – SOURCE = 1 V and 3 V

UV = SOURCE

–11.3

A_V

Voltage gain, relative to SENSE

0 V < RAMP – SOURCE < 5 V

9.5

10.7

mV/V

OVERLOAD COMPARATOR

V_{TH_OL}SENSE current overload threshold

t_RSP

100

120

140

µs

Response time

SENSE – SOURCE = 200 mV

FAULT TIMER

V_OL

FLTTIM low−level output voltage, to SOURCE

FLTTIM charging current, current limit mode

FLTTIM fault threshold voltage to SOURCE

Fault reset threshold to SOURCE

UV = –48 V

–41

µA

I_CHG

FLTTIM – SOURCE = 2 V

–54

–50

4.00

0.5

V_FLT

3.75

4.25

V_RST

I_DSG

FLTTIM Discharge current, retry mode

FLTTIM – SOURCE = 2 V

0.38

0.75

µA

SENSE − SOURCE = 80 mV,

FLTTIM – SOURCE = 2 V

Output duty cycle during retry cycles

1.5%

I_RST

FLTTIM discharge current, timer reset mode

FLTTIM – SOURCE = 2 V, SENSE = V

µA

LOGIC OUTPUTS (FLT, PG)

I_OHFLTFLT high-level output leakage current

I_OHPG

UV = –48 V, FLT – SOURCE = 80 V

UV = –45 V, PG – SOURCE = 80 V

–10

PG high-level output leakage current

FLT ON resistance

SENSE–SOURCE = 80 mV,

FLTTIM–SOURCE = 5 V, I_(FLT)= 1 mA

Ω

R_DS(on)

PG ON resistance

UV = –48 V, I_O(PG) = 1 mA

Product Folder Link(s): TPS2394

TPS2394

www.ti.com

SLVSAA9 –AUGUST 2010

DEVICE INFORMATION

PIN FUNCTIONS

I/O

DESCRIPTION

NAME

FLT

NO.

I/O

Open-drain, active-low indication that the part is in fault.

Connection for user programming of the fault timeout period.

FLTTIM

GAT

Gate drive for external N-channel MOSFET that ramps load current and disconnects in the event of a

fault.

Not connected, leave floating

I/O

Over voltage sense input.

Open-drain, active-high indication that the power MOSFET is fully enhanced.

Programming input for setting the inrush current slew rate.

Supply return (for positive grounded system).

Positive current sense input.

RAMP

RTN

SENSE

SOURCE

I/O

Negative current sense input.

Under voltage sense input.

PIN DESCRIPTIONS

FLT: Open-drain, active-low indication that TPS2394 has shut down due to a faulted load. This happens if the

load current stays limited by the linear current amplifier (LCA) for more than the fault time (time to charge the

FLTTIM capacitor). FLT is cleared when input supply drops below the UV-comparator threshold or exceeds the

OV-comparator threshold. The FLT output is pulled to SOURCE. The FLT output is able to sink 10 mA when in

fault, withstand 80 V without leakage when not faulted, and withstand transients as high as 100 V when limited

by a series resistor of at least 10 kΩ.

FLTTIM: Connection for user programming of the fault timeout period. An external capacitor connected from

FLTTIM to SOURCE establishes the timeout period to declare a fault condition. This timeout protects against

indefinite current sourcing into a faulted load, and also provides a filter against nuisance trips from momentary

current spikes or surges. TPS2394 defines a fault condition as voltage at the SENSE pin at or greater than the

42-mV fault threshold. When a fault condition exists, the timer is active. The devices manage fault timing by

charging the external capacitor to the 4-V fault threshold, then subsequently discharging it at approximately 1%

the charge rate to establish the duty cycle for retrying the load. Whenever the fault latch is set (timer expired),

GAT and FLT are pulled low.

GAT: Gate drive for an external N-channel protection power MOSFET. When input supply is above the UV

threshold and below the OV threshold, gate drive is enabled and the device begins charging the external

capacitor connected to RAMP. RAMP develops the reference voltage at the non-inverting input of the internal

LCA. The inverting input is connected to the current sense node, SENSE. The LCA acts to slew the pass

MOSFET gate to force the SENSE voltage to track the reference. The reference is internally clamped to 42 mV,

so the maximum current that can be sourced to the load is determined by the sense resistor value as I_MAX≤42

mV/R_SENSE. Once the load voltage has ramped up to the input dc potential and current demand drops off, the

LCA drives GAT 14 V above SOURCE to fully enhance the pass MOSFET, completing the low-impedance

supply return path for the load.

PG: Open-drain, active-high indication that load current is below the current limit and the power MOSFET is fully

enhanced. When commanded load current is more than the actual load current, the linear current amplifier (LCA)

will raise the power MOSFET gate voltage to fully enhance the power MOSFET. At this time, the PG output will

go high. This output can be used to enable a down-stream dc-to-dc converter. The PG output is pulled to

SOURCE and is able to sink 10 mA when in fault, withstand 80 V without leakage when power is not good, and

withstand transients as high as 100 V when limited by a series resistor of at least 10 kΩ.

Product Folder Link(s): TPS2394

TPS2394

SLVSAA9 –AUGUST 2010

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OV: Over voltage comparator input. This input is typically connected to a voltage divider between RTN and

SOURCE to sense the magnitude of the input supply. If OV is less than 1.4 V above SOURCE, and UV is more

than 1.4 V above SOURCE, and there is no fault, the linear current amp will be enabled. In the event of a fault,

pulling OV high or UV low will reset the fault latch and allow the IC to restart. OV can also be used as an

active-low logic enable input. The over-voltage comparator hysteresis is programmed by the equivalent

resistance seen looking into the divider at the OV input.

RAMP: Programming input for setting inrush current and current slew rate. An external capacitor connected

between RAMP and SOURCE establishes turn-on current slew rate. During turn-on, TPS2394 charges this

capacitor to establish the reference input to the LCA at 1% of the voltage from RAMP to SOURCE. The

closed-loop control of the LCA and the pass MOSFET maintains the V(SENSE - SOURCE) at the reference

potential, so the load current slew rate is directly set by the voltage ramp rate at the RAMP pin. When fully

charged, RAMP can exceed SOURCE by 6 V, but the reference is internally clamped to 42 mV, limiting load

current to 42 mV/R_SENSE. When the output is disabled via OV, UV, or due to a load fault, the RAMP capacitor is

discharged and held low to initialize for the next turn on.

The TPS2394 initiates ramp capacitor charging, and consequently load current slewing, at a reduced rate. This

reduced rate applies until the voltage on the RAMP pin is about 0.5 V. The maximum di/dt rate, as set by

Equation 2, is effective once the device switches to a 10-mA charging source.

RTN: Positive supply input. For negative voltage systems, this pin connects directly to the return node of the

input power bus.

SENSE: Current sense input. An external low-value resistor connected between SENSE and SOURCE is used

to monitor current magnitude. There are two internal device thresholds associated with the voltage at the SENSE

pin. During ramp-up of the load capacitance or during other periods of excessive demand, the linear current amp

(LCA) will regulate this voltage to 42 mV. Whenever the LCA is in current regulation mode, the FLTTIM capacitor

charges. If the LCA output is at its maximum, GAT is pulled 14 V above SOURCE. At this time, a fast fault such

as a short circuit can cause the SENSE voltage to rapidly exceed 120 mV (the overload threshold). In this case,

the GAT pin is pulled low rapidly, bypassing the fault timer.

SOURCE: Connection to the input supply negative rail.

UV: Under Voltage Comparator input. This input is typically connected to a voltage divider between RTN and

SOURCE to sense the magnitude of the input supply. If UV is more than 1.4 V above SOURCE, OV is less than

1.4 V above SOURCE, and there is no fault, the LCA will be enabled. In the event of a fault, pulling UV low or

OV high will reset the fault latch and allow restarting. UV can also be used as an active high logic enable input.

The under-voltage comparator hysteresis is programmed by the equivalent resistance seen looking into the

divider at the UV input.

Product Folder Link(s): TPS2394

TPS2394

www.ti.com

SLVSAA9 –AUGUST 2010

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

UNDERVOLTAGE PULL-UP CURRENT

AMBIENT TEMPERATURE

1500

1200

-9.0

-9.4

= 0 V

(RTN)

V_(RTN)= 0 V

-48 V ≤ V_(SOURCE)≤ -20 V

V_IN(UV)- V_(SOURCE)= 25 V

= -80 V

(SOURCE)

900

600

-9.8

-10.2

= -48 V

(SOURCE)

= -20 V

(SOURCE)

= -12 V

(SOURCE)

300

-10.6

-11.0

-40

-15

- Ambient Temperature - °C

-40

-15

- Ambient Temperature - °C

Figure 1.

Figure 2.

GAT HIGH-LEVEL OUTPUT VOLTAGE

RAMP OUTPUT CURRENT

AMBIENT TEMPERATURE

AMBIENT TEMPERATURE, REDUCED RATE MODE

-460

V_(RTN)= 0 V

V_OUT(RAMP)- V_(SOURCE)= 0.25 V

-480

= -48 V

(SOURCE)

= -20 V

(SOURCE)

-500

-520

-540

= -12 V

(SOURCE)

= -12 V

(SOURCE)

= -48 V

(SOURCE)

= -36 V

(SOURCE)

V_(RTN)= 0 V

-560

-580

V_IN(SENSE)= V_(SOURCE)= 0 V

I_OUT(GAT)= -10 mA

-40

-15

- Ambient Temperature - °C

-40

-15

- Ambient Temperature - °C

Figure 3.

Figure 4.

Product Folder Link(s): TPS2394

TPS2394

SLVSAA9 –AUGUST 2010

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TYPICAL CHARACTERISTICS (continued)

RAMP OUTPUT CURRENT

TIMER CHARGING CURRENT

AMBIENT TEMPERATURE, NORMAL RATE MODE

AMIBENT TEMPERATURE

-8.5

-46

-48

Average for V_OUT(RAMP)- V_(SOURCE)= 1V, 3V

V_(RTN)= 0 V

V_(FLTTIM)- V_(SOURCE)= 2 V

-80 V ≤ V_(SOURCE)≤ -12 V

-80 V ≤ V_(SOURCE)≤ -20 V

-9.1

-9.7

-52

-54

-58

-10.3

-10.9

-11.5

-40

-15

- Ambient Temperature - °C

-40

-15

- Ambient Temperature - °C

Figure 5.

Figure 6.

TIMER DISCHARGE CURRENT

FAULT LATCH THRESHOLD VOLTAGE

AMIBENT TEMPERATURE

0.50

0.45

4.25

4.15

V_(RTN)= 0 V

V_(SOURCE)= -48 V

V_(FLTTIM)- V_(SOURCE)= 2 V

Relative to SOURCE

-80 V ≤ V_(SOURCE)≤ -20 V

0.40

0.35

4.05

3.95

0.30

0.25

0.20

3.85

3.75

-40

-15

- Ambient Temperature - °C

-40

-15

- Ambient Temperature - °C

Figure 7.

Figure 8.

Product Folder Link(s): TPS2394

TPS2394

www.ti.com

SLVSAA9 –AUGUST 2010

FUNCTIONAL BLOCK DIAGRAM

RTN

Input UV

Comparator

1.4 V

Input OV

Comparator

Disable

FLT

1.4 V

Fault Latch

120 mV

4 ms

Filter

Retry

Timer

Fault

Timer

Overload

Comparator

FLTTIM

SENSE

GAT

Linear Current

Amp

99R

RAMP

Power Good

Detection

Disable

42 mV

SOURCE

Product Folder Link(s): TPS2394

TPS2394

SLVSAA9 –AUGUST 2010

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APPLICATION INFORMATION

RTN

C_LOAD

R_LOAD

RTN

POWER GOOD

FAULT

FLT

GAT

SENSE

TPS2394

R_SENSE

SOURCE

FLTTIM RAMP

C_FLT

C_RAMP

-Vin

Figure 9. Typical Application

Product Folder Link(s): TPS2394

TPS2394

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SLVSAA9 –AUGUST 2010

APPLICATION INFORMATION

Setting the Sense Resistor Value

Due to the current-limiting action of the internal LCA, the maximum allowable load current for an implementation

is easily programmed by selecting the appropriate sense resistor value. The LCA acts to limit the sense voltage

V(SENSE-SOURCE) to its internal reference. Once the voltage at the RAMP pin exceeds approximately 4 V, this

limit is the clamp voltage, V_{REF_K}. Therefore; a maximum sense resistor value can be determined from

Equation 1.

34 mV

R_SENSE

IMAX

(1)

Where:

R_SENSEis the sensing resistor value

I_IMAXis the minimum desired current limit

When setting the sense resistor value, it is important to consider two factors, the minimum current limit that may

be imposed by the TPS2394, and the maximum load under normal operation of the module. For the first factor,

the specification minimum clamp value is used, as seen in Equation 1. Second factor is to ensure the peak

operating load current is less than I_IMAX. One example of this is a switching converter which draws higher input

current, for a given power output, when the output is at the low end of its voltage range. To avoid current limit

operation under normal loading, some margin should be designed in between this maximum anticipated load and

the minimum current limit level, or I_IMAX> I_LOAD(max), for Equation 1.

For example, using a 10-mΩ sense resistor for a nominal 2-A load application provides a minimum of 1.4 A of

overhead for load variance/margin. Typical bulk capacitor charging current during turn-on is 4.2 A

(42 mV/10 mΩ).

Setting the Inrush Slew Rate

The TPS2394 device enables user-programming of the maximum current slew rate during load start-up events. A

capacitor tied to the RAMP pin (C_RAMPin the typical application diagram) controls the di/dt rate. Once the sense

resistor value has been established, a value for C_RAMP, in microfarads, can be determined from Equation 2.

11.3

C_RAMP

100 ´ R_SENSE

ø_(max)

(2)

Where:

R_SENSEis the sense resistor value in Ω

(di/dt)_(max)is the desired maximum slew rate in A/s

For example, if the desired slew rate for the typical application shown is 1500 mA/ms, the calculated value for

C_RAMPis about 7500 pF. Selecting the next larger standard value of 8200 pF provides some margin for capacitor

and sense resistor tolerances.

Setting the Fault Timing Capacitor

The fault timeout period is established by the value of the capacitor connected to the FLTTIM pin, C_FLT. The

timeout period permits riding out spurious current glitches and surges that may occur during operation of the

system, and prevents indefinite sourcing into faulted loads. However, to ensure smooth voltage ramping under all

conditions of load capacitance and input supply potential, the minimum timeout should be set to accommodate

these system variables. To do this, a rough estimate of the maximum voltage ramp time for a completely

discharged plug-in card provides a good basis for setting the minimum timer delay. This section presents a quick

procedure for calculating the timing capacitance requirement. However, for proper operation of the TPS2394,

there is an absolute minimum value of 0.01-µF for C_FLT. This minimum requirement overrides any smaller results

of Equation 7 and Equation 8.

Product Folder Link(s): TPS2394

TPS2394

SLVSAA9 –AUGUST 2010

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Due to the three-phase nature of the load current at turn-on, the load voltage ramp has potentially three distinct

phases. This profile depends on the relative values of load capacitance, input DC potential, maximum current

limit and other factors. The first two phases are characterized by the two different slopes of the current ramp; the

third phase, if required to complete load charging, is the constant-current charging at IMAX. Considering the two

current ramp phases to be one period at an average di/dt simplifies calculation of the required timing capacitor.

For the TPS2394, the typical duration of the soft-start period, t_SS, is given by Equation 3.

= 1260 ´ C

RAMP

(3)

Where:

t_SSis the soft-start period in ms

C_RAMPis given in µF

During this current ramp period, the load voltage magnitude which is attained is estimated by Equation 4.

AVG

( _SS)

LSS

2 × C

× C

× 100 × R

LOAD

RAMP SENSE

(4)

Where:

V_LSSis the load voltage reached during soft-start

i_AVGis 3.18 µA for the TPS2394

C_LOADis the load capacitance in Farads

t_SSis the soft-start period in s

The quantity i_AVGin Equation 4 is a weighted average of the two charge currents applied to C_RAMPduring turn-on,

considering the typical output values.

If the result of Equation 4 is larger than the maximum input supply value, then the load can be expected to

charge completely during the inrush slewing portion of the insertion event. However, if this voltage is less than

the maximum supply input, V_IN(MAX), the HSPM transitions to the constant-current charging of the load. The

remaining amount of time required at I_MAXis determined from Equation 5.

C_LOAD

- V_LSS

(

V_{REF_K(MIN)}

)

IN(MAX)

t_CC

R_SENSE

(5)

Where:

t_CCis the constant-current voltage ramp time, in seconds

V_{REF_K(MIN)}is the minimum clamp voltage, 34 mV

With this information, the minimum recommended value timing capacitor C_FLTcan be determined. The delay time

needed will be either a time t_SS2or the sum of t_SS2and t_CC, according to the estimated time to charge the load.

The quantity t_SS2is the duration of the normal rate current ramp period, and is given by Equation 6.

t_SS2= 0.35 ´ C_RAMP

(6)

Where:

C_RAMPis given in µF

Since fault timing is generated by the constant-current charging of C_FLT, the capacitor value is determined from

either Equation 7 or Equation 8, as appropriate.

54 ´ t_SS2

C_FLT(MIN)

3.75

54 ´

(7)

(8)

(

_SS2+ t_CC

)

C_FLT(MIN)

3.75

Where:

C_FLT(MIN)is the recommended capacitor value, in µ-Farads

t_SS2is the result of Equation 6, in seconds

t_CCis the result of Equation 5, in seconds

Product Folder Link(s): TPS2394

TPS2394

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SLVSAA9 –AUGUST 2010

Continuing this calculation example, using a 220-µF input capacitor (C_LOAD), Equation 3 and Equation 4 estimate

the load voltage ramping to approximately –45 V during the soft-start period. If the module should operate down

to –72-V input supply, approximately another 1.4 ms of constant-current charging may be required. Therefore,

Equation 6 and Equation 8 are used to determine C_FLT(MIN), and the result is approximately 0.039-µF.

Setting the Undervoltage and Overvoltage Thresholds

The UV and OV pins can be used to set the undervoltage (V_UV) and overvoltage (V_OV) thresholds of the hot swap

circuit. When the input supply is below V_UVor above V_OV, the GAT pin is held low, disconnecting power from the

load, and the PG output is deasserted. When input voltage is within the UV/OV window, the GAT pin drive is

enabled, assuming all other input conditions are valid for turn-on.

Threshold hysteresis is provided via two internal sources which are switched to either pin whenever the

corresponding input level exceeds the internal 1.4-V reference. The additional bias shifts the pin voltage in

proportion to the external resistance connected to it. This small voltage shift at the device pin is gained up by the

external divider to input supply levels.

(a)

(b)

GND

200 kΩ

1 %

RTN

4.99 kΩ

1 %

TPS2394 ⁽¹⁾

3.92 kΩ

1 %

SOURCE

-48V

R1 + R2 + R3

R2 R3

R1 + R2

V_{UV_L}

x V_THUV

V_{UV_L}

x V_THUV

R1 + R2 + R3

R8 + R9

V_{OV_L}

x V_THOV-I _HYSUVx R1

V_{OV_L}

x V_THOV

Note (1): Additional details omitted for clarity.

Figure 10. Programming the Undervoltage and Overvoltage Thresholds

The UV and OV thresholds can be individually programmed with a three-resistor divider connected to the

TPS2394 as shown in the typical application diagram, and again in Figure 10a. When the desired trip voltages

and undervoltage hysteresis have been established for the protected board, the resistor values needed can be

determined from the following equations. First, select the top leg of the divider (R1 in the diagram) to obtain the

threshold hysteresis. This value is calculated using Equation 9.

HYS_UV

R1 =

10 μA

(9)

Where:

V_{HYS_UV}is the undervoltage hysteresis value

For example, assume the typical application design targets have been set to undervoltage turn-on at 33 V (input

supply rising), turn-off at 31 V (input voltage falling), and overvoltage shutdown at 72 V. Then Equation 9 yields

R1 = 200 kΩ for the 2-V hysteresis. Once the value of R1 is selected, it is used to calculate resistors R2 and R3.

V_{UV_L}

1.4 ´ R1

- 1.4

R2 =

1 -

V_{OV_L}+ 10^-5´ R1

(

)

UV_L

(

)

(10)

Product Folder Link(s): TPS2394

TPS2394

SLVSAA9 –AUGUST 2010

www.ti.com

1.4 × R1 × V_{UV_L}

- 1.4

V_{OV_L}+ 10^-5× R1

R3 =

(

)

(

UV_L

)

(11)

Where:

V_{UV_L}is the UVLO threshold when the input supply is low; i.e., less than V_UV, and

V_{OV_L}is the OVLO threshold when the input supply is low; i.e., less than V_OV

Referring to Figure 10a, Equation 10 and Equation 11 produce R2 = 4.909 kW (4.99 kΩ selected) and R3 =

3.951 kΩ (3.92 kΩ selected), as shown. For the selected values, the expected nominal supply thresholds are

V_{UV_L}= 32.8 V, V_{UV_H}= 30.8 V, and V_{OV_L}= 72.6 V. The hysteresis of the overvoltage threshold, as seen at the

supply inputs, is given by the quantity (10 µA) × (R1 + R2). For the majority of applications, this value is almost

the same as the UV hysteresis, since typically R1 >> R2.

If more independent control is needed for the OVLO hysteresis, there are several options. One option is to use

separate dividers for both the UV and OV pins, as shown in Figure 10b. In this case, once R1 and R8 have been

selected for the required hysteresis per Equation 9, and values for the bottom resistors in the divider (R2 and R9

in Figure 10b) can be calculated using Equation 12.

REF

´ R

(TOP)

XVLO

(

- V

REF

)

XV_L

(12)

Where:

R_XVLOis R2 or R9

R_(TOP)is R1 or R8 as appropriate for the threshold being set

V_{XV_L}is the under (V_{UV_L}) or overvoltage (V_{OV_L}) threshold at the supply input, and

V_REFis either V_THUVor V_THOVfrom the specification table, as required for the resistor being calculated.

Reverse Voltage Protection

In some applications, it may be necessary to protect the TPS2394 against reverse polarity supply connections or

input transients. If the potential at SOURCE pin rises above that of the RTN pin, device damage may result. If

the application environment is such that these conditions are anticipated, a small-signal diode should be inserted

between the supply return bus and the TPS2394 RTN pin, as shown in the Typical Application diagram. A 75-V

to 100-V rated device (VRRM), such as MMBD4148 or BAV19, is recommended.

Product Folder Link(s): TPS2394

PACKAGE OPTION ADDENDUM

www.ti.com

4-Dec-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TPS2394PW

ACTIVE

TSSOP

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Request Free Samples

TPS2394PWR

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Purchase Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

0,10

0,65

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TPS2394PWR [TI]

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