TPS2413PWRG4 [TI]
N+1 and ORing Power Rail Controller; N + 1或运算电源导轨控制器
| 型号： | TPS2413PWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | N+1 and ORing Power Rail Controller |
| 文件： | 总21页 (文件大小：742K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2412
TPS2413
www.ti.com
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
N+1 and ORing Power Rail Controller
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
Control External FET for N+1 and ORing
Wide Supply Voltage Range of 3 V to 16.5 V
Controls Buses From 0.8 V to 16.5 V
The TPS2412/13 controller, in conjunction with an
external N-channel MOSFET, emulates the function
of a low forward voltage diode. The TPS2412/13 can
be used to combine multiple power supplies to a
common bus in an N+1 configuration, or to combine
redundant input power buses. The TPS2412
provides a linear turn-on control while the TPS2413
has an on/off control method.
Linear or On/Off Control Method
Internal Charge Pump for N-Channel MOSFET
Rapid Device Turnoff Protects Bus Integrity
Positive Gate Control on Hot Insertion
Soft Turn on Reduces Bus Transients
Industrial Temperature Range: –40°C to 85°C
Industry-Standard 8-pin TSSOP Package
Applications for the TPS2412/13 include a wide
range of systems including servers and telecom.
These applications often have either N+1 redundant
power supplies, redundant power buses, or both.
Redundant power sources must have the equivalent
of a diode OR to prevent reverse current during
faults and hotplug. A TPS2412/13 and N-channel
MOSFET provide this function with less power loss
than a schottky diode.
APPLICATIONS
•
•
•
•
N+1 Power Supplies
Server Blades
Telecom Systems
High Availability Systems
Accurate voltage sensing and
turn-off threshold allows operation to be tailored for a
wide range of implementations and bus
a programmable
A
C
characteristics. The TPS2412/13 are lower pin count,
feature reduced versions of the TPS2410/11.
Table 1. Family Features
Linear gate control
ON/OFF gate control
Adjustable turn-off threshold
Fast comparator filtering
Voltage monitoring
Enable control
√
√
√
√
√
√
√
√
√
√
√
√
TPS2412 /13
√
√
√
√
√
√
Mosfet fault monitoring
Status pin
NOTE: R
(SET)
is Optional
Figure 1. Typical Application
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
DEVICE
TPS2412
TPS2413
TEMPERATURE
PACKAGE(2)
ORDERING CODE
TPS2412PW
MARKING
TPS2412
TPS2413
–40°C to 85°C
PW (TSSOP - 8)
TPS2413PW
(1) Add an R suffix to the device type for tape and reel.
(2) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range, voltage are referenced to GND (unless otherwise noted)
VALUE
UNIT
V
A, C, FLTR, VDD, voltage
A above C voltage
–0.3 to 18
7.5
V
C above A voltage
18
V
GATE(2), BYP voltage
–0.3 to 30
–0.3 to 13
0.3
V
BYP to A voltage
V
GATE above BYP(2) voltage
RSET(2) voltage
V
–0.3 to 7
Indefinite
2
V
GATE short to A or C or GND
Human body model
kV
V
ESD
Charged device model
Maximum junction temperature
Storage temperature
500
TJ
Internally limited
–65 to 150
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage should not be applied to these pins.
DISSIPATION RATINGS
POWER RATING
PACKAGE
θJA– Low k °C/W
θJA– High k °C/W
High k
TA = 85°C (mW)
PW (TSSOP)
258
159
250
2
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
RECOMMENDED OPERATING CONDITIONS
voltages are referenced to GND (unless otherwise noted)
MIN
3
NOM
MAX
16.5
16.5
5
UNIT
(1)
VDD = V(C)
A, C
Input voltage range TPS2412
V
3 ≤ VDD ≤ 16.5 V
0.8
A to C
R(RSET)
C(BYP)
TJ
Operational voltage
Resistance range(2)
Capacitance Range(2)(3)
Operating junction temperature
Operating free-air temperature
V
1.5
800
–40
–40
∞
kΩ
pF
°C
°C
2200
10k
125
85
TA
(1) VDD must exceed 3 V to meet gate drive specification
(2) Voltage should not be applied to these pins.
(3) Capacitors should be X7R, 20% or better
ELECTRICAL CHARACTERISTICS(1)(2)(3)(4)(5)(6)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V(A), V(C), VDD
VDD rising
2.25
2.5
V
VDD UVLO
Hysteresis
0.25
0.66
0.1
| I(A) |, Gate in active region
| I(A) |, Gate saturated high
| I(C) |, V(AC) ≤ 0.1 V
Worst case, gate in active region
Gate saturated high
1
A current
C current
VDD current
TURN ON
mA
10
6
µA
4.25
1.2
mA
TPS2412 forward turn-on and regulation
voltage
7
7
10
13
13
mV
TPS2412 forward turn-on / turn-off difference R(RSET) = open
TPS2413 forward turn-on voltage
TURN OFF
7
mV
mV
10
Gate sinks > 10 mA at V(GATE-A) = 2 V
V(A-C) falling, R(RSET) = open
V(A-C) falling, R(RSET) = 28.7 kΩ
V(A-C) falling, R(RSET) = 3.24 kΩ
1
-17
3
-13.25
-142
5
-10
Fast turn-off threshold voltage
mV
-170
-114
V(A) = 12 V, V(A-C): 20 mV → – 20 mV,
V(GATE-A) begins to decrease
Turn-off delay
Turn-off time
70
ns
ns
V(A) = 12 V, C(GATE-GND) = 0.01 µF, V(A-C)
20 mV → – 20 mV, measure the period to
:
130
V(GATE) = V(A)
GATE
VDD = 3 V, V(A-C) = 20 mV
6
9
7
10.2
290
5
8
11.5
350
Gate positive drive voltage, V(GATE-A)
V
5 V ≤ VDD ≤ 18 V, V(A-C) = 20 mV
V(A-C) = 50 mV, V(GATE-A) = 4 V
V(A-C) = 4 mV, V(GATE-A) = 2 V
Gate source current
250
2
µA
Soft turn-off sink current (TPS2412)
mA
(1) [3 V ≤ V(A) ≤ 18 V and V(C) = VDD] or [0.8 V ≤ V(A) ≤ 3 V and 3 V ≤ VDD ≤ 18 V]
(2) C(BYP) = 2200 pF, R(RSET) = open
(3) –40°C ≤ TJ≤ 125°C
(4) Positive currents are into pins
(5) Typical values are at 25°C
(6) All voltages are with respect to GND.
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V(A-C) = –0.1 V
V(GATE) = 8 V
V(GATE) = 5 V
Period
1.75
1.25
7.5
2.35
1.75
12.5
A
Fast turn-off pulsed current, I(GATE)
µs
V(A-C) = –0.1 V, V(C) ≤ VDD, 3 V ≤ VDD ≤ 18 V,
2 V ≤ V(GATE) ≤ 18 V
Sustain turn-off current, I(GATE)
15
19.5
mA
MISCELLANEOUS
Thermal shutdown temperature
Thermal hysteresis
Temperature rising, TJ
135
10
°C
°C
FUNCTIONAL BLOCK DIAGRAM
10 V
A
V
(DD)
Charge Pump
and Bias Supply
BYP
HVUV
‘12: AMP
‘13: COMP
+
-
A
10 mV
GATE
C
0.5 V
3 mV
RSET
EN
FAST
COMP.
-
+
A
EN
C
T >135°C
RSVD
GND
BIAS
and
Control
V
(BIAS)
V
(DD)
EN
HVUV
4
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
PW PACKAGE
(TOP VIEW)
V
BYP
8
5
DD
1
4
RSET
RSVD
GND
A
C
GATE
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
I/O
DESCRIPTION
Input power for the gate drive charge pump and internal controls. VDD must be connected to a supply voltage
≥ 3 V.
VDD
1
2
PWR
I
Connect a resistor to ground to program the turn-off threshold. Leaving RSET open results in a slightly
positive V(A-C) turn-off threshold.
RSET
RSVD
GND
3
4
5
PWR This pin must be connected to GND.
PWR Device ground.
GATE
O
Connect to the gate of the external MOSFET. Controls the MOSFET to emulate a low forward-voltage diode.
Voltage sense input that connects to the simulated diode cathode. Connect to the MOSFET drain in the
typical configuration.
C
6
I
Voltage sense input that connects to the simulated diode anode. A also serves as the reference for the
charge-pump bias supply on BYP. Connect to the MOSFET source in the typical configuration.
A
7
8
I
BYP
I/O
Connect a storage capacitor from BYP to A to filter the gate drive supply voltage.
5
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
DETAILED DESCRIPTION
The following descriptions refer to the pinout and the functional block diagram.
A, C: The A pin serves as the simulated diode anode and the C as the cathode. GATE is driven high when V(AC)
exceeds 10 mV. Both devices provide a strong GATE pull-down when V(AC) is less than the programmable fast
turn-off threshold. The TPS2412 has a soft pull-down when V(AC) is less than 10 mV but above the fast turn-off
threshold.
Several internal comparator and amplifier circuits monitor these two pins. The inputs are protected from excess
differential voltage by a clamp diode and series resistance. If C falls below A by more than about 0.7 V, a small
current flows out of C. Protect the internal circuits with an external clamp if C can be more than 6 V lower
than A.
The internal charge pump output, which provides bias power to the comparators and voltage to drive GATE, is
referenced to A. Some charge pump current appears on A due to this topology. The A and C pins should be
Kelvin connected to the MOSFET source and drain. A and C connections should also be short and low
impedance, with special attention to the A connection. Residual noise from the charge pump can be reduced
with a bypass capacitor at A if the application permits.
BYP: BYP is the internal charge pump output, and the positive supply voltage for internal comparator circuits
and GATE driver. A capacitor must be connected from BYP to A. While the capacitor value is not critical, a
2200-pF ceramic is recommended. Traces to this part must be kept short and low impedance to provide
adequate filtering. Shorting this pin to a voltage below A damages the TPS2412/13.
GATE: Gate controls the external N channel MOSFET gate. GATE is driven positive with respect to A by a
driver operating from the voltage on BYP. A time-limited high current discharge source pulls GATE to GND when
the fast turn-off comparator is activated. The high-current discharge is followed by a sustaining pull-down. The
turn-off circuits are disabled by the thermal shutdown, leaving a resistive pull-down to keep the gate from
floating. The gate connection should be kept low impedance to maximize turn-off current.
GND: This is the input supply reference. GND should have a low impedance connection to the ground plane. It
carries several Amperes of rapid-rising discharge current when the external MOSFET is turned off, and also
carries significant charge pump currents.
RSET: A resistor connected from this pin to GND sets the fast V(A-C) comparator turn-off threshold. The
threshold is slightly positive when the RSET pin is left open. Current drawn by the resistor programs the turn-off
voltage to increasing negative values. The TPS2413 must have a negative threshold programmed to avoid an
unstable condition at light load. The expression for R(RSET) in terms of the trip voltage, V(OFF), follows.
æ
ç
ç
è
ö
÷
÷
ø
-470.02
- 0.00314
R
=
(RSET)
V
(OFF)
(1)
The units of the numerator are (V × V/A). V(OFF) is positive for V(A) greater than V(C), V(OFF) is less than 3 mV,
and R(RSET) is in ohms.
RSVD: Connect to ground.
VDD: VDD is the primary supply for the gate drive charge pump and other internal circuits. This pin must be
connected a source that is 3 V or greater when the external MOSFET is to be turned on. VDD may be greater or
lower than the controlled bus voltage.
A 0.01-µF bypass capacitor, or 10-Ω and a 0.01-µF filter, is recommended because charge pump currents are
drawn through VDD
.
6
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS
TPS2412 V(AC) REGULATION
VOLTAGE
vs
FAST TURNOFF THRESHOLD
PULSED GATE SINKING CURRENT
vs
vs
TEMPERATURE
TEMPERATURE
GATE VOLTAGE
3.0
12.0
11.5
5.0
4.5
R
= Open
(RSET)
T
= -40oC
J
2.5
2.0
11.0
10.5
4.0
3.5
T
= 25oC
J
T
= 85oC
J
1.5
1.0
0.5
0.0
10.0
9.5
3.0
2.5
2.0
T
= 125oC
J
9.0
8.5
8.0
1.5
1.0
0
2
4
6
8
10
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
V
− V
T
− Junction Temperature − o
C
T
− Junction Temperature − o
C
(GATE - GND)
J
J
Figure 2.
Figure 3.
Figure 4.
TURNON DELAY
vs
VDD CURRENT
vs
VDD
(POWER APPLIED UNTIL GATE IS
ACTIVE)
VDD VOLTAGE
(GATE SATURATED HIGH)
60
50
3.0
2.5
2.0
T
= -40oC
J
T
= 25oC
40
30
20
J
T
= 125oC
J
T
= 25oC
J
1.5
1.0
0.5
0.0
T
= -40oC
J
T
= 125oC
J
10
0
2
4
6
8
10
12
14
16
18
2
4
6
8
10
− V
12
14
16
18
V
− V
V
DD
DD
Figure 5.
Figure 6.
7
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)
TYPICAL TURNOFF WITH TWO ORED DEVICES ACTIVE
(VDD = 12 V, I(LOAD) = 5 A, IRL3713,
TRANSIENT APPLIED TO LEFT SIDE)
V(AC) (Left)
V(GATE) (Right)
at 5 V/div
at 20 mV/div
V(AC)
V(GATE) (Left)
at 5 V/div
GATE
50 ns/div
Figure 7.
TYPICAL TURNOFF AND RECOVERY WITH TWO ORED DEVICES ACTIVE
(VDD = 3 V, VA = 18 V, I(LOAD) = 5 A, IRL3713,
TRANSIENT APPLIED TO LEFT SIDE)
V(AC) (Left)
at 10 mV/div
V(IN)
V(IN) (Right)
V(AC)
at 20 mVac/div
V(GATE) (Right)
at 10 V/div
V(GATE) (Left)
at 10 V/div
GATE
500 μs/div
Figure 8.
8
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)
TURNOFF TIME WITH
C(GATE) = 10 nF and V(AC) = -20 mV (VDD = VA = 12 V)
V(GATE)
at 5 V/div
V(AC)
at 20 mV/div
I(GATE)
V(AC)
at 2 A/div
I(GATE
GATE
Delay = 68 ns, V(GATE) = 12 V at 103 ns
20 ns/div
Figure 9.
TURNOFF TIME WITH
C(GATE) = 10 nF and V(AC) = -20 mV (VDD = 5, VA = 1 V)
V(GATE)
at 2 V/div
V(AC)
V(AC)
at 20 mV/div
I(GATE)
at 2A/div
I(GATE
GATE
Delay = 70 ns, V(GATE) = 1 V at 113 ns
20 ns/div
Figure 10.
9
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
APPLICATION INFORMATION
OVERVIEW
The TPS2412/13 is designed to allow an output ORing in N+1 power supply applications (see Figure 12), and an
input-power bus ORing in redundant source applications (see Figure 13). The TPS2412/13 and external
MOSFET emulate a discrete diode to perform this unidirectional power combining function. The advantage to
this emulation is lower forward voltage drop and the ability to tune the operation.
The TPS2412 turns the MOSFET on with a linear control loop that regulates V(AC) to 10 mV as shown in
Figure 11. With the gate low, and V(AC) increasing to 10 mV, the amplifier drives GATE high with all available
output current until regulation is reached. The regulator controls V(GATE) to maintain V(AC) at 10 mV as long as
the MOSFET rDS(on) × I(DRAIN) is less than this the regulated voltage. The regulator drives GATE high, turning the
MOSFET fully ON when the rDS(on) × I(DRAIN) exceeds 10 mV; otherwise, V(GATE) will be near V(A) plus the
MOSFET gate threshold voltage. If the external circuits force V(AC) below 10 mV and above the programmed fast
turnoff, GATE is slowly turned off. GATE is rapidly pulled to ground if V(AC) falls to the RSET programmed fast
turn-off threshold.
The TPS2413 turns the MOSFET on and off like a comparator with hysteresis as shown in Figure 11. GATE is
driven high when V(AC) exceeds 10 mV, and rapidly turned off if V(AC) falls to the RSET programmed fast turn-off
threshold.
System designs should account for the inherent delay between a TPS2412/13 circuit becoming forward biased,
and the MOSFET actually turning ON. The delay is the result of the MOSFET gate capacitance charge from
ground to its threshold voltage by the 290 µA gate current. If there are no additional sources holding the ORed
rail voltage up, the MOSFET internal diode will conduct and maintain voltage on the ORed output, but there will
be some voltage droop. This condition is analogous to the power source being ORed in this case. The DC/DC
converter output voltage droops when its load increases from zero to a high value. Load sharing techniques that
keep all ORed sources active solve this condition.
TPS2413
(See Text)
TPS2412
Slow Turn-off
Range
(See Text)
Gate
ON
V
+ 10 V
(A)
Active
Regulation
Gate
OFF
Gnd
V
+ V
(T)
(A)
V
V
(AC)
(AC)
Programmable
Fast Turn-off
Threshold
Programmable
Fast Turn-off
Threshold
Figure 11. TPS2412/13 Operation
The operation of the two parts is summarized in Table 2.
Table 2. Operation as a Function of VAC
Turnoff Threshold(1) ≤ VAC ≤ 10 mV
V
(AC) ≤ Turnoff Threshold(1)
V(AC) > 10 mV
(MOSFET
V(AC) Forced < 10 mV
rDS(on) × ILOAD) ≤ 10 mV
Weak GATE pull-down
(OFF)
TPS2412 Strong GATE pull-down (OFF)
TPS2413 Strong GATE pull-down (OFF)
V(AC) regulated to 10 mV
GATE pulled high (ON)
GATE pulled high (ON)
Depends on previous state (Hysteresis region)
(1) Turnoff threshold is established by the value of RSET.
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
TPS2412 vs TPS2413 – MOSFET CONTROL METHODS
The TPS2412 control method yields several benefits. First, the low-current GATE driver provides a gentle
turn-on and turn-off for slowly rising and falling input voltage. Second, it reduces the tendency for on/off cycling
of a comparator based solution at light loads. Third, it avoids reverse currents if the fast turn-off threshold is left
positive. The drawback to this method is that the MOSFET appears to have a high resistance at light load when
the regulation is active. A momentary output voltage droop occurs when a large step load is applied from a
light-load condition. The TPS2412 is a better solution for a mid-rail bus that is re-regulated.
The TPS2413 turns the MOSFET on if V(AC) is greater than 10 mV, and the rapid turn-off is activated at the
programmed negative threshold. There is no linear control range and slow turn-off. The disadvantage is that the
turn-off threshold must be negative (unless a minimum load is always present) permitting a continuous reverse
current. Under a dynamic reverse voltage fault, the lower threshold voltage may permit a higher peak reverse
current. There are a number of advantages to this control method. Step loads from a light load condition are
handled without a voltage droop beyond I × R. If the redundant converter fails, applications with redundant
synchronous converters may permit a small amount of reverse current at light load in order to assure that the
MOSFET is all ready on. The TPS2413 is a better solution for low-voltage buses that are not re-regulated, and
that may see large load steps transients.
These applications recommendations are meant as a starting point, with the needs of specific implementations
over-riding them.
N+1 POWER SUPPLY – TYPICAL CONNECTION
The N+1 power supply configuration shown in Figure 12 is used where multiple power supplies are paralleled for
either higher capacity, redundancy or both. If it takes N supplies to power the load, adding an extra, identical unit
in parallel permits the load to continue operation in the event that any one of the N supplies fails. The supplies
are ORed together, rather than directly connected to the bus, to isolate the converter output from the bus when it
is plugged-in or fails short. The TPS2412/13 with an external MOSFET emulates the function of the ORing
diode.
It is possible for a malfunctioning converter in an ORed topology to create a bus overvoltage if the loading is less
than the converter's capacity (e.g. N = 1). The ORed topology shown cannot protect the bus from this condition,
even if the ORing MOSFET can be turned off. One common solution is to use two MOSFETs in a back-to-back
configuration to provide bidirectional blocking. The TPS2412/13 does not have a provision for forcing the gate off
when the overvoltage condition occurs, use of the TPS2410/11 is recommended.
ORed supplies are usually designed to share power by various means, although the desired operation could
implement an active and standby concept. Sharing approaches include both passive, or voltage droop, and
active methods. Not all of the output ORing devices may be ON depending on the sharing control method, bus
loading, distribution resistences, and TPS2412/13 settings.
Implementation
Power
Bus
Concept
DC/DC
Converter
Input
Voltage
DC/DC
Converter
Figure 12. N+1 Power Supply Example
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
INPUT ORing – TYPICAL CONNECTION
Figure 13 shows how redundant buses may be ORed to a common point to achieve higher reliability. It is
possible to have both MOSFETs ON at once if the bus voltages are matched, or the combination of tolerance
and regulation causes both TPS2412/13 circuits to see a forward voltage. The ORing MOSFET disconnects the
lower-voltage bus, protecting the remaining bus from potential overload by a fault.
Backplane
Power Buses
Concept
Implementation
Common
Buses
DC/DC
Converter
Hotswap
LOAD
Plug-In Unit
Figure 13. Example ORing of Input Power Buses
SYSTEM DESIGN AND BEHAVIOR WITH TRANSIENTS
The power system, perhaps consisting of multiple supplies, interconnections, and loads, is unique for every
product. A power distribution has low impedance, and low loss, which yields high Q by its nature. While the
addition of lossy capacitors helps at low frequencies, their benefit at high frequencies is compromised by
parasitics. Transient events with rise times in the 10 ns range may be caused by inserting or removing units,
load fluctuations, switched loads, supply fluctuations, power supply ripple, and shorts. These transients cause
the distribution to ring, creating a situation where ORing controllers may trip off unnecessarily. In particular,
when an ORing device turns off due to a reverse current fault, there is an abrupt interruption of the current,
causing a fast ringing event. Since this ringing occurs at the same point in the topology as the other ORing
controllers, they are the most likely to be effected.
The ability to operate in the presence of noise and transients is in direct conflict with the goal of precise ORing
with rapid response to actual faults. A fast response reduces peak stress on devices, reduces transients, and
promotes un-interrupted system operation. However, a control with small thresholds and high speed is most
likely to be falsely tripped by transients that are not the result of a fault. The power distribution system should be
designed to control the transient voltages seen by fast-responding devices such as ORing and hotswap devices.
While some applications may find it possible to use RSET to avoid false tripping, the TPS2410/11 provides
features beyond the TPS2412/13 including fast-comparator input filtering and STAT to dynamically shift the
turn-off threshold.
RECOMMENDED OPERATING RANGE
The maximum recommended bus voltage is lower than the absolute maximum voltage ratings on A, C, and VDD
solely to provide some margin for transients on the bus. Most power systems experience transient voltages
above the normal operating level. Short transients, or voltage spikes, may be clamped by the ORing MOSFET to
an output capacitor and/or voltage rail depending on the system design. Transient protection, e.g. a TVS diode
(transient voltage suppressor, a type of Zener diode), may be required on the input or output if the system
design does not inherently limit transient voltages below the TPS2412/13 absolute maximum ratings. If a TVS is
required, it must protect to the absolute maximum ratings at the worst case clamping current. The TPS2412/13
will operate properly up to the absolute maximum voltage ratings on A, C, and VDD
.
12
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
TPS2412 REGULATION-LOOP STABILITY
The TPS2412 uses an internal linear error amplifier to keep the external MOSFET from saturating at light load.
This feature has the benefits of setting a turn-off above 0 V, providing a soft turn-off for slowly decaying input
voltages, and helps droop-sharing redundancy at light load.
Although the control loop has been designed to accommodate a wide range of applications, there are a few
guidelines to be followed to assure stability.
•
•
Select a MOSFET C(ISS) of 1 nF or greater
Use low ESR bulk capacitors on the output C terminal, typically greater than 100µF with less than 50 mΩ
ESR
•
Maintain some minimum operational load (e.g. 10 mA or more)
Symptoms of stability issues include V(AC) undershoot and possible fast turn-off on large-transient recovery, and
a worst-case situation where the gate continually cycles on and off. These conditions are solved by following the
rules above. Loop stability should not be confused with tripping the fast comparator due to V(AC) tripping the gate
off.
Although not common, a condition may arise where the dc/dc converter transient response may cause the
GATE to cycle on and off at light load. The converter experiences a load spike when GATE transitions from OFF
to ON because the ORed bus capacitor voltage charges abruptly by as much as a diode drop. The load spike
may cause the supply output to droop and overshoot, which can result in the ORed capacitor peak charging to
the overshoot voltage. When the supply output settles to its regulated value, the ORed bus may be higher than
the source, causing the TPS2412/13 to turn the GATE off. While this may not actually cause a problem, its
occurrence may be mitigated by control of the power supply transient characteristic and increasing its output
capacitance while increasing the ORed load to capacitance ratio. Adjusting the TPS2412/13 turn-off threshold to
desensitize the redundant ORing device may help as well. Careful attention to layout and charge-pump noise
around the TPS2412/13 helps with noise margin.
The linear gate driver has a pull-up current of 290 µA and pull-down current of 3 mA typical.
MOSFET SELECTION AND R(RSET)
MOSFET selection criteria include voltage rating, voltage drop, power dissipation, size, and cost. The voltage
rating consists of both the ability to withstand the rail voltage with expected transients, and the gate breakdown
voltage. The MOSFET gate rating should be the minimum of 12 V, or the controlled rail voltage. Typically this
requires a ±20-V GATE voltage rating.
While rDS(on) is often chosen with the power dissipation, voltage drop, size and cost in mind, there are several
other factors to be concerned with in ORing applications. When using the TPS2412, the minimum voltage across
the device is 10 mV. A device that would have a lower voltage drop at full-load would be overspecified. When
using a TPS2413 or TPS2412 with RSET programmed to a negative voltage, the permitted static reverse current
is equal to the turn-off threshold divided by the rDS(on). While this current may actually be desirable in some
systems, the amount may be controlled by selection of rDS(on) and RSET. The practical range of rDS(on) for a
single MOSFET runs from the low milliohms to 40 mΩ for a single MOSFET.
MOSFETs may be paralleled for lower voltage drop (power loss) at high current. For TPS2412 operation, one
should plan for only one of the MOSFETs to carry current until the 10 mV regulation point is exceeded and the
loop forces GATE fully ON. TPS2413 operation does not rely on linear range operation, so the MOSFETs are all
ON or OFF together except for short transitional times. Beyond the control issues, current sharing depends on
the resistance match including both the rDS(on) and the connection resistance.
The TPS2412 may be used without a resistor on RSET. In this case, the turnoff V(AC) threshold is about 3 mV.
The TPS2413 may only be operated without an RSET programming resistor if the loading provides a higher
V(AC). A larger negative turnoff threshold reduces sensitivity to false tripping due to noise on the bus, but permits
larger static reverse current. Installing a resistor from RSET to ground creates a negative shift in the fast turn-off
threshold per Equation 2.
æ
ç
ç
è
ö
÷
÷
ø
-470.02
- 0.00314
R
=
(RSET)
V
(OFF)
(2)
13
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
To obtain a -10 mV fast turnoff ( V(A) is less than V(C) by 10 mV ), R(RSET) = (–470.02/ ( –0.01–0.00314) ) ≈
35,700Ω. If a 10 mΩ rDS(on) MOSFET was used, the reverse turnoff current would be calculated as follows.
V
(THRESHOLD)
I
=
(TURN_OFF)
r
DS(on)
-10 mV
10 mW
I
I
=
=
(TURN_OFF)
- 1 A
(TURN_OFF)
(3)
The sign indicates that the current is reverse, or flows from the MOSFET drain to source ( C to A ).
The turn-off speed of a MOSFET is influenced by the effective gate-source and gate-drain capacitance (CISS).
Since these capacitances vary a great deal between different vendor parts and technologies, they should be
considered when selecting a MOSFET where the fastest turn-off is desired.
GATE DRIVE, CHARGE PUMP AND C(BYP)
Gate drive of 270 µA typical is generated by an internal charge pump and current limiter. A separate supply,
VDD, is provided to avoid having the large charge pump currents interfere with voltage sensing by the A and C
pins. The GATE drive voltage is referenced to V(A) as GATE will only be driven high when V(A) > V(C). The
recommended capacitor on BYP (bypass) must be used in order to form a quiet supply for the internal
high-speed comparator. V(GATE) must not exceed V(BYP)
.
VDD, BYP, and POWERING OPTIONS
The separate VDD pin provides flexibility for operational power and controlled rail voltage. While the internal
UVLO has been set to 2.5 V, the TPS2412/13 requires at least 3 V to generate the specified GATE drive
voltage. Sufficient BYP voltage to run internal circuits occurs at VDD voltages between 2.5 V and 3 V. There are
three choices for power, A, C, or a separate supply, two of which are demonstrated in Figure 14. One choice for
voltage rails over 3.3 V is to power from C, since it is typically the source of reliable power. Voltage rails below
3.3 V nominal, e.g. 2.5 V and below, should use a separate supply such as 5 V. A separate VDD supply can be
used to control voltages above it, for example 5 V powering VDD to control a 12-V bus.
VDD is the main source of power for the internal control circuits. The charge pump that powers BYP draws most
of its power from VDD. The input should be low impedance, making a bypass capacitor a preferred solution. A
10-Ω series resistor may be used to limit inrush current into the bypass capacitor, and to provide noise filtering
for the supply.
BYP is the interconnection point between a charge pump, V(AC) monitor amplifiers and comparators, and the
gate driver. C(BYP) must be used to filter the charge pump. A 2200 pF is recommended, but the value is not
critical.
Common
Bus
Common
Bus
Common Bus Powering
Separate Bus Powering
5 V
10*
10*
Input
Input
Voltage
Voltage
0.8 V - 18 V
3.3 V - 18 V
* Optional Filtering
* Optional Filtering
Figure 14. VDD Powering Examples
14
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
ORing Examples
Applications with the TPS2412/13 are not limited to ORing of identical sections. The TPS2412/13 and external
MOSFET form a general purpose function block. Figure 15 shows a circuit with ORing between a discrete diode
and a TPS2412/MOSFET section. This circuit can be used to combine two different voltages in cases where the
output is reregulated, and the additional voltage drop in the Input 1 path is not a concern. An example is ORing
of an ac adapter on Input 1 with a lower voltage on Input 2.
Input 1
Input 2
Output
Figure 15. ORing Circuit
The TPS2412 may be a better choice in applications where inputs may be removed, causing an open-circuit
input. If the MOSFET was ON when the input is removed, VAC will be virtually zero. If the reverse turn-off
threshold is programmed negative, the TPS2412/13 will not pull GATE low. A system interruption could then be
created if a short is applied to the floating input. For example, if an ac adapter is first connected to the unit, and
then connected to the ac mains, the adapter's output capacitors will look like a momentary short to the unit. A
TPS2412 with RSET open will turn the MOSFET OFF when the input goes open circuit.
15
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TPS2412
TPS2413
SLVS728A–JANUARY 2007–REVISED FEBRUARY 2007
SUMMARIZED DESIGN PROCEDURE
The following is a summarized design procedure:
1. Choose between the TPS2412 or 2413, see TPS2412 vs TPS2413 – MOSFET Control Methods
2. Choose the VDD source. Table 3 provides a guide for where to connect VDD that covers most cases. VDD
may be directly connected to the supply, but an R(VDD) / C(VDD) of 10 Ω / 0.01 µF is recommended.
Table 3. VDD Connection Guide
VA < 3 V
Bias Supply > 3 V
3 V ≤ VA ≤ 3.6 V
VA > 3.6 V
VA or Bias Supply > 3 V. VC if always > 3 V
VC, VA, or Bias for special configurations
3. Noise voltage and impedance at the A pin should be kept low. C(A) may be required if there is noise on
the bus, or A is not low impedance. If either of these is a concern, a C(A) of 0.01 µF or more may be
required.
4. Select C(BYP) as 2200 pF, X7R, 25-V or 50-V ceramic capacitor.
5. Select the MOSFET based on considerations of voltage drop, power dissipated, voltage ratings, and gate
capacitance. See sections: MOSFET Selection and RSET and TPS2412 Regulation-Loop Stability.
6. Select R(RSET) based on which MOSFET was chosen and reverse current considerations – see MOSFET
Selection and RSET. If the noise and transient environment is not well known, make provision for R(RSET)
even when using the TPS2412.
7. Make sure to connect RSVD to ground
Layout Considerations
1. The TPS2412/13, MOSFET, and associated components should be used over a ground plane.
2. The GND connection should be short, with multiple vias to ground.
3. C(VDD) should be adjacent to the VDD pin with a minimal ground connection length to the plane.
4. The GATE connection should be short and wide (e.g., 0.025" minimum).
5. The C pin should be Kelvin connected to the MOSFET.
6. The A pin should be a short, wide, Kelvin connection to the MOSFET.
7. R(SET) should be kept immediately adjacent to the TPS2412/13 with short leads.
8. C(BYP) should be kept immediately adjacent to the TPS2412/13 with short leads.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
PACKAGING INFORMATION
Orderable Device
TPS2412PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
8
8
8
8
8
8
8
8
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2412PWG4
TPS2412PWR
TPS2412PWRG4
TPS2413PW
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2413PWG4
TPS2413PWR
TPS2413PWRG4
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
12
TPS2412PWR
TPS2413PWR
PW
PW
8
8
MLA
MLA
7.0
7.0
3.6
3.6
1.6
1.6
8
8
12
12
Q1
Q1
330
12
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TPS2412PWR
TPS2413PWR
PW
PW
8
8
MLA
MLA
342.9
342.9
336.6
336.6
20.64
20.64
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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