TPS24751RUVT [TI]
具有用于外部阻断 FET 的驱动器的 2.5V 至 18V、3mΩ、0.01A 至 12A 电子保险丝 | RUV | 36 | -40 to 85;
| 型号： | TPS24751RUVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有用于外部阻断 FET 的驱动器的 2.5V 至 18V、3mΩ、0.01A 至 12A 电子保险丝 | RUV | 36 | -40 to 85 电子 驱动 驱动器 |
| 文件： | 总47页 (文件大小：2418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS24750, TPS24751
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
带有电流监视器的 TPS2475x 12A 电子保险丝电路保护器
1 特性
3 说明
1
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2.5V 至 18V 总线运行
持续电流高达 12A
TPS2475x 可以为 2.5V 至 18V 应用提供高度集成的
负载 保护。该器件在单个适用于小外形尺寸应用的封
装内集成了一个热插拔控制器和一个 功率 MOSFET。
这些器件保护电源、负载和内部 MOSFET 不受潜在损
害事件的影响。在启动过程中，负载电流与 MOSFET
功率耗散被限制在用户选定值内。在启动之后，将允许
超过用户选定限值的电流流动，直至设定的超时为
止 — 负载与电源直接断开的极端过载情况除外。
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具有 3mΩ（典型值）RDS(on) 的集成 MOSFET
可编程电流限制
可编程 FET 安全运行区域 (SOA) 保护
从 10mA 至 12A 的高 ILimit 精度
可编程故障定时器
用于短路保护的快速断路器
可编程 VOUT 转换率，欠压 (UV) 和过压 (OV)
电源正常和故障输出
可编程 FET SOA 保护确保内部 MOSFET 始终在其安
全运行区域 (SOA) 内运行，并且负载以一个已定义的
斜升速率启动。这在提升系统稳定性的同时增加了内部
MOSFET 性能。针对系统状态监视以及下游负载控制
提供电源正常、故障和电流监视输出。
模拟负载电流监视器
热关断
通过 UL 2367 认证 – 文件编号 E339631
这些器件采用 36 引脚 7mm × 3.5mm QFN (RUV) 封
装，额定工作结温范围为 –40°C 至 +125°C。
2 应用
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服务器
高电流负载开关
通信设备
插件模块
RAID 系统
基站
器件信息(1)
器件型号
TPS24750
TPS24751
封装
封装尺寸（标称值）
VQFN
7.00mm × 3.50mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
风扇控制
应用原理图 (12V/10A)
Rsense
瞬态输出短路响应
0.002
RSET
51.1
130k
VCC SET
SENSE DRAIN
OUT
FLT
PG
EN
OV
IMON
10k
15k
GATE
PROG
GND
TIMER
470mF
1.58k
47nF
64.9k
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSC87
TPS24750, TPS24751
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Typical Characteristics.............................................. 8
Parameter Measurement Information ................ 13
Detailed Descriptions .......................................... 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 14
9.3 Feature Description ................................................ 15
9.4 Device Functional Modes........................................ 18
10 Application and Implementation........................ 25
10.1 Application Information.......................................... 25
10.2 Typical Application ................................................ 25
10.3 System Examples ................................................. 32
11 Power Supply Recommendations ..................... 34
11.1 Transient Thermal Impedance .............................. 34
12 Layout................................................................... 35
12.1 Layout Guidelines ................................................. 35
12.2 Layout Example .................................................... 35
13 器件和文档支持 ..................................................... 37
13.1 文档支持................................................................ 37
13.2 相关链接................................................................ 37
13.3 接收文档更新通知 ................................................. 37
13.4 社区资源................................................................ 37
13.5 商标....................................................................... 37
13.6 静电放电警告......................................................... 37
13.7 Export Control Notice............................................ 37
13.8 术语表 ................................................................... 38
14 机械、封装和可订购信息....................................... 38
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (November 2016) to Revision C
Page
•
已添加 将“通过 UL 2367 认证 – 文件编号 E339631”添加到了特性 部分................................................................................ 1
Changes from Revision A (September 2015) to Revision B
Page
•
•
Added designator C1 to Figure 41 ....................................................................................................................................... 26
Updated STEP 5. Select R1, R2, and R3 for UV and OV section ........................................................................................ 29
Changes from Original (October 2013) to Revision A
Page
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添加了 ESD 额定值 表、详细说明、特性 说明、器件功能模式、应用和实施、电源建议、器件和文档支持 以及机械、
封装和可订购信息................................................................................................................................................................... 1
已删除特性“FET 短路检测（TPS24752，TPS24753）” ....................................................................................................... 1
已更改应用原理图。已删除 CVIN 和 D1................................................................................................................................... 1
Deleted devices TPS24752 and TPS24753 from the data sheet........................................................................................... 3
Deleted list item from the Overview section: "Internal MOSFET short detection (TPS24752/3 only)"................................. 14
Removed notes for pin 30 and 31 from the Functional Block Diagram................................................................................ 14
Deleted section Fault Detection of Internal Mosfet Short..................................................................................................... 24
Changed Figure 40. Deleted CVIN and D1 ............................................................................................................................ 25
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Changed text in STEP 3. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT From: "maximum
steady state junction temperature (TJDMAX = TA(MAX) + ILIM2 x R(DS)ON)." To: " maximum steady state junction
temperature (TJDMAX = TA(MAX) + ILIM2 x R(DS)ON x RθJA)." ....................................................................................................... 28
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Changed Figure 46 and Figure 47. Deleted CVIN and D1..................................................................................................... 32
Added text and Figure 48 to System Examples ................................................................................................................... 33
Changed Figure 51 .............................................................................................................................................................. 35
Added Figure 52 .................................................................................................................................................................. 36
2
Copyright © 2013–2018, Texas Instruments Incorporated
TPS24750, TPS24751
www.ti.com.cn
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
5 Device Comparison Table
Operating Voltage
Part Number
Range
Function
Fault Response
Status
TPS24750RUV
TPS24751RUV
2.5 V-18 V
2.5 V-18 V
Integrated hot swap protector
Integrated hot swap protector
Latch
Active
Active
Auto retry
6 Pin Configuration and Functions
TPS24750, TPS24751 RUV Package
36-Pin VQFN
Top View
26
25
24
23
22
21
20
19
31
30
29
28
27
GND
EN
DRAIN
DRAIN
DRAIN
PROG
DRAIN
GND
DRAIN
DRAIN
TIMER
Thermal pad-2
Thermal pad-1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
The drain of the internal pass MOSFET. Connect to a terminal of current sense resistor in the
power path
DRAIN
5, 14-18, 27
I
EN
33
I
I
Active high enable input. Logic input. Connects to resistor divider
Active-low, open-drain output indicates overload fault timer has turned internal FET off
Gate driver output for the internal MOSFET
FLTb
GATE
GND
IMON
OUT
30
25
I/O
GND
O
4, 28, 32, 36
2
Ground
Load current analog and current limit program point. Connect RIMON to ground
6-13, 19-24
I/O
Internally connect to the source of internal pass MOSFET. Connect to output capacitors and load
Overvoltage comparator input. Connects to resistor divider. GATE is pulled low when OV exceeds
the threshold
OV
1
I
Pad-1
Pad-2
—
—
—
—
Tied to GND
Tied to DRAIN
Active-low, open-drain power good indicator. Status is determined by the voltage across the
MOSFET
PGb
31
O
Copyright © 2013–2018, Texas Instruments Incorporated
3
TPS24750, TPS24751
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
Power-limiting programming pin. A resistor from this pin to GND sets the maximum power
dissipation for the internal pass MOSFET
PROG
34
I
I
Current sensing input for resistor shunt from VCC to SENSE. Connect to a terminal of current
sense resistor
SENSE
26
SET
3
I
I/O
I
Current limit programming set pin. A resistor is connected from this pin to VCC
A capacitor connected from this pin to GND provides a fault timing function
Input voltage sense and power supply
TIMER
VCC
35
29
4
Copyright © 2013–2018, Texas Instruments Incorporated
TPS24750, TPS24751
www.ti.com.cn
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range, all voltages referred to GND (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
30
20
3.6
0.3
5
UNIT
V
DRAIN, EN, FLTb(2), GATE, OUT, PGb(2), SENSE, SET(2), VCC
OV
PROG(2)
Input voltage
[SET, SENSE] to VCC
IMON, TIMER
FLTb, PGb
PROG
Sink current
5
mA
Internally limited
Source current
IMON
5
mA
°C
TJ
Maximum junction temperature
Storage temperature
150
TSTG
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Do not apply voltage directly to these pins.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
OV
0
2.5
0
16
18
18
2
Input voltage
SENSE, SET(1), VCC(2)
EN, FLTb, GATE(2), PGb, OUT(2), DRAIN(2)
V
Sink current
Source current
Resistance
FLTb, PGb
IMON
0
mA
mA
kΩ
nF
0
1
PROG
4.99
1
500
TIMER
GATE(3)
External capacitance
1
µF
°C
TJ
Operating junction temperature
–40
125
(1) Do not apply voltage directly to these pins.
(2) See the Gate Clamp Diode section for additional precaution to be taken for operating voltages >14 V.
(3) External capacitance tied to GATE must be in series with a resistor no less than 1 kΩ.
7.4 Thermal Information
TPS2475x
RUV (VQFN)
36 PINS
33.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
28.2
5.8
ψJT
0.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2013–2018, Texas Instruments Incorporated
5
TPS24750, TPS24751
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
www.ti.com.cn
Thermal Information (continued)
TPS2475x
RUV (VQFN)
36 PINS
5.7
THERMAL METRIC(1)
UNIT
ψJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
RθJC(bot)
1.1
7.5 Electrical Characteristics
–40°C ≤ TJ ≤ +125°C, VCC = 12 V, VEN = 3 V, RSET = 191 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND. All voltages
referenced to GND, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
NOM
MAX UNIT
VCC
UVLO threshold, rising
UVLO threshold, falling
UVLO hysteresis(1)
2.20
2.10
2.32
2.22
0.1
2.45
2.35
V
V
V
Enabled ― IOUT + IVCC + ISENSE
Disabled(1) ― EN = 0 V, IOUT + IVCC + ISENSE
0.5
10
1
1.4 mA
mA
Supply current
0.45
OUT
1 A ≤ IOUT ≤ 10 A at TJ = 25°C
3
5
3.5 mΩ
RON
On-resistance
1 A ≤ IOUT ≤ 10 A at TJ = 125°C
6
30
mΩ
µA
V
Input bias current
VOUT = 12 V
16
Diode forward voltage
VEN = 0 V, IOUT = –100 mA, VOUT > VSENSE
VEN = 0 V, VOUT = 0 V, VDRAIN = 18 V at 25°C
VEN = 0 V, VOUT = 0 V, VDRAIN = 18 V at 125°C
0.8
0
1
1
µA
µA
pF
pF
pF
nC
nC
Leakage current - DRAIN to OUT
2
5
Ciss
Coss
Crss
Qg
Input capacitance
2710
635
48
3250
762
60
Output capacitance
VGS = 0 V, VDRAIN-OUT = 15 V, f = 1 MHz
Reverse transfer capacitance
Gate charge total (4.5 V)
Gate charge at Vth
17.5
4.1
21.5
VDRAIN-OUT = 15 V, IOUT = 20 A
Qg(th)
EN
Threshold voltage, falling
Hysteresis(1)
1.2
1.3
50
0
1.4
V
mV
µA
µs
µs
µs
Input leakage current
Turnoff time
0 V ≤ VEN ≤ 30 V
–1
3
1
25
EN ↓ to VGATE < 1 V
8
Deglitch time
EN ↑
8
14
0.4
21
Disable delay
EN ↓ to GATE ↓, CGATE = 0, tpff50–90, See Figure 28
0.1
1.8
COUT = 2.2 uF, VEN ↑ to VOUT ↑, VEN: 0 V to 3 V, VOUT : 90%
VCC
Turnon delay
800
µs
OV
Threshold voltage, rising
Hysteresis(1)
1.25
1.35
60
1.45
V
mV
µA
µs
Input leakage current
Deglitch time
0 V ≤ VOV ≤ 30 V
–1
0
1
OV rising
0.5
1.2
1.5
FLTb
PGb
Output low voltage
Sinking 2 mA
0.11
0
0.25
1
V
Input leakage current
VFLTb = 0 V, 30 V
–1
µA
Threshold
Hysteresis(1)
V(SENSE – OUT) rising, PGb going high
Measured V(SENSE – OUT) falling, PGb going low
Sinking 2 mA
140
220
70
340 mV
mV
Output low voltage
Input leakage current
0.11
0
0.25
1
V
VPGb = 0 V, 30 V
–1
µA
(1) These parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
6
Copyright © 2013–2018, Texas Instruments Incorporated
TPS24750, TPS24751
www.ti.com.cn
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
Electrical Characteristics (continued)
–40°C ≤ TJ ≤ +125°C, VCC = 12 V, VEN = 3 V, RSET = 191 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND. All voltages
referenced to GND, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
NOM
MAX UNIT
Delay (deglitch) time
Rising or falling edge
2
3.4
6
ms
PROG
TIMER
Bias voltage
Sourcing 10 µA
VPROG = 1.5 V
0.65
–0.2
0.675
0
0.7
0.2
V
Input leakage current
µA
Sourcing current
Sinking current
VTIMER = 0 V
8
8
10
10
12
12
µA
µA
mA
V
VTIMER = 2 V
VEN = 0 V, VTIMER = 2 V
2
4.5
7
Upper threshold voltage
Lower threshold voltage
1.3
0.33
1.35
0.35
1.4
0.37
V
Raise GATE until ITIMER sinking, measure V(GATE – VCC), VVCC
= 12 V
Timer activation voltage
Retry duty cycle
5
5.8
4%
7
V
During over current and short circuit conditions (TPS24751
only)
IMON
Circuit breaker threshold
650
–1
675
0
696 mV
mV
At TJ = 25°C
1
Input referred offset of servo amplifier
TJ from –40°C to +125°C
–1.5
0
1.5 mV
SET
Input referred offset of servo amplifier
Measure SET to SENSE
–1.5
0
1.5 mV
GATE
Output voltage
Clamp voltage
Sourcing current
VOUT = 12 V
23.5
12
20
0.4
6
25.7
13.9
30
28
15.5
40
V
V
Inject 10 µA into GATE, measure V(GATE – VCC)
VGATE = 12 V
µA
A
Fast turnoff, VGATE = 14 V
1
1.4
Sinking current
Sustained, VGATE = 4 V to 23 V
In inrush current limit, VGATE = 4 V to 23 V
Thermal shutdown or VEN = 0 V
11
20 mA
20
14
8
30
40
26
µA
kΩ
µs
µs
Pulldown resistance
Fast turnoff duration
20
13
18
Turnon delay
VVCC rising to GATE sourcing, tprr50-50, See Figure 29
100
375
SENSE
Input bias current
VSENSE = 12 V, sinking current
VOUT = 12 V
30
25
4
40
µA
Current limit threshold
22.5
27.5 mV
VDRAIN–OUT = 8 V, RPROG = 100 kΩ
VDRAIN–OUT = 8 V, RPROG = 50 kΩ
VDRAIN–OUT = 5.37 V, RPROG = 50 kΩ
VDRAIN–OUT = 10.3 V, RPROG = 25 kΩ
6.6
10
10
52
8
9.6
mV
14
Power limit threshold
12
12.5
60
15
Fast-trip threshold
Fast-turnoff delay(1)
68 mV
V(VCC – SENSE) = 80 mV, CGATE = 0 pF, tprf50–50, See
Figure 30
200
ns
OTSD
Threshold, rising
Hysteresis(1)
Temperature referenced to PAD1 of the device. See(2)
130
140
10
°C
°C
(2) The temperature difference between PAD1 and PAD2 must be minimized. See the SOA curve Figure 27 and Power-Limited Start-Up
section for temperature limited design.
Copyright © 2013–2018, Texas Instruments Incorporated
7
TPS24750, TPS24751
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
www.ti.com.cn
7.6 Typical Characteristics
1200
5
4
3
2
1
0
T = 125°C
1000
800
600
400
T = 25°C
T = 25°C
T = 125°C
T = –40°C
T = –40°C
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
Input Voltage, VVCC (V)
Input Voltage, VVCC (V)
EN = High
EN = 0 V
Figure 1. Supply Current vs Input Voltage at Normal
Operation
Figure 2. Supply Current vs Input Voltage at Shutdown
32
26.5
VCC Voltage = 12 V
VVCC = 12 V
28
26
25.5
25
VVCC = 2.5 V
24
T = 125°C
T = 25°C
20
16
T = –40°C
24.5
24
VVCC = 18 V
12
8
4
23.5
0
2
4
6
8
10
12
14
–50
–20
10
40
Temperature (°C)
70
100
130
Voltage, V(SENSE – OUT) (V)
Figure 3. Voltage Across RSENSE in Inrush Current Limiting
vs Temperature
Figure 4. Voltage Across RSENSE in Inrush Power Limiting vs
VDS of Internal FET
1.8
1.6
1.4
1.2
0.25
0.2
40
VVCC = 12 V
Gate Current at Current Limiting
VVCC Voltage = 12 V
32
T = –40°C
T = 25°C
0.15
0.1
24
16
1
0.05
0
T = 25°C
8
0.8
0.6
0.4
0.2
0
V(VCC – SENSE)
0
T = 125°C
–0.05
–0.1
–0.15
–0.2
–0.25
T = 125°C
–8
–16
T = –40°C
–24
–32
–40
–0.2
–10
0
10
20
30
40
Time (µs)
0
5
10 15 20 25 30 35 40 45 50 55
Voltage, V(VCC – SENSE) (mV)
VVCC = VGATE = 12 V
Figure 6. Gate Current During Fast Trip
Figure 5. Internal FET Gate Current vs Voltage Across
RSENSE During Inrush Power Limiting
8
Copyright © 2013–2018, Texas Instruments Incorporated
TPS24750, TPS24751
www.ti.com.cn
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
Typical Characteristics (continued)
0.9
0.25
0.2
32
28
24
20
16
12
8
0.7
T = 25°C
T = –40°C
0.6
0.15
0.1
T = 25°C
0.5
0.4
T = 125°C
0.05
0
0.3
0.2
V(VCC – SENSE)
T = 125°C
–0.05
–0.1
–0.15
–0.2
–0.25
T = –40°C
0.1
0
–0.1
–0.2
VVCC = 3.3 V
–10
0
10
20
30
40
Time (µs)
0
4
8
12
16
20
Input Voltage, VVCC (V)
VVCC = VGATE = 3.3 V
Figure 7. Gate Current During Fast Trip
Figure 8. Gate Voltage With Zero Gate Current vs Input
Voltage
7
2
T = 125°C
T = 25°C
VVCC = 12 V
CT = 10 nF
1.6
6
5
4
3
1.2
T = –40°C
CT = 4.7 nF
0.8
CT = 1 nF
0.4
0
–50
–20
10
40
70
100
130
0
4
8
12
16
20
Temperature (°C)
Input Voltage, VVCC (V)
Figure 10. Fault-Timer vs Temperature with Various TIMER
Capacitors
Figure 9. TIMER Activation Voltage Threshold vs Input
Voltage at Various Temperatures
1.6
2.36
VVCC = 12 V
UVLO Upper Threshold
1.4
1.2
2.32
EN Upper Threshold
1
0.8
0.6
2.28
UVLO Lower Threshold
0.4
2.24
VCC = 12 V
0.2
0
2.20
–50
0
50
Temperature (°C)
100
150
–50
–20
10
40
70
100
130
Temperature (°C)
Figure 11. EN Threshold Voltage vs Temperature
Figure 12. UVLO Threshold Voltage vs Temperature
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Typical Characteristics (continued)
240
64
63.5
63
PGb Rising
VVCC = 12 V
220
VVCC = 2.5 V
62.5
62
200
180
PGb Falling
61.5
61
160
VVCC = 18 V
60.5
140
–50
60
–20
10
40
Temperature (°C)
70
100
130
–50
–20
10
40
Temperature (°C)
70
100
130
Figure 13. Threshold Voltage of VDS vs Temperature, PGb
Rising and Falling
Figure 14. Fast-Trip Threshold Voltage vs Temperature
160
140
120
160
140
120
VVCC = 18 V
VVCC = 2.5 V
VVCC = 2.5 V
VVCC = 18 V
100
80
100
80
VVCC = 12 V
VVCC = 12 V
60
60
–50
–20
10
40
Temperature (°C)
70
100
130
–50
–20
10
40
70
100
130
Temperature (°C)
Figure 15. PGb Open-Drain Output Voltage in Low State
Figure 16. FLTb Open-Drain Output Voltage in Low State
1.344
0.7
VEN = 0 V
T = 125°C
1.342
0.6
VVCC = 18 V
VVCC = 12 V
T = 25°C
1.34
0.5
1.338
0.4
T = –40°C
VVCC = 2.5 V
1.336
0.3
1.334
0.2
–50
–20
10
40
Temperature (°C)
70
100
130
0
4
8
12
16
20
Input Voltage, VVCC (V)
Figure 18. Timer Upper Threshold Voltage vs Temperature
at Various Input Voltages
Figure 17. Supply Current vs Input Voltage at Various
Temperatures when EN Pulled Low
10
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Typical Characteristics (continued)
0.365
10.2
10.1
10
VVCC = 18 V
VVCC = 18 V
VVCC = 12 V
0.362
9.9
9.8
9.7
9.6
9.5
VVCC = 12 V
0.36
VVCC = 2.5 V
VVCC = 2.5 V
0.357
–50
–20
10
40
70
100
130
–50
–20
10
40
70
100
130
Temperature (°C)
Temperature (°C)
Figure 19. Timer Lower Threshold Voltage vs Temperature
at Various Input Voltages
Figure 20. Timer Sourcing Current vs Temperature at
Various Input Voltages
1.6
10.4
1.4
10.3
10.2
10.1
10
VVCC = 18 V
1.2
VVCC = 12 V
OV Upper Threshold
1
0.8
0.6
0.4
0.2
0
VVCC = 2.5 V
9.9
9.8
9.7
–50
0
50
Temperature (°C)
100
150
–50
–20
10
40
Temperature (°C)
70
100
130
Figure 22. OV Threshold Voltage vs Temperature
Figure 21. Timer Sinking Current vs Temperature at Various
Input Voltages
0.9
5
0.85
4.5
4
0.8
0.75
0.7
3.5
3
0.65
0.6
2.5
2
0.55
0.5
-50
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 24. Diode Drop vs Temperature
Figure 23. RDS(ON) vs Temperature
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Typical Characteristics (continued)
10
3
2.5
2
ID = 20A
VDS = 15V
8
6
4
2
0
1.5
1
0.5
0
-0.5
-50
0
5
10
15
20
25
30
35
40
0
50
100
150
g
Temperature (oC)
Q
- Gate Charge - nC (nC)
Figure 25. Gate Charge – Internal MOSFET
Figure 26. Leakage Current vs Temperature
1000
Area Limited
by RDS(on)
100
10
1 ms
10 ms
100 ms
1
Single Pulse
qJA = 62.3ºC/W
R
TA = 25ºC
0.1
0.1
1
10
100
VDS – Drain-to-Source Voltage – V
Figure 27. TPS2475x Maximum Safe Operating Area (SOA)
12
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ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
8 Parameter Measurement Information
VGATE
90%
VEN
50%
0
Time
t(pff50-90)
T0492-01
Figure 28. tpff50–90 Timing Definition
IGATE
50%
VVCC
50%
0
Time
t(prr50-50)
T0494-01
Figure 29. tprr50–50 Timing Definition
VGATE
50%
VVCC – VSENSE
50%
0
Time
t(prf50-50)
T0495-01
Figure 30. tprf50–50 Timing Definition
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9 Detailed Descriptions
9.1 Overview
The TPS2475x provides all the features needed for a positive hot-swap protector. These features include:
•
•
•
•
•
•
•
•
•
•
Undervoltage lockout
Adjustable (system-level) enable
Turnon inrush limiting
Integrated N-channel MOSFET
MOSFET protection by power limiting
Electronic circuit breaker operation with adjustable overload timeout
Charge-complete indicator for downstream converter coordination
A choice of latch or automatic restart mode
Load overvoltage protection
Precise current monitor output
The typical application diagram, shown on the front page of this data sheet, and oscilloscope plots, shown in
Figure 31 through Figure 33 and Figure 35 through Figure 39, demonstrate many of the functions of the device.
9.2 Functional Block Diagram
VIN
RSENSE
RSET
SET
SENSE
DRAIN
OUT
3
26
5
14 15 16 17 18 27
6
7
8
9
10 11 12 13 19 20 21 22 23 24
60mV
25 GATE
VCC
Charge
Pump
Inrush
Latch
DC
+
-
30uA
29
2
Gate
Comparator
Fast
Comparator
S
Q
Q
IMON
+
VCC
5.8 V
1- shot
R
Servo
Amplifier
0 ~ 60 uA
RIMON
+
A
B
+
-
PROG
PG
Comparator
34
3.4 mS
PGb
31
OUT
RPROG
20 kꢀ
+
UVLO
VCC
DC
+
+
2.32 V
2.22 V
220 mV
150 mV
33
EN
OV
1.35 V
1.30 V
14 uS
1.35 V
1.28 V
+
+
10.0 uA
10.0 uA
FLTb
30
1
Fault Logic
1.2 uS
VCC
+
TSD
1.50 V
1.35
0.35
POR
Turn off Main Circuit
36
GND
28
4
GND
GND
35
TIMER
CT
14
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ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
9.3 Feature Description
9.3.1 DRAIN
The drain of the internal pass MOSFET. Connect to a terminal of current sense resistor in the power path.
9.3.2 EN
Applying a voltage of 1.3 V or more to this pin enables the gate driver. The addition of an external resistor divider
allows the EN pin to serve as an undervoltage monitor. Cycling EN low and then back high resets the TPS24750
that has latched off due to a fault condition. This pin must not be left floating.
9.3.3 FLTb
This active-low open-drain output pulls low when the TPS2475x has remained in current limit long enough for the
fault timer to expire. The TPS24750 operates in latch mode while the TPS24751 operates in retry mode. In latch
mode, a fault timeout disables the internal MOSFET and holds FLTb low. The fault is reset when EN is pulled
low or VCC falls under UVLO. In retry mode, a fault timeout first disables the internal MOSFET, next waits
sixteen cycles of TIMER charging and discharging, and finally attempts a restart. This process repeats as long as
the fault persists. In retry mode, the FLTb pin is pulled low whenever the internal MOSFET is disabled by the
fault timer. In a sustained fault, the FLTb waveform becomes a train of pulses. The FLTb pin does not assert if
the internal MOSFET is disabled by EN, OV, overtemperature shutdown, or UVLO. This pin can be left floating
when not used.
9.3.4 GATE
This pin provides gate drive to the internal MOSFET. A charge pump sources 30 µA to enhance the internal
MOSFET. A 13.9 V clamp between GATE and VCC limits the gate-to-source voltage since VVCC is close to VOUT
in normal operation. During start up, a transconductance amplifier regulates the gate voltage of the internal FET
to provide inrush current limiting. The TIMER pin charges timer capacitor CT during the inrush. Inrush current
limiting continues until the V(GATE – VCC) exceeds the Timer Activation Voltage 5.8 V for VVCC = 12 V. Then the
TPS2475x enters into circuit breaker mode. In the circuit breaker mode, the current flowing in RSENSE is
compared with the current limit threshold derived from the MOSFET power limit scheme (see the PROG
definition). If the current flowing in RSENSE exceeds the current limit threshold, then the internal pass MOSFET
will be turned off. The GATE pin is disabled by the following three mechanisms:
1. GATE is pulled down by an 11-mA current source when
–
–
–
–
The fault timer expires during an overload current fault (VIMON > 675 mV)
VEN is below its falling threshold
VVCC drops below the UVLO threshold
VOV is above its rising threshold
2. GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V(VCC –
is greater than 60 mV, that is, the fast-trip shutdown threshold. After fast-trip shutdown is complete, an
SENSE)
11-mA sustaining current ensures that the internal FET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
GATE remains low in latch mode (TPS24750) and attempts a restart periodically in retry mode (TPS24751).
Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can
be left floating to obtain a predetermined slew rate on the output.
If used, any capacitor connecting GATE and GND must not exceed 1 μF and it must be connected in series with
a resistor of no less than 1 kΩ. No external resistor must be directly connected from GATE to GND or from
GATE to OUT.
9.3.5 GND
This pin is connected to system ground.
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Feature Description (continued)
9.3.6 IMON
A resistor connected from this pin to GND scales the current-limit and power-limit settings, as illustrated in the
Functional Block Diagram. The voltage present at this pin is proportional to the current flowing through sense
resistor RSENSE. This voltage can be used as a means of monitoring current flow through the system. The value
of RIMON can be calculated from Equation 3. This pin must not have a bypass capacitor or any other load except
for RIMON
.
9.3.7 OUT
This pin is connected to the source of the internal MOSFET inside the chip. It allows the device to measure the
drain-to-source voltage across the internal MOSFET. The power good indicator (PGb) relies upon this
information, as does the power limiting engine. The OUT pin must be bypassed to GND with a low-impedance
ceramic capacitor in the range of 10 nF to 1 μF. Connect all the OUT pins to output capacitors and load. In the
presence of cable inductance, the OUT pin must be protected from negative voltage transients by using a
clamping/Schottky diode.
9.3.8 OV
This pin is used to program the device overvoltage level. A voltage of more than 1.35 V on this pin turns off the
internal FET. A resistor divider connected from VCC to this pin provides overvoltage protection for the
downstream load. This pin must be tied to GND when not used.
9.3.9 PGb
This active low, open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits.
PGb pulls low after the drain-to-source voltage of the internal FET has fallen below 150 mV and a 3.4 ms
deglitch delay has elapsed. It goes open drain when VDS exceeds 220 mV. PGb assumes high impedance status
after a 3.4 ms deglitch delay once VDS of internal FET rises up, resulting from GATE being pulled to GND at the
following conditions:
•
•
An overload current fault occurs (VIMON > 675 mV) and the fault timer times out.
A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, that is, the fast-trip shutdown
threshold has been exceeded.
•
•
•
•
VEN is below its falling threshold.
VVCC drops below the UVLO threshold.
VOV is above its rising threshold.
Die temperature exceeds the OTSD threshold.
This pin can be left floating when not used.
9.3.10 PROG
A resistor from this pin to GND sets the maximum power permitted in the internal MOSFET during inrush. Do not
apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of 4.99 kΩ. To set the
maximum power, use Equation 1.
84375´ RSET
P
=
LIM
R
PROG ´ RSENSE ´ RIMON
(1)
where PLIM is the allowed power limit of the internal MOSFET. RSENSE is the load current monitoring resistor
connected between the VCC pin and the SENSE pin. RPROG is the resistor connected from the PROG pin to
GND. Both RPROG and RSENSE are in ohms and PLIM is in watts. PLIM is determined by the maximum allowed
thermal stress of internal MOSFET, given by Equation 2.
TJ(MAX) - TC(MAX)
P
<
LIM
RθJC(MAX)
(2)
where TJ(MAX) is the maximum desired transient junction temperature and TC(MAX) is the maximum case
temperature prior to a start or restart. RӨJC(MAX) is the junction-to-case thermal impedance of the internal pass
FET in units of °C/W. Both TJ(MAX) and TC(MAX) are in °C.
16
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Feature Description (continued)
9.3.11 SENSE
This pin connects to the negative terminal of RSENSE. It provides a means of sensing the voltage across this
resistor, as well as a way to monitor the drain-to-source voltage across the internal FET. The current limit ILIM is
set by Equation 3.
0.675 V ´ RSET
ILIM
=
RIMON ´ RSENSE
(3)
A fast-trip shutdown occurs when V(VCC – VSENSE) exceeds 60 mV.
SET: A resistor RSET is connected from this pin to the positive terminal of RSENSE. This resistor scales the current
limit and power limit settings. It coordinates with RIMON and RSENSE to determine the current limit value. The value
of RSET can be calculated from Equation 3 (see the SENSE definition).
9.3.12 TIMER
A capacitor CT connected from the TIMER pin to GND determines the overload fault timing. TIMER sources 10
µA when an overload is present, and discharges CT at 10 µA otherwise. Internal FET is turned off when VTIMER
reaches 1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period
before the internal FET is re-enabled. A minimum timing capacitance of 1 nF is recommended to ensure proper
operation of the fault timer. The value of CT can be calculated from the desired fault time tFLT, using Equation 4.
10 μA
CT
=
´ tFLT
1.35 V
(4)
Either latch mode (TPS24750) or retry mode (TPS24751) occurs if the load current exceeds the current limit
threshold or the fast trip shutdown threshold. While in latch mode, the TIMER pin continues to periodically charge
and discharge the attached capacitor. In retry mode, the internal MOSFET is disabled for sixteen cycles of
TIMER charging and discharging. The TIMER pin is pulled to GND by a 2 mA current source at the end of the
16th cycle of charging and discharging. The internal MOSFET is then re-enabled. The TIMER pin capacitor, CT,
can also be discharged to GND during latch mode or retry mode in the following way:
•
A 2-mA current sinks TIMER whenever any of the following occurs:
–
–
–
VEN is below its falling threshold.
VVCC drops below the UVLO threshold.
VOV is above its rising threshold.
TIMER is not affected when the die temperature exceeds the OTSD threshold.
9.3.13 VCC
This pin performs three functions. First, it provides biasing power to the integrated circuit. Second, it serves as an
input to the power-on reset (POR) and undervoltage lockout (UVLO) functions. Bypass capacitor C1, shown in
the typical application diagram on the front page, must be connected to the positive terminal of VVCC. A
capacitance of at least 10 nF is recommended.
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9.4 Device Functional Modes
9.4.1 Board Plug-In
Figure 31 and Figure 32 illustrate the inrush current that flows when a hot swap board under the control of the
TPS2475x is plugged into a system bus. Only the bypass capacitor charge current and small bias currents are
evident when a board is first plugged in. The TPS2475x is held inactive for a short period while internal voltages
stabilize. In this short period, GATE, PROG, and TIMER are held low and PGb, and FLTb, are held open-drain.
When the voltage on the internal VCC rail exceeds approximately 1.5 V, the power-on reset (POR) circuit
initializes the TPS2475x and a start-up cycle is ready to take place.
GATE, PROG, TIMER, PGb, and FLTb are released after the internal voltages have stabilized and the external
EN (enable) thresholds have been exceeded. The part begins sourcing current from the GATE pin to turnon
internal FET. The TPS2475x monitors both the drain-to-source voltage across internal MOSFET and the drain
current passing through it. Based on these measurements, the TPS2475x limits the drain current by controlling
the gate voltage so that the power dissipation of the internal FET does not exceed the power limit programmed
by the user. The current increases as the voltage across the FET decreases until finally the current reaches the
current limit ILIM
.
Figure 31. Inrush Mode at Hot-Swap Circuit Insertion
9.4.2 Inrush Operation
After the TPS2475x initialization is complete (as described in the Board Plug-in section) and EN is active, GATE
is enabled (VGATE starts increasing), when VGATE reaches the internal FET gate threshold, a current flows into the
downstream bulk storage capacitors. When this current exceeds the limit set by the power-limit engine, the gate
of the internal FET is regulated by a feedback loop to make the internal FET current rise in a controlled manner.
This not only limits the capacitor-charging inrush current but it also limits the power dissipation of the internal
FET to safe levels. A more complete explanation of the power-limiting scheme is given in the Action of the
Constant-Power Engine section. When the GATE is enabled, the TIMER pin begins to charge the timing
capacitor CT with a current of approximately 10 µA. The TIMER pin continues to charge CT until V(GATE-VCC)
reaches the timer activation voltage (5.8 V for VVCC = 12V). The TIMER then begins to discharge CT with a
current of approximately 10 µA. This indicates that the inrush mode is finished. If the TIMER exceeds its upper
threshold of 1.35 V before V(GATE – VCC) reaches the timer activation voltage, the GATE pin is pulled to GND and
the hot-swap circuit enters either latch mode (TPS24750) or auto-retry mode (TPS24751).
The power limit feature is disabled once the inrush operation is finished and the hotswap circuit becomes a
circuit breaker. The TPS2475x turns off the internal FET after a fault timer period once the load exceeds the
current limit threshold.
18
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Device Functional Modes (continued)
9.4.3 Action of the Constant-Power Engine
Figure 32 illustrates the operation of the constant-power engine during start-up. The circuit used to generate the
waveforms of Figure 32 was programmed to a power limit of 21 W by means of the resistor connected between
PROG and GND. At the moment current begins to flow through the internal FET, a voltage of 12 V appears
across it (input voltage VVCC = 12 V), and the constant-power engine therefore allows a current of 1.75 A (equal
to 21 W divided by 12 V) to flow. This current increases in inverse ratio as the drain-to-source voltage
diminishes, so as to maintain a constant dissipation of 21 W. The constant-power engine adjusts the current by
altering the reference signal fed to the current limit amplifier. The lower part of Figure 32 shows the measured
power dissipated in the internal FET, labeled FET PWR, remaining substantially constant during this period of
operation, which ends when the current through the FET reaches the current limit ILIM. This behavior can be
considered a form of foldback limiting, but unlike the standard linear form of foldback limiting, it allows the power
device to operate near its maximum capability, thus reducing the start-up time.
Figure 32. Computation of Power Stress During Startup
9.4.4 Circuit Breaker and Fast Trip
The TPS2475x monitors load current by sensing the voltage across RSENSE. The TPS2475x incorporates two
distinct thresholds: a current-limit threshold and a fast-trip threshold.
The functions of circuit breaker and fast-trip turnoff are shown in Figure 33 through Figure 36.
Figure 33 shows the behavior of the TPS2475x when a fault in the output load causes the current passing
through RSENSE to increase to a value above the current limit but less than the fast-trip threshold. When the
current exceeds the current-limit threshold, a current of approximately 10 μA begins to charge timing capacitor
CT. If the voltage on CT reaches 1.35 V, then the internal FET is turned off. The TPS24750 version latches off,
while as the TPS24751 version commences a restart cycle. In either event, fault pin FLTb pulls low to signal a
fault condition. Overload between the current limit and the fast-trip threshold is permitted for this period. This
shutdown scheme is sometimes called an electronic circuit breaker.
The fast-trip threshold protects the system against a severe overload or a dead short circuit. When the voltage
across the sense resistor RSENSE exceeds the 60-mV fast-trip threshold, the GATE pin immediately pulls the
internal FET gate to ground with approximately 1 A of current. The fast-trip circuit holds the internal FET off for
only a few microseconds, after which the TPS2475x turns back on slowly, allowing the current-limit feedback
loop to take over the gate control of the internal FET. Then the hot-swap circuit goes into latch mode (TPS24750)
or auto-retry mode (TPS24751). Figure 35 and Figure 36 illustrate the behavior of the system when the current
exceeds the fast-trip threshold.
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Device Functional Modes (continued)
Figure 33. Circuit-Breaker Mode During Overload Condition
ILIMIT
RSENSE
RSET
VCC
SENSE
DRAIN
GATE
OUT
SET
Internal FET
+
60mV
Fast Trip
Comparator
Server Amp
A1
+
A2
VCP
675mV
Current
Limit Amp
PROG
RPROG
IMON
RIMON
-
+
Figure 34. Partial Diagram of the TPS2475x with Selected External Components
20
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Device Functional Modes (continued)
Figure 35. Current Limit During Output-Load Short-Circuit
Condition (Overview)
Figure 36. Current Limit During Output-Load Short-Circuit
Condition (Onset)
9.4.5 Automatic Restart
In Auto-retry versions (TPS24751), device automatically initiates a restart after a fault has caused it to turnoff the
internal FET. Internal control circuits use CT to count 16 cycles before re-enabling the FET as shown in
Figure 37. This sequence repeats if the fault persists. The timer has a 1:1 charge-to-discharge current ratio. For
the very first cycle, the TIMER pin starts from 0 V and rises to the upper threshold of 1.35 V and subsequently
falls to 0.35 V before restarting. For the following 16 cycles, 0.35 V is used as the lower threshold. This small
duty cycle often reduces the average short-circuit power dissipation to levels associated with normal operation
and eliminates special thermal considerations for surviving a prolonged output short.
Figure 38. Latch After Overload Fault
Figure 37. Auto-Restart Cycle Timing
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Device Functional Modes (continued)
9.4.6 Start-Up with Short on Output
The TPS2475x has ability of detecting the short at the output during start-up and ensure shutdown of the hot-
swap circuit/system with fault indication. During start-up, after the initialization process is complete and the GATE
is enabled, the device limits the power as explained in the Action of the Constant-Power Engine section and the
TIMER pin begins to charge the timing capacitor CT with approximately 10 µA constant current source. If the
voltage on CT reaches its upper limit threshold of 1.35V, during start-up cycle itself, then the internal FET is
turned off and fault pin FLTb is pulled low to signal the fault condition. After this, the hot-swap circuit enters either
in latch mode (TPS24750) or auto-retry mode (TPS24751). Figure 39 shows the behavior of the TPS2475x for
start-up with short on the output.
This feature help to ensure early detection of fault and quick isolation of the subsystem to ensure stability of the
other units connected on the DC bus.
Figure 39. Start-Up with Short on Output
22
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Device Functional Modes (continued)
9.4.7 PGb, FLTb, and Timer Operations
The open-drain PGb output provides a deglitched end-of-inrush indication based on the voltage across internal
FET. PGb is useful for preventing a downstream dc/dc converter from starting while its input capacitor COUT is
still charging. PGb goes active-low about 3.4 ms after COUT is charged. This delay allows the internal FET to fully
turnon and any transients in the power circuits to end before the converter starts up. This type of sequencing
prevents the downstream converter from demanding full current before the power-limiting engine allows the
internal FET to conduct the full current set by the current limit ILIM. Failure to observe this precaution may prevent
the system from starting. The pullup resistor shown on the PGb pin in the typical system block diagram
application diagram Figure 41 is illustrative only; the actual connection to the converter depends on the
application. The PGb pin may indicate that inrush has ended before the MOSFET is fully enhanced, but the
downstream capacitor will have been charged to substantially its full operating voltage. After the hot-swap circuit
successfully starts up, the PGb pin can return to a high-impedance status whenever the drain-to-source voltage
of internal FET exceeds its upper threshold of 340 mV, which presents the downstream converters a warning
flag. This flag may occur as a result of overload fault, output short fault, input overvoltage, higher die
temperature, or the GATE shutdown by UVLO, EN.
FLTb is an indicator that the allowed fault-timer period during which the load current can exceed the programmed
current limit (but not the fast-trip threshold) expires. The fault timer starts when a current of approximately 10 μA
begins to flow into the external capacitor CT, and ends when the voltage of CT reaches TIMER upper threshold,
that is, 1.35 V. FLTb pulls low at the end of the fault timer. Otherwise, FLTb assumes a high-impedance state.
The fault-timer state requires an external capacitor CT connected between the TIMER pin and GND pin. The
duration of the fault timer is the charging time of CT from 0 V to its upper threshold of 1.35 V. The fault timer
begins to count under any of the following three conditions:
1. In the inrush mode, TIMER begins to source current to the timer capacitor, CT, when device is enabled.
TIMER begins to sink current from the timer capacitor, CT when V(GATE – VCC) exceeds the timer activation
voltage (see the Inrush Operation section). If V(GATE – VCC) does not reach the timer activation voltage before
TIMER reaches 1.35 V, then the TPS2475x disables the internal FET. After the MOSFET turns off, the timer
goes into either latch mode (TPS24750) or retry mode (TPS24751).
2. In an overload fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of
1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground.
After the fault timer period, TIMER may go into latch mode (TPS24750) or retry mode (TPS24751).
3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the programmed current limits following a fast-trip shutdown of internal FET. When the timer
capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer
capacitor, CT, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch
mode (TPS24750) or retry mode (TPS24751).
If the fault current drops below the programmed current limit within the fault timer period, VTIMER decreases and
the internal pass MOSFET remains enabled.
The behaviors of TIMER are different in the latch mode and retry mode. If the timer capacitor reaches the upper
threshold of 1.35 V, then:
•
In latch mode(TPS24750), the TIMER pin continues to charge and discharge the attached capacitor
periodically until device is disabled by UVLO, EN, or OV, as shown in Figure 38.
•
In retry mode(TPS24751), TIMER charges and discharges CT between the lower threshold of 0.35 V and the
upper threshold of 1.35 V for sixteen cycles before the device attempts to re-start. The TIMER pin is pulled to
GND at the end of the 16th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the initial
half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload fault is
removed or the TPS2475x is disabled by UVLO, EN or OV.
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Device Functional Modes (continued)
9.4.7.1 Overtemperature Shutdown
The TPS2475x includes a built-in overtemperature shutdown circuit designed to disable the gate driver and
hence turnoff the internal FET if the die temperature exceeds approximately 140°C. An overtemperature
condition also causes the FLTb and PGb pins to go to high-impedance states. Normal operation resumes once
the die temperature has fallen approximately 10°C.
9.4.7.2 Start-Up of Hot-Swap Circuit by VCC or EN
The connection and disconnection between a load and the input power bus are controlled by turning on and
turning off the internal FET.
The TPS2475x has two ways to turnon the internal FET:
•
Increasing VVCC above UVLO upper threshold while EN is already higher than its upper threshold sources
current to the gate of internal FET. After an inrush period, the TPS2475x fully turns on internal FET.
•
Increasing EN above its upper threshold while VVCC is already higher than the UVLO upper threshold sources
current to the gate of internal FET. After an inrush period, the TPS2475x fully turns on internal FET.
The EN pin can be used to start up the TPS2475x at a selected input voltage VVCC
.
To isolate the load from the input power bus, the internal FET can be disabled by any of the following conditions:
UVLO, EN, load current above the current-limit threshold, hard short at load, OV, or OTSD. Three separate
mechanisms disable the internal FET by pulling down the GATE as described below:
1. GATE is pulled down by an 11-mA current source when any of the following occurs.
–
–
–
–
The fault timer expires during an overload current fault (VIMON > 675 mV).
VEN is below its falling threshold.
VVCC drops below the UVLO threshold.
VOV is above its rising threshold.
2. GATE is pulled down by a 1-A current source for 13.5 μs when a hard output short circuit occurs and V(VCC –
is greater than 60 mV, that is, the fast-trip shutdown threshold. After fast-trip shutdown is complete, an
SENSE)
11-mA sustaining current ensures that the internal FET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
24
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ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS2475x provide highly integrated load protection for 2.5 V to 18 V applications. The devices integrate a
hot swap controller and a power MOSFET in a single package for small form factor applications. These devices
protect source, load and internal MOSFET from potentially damaging events in applications such as Servers,
Plug-In Modules, RAID systems, Base stations and Fan Control.
The following design procedure can be used to select component values for the device.
Additionally, a spreadsheet design tool TPS2475x Design Calculator Tool (SLVC545) is available on web folder.
10.2 Typical Application
Rsense
RSET
VCC SET
SENSE DRAIN
OUT
FLT
PG
EN
OV
IMON
GATE
PROG
GND
TIMER
Figure 40. Gate Capacitor (dV/dt) Control Inrush Mode
10.2.1 Design Requirements
For this design example, use the parameters shown in Table 1.
Table 1. Design Parameters
Parameter
Value
12 V
Input voltage V(VCC)
Undervoltage lockout set point, VUV
Overvoltage protection set point , VOV
Load after PG asserted , RLOAD
Current limit, ILIM
8.4 V
14 V
1.2 Ω
11 A
Load capacitance , COUT
470 μF
60°C
Maximum ambient temperatures , TA
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10.2.2 Detailed Design Procedure
10.2.2.1 Power-Limited Start-Up
This design example assumes a 12-V system voltage with an operating tolerance of ±2 V. The rated load current
is 10 A. If the current exceeds 11 A, then the device must shut down and then attempt to restart. Ambient
temperatures may range from 20°C to 60°C. The load has a minimum input capacitance of 470 μF. The load is
turned on only after the PG signal is asserted. Figure 41 shows a simplified system block diagram of the
proposed application.
This design procedure seeks to control the junction temperature of device under both static and transient
conditions by proper selection of current limit, fault timeout, and power limit. The design procedure assumes the
worst case as a unit running at full load and maximum ambient temperature experiences a short circuit event.
Adjust this procedure to fit the application and design criteria.
Rsense
PROTECTION
LOAD
5VDC
RSET
12V Main Bus
Supply
VCC SET
EN
SENSE DRAIN
OUT
FLTb
PGb
C1
0.1 mF
OV
Specifications (at output) :
Peak Current Limit = 11A
Nominal Current = 10A
IMON
GATE
PROG
GND
TIMER
Figure 41. Simplified Block Diagram of the System Constructed in the Design Example
10.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON
The recommended range of the current-limit threshold voltage, V(VCC – SENSE), extends from 10 mV to 42 mV.
Values near the low threshold of 10 mV may be affected by system noise. Values near the upper threshold of
42 mV may be too close to the minimum fast-trip threshold voltage of 52 mV. Values near the middle of this
range help minimize both concerns.
To achieve high efficiency, the power dissipation in RSENSE must be kept to a minimum. A RSENSE of 2 mΩ
develops a voltage of 22 mV at the specified peak current limit of 11 A, while dissipating only 200 mW at the
rated 10-A current. This represents a 0.17% power loss.
For best performance, a current of approximately 0.5 mA (see the Recommended Operatings Conditions table)
must flow into the SET pin and out of the IMON pin when the TPS2475x is in current limit. The voltage across
RSET nominally equals the voltage across RSENSE, or 22 mV. Dividing 22 mV by 0.5 mA gives a recommended
value of RSET of 44 Ω. A 51.1-Ω, 1% resistor was chosen. Using Equation 3, the value of RIMON must equal 1568
Ω, or as near as practically possible. A 1.58-kΩ, 1% resistor was chosen. See Equation 5.
26
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0.675 V ´RSET
=
ILIM
RIMON ´RSENSE
therefore,
0.675 V ´51.1
11´0.002
RIMON
=
=1567.8
(5)
10.2.2.1.2 STEP 2. Choose Power-Limit Value, PLIM, and RPROG
The internal MOSFET dissipates large amounts of power during inrush. The power limit PLIM of the TPS2475x
must be set to prevent the internal FET die temperature from exceeding a short-term maximum temperature,
TJ(MAX)2. The short-term TJ(MAX)2 could be set ≤125°C to have sufficient margin to the internal maximum FET
junction temperature. Equation 6 is an expression for calculating PLIM
.
é
ë
ù
TJ(MAX)2
-
I
MAX
2 ´RDS(on) ´RqCA + T
(
)
A(MAX) û
P
£ 0.8´
LIM
RqJC
therefore,
11 A 2 ´5 mW ´ 33.7°C/ W -1.1°C/ W + 60°C
é
ë
ù
ú
û
125°C -
(
(
)
(
)
)
ê
P
£ 0.8´
= 32.93 W
LIM
1.1°C/ W
(6)
In the above equation, RθCA= RθJA – RθJC
Where, RθCA is the case-to-ambient thermal resistance (RθCA is a strong function of the user defined PCB layout
and heat sinking provided on Pad-2 of the device and can vary accordingly), RθJA is the junction-to-ambient
thermal resistance and RθJC is the junction-to-case thermal resistance of the device, (In Equation 6 , the values
are used from the TPS2475x Thermal Information table), rDS(on) is internal FET on-resistance at the maximum
operating temperature, and the factor of 0.8 represents the tolerance of the constant-power engine. For an
ambient temperature of 60°C, the calculated maximum PLIM is 33 W. Power limit selected must be lower than
value obtained in Equation 6, to have substantial safe margin considering the tolerance of components and
extended system temperatures. Power limit (PLIM) of 21 W is considered for this design. From Equation 1, a 64.9-
kΩ, 1% resistor is selected for RPROG (see Equation 7).
84375´R SET
RPROG
=
P
LIM ´R SENSE ´RIMON
therefore,
84375´51.1
21´ 0.002W ´1580W
RPROG
=
= 64.97 kW
(7)
Power Limit fold back (PLIM-FB) is the ratio of operating current (ILIM) and minimum power limited (regulated)
current (when VOUT = 0V). Degradation of programmed power limit (PLIM) accuracy and start up issues may occur
if PLIM-FB is too large. Equation 8 calculates VSNS-PL_MIN (minimum sense voltage during power limit) and PLIM-FB
.
To ensure reliable operation, verify that PLIM-FB < 12 and VSNS-PL_MIN ≥ 3mV.
P
LIM ´RSENSE
21W ´ 2 mW
VSNS-PL _MIN
=
=
= 3 mV ( ³ 3 mV)
VCC(MAX)
14 V
I
LIM ´ VCC(MAX)
11 A ´14 V
P
=
=
= 7.33 (< 12)
LIM-FB
P
21 W
LIM
(8)
27
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If the above conditions are not met, please adjust and align RSENSE, PLIM set, and TA(MAX) appropriately to satisfy
the above conditions.
10.2.2.1.3 STEP 3. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT
The maximum output voltage rise time, tON, set by timer capacitor CT must suffice to fully charge the load
capacitance COUT without triggering the fault circuitry. Equation 9 defines tON for two possible inrush cases.
Assuming that only the load capacitance draws current during startup,
C
OUT ´ V2
2´P
C
OUT ´P
2´I2
VCC(MAX)
LIM
LIM
+
if
P
< ILIM ´ VVCC(MAX)
LIM
LIM
tON
=
C
OUT ´ VVCC(MAX)
if
P
> ILIM ´ VVCC(MAX)
LIM
ILIM
therefore,
470 μF´ 21 W 470 μF´14 ´14
tON
=
+
= 2.234 ms
2´ 11´11
(
2´ 21
)
(9)
The next step is to determine the minimum fault-timer period. In Equation 9, the output rise time is tON. This is the
amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer uses
the difference between the input voltage and the gate voltage to determine if the TPS2475x is still in inrush limit.
The fault timer continues to run until VGS rises 5.8 V (for VVCC = 12 V) above the input voltage. Some additional
time must be added to the charge time to account for this additional gate voltage rise. The minimum fault time
can be calculated using Equation 10.
QGINT + QGBLK
+
tFLT = tON
IG
therefore,
22 nC +17 nC
tFLT = tON
+
= tON +1.95 ms = 4.184 ms
20 μA
(10)
where QGINT is the Gate charge of the internal FET to reach the 5.8 V gate voltage (see Figure 25), QGBLK is the
Gate charge of blocking FET (for this design, it is considered that CSD17501Q5A SLPS303 blocking FET is
used, take this as '0' if blocking FET is not used) and IGATE is the minimum gate sourcing current of the
TPS2475x, or 20 μA. Overall, Equation 10 leads to a minimum fault time of 4.184 ms. Considering the tolerances
of COUT, CT, ILIM , ITIMER and PLIM, the fault timer must be set to a value ≥ 1.4 times of tFLT obtained, to avoid
turning off during start-up, but need to be lower than any maximum fault time limit determined by the device SOA
curve (see Figure 27).
For this example, we select 6.3 ms (1.5 x TFLT) to allow for variation of system parameters such as temperature,
load, component tolerance, and input voltage. As per SOA curve (TA = 25oC), for approximately 6.5 ms, the
power handled by the device is approximately 70 W at 12 V (value obtained from extrapolation). This need to be
scaled (derated) by a factor of (150 –TJDCMAX))/(150 – TA), where TJDCMAX is the maximum steady state junction
2
temperature (TJDMAX = TA(MAX) + ILIM × R(DS)ON × RθJA). The scaled power is approximately 34 W. So the power
limit of 21 W considered has safe margin of 38% over the derated SOA. This can be depicted through the
Figure 42. Also, from Figure 42, from the blue dotted line shown, it can be analyzed that the device at TA = 25oC,
can tolerate 12 V and 10 A for approximately time 1 ms and can take power of 21 W for duration of
approximately 70 to 75 ms.
The timing capacitor is calculated in Equation 11 as 46.67 nF. Selecting the next-highest standard value, 47 nF,
yields a 6.35 ms fault time.
28
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10 μA ´ tFLT
CT =
1.35
therefore,
10 μA ´6.3 ms
CT =
= 46.67 nF
1.35
(11)
1000
Area Limited
by RDS(on)
100
10
1
1 ms
10 ms
Margin
100ms
Single Pulse
qJA = 62.5ºC/W
R
TA = 25ºC
0.1
0.1
1
10
100
VDS – Drain-to-Source Voltage – V
Figure 42. Design Example SOA
10.2.2.1.4 STEP 4. Calculate the Retry-Mode Duty Ratio
In retry mode, the TPS24751 is on for one charging cycle and off for 16 charge-discharge cycles, as can be seen
in Figure 37. The first CT charging cycle is from 0 V to 1.35 V, which gives 6.35 ms. The first CT discharging
cycle is from 1.35 V to 0.35 V, which gives 4.7 ms. Therefore, the total time is 6.35 ms + 33 × 4.7 ms = 161.45
ms. As a result, the retry mode duty ratio is 6.35 ms/161.45 ms = 3.93%. So effective steady state power
dissipation in device during continuos short conditions is 4% of PLIM
.
10.2.2.1.5 STEP 5. Select R1, R2, and R3 for UV and OV
Next, select the values of the OV and UV resistors, R1, R2, and R3, as shown in the typical system application
diagram Figure 41 . From the TPS2475x electrical specifications, VOVTHRESH = 1.35 V and VENTHRESH = 1.35 V.
VOV is the overvoltage trip voltage, which in this case is 14 V. VUV is the undervoltage trip voltage, which for this
example equals 8.4 V.
R
3
VOVTHRESH
=
ì VOV
R1
+ R
2
+ R
3
(12)
R
2 +
R
3
VENTHRESH
=
ì VUV
R
1
+ R
2
+ R
3
(13)
Assume R3 is 1.5 kΩ and use Equation 12 to solve for (R1 + R2). Use Equation 13 and the (R1 + R2) from
Equation 12 to solve for R2 and finally for R1. From Equation 12, (R1 + R2) = 14.05 kΩ. From Equation 13, R2 = 1
kΩ and R1 = 13.05 kΩ. Scaling all three resistors by a factor of ten to use less supply current for these voltage
references and using standard 1% resistor values gives R1 = 130 kΩ, R2 = 10 kΩ, and R3 = 15 kΩ.
10.2.2.1.6 STEP 6. Choose R4, R5, and C1
As per the typical application diagram on the front page, R4, and R5 are required only if PGb, and FLTb are used;
these resistors serve as pull-ups for the open-drain output drivers. The current sunk by each of these pins must
not exceed 2 mA (refer to the Recommended Operating Conditions table). C1 is a bypass capacitor to help
control transient voltages, unit emissions, and local supply noise while in the disabled state. Where acceptable, a
value in the range of 0.001 μF to 0.1 μF is recommended.
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10.2.2.2 Alternative Design Example: Gate Capacitor (dv/dt) Control in Inrush Mode
The TPS2475x can be used in applications that expect a constant inrush current. This current is controlled by a
capacitor connected from the GATE terminal to GND. A resistor of 1 kΩ placed in series with this capacitor
prevents it from slowing a fast-turnoff event. In this mode of operation, the internal FET operates as a source
follower, and the slew rate of the output voltage approximately equals the slew rate of the gate voltage (see
Figure 43).
To implement a constant-inrush-current circuit, choose the time to charge, ∆t, using Equation 14.
COUT ´ VVCC
Dt =
ICHG
(14)
where COUT is the output capacitance, VVCC is the input voltage, and ICHG is the desired charge current. Choose
ICHG < PLIM / VVCC to prevent power limiting from affecting the desired current.
To select the gate capacitance use Equation 15. where, IGATE is the nominal gate current and CINTRS, the
effective capacitance contributed by the internal FET (approximately 175 pF). In addition, the effect of other
capacitances like the capacitance offered by the usage of the Blocking FET (CBLK) and other component
capacitances CPR (due to external gate protection diodes, such as Zener diode and board parasitic) to be
accounted for arriving at exact value of CGATE. The TIMER capacitor, CT, must be programmed for timing greater
than the total turnon time (tON), to ensure and avoid fault detection during start-up.
Typical application circuit with Gate Capacitor (dV/dt) Control Inrush Mode is shown in Figure 43. The turnon
waveform with CGATE of 4.7 nF and series resistor of 1 kΩ is shown in Figure 44.
æ
ö
Dt
CGATE = I
ç GATE
´
- C
÷
INTRS
VVCC ø
è
(15)
To Load
From Source
CBLK
CPR
Part of
TPS24750
Other capacitances that
can be on board
GATE
CGATE
IG
30 ꢀA
1 kΩ
GND
Figure 43. Gate Capacitor (dV/dt) Control Inrush Mode.
10.2.2.3 Additional Design Considerations
10.2.2.3.1 Use of PGb
Use the PGb pin to control and coordinate a downstream dc/dc converter. If this is not done, then a long time
delay is needed to allow COUT to fully charge before the converter starts. An undesirable latch-up condition can
be created between the TPS2475x output characteristic and the dc/dc converter input characteristic if the
converter starts while COUT is still charging; using the PGb pin is one way to avoid this.
30
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10.2.2.3.2 Output Clamp Diode
Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a
current-limit event. The OUT pin ratings can be satisfied by connecting a diode from OUT to GND. The diode
must be selected to control the negative voltage at the full short-circuit current. Schottky diodes are generally
recommended for this application.
10.2.2.3.3 Gate Clamp Diode
The TPS2475x has a relatively well-regulated gate voltage of 12 V-15.5 V with a supply voltage VVCC higher than
4 V. For the applications with operating voltage greater than 14 V, a negative gate clamp (of ≤15.5 V) is needed
as shown in Figure 47. In addition, a series resistance of several hundred ohms or a series silicon diode is
recommended to prevent the output capacitance from discharging through the gate driver to ground. For
applications with Blocking FET, a small clamp Zener from gate to OUT is recommended if VGS of external
blocking FET is rated below 12 V.
10.2.2.3.4 Bypass Capacitors
It is a good practice to provide low-impedance ceramic capacitor bypassing of the VCC and OUT pins. Values in
the range of 10 nF to 1 µF are recommended. Some system topologies are insensitive to the values of these
capacitors; however, some are not and require minimization of the value of the bypass capacitor. Input
capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the low-
impedance power bus when inserted. This stresses the connector contacts and causes a short voltage sag on
the input bus. Small amounts of capacitance (that is, 10 nF to 0.1 µF) are often tolerable in these systems.
10.2.2.3.5 Output Short-Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
10.2.3 Application Curves
VOUT
Gate
I_IN
Timer
Figure 45. Inrush Mode at Hot-Swap Circuit Insertion
Figure 44. Turnon with Gate Capacitor (dv/dt) Control
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10.3 System Examples
Rsense
RSET
VCC SET
SENSE DRAIN
OUT
FLT
PG
EN
OV
IMON
GATE
PROG
GND
TIMER
Figure 46. Reverse Blocking Implementation
Rsense
RSET
VCC SET
SENSE DRAIN
OUT
FLT
PG
EN
OV
IMON
GATE
PROG
GND
TIMER
Figure 47. Negative Voltage Gate Protection
32
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System Examples (continued)
The TPS2475x can be configured as a high current load switch with low external part count. The schematic
diagram of load switch configuration is shown in Figure 48. The output voltage ramp rate is controlled with RC
circuit (Rgate and Cgate) at the Gate pin of the device. For detailed design process refer to the application note 12-
A Integrated Load Switch Using TPS24750/51.
Due to their robust protection features along with low RDS(on) of 3 mΩ integrated MOSFET and precise current-
limiting, the TPS2475x eFuses finds usage in power supply modules for Position Encoder Interfaces in
applications such as Servo Drives and Position Control. Refer to the following TI Designs for system usage
examples of the TPS2475x in these applications.
Power Supply with Programmable Output Voltage and Protection for Position Encoder Interfaces
Interface to a 5-V BiSS® Position Encoder
VCC SET
SENSE DRAIN
OUT
FLT
PG
EN
OV
IMON
GATE
PROG
GND
TIMER
Cgate
R
gate
Figure 48. TPS2475x Configured as Simple 12-A Load Switch
Copyright © 2013–2018, Texas Instruments Incorporated
33
TPS24750, TPS24751
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
www.ti.com.cn
11 Power Supply Recommendations
The device is designed for supply voltage range of 2.5 V ≤ V(VCC) ≤ 18 V. If the input supply is located more than
a few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power
supply must be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.
11.1 Transient Thermal Impedance
TA = 25°C (unless otherwise stated)
1 in
TPS24750
Typ RꢀJA = 62.3oC/W
Max RꢀJA = 65oC/W
1 in
when mounted on a
2
2
1 inch (6.45-cm ) of
1oz.(0.0355-mm thick) Cu.
Copper
Figure 49. Board Details - Thermal Impedance Characteristic
10
1
0.1
0.01
0.001
0.0001
0.00001
0.000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
10k
tp - Pulse Duration - s
Figure 50. Transient Thermal Impedance with Test Board Details as Shown in Figure 49
34
Copyright © 2013–2018, Texas Instruments Incorporated
TPS24750, TPS24751
www.ti.com.cn
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
12 Layout
12.1 Layout Guidelines
The TPS2475x applications require careful attention to layout to ensure proper performance and to minimize
susceptibility to transients and noise. In general, all traces must be as short as possible, but the following list
deserves first consideration:
•
•
Decoupling capacitors on VCC pin must have minimal trace lengths to the pin and to GND.
Traces to SET and SENSE must be short and run side-by-side to maximize common-mode rejection. Kelvin
connections must be used at the points of contact with RSENSE. See Figure 51 and Figure 52 for a PCB layout
example.
•
•
SET runs must be short on both sides of RSET.
High current carrying Power path connections must be as short as possible and sized to carry at least twice
the full-load current, more if possible.
•
•
Connections to IMON pin must be minimized after the previously described connections have been placed.
The reference must should be a copper plane or island. Use via holes if necessary for direct connections of
components to their appropriate return ground plane or island.
•
Thermal Considerations: When properly mounted the PowerPAD package provides significantly greater
cooling ability than an ordinary package. To operate at rated power, PowerPAD-2 must be soldered directly to
the PC board DRAIN plane directly under the device. The PowerPAD-2 is at the DRAIN potential and can be
connected using multiple vias to the inner and bottom layers of the DRAIN. The bottom side of the circuit
board is highly recommended to be used for DRAIN plane to increase heat sinking in higher current
applications. Refer to Technical Briefs: PowerPADTM Thermally Enhanced Package, SLMA002) and
PowerPAD™ Made Easy, SLMA004) for more information on using this PowerPad package.
•
•
The thermal via land pattern specific to the TPS2475x can be downloaded from the device webpage.
Protection devices such as snubbers, TVS, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, the
protection Schottky diode suggested to address transients due to heavy inductive loads, must be physically
close to the OUT pins.
12.2 Layout Example
LOAD CURRENT
PATH
LOAD CURRENT
PATH
RSENSEx
TPS24750
TPS24750
Method 1
Figure 51. Recommended RSENSE Layout
Copyright © 2013–2018, Texas Instruments Incorporated
35
TPS24750, TPS24751
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
www.ti.com.cn
Layout Example (continued)
Top Layer
Top Layer Signal Ground Plane
Bottom Layer Drain plane
Via to Bottom Layer
Track in bottom or internal layer
BOTTOM LAYER (DRAIN PLANE)
Having DRAIN plane copper pour
area on bottom layer maximizes heat
sinking ability
RSENSE
VOUT
VIN
OUT 19
13
12
11
OUT
OUT
OUT
20
21
OUT
OUT
22
10
OUT
OUT
OUT
GATE
OUT
OUT
OUT
23
24
9
8
See Note 1
25
26
7
OUT
SENSE
6
5
OUT
DRAIN 27
DRAIN
28
29
GND
VCC
4
3
GND
SET
30
31
FLTb
PGb
2
1
IMON
OV
SIGNAL GROUND
TOP LAYER
Power Ground
(1) Optional: Needed only to suppress the transients caused by inductive load switching.
Figure 52. Layout Example
36
版权 © 2013–2018, Texas Instruments Incorporated
TPS24750, TPS24751
www.ti.com.cn
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
《PowerPADTM 耐热增强型封装》（TI 文献编号 SLMA002）
《PowerPAD™ 速成》
《适用于位置编码器接口且具有可编程输出电压和保护功能的电源》
《5V BiSS® 位置编码器接口》
《采用 TPS24750/51 的 12A 集成负载开关》
《TPS2475X EVM 用户指南》
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TPS24750
TPS24751
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
版权 © 2013–2018, Texas Instruments Incorporated
37
TPS24750, TPS24751
ZHCSBP7C –OCTOBER 2013–REVISED DECEMBER 2018
www.ti.com.cn
13.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
38
版权 © 2013–2018, Texas Instruments Incorporated
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2019 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS24750RUVR
TPS24750RUVT
TPS24751RUVR
TPS24751RUVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
RUV
RUV
RUV
RUV
36
36
36
36
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
TPS24750
NIPDAU
NIPDAU
NIPDAU
TPS24750
TPS24751
TPS24751
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS24750RUVR
TPS24750RUVT
TPS24751RUVR
TPS24751RUVT
VQFN
VQFN
VQFN
VQFN
RUV
RUV
RUV
RUV
36
36
36
36
3000
250
330.0
180.0
330.0
180.0
16.4
16.4
16.4
16.4
3.85
3.85
3.85
3.85
7.35
7.35
7.35
7.35
1.2
1.2
1.2
1.2
8.0
8.0
8.0
8.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Dec-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS24750RUVR
TPS24750RUVT
TPS24751RUVR
TPS24751RUVT
VQFN
VQFN
VQFN
VQFN
RUV
RUV
RUV
RUV
36
36
36
36
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
38.0
35.0
38.0
35.0
3000
250
Pack Materials-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
TPS24770
具有电流监控功能的 2.5V 至 18V 高性能热插拔控制器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS24770RGER
具有电流监控功能的 2.5V 至 18V 高性能热插拔控制器 | RGE | 24 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS24770RGET
具有电流监控功能的 2.5V 至 18V 高性能热插拔控制器 | RGE | 24 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS24771
具有模拟电流监控器的 2.5V 至 18V 高性能热插拔控制器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS24771RGER
具有模拟电流监控器的 2.5V 至 18V 高性能热插拔控制器 | RGE | 24 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS24771RGET
具有模拟电流监控器的 2.5V 至 18V 高性能热插拔控制器 | RGE | 24 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS24772
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TPS24772RGER
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TPS24772RGET
2.5V 至 18V 高性能热插拔控制器 | RGE | 24 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TPS2480
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TPS2480PW
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TPS2480PWR
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