TPS2553D [TI]
低电平有效且具有闭锁和反向阻断功能的 0.075-1.7A 可调节高电平有效、反向阻断，提供多种包装的 ILIMIT 2.5-6.5V 85mΩ USB 电源开关;
| 型号： | TPS2553D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低电平有效且具有闭锁和反向阻断功能的 0.075-1.7A 可调节高电平有效、反向阻断，提供多种包装的 ILIMIT 2.5-6.5V 85mΩ USB 电源开关 开关 电源开关 |
| 文件： | 总33页 (文件大小：1115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS2552D, TPS2553D
ZHCSFI7 –SEPTEMBER 2016
TPS255xD 高精度可调式限流配电开关
1 特性
3 说明
1
•
•
•
•
•
•
•
最大负载电流可达 1.5A
TPS2552D 和 TPS2553D 配电开关专门用于 电流 限
制精度有要求或者会遇到重电容负载和短路的应用，并
可提供高达 1.5A 的持续负载电流。这些器件借助一个
外部电阻器提供一个 75mA至 1.7A（典型值）间的可
编程电流限制阈值。在更高电流限制设置上可实现严格
至 ±6% 的电流限制精度。对电源开关的上升和下降次
数进行控制以大大降低接通/切断期间的电流冲击。
1.7A 电流下的电流限制精度为 ±6%（典型值）
满足 USB 限流要求
与 TPS2550/51 向后兼容
可调电流限制值，75mA-1700mA（典型值）
恒流（TPS2552D 和 TPS2553D）
TPS2552D（支持低电流）和 TPS2553D（支持高
电流）
当输出负载超过电流限制阈值时，TPS2552D/3D 器件
会通过使用恒流模式将输出电流限制到安全水平。当输
出电压被驱动至高于输入电压时，内部反向电压比较器
将禁用电源开关以保护此开关输入端的器件。在过流和
反向电压情况下，FAULT 输出被置为低电平。
•
•
快速过流响应 - 2μs（典型值）
85mΩ 高侧金属氧化物半导体场效应晶体管
(MOSFET)（DBV 封装）
•
•
•
•
反向输入-输出电压保护
工作范围：2.7V 至 6.5V
内置软启动
器件信息(1)
封装
15kV ESD 保护，符合 IEC 61000-4-2 标准（带外
部电容）
器件型号
TPS2552D
TPS2553D
封装尺寸（标称值）
2.90mm x 1.60mm
2.90mm x 1.60mm
SOT-23 (6)
SOT-23 (6)
•
•
UL列表 - 文件号E169910 和 NEMKO IEC60950-1-
am1 ed2.0
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
请见TI 开关系列产品
2 应用
•
•
•
•
USB 端口/集线器
数字电视
机顶盒
网络语音 (VOIP) 电话
简化电路原理图
TPS2552D/53D
5V USB
Input
RFAULT
100 kW
USB Data
0.1 mF
USB
Port
IN
OUT
120 mF
ILIM
RILIM
Fault Signal
Control Signal
FAULT
EN
USB requirement only*
20 kW
GND
*USB requirement that downstream
facing ports are bypassed with at least
120 mF per hub
Power Pad
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDL7
TPS2552D, TPS2553D
ZHCSFI7 –SEPTEMBER 2016
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
10 Application and Implementation........................ 17
10.1 Application Information.......................................... 17
10.2 Typical Applications .............................................. 17
11 Power Supply Recommendations ..................... 25
11.1 Self-Powered and Bus-Powered Hubs ................. 25
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Typical Characteristics.............................................. 8
Parameter Measurement Information ................ 11
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 14
9.5 Programming........................................................... 15
11.2 Low-Power Bus-Powered and High-Power Bus-
Powered Functions .................................................. 25
11.3 Power Dissipation and Junction Temperature ...... 25
12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
12.2 Layout Example .................................................... 26
13 器件和文档支持 ..................................................... 27
13.1 器件支持................................................................ 27
13.2 相关链接................................................................ 27
13.3 接收文档更新通知 ................................................. 27
13.4 社区资源................................................................ 27
13.5 商标....................................................................... 27
13.6 静电放电警告......................................................... 27
13.7 Glossary................................................................ 27
14 机械、封装和可订购信息....................................... 27
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2016 年 9 月
*
最初发布版本
2
Copyright © 2016, Texas Instruments Incorporated
TPS2552D, TPS2553D
www.ti.com.cn
ZHCSFI7 –SEPTEMBER 2016
5 Device Comparison Table
Copyright © 2016, Texas Instruments Incorporated
3
TPS2552D, TPS2553D
ZHCSFI7 –SEPTEMBER 2016
www.ti.com.cn
6 Pin Configuration and Functions
TPS2552D/3D
DBV Package
Top View
6
1
2
3
IN
OUT
ILIM
GND
EN
5
4
FAULT
EN = Active Low for the TPS2552D
EN = Active High for the TPS2553D
Pin Functions
PIN
TPS2552D
TPS2553D
I/O
DESCRIPTION
NAME
EN
DBV
DBV
3
–
2
–
3
2
I
I
Enable input, logic low turns on power switch
EN
Enable input, logic high turns on power switch
GND
Ground connection; connect externally to PowerPAD
Input voltage; connect a 0.1 μF or greater ceramic
capacitor from IN to GND as close to the IC as possible.
IN
1
1
I
Active-low open-drain output, asserted during overcurrent,
overtemperature, or reverse-voltage conditions.
FAULT
OUT
4
6
5
4
6
5
O
O
O
Power-switch output
External resistor used to set current-limit threshold;
recommended 15 kΩ ≤ RILIM ≤ 232 kΩ.
ILIM
Internally connected to GND; used to heat-sink the part to
the circuit board traces. Connect PowerPAD to GND pin
externally.
PowerPAD
™
–
–
4
版权 © 2016, Texas Instruments Incorporated
TPS2552D, TPS2553D
www.ti.com.cn
ZHCSFI7 –SEPTEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)
MIN
–0.3
–7
MAX
UNIT
V
Voltage range on IN, OUT, EN , ILIM, FAULT
Voltage range from IN to OUT
7
7
V
IO
Continuous output current
Continuous total power dissipation
Continuous FAULT sink current
ILIM source current
Internally Limited
See the Thermal Information
0
25
1
mA
mA
°C
0
TJ
Maximum junction temperature
–40
–65
150
150
Tstg Storage temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltages are referenced to GND unless otherwise noted.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±500
V(ESD)
Electrostatic discharge
V
IEC 61000-4-2 contact discharge(3)
IEC 61000-4-2 air-gap discharge(3)
±8000
±15000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Surges per EN61000-4-2. 1999 applied to output terminals of EVM. These are passing test levels, not failure threshold.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
0
NOM
MAX
6.5
UNIT
VIN
VEN
VEN
VEN
VIH
VIL
Input voltage, IN
Enable voltage
Enable voltage
V
TPS2552D
TPS2553D
6.5
V
V
V
0
6.5
0
6.5
High-level input voltage on EN
Low-level input voltage on EN
1.1
0.66
1.2
1.5
232
10
–40 °C ≤ TJ ≤ 125 °C
–40 °C ≤ TJ ≤ 105 °C
0
0
Continuous output
current, OUT
IOUT
A
RILIM
IO
Current-limit threshold resistor range (nominal 1%) from ILIM to GND
Continuous FAULT sink current
15
0
KΩ
mA
μF
Input de-coupling capacitance, IN to GND
0.1
–40
Operating virtual
junction
I
OUT ≤ 1.2 A
OUT ≤ 1.5 A
125
105
TJ
°C
temperature(1)
I
–40
(1) See "Dissipation Rating Table" and "Power Dissipation and Junction Temperature" sections for details on how to calculate maximum
junction temperature for specific applications and packages.
版权 © 2016, Texas Instruments Incorporated
5
TPS2552D, TPS2553D
ZHCSFI7 –SEPTEMBER 2016
www.ti.com.cn
7.4 Thermal Information
TPS2552D
DBV
TPS2553D
DBV
THERMAL METRIC(1)
UNIT
6 PINS
182.6
122.2
29.4
6 PINS
182.6
122.2
29.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
20.8
20.8
ψJB
28.9
28.9
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6
版权 © 2016, Texas Instruments Incorporated
TPS2552D, TPS2553D
www.ti.com.cn
ZHCSFI7 –SEPTEMBER 2016
7.5 Electrical Characteristics
over recommended operating conditions, VEN = VIN, RFAULT = 10 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP MAX UNIT
POWER SWITCH
DBV package, TJ = 25°C
DBV package, –40°C ≤TJ ≤125°C
rDS(on) Static drain-source on-state resistance DRV package, TJ = 25°C
DRV package, –40°C ≤TJ ≤105°C
85
95
135
115
140
150
1.5
1
100
mΩ
DRV package, –40°C ≤TJ ≤125°C
VIN = 6.5 V
1.1
0.7
tr
tf
Rise time, output
Fall time, output
VIN = 2.5 V
VIN = 6.5 V
VIN = 2.5 V
CL = 1 μF, RL = 100 Ω,
(see 图 20)
ms
0.2
0.2
0.5
0.5
ENABLE INPUT EN OR EN
Enable pin turn on/off threshold
Input current
0.66
–0.5
1.1
0.5
3
V
IEN
ton
toff
VEN = 0 V or 6.5 V, VEN = 0 V or 6.5 V
μA
ms
ms
Turnon time
Turnoff time
CL = 1 μF, RL = 100 Ω, (see 图 20)
3
CURRENT LIMIT
RILIM = 15 kΩ
–40°C ≤TJ ≤105°C
TJ = 25°C
1610 1700 1800
1215 1295 1375
1200 1295 1375
RILIM = 20 kΩ
–40°C ≤TJ ≤125°C
TJ = 25°C
Current-limit threshold (Maximum DC output current IOUT delivered to
load) and Short-circuit current, OUT connected to GND
IOS
490
475
110
50
520
520
130
75
550
565
150
100
mA
RILIM = 49.9 kΩ
–40°C ≤TJ ≤125°C
RILIM = 210 kΩ
ILIM shorted to IN
tIOS
Response time to short circuit
VIN = 5 V (see 图 21)
2
μs
REVERSE-VOLTAGE PROTECTION
Reverse-voltage comparator trip point
95
3
135
5
190
7
mV
ms
(VOUT – VIN
)
Time from reverse-voltage condition to
MOSFET turn off
VIN = 5 V
SUPPLY CURRENT
IIN_off Supply current, low-level output
VIN = 6.5 V, No load on OUT, VEN = 0 V
0.1
120
100
0.01
1
150
130
1
μA
μA
μA
μA
RILIM = 20 kΩ
IIN_on Supply current, high-level output
VIN = 6.5 V, No load on OUT
VOUT = 6.5 V, VIN = 0 V
RILIM = 210 kΩ
IREV
Reverse leakage current
TJ = 25 °C
UNDERVOLTAGE LOCKOUT
UVLO Low-level input voltage, IN
Hysteresis, IN
VIN rising
2.35
25
2.45
V
TJ = 25 °C
mV
FAULT FLAG
VOL
Output low voltage, FAULT
Off-state leakage
I/FAULT = 1 mA
V/FAULT = 6.5 V
180
1
mV
μA
FAULT assertion or de-assertion due to overcurrent condition
FAULT assertion or de-assertion due to reverse-voltage condition
5
2
7.5
4
10
6
ms
ms
FAULT deglitch
THERMAL SHUTDOWN
Thermal shutdown threshold
155
135
°C
°C
°C
Thermal shutdown threshold in
current-limit
Hysteresis
10
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
版权 © 2016, Texas Instruments Incorporated
7
TPS2552D, TPS2553D
ZHCSFI7 –SEPTEMBER 2016
www.ti.com.cn
7.6 Typical Characteristics
TPS2552D
10 mF
VIN
VOUT
IN
OUT
R
FAULT
10 kW
150 mF
ILIM
Fault Signal
Control Signal
FAULT
EN
R
ILIM
GND
Power Pad
图 2. Turnon Delay and Rise Time
图 1. Typical Characteristics Reference Schematic
图 4. Device Enabled into Short-Circuit
图 3. Turnoff Delay and Fall Time
图 6. Short-Circuit to Full-Load Recovery Response
图 5. Full-Load to Short-Circuit Transient Response
8
版权 © 2016, Texas Instruments Incorporated
TPS2552D, TPS2553D
www.ti.com.cn
ZHCSFI7 –SEPTEMBER 2016
Typical Characteristics (接下页)
图 8. Short-Circuit to No-Load Recovery Response
图 7. No-Load to Short-Circuit Transient Response
图 9. No Load to 1-Ω Transient Response
图 10. 1-Ω to No Load Transient Response
图 12. Reverse-Voltage Protection Recovery
图 11. Reverse-Voltage Protection Response
版权 © 2016, Texas Instruments Incorporated
9
TPS2552D, TPS2553D
ZHCSFI7 –SEPTEMBER 2016
www.ti.com.cn
Typical Characteristics (接下页)
2.40
0.40
0.36
0.32
R
= 20 kW
ILIM
R
= 20 kW
ILIM
2.39
2.38
2.37
2.36
2.35
2.34
2.33
2.32
2.31
2.30
0.28
0.24
0.20
0.16
0.12
0.08
UVLO Rising
V
= 6.5 V
IN
UVLO Falling
V
= 2.5 V
IN
0.04
0
-50
0
50
- Junction Temperature - °C
100
150
-50
0
50
100
150
T
T
- Junction Temperature - °C
J
J
图 14. IIN – Supply Current, Output Disabled – μA
图 13. UVLO – Undervoltage Lockout – V
150
135
120
105
90
20
18
16
14
R
= 20 kW
V
= 5 V,
IN
ILIM
V
= 6.5 V
IN
V
= 5 V
IN
R
T
= 20 kW,
ILIM
= 25°C
A
12
10
75
V
= 3.3 V
IN
V
= 2.5 V
IN
60
45
30
8
6
4
15
0
2
0
-50
0
50
- Junction Temperature - °C
100
150
0
1.5
3
4.5
6
T
J
Peak Current - A
图 15. IIN – Supply Current, Output Enabled – μA
图 16. Current Limit Response – μs
150
1400
1300
1200
125
DRV Package
T
= -40°C
= 25°C
1100
1000
900
800
700
600
500
400
300
200
A
T
100
A
T
= 125°C
DBV Package
A
75
50
25
0
V
= 6.5 V,
IN
R
= 20 kW
ILIM
100
0
0
100
200
300
400
V - V
IN
500
- 100 mV/div
OUT
600
700
800
900
1000
-50
0
50
100
150
T
- Junction Temperature - °C
J
图 18. Switch Current Vs. Drain-Source Voltage Across
图 17. MOSFET rDS(on) Vs. Junction Temperature
Switch
10
版权 © 2016, Texas Instruments Incorporated
TPS2552D, TPS2553D
www.ti.com.cn
ZHCSFI7 –SEPTEMBER 2016
Typical Characteristics (接下页)
150
140
130
120
110
100
T
= 25°C
T
= -40°C
A
A
T
= 125°C
A
90
80
70
60
50
40
30
V
= 6.5 V,
20
10
0
IN
R
= 200 kW
ILIM
0
100
200
300
400
- V
500
- 100 mV/div
OUT
600
700
800
900
1000
V
IN
图 19. Switch Current Vs. Drain-Source Voltage Across Switch
8 Parameter Measurement Information
OUT
t
f
t
r
R
C
L
L
90%
90%
V
OUT
%
%
10
10
TEST CIRCUIT
V
%
50
50%
V
50%
EN
50%
EN
t
off
t
t
on
off
t
t
off
on
90%
90%
V
V
OUT
OUT
10%
%
10
VOLTAGE WAVEFORMS
图 20. Test Circuit and Voltage Waveforms
I
OS
I
OUT
t
IOS
图 21. Response Time to Short Circuit Waveform
版权 © 2016, Texas Instruments Incorporated
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TPS2552D, TPS2553D
ZHCSFI7 –SEPTEMBER 2016
www.ti.com.cn
Parameter Measurement Information (接下页)
Decreasing
Load Resistance
V
OUT
Decreasing
Load Resistance
I
OUT
I
OS
图 22. Output Voltage Vs. Current-Limit Threshold
12
版权 © 2016, Texas Instruments Incorporated
TPS2552D, TPS2553D
www.ti.com.cn
ZHCSFI7 –SEPTEMBER 2016
9 Detailed Description
9.1 Overview
The TPS2552D and TPS2553D are current-limited, power-distribution switches using N-channel MOSFETs for
applications where short circuits or heavy capacitive loads will be encountered and provide up to 1.5 A of
continuous load current. These devices allow the user to program the current-limit threshold between 75 mA and
1.7 A (typ) via an external resistor. Additional device shutdown features include overtemperature protection and
reverse-voltage protection. The device incorporates an internal charge pump and gate drive circuitry necessary
to drive the N-channel MOSFET. The charge pump supplies power to the driver circuit and provides the
necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input
voltages as low as 2.7 V and requires little supply current. The driver controls the gate voltage of the power
switch. The driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large
current and voltage surges and provides built-in soft-start functionality. There are two device families that handle
overcurrent situations differently. The TPS255xD family enters constant-current mode when the load exceeds the
current-limit threshold.
9.2 Functional Block Diagram
-
Reverse
Voltage
Comparator
+
CS
OUT
IN
Current
Sense
Charge
Pump
Current
Limit
Driver
EN
FAULT
(Note A)
UVLO
GND
ILIM
Thermal
Sense
8-ms Deglitch
Copyright © 2016, Texas Instruments Incorporated
A. TPS255x parts enter constant current mode during current limit condition
9.3 Feature Description
9.3.1 Overcurrent Conditions
The TPS2552D and TPS2553D respiond to overcurrent conditions by limiting their output current to the IOS levels
shown in 图 23. When an overcurrent condition is detected, the device maintains a constant output current and
reduces the output voltage accordingly. Two possible overload conditions can occur.
The first condition is when a short circuit or partial short circuit is present when the device is powered-up or
enabled. The output voltage is held near zero potential with respect to ground and the TPS2552D and
TPS2553D ramps the output current to IOS. The TPS2552D and TPS2553D devices limits the current to IOS until
the overload condition is removed or the device begins to thermal cycle.
The second condition is when a short circuit, partial short circuit, or transient overload occurs while the device is
enabled and powered on. The device responds to the overcurrent condition within time tIOS (see 图 21). The
current-sense amplifier is overdriven during this time and momentarily disables the internal current-limit
MOSFET. The current-sense amplifier recovers and limits the output current to IOS. Similar to the previous case,
the TPS2552D and TPS2553D devices limit the current to IOS until the overload condition is removed or the
device begins to thermal cycle.
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TPS2552D, TPS2553D
ZHCSFI7 –SEPTEMBER 2016
www.ti.com.cn
Feature Description (接下页)
The TPS2552D/53D thermal cycles if an overload condition is present long enough to activate thermal limiting in
any of the above cases. The device turns off when the junction temperature exceeds 135°C (typ) while in current
limit. The device remains off until the junction temperature cools 10°C (typ) and then restarts. The
TPS2552D/53D cycle on/off until the overload is removed (see 图 6 and 图 8) .
9.3.2 Reverse-Voltage Protection
The reverse-voltage protection feature turns off the N-channel MOSFET whenever the output voltage exceeds
the input voltage by 135 mV (typ) for 4-ms (typ).A reverse current of (VOUT – VIN)/rDS(on)) are present when this
occurs. This prevents damage to devices on the input side of the TPS2552D/53D by preventing significant
current from sinking into the input capacitance. The TPS2552D/53D devices allow the N-channel MOSFET to
turn on once the output voltage goes below the input voltage for the same 4-ms deglitch time. The reverse-
voltage comparator also asserts the FAULT output (active-low) after 4-ms.
9.3.3 FAULT Response
The FAULT open-drain output is asserted (active low) during an overcurrent, overtemperature or reverse-voltage
condition. The TPS2552D/53D asserts the FAULT signal until the fault condition is removed and the device
resumes normal operation. The TPS2552D/53D are designed to eliminate false FAULT reporting by using an
internal delay "deglitch" circuit for overcurrent (7.5-ms typ) and reverse-voltage (4-ms typ) conditions without the
need for external circuitry. This ensures that FAULT is not accidentally asserted due to normal operation such as
starting into a heavy capacitive load. The deglitch circuitry delays entering and leaving fault conditions.
Overtemperature conditions are not deglitched and assert the FAULT signal immediately.
9.3.4 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn-
on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large current
surges.
9.3.5 ENABLE
The logic enable controls the power switch, bias for the charge pump, driver, and other circuits to reduce the
supply current. The supply current is reduced to less than 1-μA when a logic high is present on EN or when a
logic low is present on EN. A logic low input on EN or a logic high input on EN enables the driver,A logic high
input on EN enables the driver, control circuits, and power switch. The enable input is compatible with both TTL
and CMOS logic levels.
9.3.6 Thermal Sense
The TPS2552D/53D self-protection features use two independent thermal sensing circuits that monitor the
operating temperature of the power switch and disable operation if the temperature exceeds recommended
operating conditions. The TPS2552D/53D devices operate in constant-current mode during an overcurrent
conditions, which increases the voltage drop across power-switch. The power dissipation in the package is
proportional to the voltage drop across the power switch, which increases the junction temperature during an
overcurrent condition. The first thermal sensor turns off the power switch when the die temperature exceeds
135°C (min) and the part is in current limit. Hysteresis is built into the thermal sensor, and the switch turns on
after the device has cooled approximately 10°C.
The TPS2552D/3D also have a second ambient thermal sensor. The ambient thermal sensor turns off the power-
switch when the die temperature exceeds 155°C (min) regardless of whether the power switch is in current limit
and will turn on the power switch after the device has cooled approximately 10°C. The TPS2552D/53D families
continue to cycle off and on until the fault is removed.
The open-drain fault reporting output FAULT is asserted (active low) immediately during an overtemperature
shutdown condition.
9.4 Device Functional Modes
There are no other functional modes.
14
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ZHCSFI7 –SEPTEMBER 2016
9.5 Programming
9.5.1 Programming the Current-Limit Threshold
The overcurrent threshold is user programmable via an external resistor. The TPS2552D/53D use an internal
regulation loop to provide a regulated voltage on the ILIM pin. The current-limit threshold is proportional to the
current sourced out of ILIM. The recommended 1% resistor range for RILIM is 15 kΩ ≤ RILIM ≤ 232 kΩ to ensure
stability of the internal regulation loop. Many applications require that the minimum current limit is above a certain
current level or that the maximum current limit is below a certain current level, so it is important to consider the
tolerance of the overcurrent threshold when selecting a value for RILIM. The following equations and 图 23 can be
used to calculate the resulting overcurrent threshold for a given external resistor value (RILIM). 图 23 includes
current-limit tolerance due to variations caused by temperature and process. However, the equations do not
account for tolerance due to external resistor variation, so it is important to account for this tolerance when
selecting RILIM. The traces routing the RILIM resistor to the TPS2552D/53D should be as short as possible to
reduce parasitic effects on the current-limit accuracy.
RILIM can be selected to provide a current-limit threshold that occurs 1) above a minimum load current or 2)
below a maximum load current.
To design above a minimum current-limit threshold, find the intersection of RILIM and the maximum desired load
current on the IOS(min) curve and choose a value of RILIM below this value. Programming the current limit above a
minimum threshold is important to ensure start up into full load or heavy capacitive loads. The resulting maximum
current-limit threshold is the intersection of the selected value of RILIM and the IOS(max) curve.
To design below a maximum current-limit threshold, find the intersection of RILIM and the maximum desired load
current on the IOS(max) curve and choose a value of RILIM above this value. Programming the current limit below a
maximum threshold is important to avoid current limiting upstream power supplies causing the input voltage bus
to droop. The resulting minimum current-limit threshold is the intersection of the selected value of RILIM and the
IOS(min) curve.
Current-Limit Threshold Equations (IOS):
22980V
IOSmax (mA) =
RILIM0.94kW
23950V
RILIM0.977kW
IOSnom(mA) =
25230V
RILIM1.016kW
IOSmin(mA) =
(1)
where 15 kΩ ≤ RILIM ≤ 232 kΩ.
While the maximum recommended value of RILIM is 232 kΩ, there is one additional configuration that allows for
a lower current-limit threshold. The ILIM pin may be connected directly to IN to provide a 75 mA (typ) current-limit
threshold. Additional low-ESR ceramic capacitance may be necessary from IN to GND in this configuration to
prevent unwanted noise from coupling into the sensitive ILIM circuitry.
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www.ti.com.cn
Programming (接下页)
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
I
OS(max)
I
OS(nom)
400
300
I
200
100
OS(min)
0
15 25 35 45 55 65 75 85 95 105 115 125 135 145 155 165 175 185 195 205 215 225 235
- Current Limit Resistor - kW
R
ILIM
图 23. Current-Limit Threshold vs RILIM
16
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www.ti.com.cn
ZHCSFI7 –SEPTEMBER 2016
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Constant-Current and Impact on Output Voltage
During normal operation the N-channel MOSFET is fully enhanced, and VOUT = VIN - (IOUT x rDS(on)). The voltage
drop across the MOSFET is relatively small compared to VIN, and VOUT ≉ VIN.
The TPS2552D/53D devices limit current to the programmed current-limit threshold set to RILIM by operating the
N-channel MOSFET in the linear mode. During current-limit operation, the N-channel MOSFET is no longer fully-
enhanced and the resistance of the device increases. This allows the device to effectively regulate the current to
the current-limit threshold. The effect of increasing the resistance of the MOSFET is that the voltage drop across
the device is no longer negligible (VIN ≠ VOUT), and VOUT decreases. The amount that VOUT decreases is
proportional to the magnitude of the overload condition. The expected VOUT can be calculated by IOS × RLOAD
,
where IOS is the current-limit threshold and RLOAD is the magnitude of the overload condition. For example, if IOS
is programmed to 1 A and a 1 Ω overload condition is applied, the resulting VOUT is 1 V.
The TPS2552D/53D devices assert the FAULT flag after the deglitch period and continue to regulate the current
to the current-limit threshold indefinitely. In practical circuits, the power dissipation in the package will increase
the die temperature above the overtemperature shutdown threshold (135°C min), and the device will turn off until
the die temperature decreases by the hysteresis of the thermal shutdown circuit (10°C typ). The device will turn
on and continue to thermal cycle until the overload condition is removed. The TPS2552D/53D devices resume
normal operation once the overload condition is removed.
10.2 Typical Applications
10.2.1 Two-Level Current-Limit Circuit
Some applications require different current-limit thresholds depending on external system conditions. 图 24
shows an implementation for an externally controlled, two-level current-limit circuit. The current-limit threshold is
set by the total resistance from ILIM to GND (see the Programming the Current-Limit Threshold section). A logic-
level input enables/disables MOSFET Q1 and changes the current-limit threshold by modifying the total
resistance from ILIM to GND. Additional MOSFET/resistor combinations can be used in parallel to Q1/R2 to
increase the number of additional current-limit levels.
注
ILIM should never be driven directly with an external signal.
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Typical Applications (接下页)
Input
0.1 mF
Output
IN
OUT
R
R
FAULT
C
LOAD
LOAD
100 kW
R1
210 kW
ILIM
R2
22.1 kW
Fault Signal
FAULT
EN
GND
Control Signal
Power Pad
Q1
2N7002
Current Limit
Control Signal
Copyright © 2016, Texas Instruments Incorporated
图 24. Two-Level Current-Limit Circuit
10.2.1.1 Design Requirements
For this example, use the parameters shown in 表 1.
表 1. Design Requirements
PARAMETER
Input voltage
VALUE
5 V
Output voltage
5 V
Above a minimum current limit
Below a maximum current limit
1000 mA
500 mA
10.2.1.2 Detailed Design Procedures
10.2.1.2.1 Designing Above a Minimum Current Limit
Some applications require that current limiting cannot occur below a certain threshold. For this example, assume
that 1 A must be delivered to the load so that the minimum desired current-limit threshold is 1000 mA. Use the
IOS equations and 图 23 to select RILIM
.
IOSmin (mA) = 1000mA
25230V
RILIM1.016kW
IOSmin (mA) =
1
æ
ç
ç
ö1.016
25230V
mA
÷
÷
÷
÷
ø
RILIM (kW) =
ç
ç
è
I
OSmin
RILIM (kW) = 24kW
(2)
Select the closest 1% resistor less than the calculated value: RILIM = 23.7 kΩ. This sets the minimum current-limit
threshold at 1 A . Use the IOS equations, 图 23, and the previously calculated value for RILIM to calculate the
maximum resulting current-limit threshold.
RILIM(kW) = 23.7kW
22980V
RILIM0.94kW
IOSmax (mA) =
22980V
23.70.94kW
IOSmax (mA) =
IOSmax (mA) = 1172.4mA
(3)
The resulting maximum current-limit threshold is 1172.4 mA with a 23.7 kΩ resistor.
18
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ZHCSFI7 –SEPTEMBER 2016
10.2.1.2.2 Designing Below a Maximum Current Limit
Some applications require that current limiting must occur below a certain threshold. For this example, assume
that the desired upper current-limit threshold must be below 500 mA to protect an up-stream power supply. Use
the IOS equations and 图 23 to select RILIM
.
IOSmax (mA) = 500mA
22980V
RILIM0.94kW
IOSmax (mA) =
1
æ
ç
ç
ö0.94
22980V
÷
÷
÷
÷
ø
RILIM(kW) =
ç
ç
I
mA
è OSmax
RILIM(kW) = 58.7kW
(4)
Select the closest 1% resistor greater than the calculated value: RILIM = 59 kΩ. This sets the maximum current-
limit threshold at 500 mA . Use the IOS equations, 图 23, and the previously calculated value for RILIM to calculate
the minimum resulting current-limit threshold.
RILIM(kW) = 59kW
25230V
RILIM1.016kW
IOSmin(mA) =
25230V
591.016kW
IOSmin(mA) =
IOSmin(mA) = 400.6mA
(5)
The resulting minimum current-limit threshold is 400.6 mA with a 59 kΩ resistor.
10.2.1.2.3 Accounting for Resistor Tolerance
The previous sections described the selection of RILIM given certain application requirements and the importance
of understanding the current-limit threshold tolerance. The analysis focused only on the TPS2552D/53D
performance and assumed an exact resistor value. However, resistors sold in quantity are not exact and are
bounded by an upper and lower tolerance centered around a nominal resistance. The additional RILIM resistance
tolerance directly affects the current-limit threshold accuracy at a system level. The following table shows a
process that accounts for worst-case resistor tolerance assuming 1% resistor values. Step one follows the
selection process outlined in the application examples above. Step two determines the upper and lower
resistance bounds of the selected resistor. Step three uses the upper and lower resistor bounds in the IOS
equations to calculate the threshold limits. It is important to use tighter tolerance resistors, e.g. 0.5% or 0.1%,
when precision current limiting is desired.
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表 2. Common RILIM Resistor Selections
DESIRED
RESISTOR TOLERANCE
ACTUAL LIMITS
IDEAL
RESISTOR
CLOSEST
1% RESISTOR
NOMINAL
CURRENT LIMIT
(mA)
IOS MIN
(mA)
IOS NOM
(mA)
IOS MAX
(mA)
1% LOW (kΩ) 1% HIGHT (kΩ)
(kΩ)
(kΩ)
75
SHORT ILIM to IN
50.0
101.3
173.7
262.1
351.2
448.3
544.3
630.2
729.1
824.7
908.3
1023.7
1106.0
1215.1
1310.1
1412.5
1512.5
1594.5
75.0
120.0
201.5
299.4
396.7
501.6
604.6
696.0
800.8
901.5
989.1
1109.7
1195.4
1308.5
1406.7
1512.4
1615.2
1699.3
100.0
142.1
120
226.1
134.0
88.5
65.9
52.5
43.5
37.2
32.4
28.7
25.8
23.4
21.4
19.7
18.3
17.0
16.0
15.0
226
133
223.7
131.7
87.8
65.8
51.8
42.8
37.0
32.1
28.4
25.8
23.0
21.3
19.4
18.0
16.7
15.6
14.9
228.3
134.3
89.6
67.2
52.8
43.6
37.8
32.7
29.0
26.4
23.4
21.7
19.8
18.4
17.1
16.0
15.2
200
233.9
300
88.7
66.5
52.3
43.2
37.4
32.4
28.7
26.1
23.2
21.5
19.6
18.2
16.9
15.8
15.0
342.3
400
448.7
500
562.4
600
673.1
700
770.8
800
882.1
900
988.7
1000
1100
1200
1300
1400
1500
1600
1700
1081.0
1207.5
1297.1
1414.9
1517.0
1626.4
1732.7
1819.4
10.2.1.2.4 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance should be
optimized for the particular application. For all applications, a 0.1μF or greater ceramic bypass capacitor between
IN and GND is recommended as close to the device as possible for local noise de-coupling. This precaution
reduces ringing on the input due to power-supply transients. Additional input capacitance may be needed on the
input to reduce voltage overshoot from exceeding the absolute maximum voltage of the device during heavy
transient conditions. This is especially important during bench testing when long, inductive cables are used to
connect the evaluation board to the bench power-supply.
Placing a high-value electrolytic capacitor on the output pin is recommended when large transient currents are
expected on the output.
10.2.1.3 Application Curves
图 25. Turn on Delay and Rise Time
图 26. Reverse-Voltage Protection Recovery
20
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ZHCSFI7 –SEPTEMBER 2016
10.2.2 Auto-Retry Functionality
Some applications require that an overcurrent condition disables the part momentarily during a fault condition
and re-enables after a pre-set time. This auto-retry functionality can be implemented with an external resistor and
capacitor. During a fault condition, FAULT pulls low disabling the part. The part is disabled when EN is pulled
low, and FAULT goes high impedance allowing CRETRY to begin charging. The part re-enables when the voltage
on EN reaches the turnon threshold, and the auto-retry time is determined by the resistor/capacitor time
constant. The device continues to cycle in this manner until the fault condition is removed.
TPS2553D
0.1 mF
Input
Output
IN
OUT
R
R
LOAD
FAULT
C
LOAD
100 kW
ILIM
R
ILIM
FAULT
EN
20 kW
GND
C
RETRY
Power Pad
0.1 mF
图 27. Auto-Retry Functionality
Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal. 图
28 shows how an external logic signal can drive EN through RFAULT and maintain auto-retry functionality. The
resistor/capacitor time constant determines the auto-retry time-out period.
TPS2553D
0.1 mF
Input
Output
IN
OUT
R
LOAD
C
LOAD
ILIM
External Logic
Signal & Driver
R
R
FAULT
ILIM
FAULT
EN
100 kW
20 kW
GND
C
RETRY
Power Pad
0.1 mF
图 28. Auto-Retry Functionality With External EN Signal
10.2.2.1 Design Requirements
For this example, use the parameters shown in 表 3.
表 3. Design Requirements
PARAMETER
Input voltage
Output voltage
Current
VALUE
5 V
5 V
1200 mA
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10.2.2.2 Detailed Design Procedure
Refer to Programming the Current-Limit Threshold section for the current limit setting. For auto-retry functionality,
once FAULT asserted, EN pull low, TPS2553D is disabled, FAULT des-asserted, CRETRY is slowly charged to EN
logic high via RFAULT, then enable, after deglitch time, FAULT asserted again. In the event of an over-load,
TPS2553D cycles and has output average current. ON-time with output current is decided by FAULT deglitch
time. OFF-time without output current is decided by RFAULT x CRETRY constant time to EN logic high and ton time.
Therefore, set the RFAULT × CRETRY to get the desired output average current during overload.
22
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ZHCSFI7 –SEPTEMBER 2016
10.2.3 Typical Application as USB Power Switch
TPS2552D/53D
5V USB
Input
USB Data
0.1 mF
USB
Port
IN
OUT
RFAULT
100 kW
120 mF
ILIM
RILIM
Fault Signal
Control Signal
FAULT
EN
USB requirement only*
20 kW
GND
*USB requirement that downstream
facing ports are bypassed with at least
120 mF per hub
Power Pad
图 29. Typical Application as USB Power Switch
10.2.3.1 Design Requirements
For this example, use the parameters shown in 表 4.
表 4. Design Requirements
PARAMETER
Input voltage
Output voltage
Current
VALUE
5 V
5 V
1200 mA
10.2.3.1.1 USB Power-Distribution Requirements
USB can be implemented in several ways regardless of the type of USB device being developed. Several power-
distribution features must be implemented.
•
SPHs must:
–
–
Current limit downstream ports
Report overcurrent conditions
•
BPHs must:
–
–
–
Enable/disable power to downstream ports
Power up at <100 mA
Limit inrush current (<44 Ω and 10 μF)
•
Functions must:
–
–
Limit inrush currents
Power up at <100 mA
The feature set of the TPS2552D/53D meets each of these requirements. The integrated current limiting and
overcurrent reporting is required by self-powered hubs. The logic-level enable and controlled rise times meet the
need of both input and output ports on bus-powered hubs and the input ports for bus-powered functions.
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10.2.3.2 Detailed Design Procedure
10.2.3.2.1 Universal Serial Bus (USB) Power-Distribution Requirements
One application for this device is for current limiting in universal serial bus (USB) applications. The original USB
interface was a 12-Mb/s or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC
peripherals (e.g., keyboards, printers, scanners, and mice). As the demand for more bandwidth increased, the
USB 2.0 standard was introduced increasing the maximum data rate to 480-Mb/s. The four-wire USB interface is
conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data,
and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply. The USB specification classifies two different classes of
devices depending on its maximum current draw. A device classified as low-power can draw up to 100 mA as
defined by the standard. A device classified as high-power can draw up to 500 mA. It is important that the
minimum current-limit threshold of the current-limiting power-switch exceed the maximum current-limit draw of
the intended application. The latest USB standard should always be referenced when considering the current-
limit threshold
The USB specification defines two types of devices as hubs and functions. A USB hub is a device that contains
multiple ports for different USB devices to connect and can be self-powered (SPH) or bus-powered (BPH). A
function is a USB device that is able to transmit or receive data or control information over the bus. A USB
function can be embedded in a USB hub. A USB function can be one of three types included in the list below.
•
•
•
Low-power, bus-powered function
High-power, bus-powered function
Self-powered function
SPHs and BPHs distribute data and power to downstream functions. The TPS2552D/53D have higher current
capabilities than required for a single USB port allowing it to power multiple downstream ports.
24
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ZHCSFI7 –SEPTEMBER 2016
11 Power Supply Recommendations
11.1 Self-Powered and Bus-Powered Hubs
A SPH has a local power supply that powers embedded functions and downstream ports. This power supply
must provide between 4.75 V to 5.25 V to downstream facing devices under full-load and no-load conditions.
SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller.
Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.
A BPH obtains all power from an upstream port and often contains an embedded function. It must power up with
less than 100 mA. The BPH usually has one embedded function, and power is always available to the controller
of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the
embedded function may need to be kept off until enumeration is completed. This is accomplished by removing
power or by shutting off the clock to the embedded function. Power switching the embedded function is not
necessary if the aggregate power draw for the function and controller is less than 100 mA. The total current
drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the
downstream ports, and it is limited to 500 mA from an upstream port.
11.2 Low-Power Bus-Powered and High-Power Bus-Powered Functions
Both low-power and high-power bus-powered functions obtain all power from upstream ports. Low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 μF at power up, the device must implement inrush current limiting.
11.3 Power Dissipation and Junction Temperature
The low on-resistance of the N-channel MOSFET allows small surface-mount packages to pass large currents. It
is good design practice to estimate power dissipation and junction temperature. The below analysis gives an
approximation for calculating junction temperature based on the power dissipation in the package. However, it is
important to note that thermal analysis is strongly dependent on additional system level factors. Such factors
include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating
power. Good thermal design practice must include all system level factors in addition to individual component
analysis.
Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating
temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on)
from the typical characteristics graph. Using this value, the power dissipation can be calculated using 公式 6.
2
PD = rDS(on) × IOUT
where
•
•
•
•
PD = Total power dissipation (W)
rDS(on) = Power switch on-resistance (Ω)
IOUT = Maximum current-limit threshold (A)
This step calculates the total power dissipation of the N-channel MOSFET.
(6)
Finally, calculate the junction temperature:
TJ = PD × θJA + TA
where
•
•
•
TA = Ambient temperature (°C)
θJA = Thermal resistance (°C/W)
PD = Total power dissipation (W)
(7)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat
the calculation using the "refined" rDS(on) from the previous calculation as the new estimate. Two or three
iterations are generally sufficient to achieve the desired result. The final junction temperature is highly dependent
on thermal resistance θJA, and thermal resistance is highly dependent on the individual package and board
layout. The Thermal Information Table provides example thermal resistances for specific packages and board
layouts.
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www.ti.com.cn
12 Layout
12.1 Layout Guidelines
•
•
•
•
TI recommends placing the 100-nF bypass capacitor near the IN and GND pins, and make the connections
using a low-inductance trace.
TI recommends placing a high-value electrolytic capacitor and a 100-nF bypass capacitor on the output pin is
recommended when large transient currents are expected on the output.
The traces routing the RILIM resistor to the device should be as short as possible to reduce parasitic effects
on the current limit accuracy.
The PowerPAD should be directly connected to PCB ground plane using wide and short copper trace.
12.2 Layout Example
/FAULT
IN
1
2
3
6
5
4
OUT
ILIM
EN
图 30. Layout Recommendation
26
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TPS2552D, TPS2553D
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ZHCSFI7 –SEPTEMBER 2016
13 器件和文档支持
13.1 器件支持
有关 TI 开关产品组合的信息，请访问此处。
13.2 相关链接
下面的表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，以及样片或购买的快速访
问。
表 5. 相关链接
器件
产品文件夹
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TPS2552D
TPS2553D
13.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
13.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS2552DDBVR
TPS2552DDBVT
TPS2553DDBVR
TPS2553DDBVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
15IL
15IL
15JL
15JL
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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