TPS25810RVCT [TI]

具有 VCONN 的 USB Type-C™ 电源控制器和 3A 电源开关 | RVC | 20 | -40 to 125;


型号：	TPS25810RVCT
厂家：	TEXAS INSTRUMENTS
描述：	具有 VCONN 的 USB Type-C™ 电源控制器和 3A 电源开关 \| RVC \| 20 \| -40 to 125 开关控制器电源开关接口集成电路
文件：	总39页 (文件大小：1349K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

TPS25810 具有负载检测功能的 USB Type-C DFP 控制器和电源开关

1 特性

3 说明

•

兼容 USB Type-C 版本 1.2 的下行数据端口 (DFP)

控制器

TPS25810 是一款 USB Type-C 下行端口 (DFP) 控制

器，集成了一个额定电流为 3A 的 USB 电源开关。

TPS25810 监视 Type-C 配置通道 (CC) 线路，确定何

时连接了 USB 设备。如果连接了上行端口 (UFP) 设

备，TPS25810 将对 V_BUS供电并将可选的 V_BUS拉电

流能力通过直通 CC 线通告给 UFP。如果使用电子标

记电缆连接了 UFP，TPS25810 还会将 V_CONN电源施

加于电缆 CC 引脚。TPS25810 还会识别何时连接了

Type-C 音频或调试附件。

•

连接器连接/断开检测

配置通道 (CC) STD/1.5A/3A 电流能力通告

超高速极性确定

V_BUS应用和放电

V_CONN应用于电子标记电缆

音频和调试附件识别

端口未连接时，I_DDQ的典型值为 0.7µA

三个输入电源选项

TPS25810 在未连接设备时的电流消耗低于 0.7uA（典

型值）。未连接 UFP 时，可使用 UFP 输出禁用高功

率 5V 电源，从而在 S4/S5 系统功耗状态下节省更多

系统电力。在此模式下，器件能够由电压较低 (3.3V)

的辅助电源 (AUX) 供电运行，该电源通常在低功耗状

态 (S4/S5) 下为系统微控制器供电。

–

IN1：USB 充电电源

IN2：V_CONN电源

AUX：器件电源

•

电源唤醒可保证系统冬眠 (S4) 和关闭 (S5) 功耗状

态下的低功耗

34mΩ（典型值）高侧金属氧化物半导体场效应晶

体管 (MOSFET)

TPS25810 34mΩ 电源开关有两个可选的固定电流限

值，与 Type-C 电流水平相对应。FAULT 输出会在开

关处于过流或过热条件下发出信号。在所有端口不能同

时提供高电流 (3A) 的环境下，LD_DET 输出可对多个

高电流 Type-C 端口的功率管理进行控制。

•

1.7/3.4A I_Limit(±7.1%) - 可编程

端口功率管理可实现多端口的功率资源优化

封装：20 引脚晶圆级四方扁平无引线 (WQFN) 封

(1)

装 (3mm x 4mm)

•

UL列表 - 文件号E169910

器件信息⁽¹⁾

器件型号

TPS25810

封装

封装尺寸（标称值）

2 应用

超薄四方扁平无引线

(WQFN) (20)

•

笔记本中的 USB Type C 主机端口，用于休眠充电

3.00mm x 4.00mm

LCD 监视器/扩展坞和充电托板

Type C USB 壁式充电器

(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

(1) CC 引脚符合 IEC-61000-4-2 标准

简化电路原理图

6 x 100kΩ

(

)

optional

TPS25810

Bus Power

CC Power

4.5 Vœ 6.5V

4.5 Vœ 5.5V

2.9 Vœ 5.5V

V^BUS

OUT

IN1

FAULT

LD_DET

CC1

IN2

Power Switch

Status Signals

Auxiliary Power

AUX

120mF

CC2

UFP

Control Signals

CHG

CHG_HI

REF

POL

Type- C DFP

Status Signals

AUDIO

DEBUG

Power Pad

6.8mF

100 kΩ

(1%)

REF_RTN GND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSCR1

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

7.4 Device Functional Modes........................................ 21

Application and Implementation ........................ 22

8.1 Application Information............................................ 22

8.2 Typical Applications ................................................ 22

Power Supply Recommendations...................... 27

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 7

6.7 Typical Characteristics.............................................. 9

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 13

7.3 Feature Description................................................. 13

10 Layout................................................................... 28

10.1 Layout Guidelines ................................................. 28

10.2 Layout Example .................................................... 29

11 器件和文档支持 ..................................................... 30

11.1 器件支持 ............................................................... 30

11.2 文档支持 ............................................................... 30

11.3 接收文档更新通知 ................................................. 30

11.4 社区资源................................................................ 30

11.5 商标....................................................................... 30

11.6 静电放电警告......................................................... 30

11.7 Glossary................................................................ 30

12 机械、封装和可订购信息....................................... 30

4 修订历史记录

Changes from Revision B (May 2016) to Revision C

Page

•

更改了特性：将兼容 USB Type-C 1.1 的 DFP 控制器更改为兼容 USB Type-C 1.2 的 DFP 控制器..................................... 1

Changed text From: Type-C spec revision 1.1 To: Type-C spec revision 1.2 in the Overview section............................... 11

Replaced 图 15 .................................................................................................................................................................... 18

Changes from Revision A (September 2015) to Revision B

Page

•

已添加添加了脚注：CC 引脚符合 IEC-61000-4-2 标准......................................................................................................... 1

已更改将特性部分中的“正接受 UL 和 CB 测试”更改为“UL 认证列名”- 文件编号E169910 ................................................... 1

已更改将简化电路原理图中的 10µF 更改为 6.8µF ................................................................................................................ 1

Added text to REF description ............................................................................................................................................... 3

Added IEC information to ESD Ratings ................................................................................................................................. 4

Changed IN2 I_Iparameter description in Electrical Characteristics ...................................................................................... 7

Changed t_resto t_iosin Switching Characteristics .................................................................................................................... 8

已添加 text to Detecting a Connection section .................................................................................................................... 12

已更改 Rp to Rds in 图 12 ................................................................................................................................................... 12

已更改 loss to drop in 图 14 ................................................................................................................................................ 16

已添加 text and 图 15 to Plug Polarity Detection.................................................................................................................. 18

已添加 last sentence to Input and Output Capacitance ...................................................................................................... 23

已添加 ESD Considerations to Layout Guidelines ............................................................................................................... 28

已添加《保护 TPS25810 免受高电压 DFP 损坏》添加到了“相关文档”............................................................................... 30

Changes from Original (September 2015) to Revision A

Page

•

已更改 “产品预览”更改为“生产数据”........................................................................................................................................ 1

TPS25810

www.ti.com.cn

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

5 Pin Configuration and Functions

RVC Package

20-Pin WQFN

Top View

C!Ü[Ç

Lb1

59.ÜD

Çhermal

tad

ꢀÜÇ

//2

Db5

//1

Lb1

Lb2

!Üó

Pin Functions

I/O

DESCRIPTION

NAME

NUMBER

Fault event indicator. Open-drain logic output that asserts low to indicate current limit or thermal shutdown event

due to over temperature.

FAULT

IN1

IN2

2, 3

V_BUSinput supply. Internal power switch connects IN1 to OUT.

V_CONNinput supply. Internal power switch connects IN2 to CC1 or CC2. Short to IN1 if only one supply is used.

Auxiliary input supply. Connect to always alive system rail to use the Power Wake feature. Short to IN1 and IN2 if

only one supply is used.

AUX

Enable logic input to turn the device on and off.

Charge logic input to select between standard USB (500 mA for a Type C receptacle supporting only USB 2.0 and

900 mA for Type C receptacle supporting USB 3.1) or Type-C current sourcing ability.

CHG

High-charge logic input to select between 1.5-A and 3-A Type-C current sourcing capability. Valid when CHG is

set to Type-C current.

CHG_HI

REF_RTN

REF

Precision signal reference return. Connect to REF pin via 100-kΩ, 1% resistor.

Analog input used to generate internal current reference. Connect a 1% or better, 100 ppm, 100-kΩ resistor

between this pin and REF_RTN.

CC1

GND

I/O

–

Analog input/output that connects to the Type-C receptacle CC1 pin

Power ground

CC2

I/O

Analog input/output that connects to the Type-C receptacle CC2 pin.

Power switch output.

OUT

14,15

DEBUG

AUDIO

Open-drain logic output that asserts when a Type-C Debug accessory is identified on the CC lines.

Open-drain logic output that asserts when a Type-C Audio accessory is identified on the CC lines.

Polarity open-drain logic output that signals which Type-C CC pin is connected to the CC line. This gives the

information needed to mux the super speed lines. Asserted when the CC2 pin is connected to the CC line in

cable.

POL

UFP

–

Open-drain logic output that asserts when a Type-C UFP is identified on the CC lines.

Load-detect open-drain logic output that signals when a device set to source Type-C 3 A current is sourcing over

1.95 A nominal.

LD_DET

Thermal Pad

Thermal pad on bottom of package.

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range, voltages are respect to GND (unless otherwise noted)

(1)

MIN

MAX

UNIT

IN1, IN2, AUX, EN, CHG, CHG_HI, REF, OUT, LD_DET,

FAULT, CC1, CC2, UFP, POL, AUDIO, DEBUG

–0.3

Pin voltage, V

Internally

connected

to GND

REF_RTN

Internally

limited

Pin positive source current, I_SRC

Pin positive sink current, I_SNK

OUT, REF, CC1, CC2

OUT (while applying VBUS)

CC1, CC2 (while applying V_CONN

)

Internally

limited

LD_DET, FAULT, UFP, POL, AUDIO, DEBUG

Operating junction temperature, T_J

Storage temperature range, T_stg

–40

–65

180

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽²⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽³⁾

Electrostatic

discharge

(1)

V_(ESD)

IEC61000-4-2 contact discharge, CC1 and CC2

IEC⁽⁴⁾

±8000

±15000

IEC61000-4-2 air discharge, CC1 and CC2

(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into

the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(4) Surges per IEC61000-402, 1999 applied between CC1/CC2 and output ground of the TPS25810EVM-745.

6.3 Recommended Operating Conditions

Voltages are with respect to GND (unless otherwise noted)

MIN NOM

MAX UNIT

IN1

4.5

2.9

6.5

V_I

Supply voltage

IN2

5.5

AUX

V_I

Input voltage

EN, CHG, CHG_HI

V_IH

V_IL

High-level input voltage

Low-level voltage

1.17

0.63

5.5

Used on LD_DET, FAULT, UFP, POL, AUDIO,

DEBUG

V_PU

I_SRC

I_SNK

Pull-up voltage

OUT

Positive source current

CC1 or CC2 when supplying VCONN

250

Positive sink current (10 ms moving

average)

LD_DET, FAULT, UFP, POL, AUDIO, DEBUG

Internally

Limited

I_{SNK_PULSE}Positive repetitive pulse sink current LD_DET, FAULT, UFP, POL, AUDIO, DEBUG

R_REF

T_J

Reference Resistor

100

102

125

kΩ

Operating junction temperature

–40

°C

TPS25810

www.ti.com.cn

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

6.4 Thermal Information

TPS25810

THERMAL METRIC⁽¹⁾

RVC (WQFN)

UNIT

20 PINS

39.3

43.4

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.7

ψ_JB

R_θJC(bot)

4.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF= 100

kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined positive out of the indicated pin

(unless otherwise noted)

PARAMETER

OUT - POWER SWITCH

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_J= 25°C, I_OUT= 3 A

R_DS(on)

On resistance⁽¹⁾

–40°C ≤ T_J≤ 85°C, I_OUT= 3 A

–40°C ≤ T_J≤ 125°C, I_OUT= 3 A

V_OUT= 6.5 V, V_IN1= V_EN= 0 V,

mΩ

I_REV

OUT to IN reverse leakage current –40°C ≤ T_J≤ 85°C,

µA

I_REVis current out of IN1 pin

OUT - CURRENT LIMIT

V_CHG= 0 V or V_CHG= V_AUXand V_{CHG_HI}= 0

1.58

3.16

1.7

3.4

1.82

(1)

I_OS

Short circuit current limit

V_CHG= V_AUXand V_{CHG_HI}= V_AUX

3.64

R_REF= 10 Ω

OUT - DISCHARGE

V_OUT= 4 V, UFP signature removed from

CC lines, time < t_{w_DCHG}

Discharge resistance

400

100

500

150

600

250

V_OUT= 4 V, No UFP signature on CC lines,

time > t_{w_DCHG}

Bleed discharge resistance

kΩ

REF

V_O

Output voltage

0.78

9.5

0.8

0.82

15.3

I_OS

Short circuit current

R_REF= 10 Ω

µA

FAULT

V_OL

Output low voltage

Off-state leakage

I_FAULT= 1 mA

V_FAULT= 5.5 V

350

µA

I_OFF

LD_DET

V_OL

Output low voltage

Off-state leakage

I_{LD_DET}= 1 mA

V_{LD_DET}= 5.5 V

350

µA

I_OFF

OUT sourcing, rising threshold

current for load detect

Hysteresis⁽²⁾

I_TH

1.8

1.95

125

2.1

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account

separately.

(2) These parameters are provided for reference only and do not constitute part of TI’s published specifications for purposes of TI’s product

warranty.

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

Electrical Characteristics (continued)

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF= 100

kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined positive out of the indicated pin

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CC1/CC2 - V_CONNPOWER SWITCH

T_J= 25°C, I_OUT= 250 mA

365

420

530

600

R_DS(on)

On resistance

-40°C ≤ T_J≤ 85°C, I_OUT= 250 mA

-40°C ≤ T_J≤ 125°C, I_OUT= 250 mA

mΩ

CC1/CC2 - V_CONNPOWER SWITCH - CURRENT LIMIT

300

355

410

800

I_OS

Short circuit current limit⁽¹⁾

R_REF= 10 Ω

CC1/CC2 – CONNECT MANAGEMENT – DANGLING ELECTRONICALLY MARKED CABLE MODE

Sourcing current on the pass-

0 V ≤ V_CCx≤ 1.5 V

µA

through CC Line

I_SRC

Sourcing current on the Ra CC

0 V ≤ V_CCx≤ 1.5 V

line

CC1/CC2 – CONNECT MANAGEMENT – ACCESSORY MODE

CCx Sourcing current

0 V ≤ V_CCx≤ 1.5 V

µA

(CC2- Audio, CC1-Debug)

I_SRC

CCx Sourcing current

0 V ≤ V_CCx≤ 1.5 V

(2)

(CC1- Audio, CC2-Debug)

CC1/CC2 – CONNECT MANAGEMENT – UFP MODE

0 V ≤ V_CCx≤ 1.5 V

V_IN1< V_{TH_UVLO_IN1}or V_IN2< V_{TH_UVLO_IN2}

Sourcing current with either IN1 or

IN2 in UVLO

I_SRC

µA

V_CHG= 0 V and V_{CHG_HI}= 0 V

0 V ≤ V_CCx≤ 1.5 V

V_CHG= V_AUXand V_{CHG_HI}= 0 V

0 V ≤ V_CCx≤ 1.5 V

I_SRC

Sourcing current

170

312

180

330

190

348

V_CHG= V_AUXand V_{CHG_HI}= V_AUX

0 V ≤ V_CCx≤ 2.45 V

UFP, POL, AUDIO, DEBUG

V_OL

I_OFF

Output low voltage

Off-state leakage

I_{SNK_PIN}= 1 mA

V_PIN= 5.5 V

250

µA

EN, CHG, CHG_HI - LOGIC INPUTS

V_TH

Rising threshold voltage

Falling threshold voltage

Hysteresis⁽²⁾

0.925

0.875

1.15

0.5

0.65

–0.5

µA

I_IN

Input current

V_EN= 0 V or 6.5 V

OVER TEMPERATURE SHUT DOWN

Rising threshold temperature for

device shutdown

Hysteresis⁽²⁾

T_{TH_OTSD2}

155

135

°C

Rising threshold temperature for

OUT/ V_CONNswitch shutdown in

current limit

Hysteresis⁽²⁾

T_{TH_OTSD1}

°C

IN1

V_{TH_UVLO_IN1}Rising threshold voltage for UVLO

Hysteresis⁽²⁾

3.9

4.1

4.3

100

TPS25810

www.ti.com.cn

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

Electrical Characteristics (continued)

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF= 100

kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined positive out of the indicated pin

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Disabled supply current

V_EN= 0 V, -40°C ≤ T_J≤ 85°C

µA

Enabled supply current with CC

lines open

-40°C ≤ T_J≤ 85°C

µA

Enabled supply current with

accessory or dangling

electronically marked cable

signature on CC lines

I_I

V_CHG= 0 V, or V_CHG= V_AUXand V_{CHG_HI}

0 V

100

110

Enabled supply current with UFP

attached

µA

IN2

V_{TH_UVLO_IN2}Rising threshold voltage for UVLO

Hysteresis⁽²⁾

3.9

4.1

4.3

100

µA

I_I

Disabled supply current

V_EN= 0 V, -40°C ≤ T_J≤ 85°C

-40°C ≤ T_J≤ 85°C

Enabled supply current with CC

lines open

µA

Enabled supply current with

accessory or dangling

electronically marked cable

signature on CC lines

I_I

µA

Enabled supply current with UFP

signature on CC lines

(Includes IN current that provides

the CC output current to the UFP

Rd resistor)

V_CHG= 0 V, 0 V ≤ V_CCx≤ 1.5 V

198

348

110

215

373

V_CHG= V_INand V_{CHG_HI}= 0 V, 0 V ≤ V_CCx

1.5 V

≤

I_I

µA

0 V ≤ V_CCx≤ 2.45 V

AUX

V_{TH_UVLO_AUX}Rising threshold voltage for UVLO

Hysteresis⁽²⁾

2.65

2.75

100

2.85

µA

I_I

Disabled supply current

V_EN= 0 V, -40°C ≤ T_J≤ 85°C

-40°C ≤ T_J≤ 85°C

Enabled internal supply current

with CC lines open

I_I

0.7

µA

Enabled supply current with

accessory or dangling active cable

signature on CC lines

I_I

140

185

µA

Enabled supply current with UFP

termination on CC lines and with

either IN1 or IN2 in UVLO

I_I

V_IN1< V_{TH_UVLO_IN1}or V_IN2< V_{TH_UVLO_IN2}

145

190

µA

Enabled supply current with UFP

termination on CC lines

6.6 Switching Characteristics

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF= 100

kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined positive out of the indicated pin

(unless otherwise noted)

PARAMETER

OUT - POWER SWITCH

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_r

t_f

Output voltage rise time

Output voltage fall time

V_IN1= 5 V, C_L= 1 µF, R_L= 100 Ω

(measured from 10% to 90% of final

value)

1.2

1.8

2.5

0.35

0.55

0.75

t_on

t_off

Output voltage turn-on time

Output voltage turn-off time

2.5

3.5

V_IN1= 5 V, C_L= 1 µF, R_L= 100 Ω

4.5

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

Switching Characteristics (continued)

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF= 100

kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined positive out of the indicated pin

(unless otherwise noted)

PARAMETER

OUT - CURRENT LIMIT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Current limit response time to short

circuit

V_IN1- V_OUT= 1 V, R_L= 10 mΩ, see

图 1

t_ios

1.5

µs

FAULT

t_DEGA

Asserting deglitch due to over

current

5.5

8.2

10.7

Asserting deglitch due to over

temperature in current limit⁽¹⁾

t_DEGA

t_DEGD

De-asserting deglitch

8.2

LD_DET

t_DEGA

Asserting deglitch

t_DEGD

De-asserting deglitch

1.45

2.15

2.9

OUT - DISCHARGE

R_DCHGdischarge time

CC1/CC2 - V_CONNPOWER SWITCH

V_OUT= 1 V, time I_{SNK_OUT}> 1 mA

after UFP signature removed from

CC lines

t_r

t_f

Output voltage rise time

Output voltage fall time

V_IN2= 5 V, C_L= 1 µF, R_L= 100 Ω

(measured from 10% to 90% of final

value)

0.15

0.18

0.25

0.22

0.35

0.26

t_on

t_off

Output voltage turn-on time

Output voltage turn-off time

1.5

0.4

V_IN2= 5 V, C_L= 1 µF, R_L= 100 Ω

0.3

0.55

CC1/CC2 - V_CONNPOWER SWITCH - CURRENT LIMIT

Current limit response time to short

circuit

V_IN2– V_CONN= 1 V, R = 10 mΩ, see

图 1

t_res

µs

UFP, POL, AUDIO, DEBUG

t_DEGR

t_DEGF

Asserting deglitch

100

7.9

150

200

De-asserting deglitch

12.5

17.7

(1) These parameters are provided for reference only and do not constitute part of TI’s published specifications for purposes of TI’s product

warranty.

I_OS

I_OUT

t_ios

图 1. Output Short Circuit Parameter Diagram

TPS25810

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ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

6.7 Typical Characteristics

500

450

400

350

300

250

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

图 2. VBUS Current Limiting Switch On Resistance vs

图 3. VCONN Current Limiting Switch On Resistance vs

Temperature

0.25

4000

3500

3000

2500

2000

1500

1000

500

0.2

0.15

0.1

VBUS ILIM 3 A

VBUS ILIM 1.5 A

VCONN_ILIM

0.05

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

Device = Disabled; (VOUT-VIN) =6.5V

图 4. OUT Reverse Leakage Current vs Temperature

图 5. ILIM for VBUS and VCON vs Temperature

2010

350

300

250

200

150

100

LD_DET Threshold Rising

LD_DET Threshold Falling

1990

1970

1950

1930

1910

1890

1870

1850

1830

1810

1790

1770

1750

UFP 3 A

UFP 1.5 A

UFP 0.5 A/0.9 A

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

图 6. LD_DET Threshold vs Temperature

图 7. CC Sourcing Current to UFP vs Temperature

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

Typical Characteristics (接下页)

100

400

350

300

250

200

150

100

IN1 UFP 3 A

IN1 UFP 0.5 A/1.5 A

IN2 UFP 3 A

IN2 UFP 1.5 A

IN2 UFP 0.5 A

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

图 8. IN1 Current with UFP vs Temperature

图 9. IN2 Current with UFP vs Temperature

-40 -25 -10

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

V_AUX= 5 V

图 10. AUX Current with UFP vs Temperature

TPS25810

www.ti.com.cn

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

7 Detailed Description

7.1 Overview

The TPS25810 is a highly integrated USB Type-C Downstream Facing Port (DFP) controller with built-in power

switch developed for the new USB Type-C connector and cable. The part provides all functionality needed to

support a USB Type C DFP in a system where USB power delivery (PD) source capabilities (for example, VBUS

> 5 V) are not implemented. The device is designed to be compliant to Type-C spec revision 1.2.

7.1.1 USB Type C Basic

For a detailed description of the Type-C spec refer to the USB-IF website to download the latest released

version. Some of the basic concepts of the Type-C spec that pertains to understanding the operation of the

TPS25810 (a DFP device) are described as follows.

USB Type-C removes the need for different plug and receptacle types for host and device functionality. The

Type-C receptacle replaces both Type-A and Type-B receptacle since the Type-C cable is plug-able in either

direction between host and device. A host-to-device logical relationship is maintained via the configuration

channel (CC). Optionally hosts and devices can be either providers or consumers of power when USB PD

communication is used to swap roles.

All USB Type-C ports operate in one of below three data modes:

•

Host mode: the port can only be host (provider of power)

Device mode: the port can only be device (consumer of power)

Dual-Role mode: the port can be either host or device

Port types:

•

DFP (Downstream Facing Port): Host

UFP (Upstream Facing Port): Device

DRP (Dual-Role Port): Host or Device

Valid DFP-to-UFP connections:

•

表 1 describes valid DFP-to-UFP connections

Host to Host or Device to Device have no functions

表 1. DFP-to-UFP Connections

DEVICE-MODE

PORT

HOST-MODE PORT

DUAL-ROLE PORT

Host-Mode Port

Device-Mode Port

Dual-Role Port

No Function

Works

No Function

Works

Works⁽¹⁾

Works

(1) This may be automatic or manually driven.

7.1.2 Configuration Channel

The function of the configuration channel is to detect connections and configure the interface across the USB

Type-C cables and connectors.

Functionally the Configuration Channel (CC) is used to serve the following purposes:

•

Detect connect to the USB ports

Resolve cable orientation and twist connections to establish USB data bus routing

Establish DFP and UFP roles between two connected ports

Discover and configure power: USB Type-C current modes or USB Power Delivery

Discovery and configure optional Alternate and Accessory modes

Enhances flexibility and ease of use

Typical flow of DFP to UFP configuration is shown in 图 11:

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

图 11. Flow of DFP to UFP Configuration

7.1.3 Detecting a Connection

DFPs and DRPs fulfill the role of detecting a valid connection over USB Type-C. 图 12 shows a DFP to UFP

connection made with Type C cable. As shown in 图 12, the detection concept is based on being able to detect

terminations in the product which has been attached. A pull-up and pull-down termination model is used. A pull-

up termination can be replaced by a current source.

•

In the DFP-UFP connection the DFP monitors both CC pins for a voltage lower than the unterminated

voltage.

•

An UFP advertises Rd on both its CC pins (CC1 and CC2).

A powered cable advertises Ra on only one of CC pins of the plug. Ra is used to inform the source to apply

VCONN.

•

An analog audio device advertises Ra on both CC pins of the plug, which identifies it as an analog audio

device. VCONN is not applied on either CC pin in this case.

UFP monitors for

connection

DFP monitors for

connection

Cable

Rds

DFP monitors for

connection

UFP monitors for

connection

图 12. DFP-UFP Connection

TPS25810

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ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

7.2 Functional Block Diagram

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7.3 Feature Description

The TPS25810 is a DFP Type C port controller with integrated power switch for VCONN and VBUS. The

TPS25810 does not support BC1.2 charging modes since it does not interact with USB D+/D- data lines. It can

be used in conjunction with a BC 1.2 device like the TPS2514A, to support BC1.2 and Type C charging modes in

a single Type C DFP port. See the TPS25810 EVM user's guide (SLVUAI0) and Application and Implementation

section of this data sheet for more details. The TPS25810 can be used in a USB 2.0 only or USB 3.1 port

implementation. When used in a USB 3.1 port, the TPS25810 can control an external super speed MUX to

handle the Type C flippable feature.

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

Feature Description (接下页)

7.3.1 Configuration Channel Pins CC1 and CC2

The TPS25810 has two pins, CC1 and CC2 that serve to detect an attachment to the port and resolve cable

orientation. These pins are also used to establish current broadcast to a valid UFP, configure VCONN, and

detect Debug or Audio Adapter Accessory attachment.

表 2 lists TPS25810 response to various attachments to its port.

表 2. TPS25810 Response

TPS25810 RESPONSE⁽¹⁾

V_CONN

On CC1 or

CC2

TPS25810 TYPE C PORT

CC1

CC2

OUT

POL

UFP

AUDIO

DEBUG

Nothing Attached

UFP Connected

OPEN

IN1

Hi-Z

LOW

Hi-Z

OPEN

IN1

LOW

Powered Cable/No UFP

Connected

OPEN

IN1

Hi-Z

Powered Cable/No UFP

Connected

Powered Cable/UFP

Connected

CC2

LOW

Powered Cable/UFP

Connected

IN1

CC1

LOW

Hi-Z

LOW

Hi-Z

LOW

Hi-Z

Debug Accessory Connected

OPEN

Audio Adapter Accessory

Connected

LOW

(1) POL, UFP, AUDIO, and DEBUG are open drain outputs; pull high with 100 kΩ to AUX when used. Tie to GND or leave open when not

used.

7.3.2 Current Capability Advertisement and Overload Protection

The TPS25810 supports all three Type-C current advertisements as defined by the USB Type C standard.

Current broadcast to a connected UFP is controlled by the CHG and CHG_HI pins. For each broadcast level the

device protects itself from a UFP that draws current in excess of the port’s USB Type-C Current advertisement

by setting the current limit as shown in 表 3.

表 3. USB Type-C Current Advertisement

CC CAPABILITY

BROADCAST

LOAD DETECT

THRESHOLD (typ)

CHG

CHG_HI

CURRENT LIMIT (typ)

STD

1.5 A

3 A

1.7 A

3.4 A

1.95 A

Under overload conditions, the internal current-limit regulator limits the output current to selected ILIM for OUT

and fixed internal VCONN current limit as shown in the Electrical Characteristics. When an overload condition is

present, the device maintains a constant output current, with the output voltage determined by (i_OSx RLOAD).

Two possible overload conditions can occur. The first overload condition occurs when either: 1) input voltage is

first applied, enable is true, and a short circuit is present (load which draws IOUT > i_OS), or 2) input voltage is

present and the TPS25810 is enabled into a short circuit. The output voltage is held near zero potential with

respect to ground and the TPS25810 ramps the output current to i_OS. The TPS25810 limits the current to i_OSuntil

the overload condition is removed or the device begins to thermal cycle. This is demonstrated in 图 24 where the

device was enabled into a short, and subsequently cycles current off and on as the thermal protection engages.

TPS25810

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ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

The second condition is when an overload occurs while the device is enabled and fully turned on. The device

responds to the overload condition within time i_OS(see 图 1) when the specified overload (per Electrical

Characteristics) is applied. The response speed and shape vary with the overload level, input circuit, and rate of

application. The current-limit response varies between simply settling to i_OSor turnoff and controlled return to i_OS

Similar to the previous case, the TPS25810 limits the current to i_OSuntil the overload condition is removed or the

device begins to thermal cycle.

The TPS25810 thermal cycles if an overload condition is present long enough to activate thermal limiting in any

of the above cases. This is due to the relatively large power dissipation [(VIN – VOUT) x i_OS] driving the junction

temperature up. The device turns off when the junction temperature exceeds 135°C (min) while in current limit.

The device remains off until the junction temperature cools 20°C and then restarts. The TPS25810 current limit

profile is shown in 图 13.

VIN

Slope = -r_DSON

V_OUT

0 A

0 V

I_OUT

I_OS

图 13. Current Limit Profile

7.3.3 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn-

on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage droop during turn on.

7.3.3.1 Device Power Pins (IN1, IN2, AUX, OUT, and GND)

The device has multiple input power pins; IN1, IN2 and AUX. IN1 is connected to OUT by the internal power FET

and serves the supply for the Type-C charging current. IN2 is the supply for VCONN and ties directly between

the VCONN power switch on its input and CC1 or CC2 on its output. AUX or auxiliary input supply provides

power to the chip. Refer to Functional Block Diagram.

In the simplest implementation where multiple supplies are not available; IN1, IN2, and AUX can be tied together.

However in mobile systems (battery powered) where system power savings is paramount, IN1 and IN2 can be

that typically powers the system uC when the system is in hibernate or sleep power state. Unlike IN1 and IN2,

AUX can operate directly from a 3.3-V supply commonly used to power the uC when the system is put in low

power mode. A ceramic bypass capacitor close to the device from IN/AUX to GND is recommended to alleviate

bus transients.

The recommended operating voltage range for IN1/IN2 is 4.5 V to 5.5 V while AUX can be operated from 2.9 V

to 5.5 V. However IN1, the high power supply, can operate up to 6.5 V. This higher input voltage affords a larger

IR drop budget in systems where a long cable harness is used and results in high IR drops with 3-A charging

current. Increasing IN1 beyond 5.5 V enables longer cable/board trace lengths between the device and Type C

receptacle while meeting the USB spec for VBUS at connector ≥ 4.75 V.

图 14 illustrates the point. In this example IN1 is at 5 V which restricts the IR drop budget from DC-DC to

connector to 250 mV.

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

Total IR loss Budget = 250 mV

Trace IR drop Budget at 3 A

= 250-165 = 85 mV

V_Trace1

V_Trace2

V_TPS25810

V_DC-DC = 5 V

5 V DC-DC

V_Connector

= 4.75 V (MIN)

IN1

OUT

MaxRds_On

= 55 mΩ

165 mV drop at 3 A

82.5 mV drop at 1.5 A

图 14. Total IR Loss Budget

7.3.3.2 FAULT Response

The FAULT pin is an open drain output that asserts (active low) when device OUT current exceeds its

programmed value and the over temperature threshold is crossed (T_{TH_OTSD1}). Refer to the Electrical

Characteristics for over current and temperature values. The FAULT signal remains asserted until the fault

condition is removed and the device resumes normal operation. The TPS25810 is designed to eliminate false

overcurrent fault reporting by using an internal deglitch circuit.

Connect FAULT with a pull-up resistor to AUX. FAULT can be left open or tied to GND when not used.

7.3.3.3 Thermal Shutdown

The device has two internal over temperature shutdown thresholds, T_{TH_OTSD1}and T_{TH_OTSD2}, to protect the

internal FET from damage and overall safety of the system. T_{TH_OTSD2}> T_{TH_OTSD1}. FAULT is asserted low to

signal a fault condition when device temperature exceeds T_{TH_OTSD1}and the current limit switch is disabled.

However when T_{TH_OTSD2}is exceeded all open drain outputs are left open and the device is disabled such that

minimum power/heat is dissipated. The device attempts to power-up when die temperature decreases by 20°C.

7.3.3.4 REF

A 100-kΩ (1% or better recommended) resistor is connected from this pin to REF_RTN. This pin sets the

reference current required to bias the internal circuitry of the device. The overload current limit tolerance and CC

currents depend upon the accuracy of this resistor, using a ±1% low tempco resistor, or better, yields the best

current limit accuracy and overall device performance.

7.3.3.5 Audio Accessory Detection

The USB Type-C spec defines an audio adapter decode state which allows implementation of an analog USB

Type-C to 3.5-mm headset adapter. The TPS25810 detects an audio accessory device when both CC1 and CC2

pins sees V_Ravoltage (when pulled to ground by Ra resistor). The device asserts the open drain AUDIO pin low

to indicate the detection of such a device.

TPS25810

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ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

表 4. Audio Accessory Detection

CC1

CC2

AUDIO

STATE

Asserted (pulled low)

Audio Adapter Accessory Connected

Platforms supporting this extension can trigger off of the AUDIO pin to enable accessory mode circuits to support

the audio function. When the Ra pull-down is removed from the CC2 pin, AUDIO is de-asserted or pulled high.

The TPS25810 monitors the CC2 pin for audio device detach. When this function is not needed (for example in a

data-less port) AUDIO can be tied to GND or left open.

7.3.3.6 Debug Accessory Detection

The Type-C spec supports an optional Debug Accessory mode used for debug only and must not be used for

communicating with commercial products. When the TPS25810 detects V_Rdvoltage on both CC1 and CC2 pins

(when pulled to ground by an Rd resistor), it asserts DEBUG low. With DEBUG is asserted, the system can enter

debug mode for factory testing or a similar functional mode. DEBUG de-asserts or pulls high when Rd is

removed from CC1. The TPS25810 monitors the CC1 pin for Debug Accessory detach.

If Debug accessory mode is not used, tie DEBUG to GND or leave it open.

表 5. Debug Accessory Detection

CC1

CC2

POL

STATE

Asserted (pulled low)

Debug Accessory Mode connected

7.3.3.7 Plug Polarity Detection

Reversible Type-C plug orientation is reported by the POL pin when a UFP is connected. However when no UFP

is attached, POL remains de-asserted irrespective of cable plug orientation. 表 6 describes the POL state based

on which device CC pin detects V_RDfrom an attached UFP pull-down.

表 6. Plug Polarity Detection

CC1

CC2

Open

POL

Hi-z

STATE

UFP connected

Open

Asserted (pulled low)

UFP connected with reverse plug orientation

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

图 15 shows an example implementation which utilizes the POL terminal to control the SEL terminal on the

HD3SS3212. The HD3SS3212 provides switching on the differential channels between Port B and Port C to Port

A depending on cable orientation.

3.3 V

HD3SS3212

USB C

SSTXp2

0.1 µF

B0+

Dp1

Dp2

USB Host

SSTXp

V_CC

B0–

C0+

C0–

B1+

B1–

C1+

C1–

SSTXn2

SSTXp1

SSTXn1

SSRXp2

SSRXn2

SSRXp1

SSRXn1

A0+

A0–

Dm1

Dm2

SSTXn

SSRXp

A1+

A1–

SSRXn

GND

OEn

SEL

3.3 V

GND

TPS25810

OUT

5 V

POL

OUT

UFP

CC1

CC2

IN1

5 V

IN2

CHG

AUX

CHG H_I

FAULT

LD_DET

AUDIO

REF

REF_RTN

GND

DEBUG

Thermal Pad

图 15. Example Implementation

7.3.3.8 Device Enable Control

The logic enable pin controls the power switch and device supply current. The supply current is reduced to less

than 1 μA when a logic low is present on EN. The EN pin provides a convenient way to turn on or turn off the

device while it is powered. The enable input threshold has hysteresis built-in. When this pin is pulled high, the

device is turned on or enabled. When the device is disabled (EN pulled low) the internal FETs tied to IN1 and

IN2 are disconnected, all open drain outputs are left open (Hi-Z), and the CC1/CC2 monitor block is turned off.

The EN terminal should not be left floating.

7.3.3.9 Load Detect

The load detect function in the device is enabled when it is set to broadcast high current V_BUScharging (CHG =

CHG_HI = High) on the CC pin. In this mode the device monitors the current to a UFP; if the current exceeds

1.95 A (TYP) the LD_DET pin asserts. Since LD_DET is an open drain output, pull it high with 100 kΩ to AUX

when used; tie it to GND or leave open when not used.

TPS25810

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ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

7.3.3.10 Power Wake

The power wake feature supported in the TPS25810 offers the mobile systems designer a way to save on

system power when no UFP is attached to the Type-C port. Refer to 图 16. To enable power wake the UFP from

device #1 and #2 are tied together (each with its own 100-kΩ pull-up) to the enable pin of a 5 V/6 A dc-dc buck

converter. When no UFP is detected on both Type-C ports, the EN pin of the dc-dc is pulled high thereby

disabling it. Since both TPS25810s are powered by an always-on 3.3-V LDO, turning off the IN1/IN2 supply does

not affect its operation in detach state. Anytime a UFP is detected on either port, the corresponding TPS25810

UFP pin is pulled low enabling the dc-dc to provide charging current to the attached UFP. Turning off the high

power dc-dc when ports are unattached saves on system power. This method can save a significant amount of

power considering the TPS25810 only requires < 5 µA when no UFP device is connected.

Both /UFP High

Converter

Disabled

OUT

CC1

CC2

IN1

No UFP

Attached

TPS54620

Buck

Converter

IN2

AUX

CHG

TPS25810

/UFP_1

CHG_HI

12V

/UFP_1 /UFP_2

(High)

OUT

CC1

CC2

IN1

No UFP

Attached

IN2

AUX

CHG

LP2950-33

TPS25810

LDO

/UFP_2

CHG_HI

One /UFP Low

Converter

Enabled

OUT

CC1

CC2

IN1

TPS54620

Buck

Converter

UFP

Attached

IN2

AUX

CHG

TPS25810

/UFP_1

CHG_HI

12V

/UFP_1

(Low)

/UFP_2

(High)

OUT

CC1

CC2

IN1

No UFP

Attached

IN2

AUX

CHG

LP2950-33

LDO

TPS25810

/UFP_2

CHG_HI

图 16. Power Wake Implementation

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

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7.3.3.11 Port Power Management (PPM)

PPM is the intelligent and dynamic allocation of power made possible with the use of the LD_DET pin. It is for

systems that have multiple charging ports but cannot power them all at their maximum charging current

simultaneously.

Goals of PPM are:

1. Enhances user experience since user does not have to search for high current charging port.

2. Lowered cost and size of power supply needed for implementing high current charging in a multi-port system.

7.3.3.12 Implementing PPM in a System with Two Type-C Ports

图 17 shows PPM and power wake implemented in a system with two Type C ports both initially set to broadcast

high current charging (3 A, CHG and CHG_HI pulled high via a 100 kΩ to AUX). To enable PPM tie the LD_DET

pin from TPS25810 #1 to CHG_HI of TPS25810 #2 and vice versa as shown in 图 17. Each device

independently monitors charging current drawn by its attached UFP.

IN1, IN2 are connected to a TPS54620; a 6-A synchronous step-down converter. AUX is powered by a LP2950-

33; a low quiescent current 3.3-V LDO. With no UFP attached to either Type C port the TPS25810 is powered by

the LP2950-33. This method saves a significant amount of power considering the TPS25810 requires less than 2

µA when no USB device is connected.

OUT

CC1

CC2

IN1

IN2

TPS54620

Buck

Converter

TPS25810

AUX

CHG

/LD_DET_1

/UFP_1

CHG_HI

12V

/UFP_1 /UFP_2

OUT

CC1

CC2

IN1

IN2

3.0A Broadcast

LP2950-33

LDO

TPS25810

AUX

CHG

/LD_DET_2

/UFP_2

CHG_HI

图 17. PPM and Power Wake Implemented

7.3.3.13 PPM Operation

When no UFP is attached, or either of the two attached UFP is drawing current less than the LD_DET threshold

(1.95 A typical), the LD_DET output for both devices is high (shown in blue in 图 18). Now when a UFP is

attached to device #1 that draws a charging current higher than the LD_DET threshold (1.95 A), this causes

LD_DET to assert or pull-low (shown in red in 图 18). Since the LD-DET pins of the #1 and #2 devices are

connected to the other devices CHG_HI pin, a high current detection on device #1 forces device #2 to broadcast

1.5 A or medium charging current capability on its CC pin. The Type C specification requires a UFP to monitor

the CC pins continuously and adjust its current consumption (within 60 ms) to remain within the value advertised

by the DFP.

图 19 shows the case when a UFP attached to Device 1 reduces its charging current below the LD_DET

threshold, which causes LD-DET to de-assert, thereby toggling device #2 CH_HI pin from low to high.

This scheme:

•

Delivers a better user experience as the user does not have to worry about the maximum charging current

rating of the host ports, both ports initially advertise high current charging.

TPS25810

www.ti.com.cn

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

•

Enables a smaller and lower cost power supply as the loading is controlled and never allowed to exceed 5 A.

OUT

CC1

CC2

IN1

IN2

TPS54620

Buck

Converter

3.0A USB Device Connected

TPS25810

AUX

CHG

/LD_DET_1

/UFP_1

CHG_HI

12V

/UFP_1 /UFP_2

OUT

CC1

CC2

IN1

IN2

1.5A Broadcast

LP2950-33

LDO

TPS25810

AUX

CHG

/LD_DET_2

/UFP_2

CHG_HI

图 18. 3-A USB Device Connected

OUT

CC1

CC2

IN1

IN2

TPS54620

Buck

Converter

1.5A USB Device Connected

TPS25810

AUX

CHG

/LD_DET_1

/UFP_1

CHG_HI

12V

/UFP_1 /UFP_2

OUT

CC1

CC2

IN1

IN2

3.0A Broadcast

LP2950-33

LDO

TPS25810

AUX

CHG

/LD_DET_2

/UFP_2

CHG_HI

图 19. 1.5-A USB Device Connected

7.4 Device Functional Modes

The TPS25810 is a Type-C controller with integrated power switch that supports all Type-C functions in a

downstream facing port. It is also used to manage current advertisement and protection to a connected UFP and

active cable. The device starts its operation by monitoring the AUX bus. When VAUX exceeds the under voltage-

lockout threshold, the device samples the EN pin. A high level on this pin enables the device and normal

operation begins. Having successfully completed its start-up sequence, the device now actively monitors its CC1

and CC2 pins for attachment to a UFP. When a UFP is detected on either the CC1 or CC2 pin the internal

MOSFET starts to turn-on after the required de-bounce time is met. The internal MOSFET starts conducting and

allows current to flow from IN1 to OUT. If Ra is detected on the other CC pin (not connected to UFP), VCONN is

applied to allow current to flow from IN2 to the CC pin connected to Ra. For a complete listing of various device

operational modes refer to 表 2.

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS25810 is a Type-C DFP controller that supports all Type-C DFP required functions. The TPS25810 only

applies power to V_BUSwhen it detects that a UFP is attached and removes power when it detects the UFP is

detached. The device exposes its identity via its CC pin advertising its current capability based on CHG and

CHG_HI pin settings. The TPS25810 also limits its advertised current internally and provides robust protection to

a fault on the system V_BUSpower rail.

After a connection is established by the TPS25810, the device is capable of providing V_CONNto power circuits in

the cable plug on the CC pin that is not connected to the CC wire in the cable. V_CONNis internally current limited

and has its own supply pin IN2. Apart from providing charging current to a UFP, the TPS25810 also supports

Audio and Debug accessory modes.

The following design procedure can be used to implement a full featured Type-C DFP.

注

BC 1.2 is not supported in the TPS25810. To support BC1.2 with Type-C charging modes

in a single C connector, a device like a TPS2514A will need to be used.

8.2 Typical Applications

8.2.1 Type C DFP Port Implementation without BC 1.2 Support

图 20 shows a minimal Type-C DFP implementation capable of supporting 5-V and 3-A charging.

USB Type C

Receptacle

TPS25810RVC

IN1

VBUS

OUT

CC2

CC1

IN1

IN2

AUX

FAULT

LD_DET

10uF

CHG

CHG_HI

UFP

POL

AUDIO

REF

DEBUG

100 kΩ

(1%)

GND

REF_RTN

PAD

图 20. Type-C DFP Port Implementation without BC 1.2 Support

TPS25810

www.ti.com.cn

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

Typical Applications (接下页)

8.2.1.1 Design Requirements

8.2.1.1.1 Input and Output Capacitance

Input and output capacitance improves the performance of the device. The actual capacitance should be

optimized for the particular application. For all applications, a 0.1-μF or greater ceramic bypass capacitor

between IN and GND is recommended as close to the device as possible for local noise de-coupling.

All protection circuits such as the TPS25810 have the potential for input voltage overshoots and output voltage

undershoots. Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt

application of input voltage in conjunction with input power bus inductance and input capacitance when the IN

terminal is high impedance (before turn on). Theoretically, the peak voltage is 2 times the applied. The second

cause is due to the abrupt reduction of output short circuit current when the TPS25810 turns off and energy

stored in the input inductance drives the input voltage high. Input voltage droops may also occur with large load

steps and as the TPS25810 output is shorted. Applications with large input inductance (for instance connecting

the evaluation board to the bench power-supply through long cables) may require large input capacitance to

reduce the voltage overshoot from exceeding the absolute maximum voltage of the device.

The fast current-limit speed of the TPS25810 to hard output short circuits isolate the input bus form faults.

However, ceramic input capacitance in the range of 1 μF to 22 μF adjacent to the TPS25810 input aids in both

response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are

permitted. Output voltage undershoot is caused by the inductance of the output power bus just after a short has

occurred and the TPS25810 has abruptly reduced OUT current. Energy stored in the inductance drives the OUT

voltage down and potentially negative as it discharges. An application with large output inductance (such as from

a cable) benefits from use of a high-value output capacitor to control voltage undershoot.

When implementing a USB standard application, 120 μF minimum output capacitance is required. Typically a

150-μF electrolytic capacitor is used, which is sufficient to control voltage undershoots. Since in Type-C DFP is a

cold socket when no UFP is attached, the output capacitance should be placed at the IN pin versus OUT as is

used in USB Type A ports. It is also recommended to put a 10-μF ceramic capacitor on the OUT pin for better

voltage bypass.

8.2.1.2 Detailed Design Procedure

The TPS25810 device supports three different input voltages based on the application. In the simplest

implementation all input supplies are tied to a single voltage source as shown in 图 20 which is set to 5 V.

However, it is recommended to set a slightly higher (100 mV to 200 mV) input voltage, when possible, to

compensate for IR drop from the source to the Type C connector.

Other design considerations are listed below:

•

Place at least 120 µF of bypass capacitance close to the IN pins versus OUT as Type C is a cold socket

connector.

A 10-µF bypass capacitor is recommended placed near a Type-C receptacle V_BUSpin to handle load

transients.

Depending on the max current level advertisement supported by the Type-C port in the system, set CHG and

CHG_HI levels accordingly. 3 A advertisement is shown in 图 20.

EN, CHG, and CHG_HI pins can be tied directly to GND or VAUX without a pull-up resistor.

–

CHG and CHG_HI can also be dynamically controlled by a µC to change the current advertisement level

to the UFP.

•

When an open drain output of the TPS25810 is not used, it can be left as NC or tied to GND.

Use a 1% 100-kΩ resistor to connect between the REF and REF_RTN pins placing it close to the device pin

and isolated from switching noise on the board.

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

Typical Applications (接下页)

8.2.1.3 Application Curves

VIN

CC1

VIN

VBUS

CC2

CC1

Time 20 ms/div

Basic Start-Up: IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V,

CC1 = Rd, CC2 = Open

Time 50 ms/div

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V, CC1 = Open,

CC2 = Open then Rd

图 21. Basic Start-Up

图 22. Start-Up

VBUS VIN

VIN

VBUS

CC1

Time 50 ms/div

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V, CC1 = Rd, CC2

= Open, OUT = Shorted

Time 200 ms/div

IN1 = IN2 = AUX = EN = 5 V; CHG = CHG_HI = 0 V, CC1 =

Open, CC2 = Rd, OUT = Open→5 Ω

图 24. Hot-Plug to Short

图 23. Load Step

VIN

VBUS

VOUT

CC1

CC2

Time 20 ms/div

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V, CC1 = Short,

CC2 = Rd

Time 20 ms/div

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V, CC1 = Open,

CC2 = Rd→Open

图 25. Short On CC1

图 26. Remove Rd

TPS25810

www.ti.com.cn

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

Typical Applications (接下页)

VIN

VBUS

CC2

CC1

Time 50 ms/div

V_IN5 V→3.5 V (100 ms)→5 V (1 V/ms),

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V,

CC1 = Rd,

CC2 = Ra

图 27. Brown-Out Test

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

Typical Applications (接下页)

8.2.2 Type-C DFP Port Implementation with BC 1.2 (DCP Mode) Support

图 28 shows a Type-C DFP implementation capable of supporting 5 V and 3 A charging in a Type-C port that is

also able to support charging of legacy devices when used with a Type C – µB cable assembly for charging

phones and handheld devices equipped with µB connector.

This implementation requires the use of a TPS2514A, a USB dedicated charging port (DCP) controller with auto-

detect feature to charge not only BC1.2 compliant handheld devices but also popular phones and tablets that

incorporate their own propriety charging algorithm. Refer to TPS2514A specifications available at www.ti.com for

more details.

TPS2514ADBV

IN DM1

0.1uF

DP1

GND

TPS25810RVC

IN1

VBUS

OUT

CC2

CC1

IN1

IN2

AUX

FAULT

LD_DET

10uF

CHG

CHG_HI

UFP

POL

USB Type C

Receptacle

AUDIO

REF

DEBUG

100 kΩ

(1%)

GND

REF_RTN

PAD

图 28. Type C DFP Port Implementation with BC 1.2 (DCP Mode) Support

8.2.2.1 Design Requirements

Refer to Design Requirements for the Design Requirements.

8.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure for the Detailed Design Procedure.

8.2.2.3 Application Curves

Refer to Application Curves for the Application Curves.

TPS25810

www.ti.com.cn

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

9 Power Supply Recommendations

The device has three power supply inputs; IN1, which is directly connected to OUT via the power MOSFET, is

tied to the VBUS pin in the Type-C receptacle. IN2 also has a current limiting switch and is MUXed either to the

CC1 or CC2 pin in the Type-C receptacle depending on cable plug polarity. AUX is the chip supply. In most

applications all three supplies are tied together. In a special implementation like power wake IN1/IN2 are tied to a

single supply while AUX is powered by a supply that is always ON and can be as low as 2.9 V.

USB Specification Revisions 2.0 and 3.1 require VBUS voltage at the connector to be between 4.75 V to 5.5 V.

Depending on layout and routing from supply to the connector the voltage droop on VBUS has to be tightly

controlled. Locate the input supply close to the device. For all applications, a 10-μF or greater ceramic bypass

capacitor between OUT and GND is recommended as close to the Type-C connector of the device as possible

for local noise decoupling. The power supply should be rated higher than the current limit set to avoid voltage

droops during over current and short-circuit conditions.

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

Layout best practices as it applies to the TPS25810 are listed below.

•

For all applications a 10-µF ceramic capacitor is recommended near the Type-C receptacle and another 120-

µF ceramic capacitor close to IN1 pin.

–

The optimum placement of the 120-µF capacitor is closest to the IN1 and GND pins of the device.

Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN1 pin,

and the GND pin of the IC. See 图 29 for a PCB layout example.

•

High current carrying power path connections to the device should be as short as possible and should be

sized to carry at least twice the full-load current.

–

Have the input and output traces as short as possible. The most common cause of voltage drop failure in

USB power delivery is the resistance associated with the VBUS trace. Trace length, maximum current

being supplied for normal operation, and total resistance associated with the VBUS trace must be taken

into account while budgeting for voltage drop.

For example, a power carrying trace that supplies 3 A, at a distance of 20 inches, 0.100-in. wide, with 2-

oz. copper on the outer layer will have a total resistance of approximately 0.046 Ω and voltage drop of

0.14 V. The same trace at 0.050-in.-wide will have a total resistance of approximately 0.09 Ω and voltage

drop of 0.28 V.

Make power traces as wide as possible.

•

The resistor attached to the REF pin of the device has several requirements:

–

It is recommended to use a 1% 100-kΩ low tempco resistor.

It should be connected to pins REF and REF_RTN (pin 9 and pin 10 respectively).

The REF_RTN pin should be isolated from the GND plane. See 图 29.

The trace routing between the REF and REF_RTN pins of the device should be as short as possible to

reduce parasitic effects on current limit and current advertisement accuracy. These traces should not have

any coupling to switching signals on the board.

Locate all TPS25810 pull-up resistors for open-drain outputs close to their connection pin. Pull up resistors

should be 100 kΩ.

–

When a particular open drain output is not used/needed in the system leave the associated pin open or

tied to GND.

•

Keep the CC lines close to the same length.

Thermal Considerations:

–

When properly mounted, the thermal pad package provides significantly greater cooling ability than an

ordinary package. To operate at rated power, the thermal pad must be soldered to the board GND plane

directly under the device. The thermal pad is at GND potential and can be connected using multiple vias

to inner layer GND. Other planes, such as the bottom side of the circuit board can be used to increase

heat sinking in higher current applications. Refer to Technical Briefs: PowerPad™ Thermally Enhanced

Package (TI literature Number SLMA002) and PowerPAD™ Made Easy (TI Literature Number SLMA004)

or more information on using this thermal pad package.

–

The thermal via land pattern specific to the TPS25810 can be downloaded from the device web page at

www.ti.com.

Obtaining acceptable performance with alternate layout schemes is possible; however the layout example

in the following section has been shown to produce good results and is intended as a guideline.

•

ESD Considerations

–

TPS25810 has built in ESD protection for CC1 and CC2. Keep trace length to a minimum from the type-C

receptacle to the TPS25810 on CC1 and CC2.

–

10-uF output cap should be placed near Type-C receptacle

Refer to the TPS25810EVM-745 Evaluation Module for an example of a double layer board that passes

IEC61000-4-2 testing

–

Do not create stubs or test points on the CC lines. Keep the traces short if possible and use minimal via

along the traces (1-2 inches or less).

Refer to ESD Protection Layout Guide for additional information (TI Literature Number SLVA680)

TPS25810

www.ti.com.cn

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

Layout Guidelines (接下页)

–

Have a dedicated ground plane layer if possible to avoid differential voltage buildup

10.2 Layout Example

Top Layer Signal Trace

Top Layer Signal Ground Plane

Bottom Layer Signal Trace

Bottom Layer Signal Ground Plane

Via to Bottom Layer Signal Ground Plane

Via to Bottom Layer Signal

AUX

Thermal

Pad

IN1

OUT

IN2

CC2

GND

CC1

AUX

Signal Ground

Bottom Layer

Signal Ground

Top Layer

图 29. Layout Example

TPS25810

ZHCSE73C –SEPTEMBER 2015–REVISED JULY 2017

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 文档支持

11.2.1 相关文档

《PowerPad™ 耐热增强型封装》（TI 文献编号：SLMA002）

《PowerPAD™ 速成》（TI 文献编号：SLMA004）

《TPS25810EVM-745 用户指南》（文献编号：SLVUA0）

《TPS25810 高压 DFP 保护》（文献编号：SLVA751）

11.3 接收文档更新通知

要接收文档更新通知，请导航至德州仪器 TI.com.cn 上的器件产品文件夹。请单击右上角的通知我进行注册，即可

收到任意产品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不

会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS25810RVCR

TPS25810RVCT

ACTIVE

WQFN

RVC

3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

250 RoHS & Green NIPDAU Level-2-260C-1 YEAR

-40 to 125

25810

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS25810RVCR

TPS25810RVCT

WQFN

RVC

3000

250

330.0

180.0

12.4

3.3

4.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS25810RVCR

TPS25810RVCT

WQFN

RVC

3000

250

346.0

367.0

210.0

346.0

367.0

185.0

33.0

38.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RVC0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

0.45

0.35

4.1

3.9

0.25

0.15

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

2X 1.5

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

16X 0.5

SYMM

2.5

2.6 0.1

SEE TERMINAL

DETAIL

0.25

20X

0.15

PIN 1 ID

(OPTIONAL)

0.1

C A B

1.6 0.1

0.05

0.45

0.35

20X

4219150/B 03/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RVC0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.6)

SYMM

(R0.05)

TYP

20X (0.6)

20X (0.2)

(1)

TYP

(3.8)

(2.6)

SYMM

16X (0.5)

(

0.2) TYP

VIA

(1 TYP)

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219150/B 03/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RVC0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

2X (1.47)

20X (0.6)

20X (0.2)

(R0.05) TYP

SYMM

(1.15)

(3.8)

(0.675)

TYP

16X (0.5)

METAL

TYP

SYMM

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD X

81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219150/B 03/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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