TPS25814RSMR_技术文档

TPS25814

ZHCSMU5A –JULY 2020 –REVISED DECEMBER 2020

TPS25814 具有集成拉电流电源开关的USB Type-C^®控制器

• 15W USB-C 充电器

• 集线站和集线器

1 特性

• 符合USB Type-C 规范

3 说明

– 线缆连接和方向检测

– 集成式VCONN 开关

– 26V 耐压CC 引脚

TPS25814 是一款独立的 USB Type-C 控制器，可为

一个 USB Type-C 连接器提供电缆插拔和方向检测功

能。在连接电缆时，TPS25814 根据 USB Type-C 规

范执行电缆检测。在线缆检测完成后，TPS25814 会启

用内部电源路径。状态指示器引脚可用于控制外部多路

复用器。

– 可配置电流广播

• 集成式VBUS 供电端口电源开关

– 5V、3A、36mΩ电源开关

– UL 认证组件(E169910)

– 欠压和过压保护

器件信息

器件型号⁽¹⁾

TPS25814

封装尺寸（标称值）

– 高达3A 的可配置电流限制

• USB type-C 连接器系统软件接口(USCI) 支持

• 支持工业温度范围

封装

QFN (RSM)

4.0mm x 4.0mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 面向多端口系统的可选简易电源管理

2 应用

• 笔记本电脑和台式机

3.3V

VIN_3V3

TPS25814

PP5V

V_BUS

5 V

3 A

EC Host

Interface

(slave)

Type-C Rp & state

machine,

VCONN switches

CC

V_CONN

CC1/2

2

EC

(master)

USB

Type-C

Connector

DEBUG

FAULT

POL

USB_P

USB_N

D+

D-

Status

Indicators

SINK

GND

CHG_HI

EN

CTL

2 ADCIN pins

(I2C addr)

Control

Inputs

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSEZ5

TPS25814

www.ti.com.cn

ZHCSMU5A –JULY 2020 –REVISED DECEMBER 2020

Table of Contents

8.2 Functional Block Diagram.........................................15

8.3 Feature Description...................................................16

8.4 Device Functional Modes..........................................25

9 Application and Implementation..................................28

9.1 Application Information............................................. 28

9.2 Typical Application.................................................... 28

10 Power Supply Recommendations..............................31

10.1 3.3-V Power............................................................ 31

10.2 1.5-V Power............................................................ 31

10.3 Recommended Supply Load Capacitance..............31

11 Layout...........................................................................32

11.1 Layout Guidelines................................................... 32

11.2 Layout Example...................................................... 32

11.3 Component Placement............................................32

11.4 Routing and View Placement.................................. 33

12 Device and Documentation Support..........................38

12.1 Device Support....................................................... 38

12.2 Documentation Support.......................................... 38

12.3 支持资源..................................................................38

12.4 Trademarks.............................................................38

12.5 静电放电警告.......................................................... 38

12.6 术语表..................................................................... 38

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings ....................................... 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions ........................5

6.4 Recommended Capacitance ......................................6

6.5 Thermal Information ...................................................6

6.6 Power Supply Characteristics ....................................6

6.7 Power Consumption ...................................................7

6.8 PP_5V Power Switch Characteristics ........................ 7

6.9 Power Path Supervisory ............................................ 8

6.10 CC Cable Detection Parameters ..............................8

6.11 CC VCONN Parameters .......................................... 9

6.12 Thermal Shutdown Characteristics ..........................9

6.13 Input/Output (I/O) Characteristics .......................... 10

6.14 BC1.2 Characteristics ............................................ 10

6.15 I2C Requirements and Characteristics .................. 10

6.16 Typical Characteristics ...........................................12

7 Parameter Measurement Information..........................13

8 Detailed Description......................................................14

8.1 Overview...................................................................14

Information.................................................................... 38

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (July 2020) to Revision A (December 2020)

Page

• 首次公开发布...................................................................................................................................................... 1

2

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ZHCSMU5A –JULY 2020 –REVISED DECEMBER 2020

5 Pin Configuration and Functions

LDO_3V3

ADCIN1

ADCIN2

LDO_1V5

EN

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

CC1

USB_N

USB_P

NC

Thermal

Pad

(GND)

GND

DEBUG

GND

FAULT

SINK

I2C_EC_SDA

CHG_HI

Not to Scale

图5-1. RSM Package 32-pin QFN Top View

表5-1. Pin Functions

TYPE⁽¹⁾RESET Description

NAME

ADCIN1

ADCIN2

CC1

NO.

2

I

Hi-Z

Configuration input. Connect to a resistor divider to LDO_3V3.

I/O for USB Type-C .

3

24

25

I/O

I

CC2

I/O for USB Type-C .

CHG_HI

Charge logic input to select between minimum or maximum Type-C current

advertisement.

17

30

6

CTL

I

O

I

Hi-Z

Low

This pin controls which BC 1.2 mode is used. Pull to GND for CDP mode. Pull

high for DCP mode.

DEBUG

EN

Open-drain logic output that is asserted low when a Type-C debug accessory

is detected.

When this pin is pulled low or left floating, the device will be disabled and

remain in the Type-C Error Recovery state.

5

7

FAULT

GND

O

Hi-Z

Open-drain logic output that asserts when an over-current fault is detected.

Ground. Connect to ground plane.

11,12,14,15,16,

19,20

—

I2C slave serial clock input. Tie to pullup voltage through a resistor when

used or unused. Connect to Embedded Controller (EC).

I2C_EC_SCL

I2C_EC_SDA

9

8

I

Hi-Z

I2C slave serial data. Open-drain output. Tie to pullup voltage through a

resistor when used or unused. Connect to Embedded Controller (EC).

I/O

I2C slave interrupt. Active low. Connect to external voltage through a pull-up

resistor. May also be used as a general purpose digital output. Connect to

Embedded Controller (EC).

I2C_EC_IRQ

LDO_1V5

10

4

O

Hi-Z

Output of the CORE LDO. Bypass with capacitance C_{LDO_1V5}to GND. This

pin cannot source current to external circuits.

—

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表5-1. Pin Functions (continued)

TYPE⁽¹⁾RESET Description

NAME

LDO_3V3

POL

NO.

Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with

capacitance C_{LDO_3V3}to GND.

1

O

—

Hi-Z

Open-drain logic output that gives the information needed to mux the

13

superspeed lines. It is asserted low when CC2 is connected to the cable CC

line.

PP5V

SINK

28,29

18

I

5-V System Supply to VBUS, supply for CCy pins as VCONN.

—

O

Hi-Z

Open-drain logic output that asserts low when a Type-C Sink is identified on

the CC lines.

USB_N

USB_P

VBUS

VIN_3V3

NC

23

22

I/O

I

Hi-Z

I/O for BC 1.2 functionality. Connect to the USB D- line.

I/O for BC 1.2 functionality. Connect to the USB D+ line.

5-V to 20-V input. Bypass with capacitance C_VBUSto GND.

Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.

This pin has no functionality. Leave floating.

26,27

32

—

21,31

—

(1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–0.5

MAX

6

UNIT

PP5V

VIN_3V3

4

V

ADCIN1, ADCIN2

4

VBUS⁽⁴⁾

28

26

Input voltage range ⁽²⁾

CC1, CC2 ⁽⁴⁾

V

SINK, FAULT, CHG_HI, USB_P, USB_N, CTL,

POL, DEBUG, EN

-0.3

6.0

I2C_EC_SDA, I2C_EC_SCL, I2C_EC_IRQ

4

–0.3

LDO_1V5⁽³⁾

Output voltage range ⁽²⁾

2

LDO_3V3⁽³⁾

4

internally limited

1

Source or sink current VBUS

Positive source current on CC1, CC2

Positive sink current on CC1, CC2 while VCONN

1

Source current

switch is enabled

A

positive sink current for I2C_EC_SDA,

I2C_EC_SCL

internally limited

positive source current for LDO_3V3, LDO_1V5

internally limited

T_JOperating junction temperature

T_STGStorage temperature

175

150

°C

–40

–55

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.

(3) Do not apply voltage to these pins.

(4) A TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such as TVS2200.

6.2 ESD Ratings

PARAMETER

TEST CONDITIONS

VALUE

UNIT

Human body model (HBM), per ANSI/

ESDA/JEDEC JS-001, all pins⁽¹⁾

±1000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per

JEDEC specificationJESD22-C101, all

pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

3.0

4.9

4

MAX

UNIT

VIN_3V3

PP5V

3.6

5.5

22

V_I

Input voltage range ⁽¹⁾

V

VBUS

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6.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

I2C_EC_SDA, I2C_EC_SCL,

I2C_EC_IRQ, ADCIN1, ADCIN2

0

3.6

V_IO

I/O voltage range ⁽¹⁾

SINK, FAULT, CHG_HI, USB_P,

USB_N, CTL, POL, DEBUG, EN

V

0

5.5

CC1, CC2

VBUS

5.5

3

A

I_O

Output current (from PP5V)

CC1, CC2

315

5

mA

Output current (from VBUS LDO) current from LDO_3V3

I

_{PP_5V}≤1.5 A, I_{PP_CABLE}≤315

105

–40

mA

T_A

T_J

Ambient operating temperature

Operating junction temperature

°C

85

I

_{PP_5V}≤3 A, I_{PP_CABLE}≤315 mA

–40

125

(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.

6.4 Recommended Capacitance

over operating free-air temperature range (unless otherwise noted)

PARAMETER⁽¹⁾

VOLTAGE RATING

MIN

5

NOM

10

MAX

UNIT

µF

C_{VIN_3V3}

C_{LDO_3V3}

C_{LDO_1V5}

C_VBUS

Capacitance on VIN_3V3

6.3 V

4 V

Capacitance on LDO_3V3

Capacitance on LDO_1V5

Capacitance on VBUS

Capacitance on PP5V

5

10

25

12

10

µF

4.5

1

µF

25 V

10 V

4.7

µF

C_PP5V

120

µF

(1) Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by

50% at the required operating voltage, then the required external capacitor value would be 10 µF.

6.5 Thermal Information

TPS25814

THERMAL METRIC⁽¹⁾

QFN (RSM)

32 PINS

30.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

Junction-to-case (top) thermal resistance

24.5

Junction-to-board (bottom) thermal

resistance

R_θJC

2

°C/W

R_θJB

Junction-to-board thermal resistance

9.8

0.2

°C/W

Junction-to-top characterization parameter

ψ_JT

Junction-to-board characterization

parameter

9.7

°C/W

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.6 Power Supply Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIN_3V3, VBUS

rising

falling

3.6

3.5

3.9

3.8

V_{VBUS_UVLO}

VBUS UVLO threshold.

V

hysteresis

0.1

6

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6.6 Power Supply Characteristics (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6 V

PARAMETER

TEST CONDITIONS

MIN

2.56

2.44

TYP

2.66

2.54

0.12

MAX

2.76

2.64

UNIT

rising, V_VBUS=0

voltage required on VIN_3V3 for

power on

V_{VIN3V3_UVLO}

falling, V_VBUS=0

hysteresis

V

LDO_3V3, LDO_1V5

V_{LDO_3V3}

V_{VIN_3V3}= 0V, 10 µA ≤I_LOAD

18 mA, V_VBUS≥3.9V

≤

voltage on LDO_3V3

3.0

3.4

1.5

3.6

1.4

V

R_{LDO_3V3}

Rdson of VIN_3V3 to LDO_3V3 I_{LDO_3V3}=50mA

up to maximum internal loading

condition.

Ω

V_{LDO_1V5}

voltage on LDO_1V5

1.49

1.65

V

6.7 Power Consumption

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6 V, no GPIO loading

PARAMETER

TEST CONDITIONS

MIN

TYP

3

MAX UNIT

I_{VIN_3V3,ActSrc}

I_{VIN_3V3,IdlSrc}

current into VIN_3V3

Active Source mode: V_VBUS=5.0V, V_{VIN_3V3}=3.3V

Idle Source mode: V_VBUS=5.0V, V_{VIN_3V3}=3.3V

mA

current into VIN_3V3

1.0

Power drawn into PP5V

and VIN_3V3 in Modern

Standby Source Mode

CCm floating, CCn tied to GND through 5.1kΩ, V_PP5V= 5V,

P_MstbySrc

4.5

mW

V_{VIN_3V3}=3.3V, I_VBUS=0, T_J=25^oC

I_{VIN_3V3,SleepSrc}

I_PP5V,Sleep

current into VIN_3V3

current into PP5V

Sleep source mode: V_VBUS=0V, V_{VIN_3V3}=3.3V

Sleep mode: V_VBUS=0V, V_{VIN_3V3}=3.3V

61

2

µA

Active Source mode: V_VBUS=5.0V, V_VBUS=5.0V,

V_{VIN_3V3}=3.3V. No external load on VBUS.

I_PP5V,ActSrc

current into PP5V

0.5

mA

6.8 PP_5V Power Switch Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6V

PARAMETER

TEST CONDITIONS

I_LOAD= 3 A, T_J=25^oC

I_LOAD= 3 A, T_J=125^oC

MIN

TYP

MAX

UNIT

mΩ

R_{PP_5V}

Resistance from PP5V to VBUS

36

38

53

V_PP5V= 0V, V_VBUS= 5.5V,

PP_5V disabled, T_J≤85^oC,

measure I_PP5V

I_{PP5V_REV}

VBUS to PP5V leakage current

PP5V to VBUS leakage current

5

µA

V_PP5V= 5.5V, V_VBUS= 0V,

PP_5V disabled, T_J≤85^oC,

measure I_VBUS

I_{PP5V_FWD}

15

I_LIM5V

Current limit setting

1.5A setting

3.0A setting

2.3

2.70

3.78

A

3.22

PP5V to VBUS current sense

accuracy

I_VBUS

3.05

3.5

3.75

A/V

mV

µs

3.64A ≥I_VBUS≥1A

RCP clears and PP_5V starts turning

on when V_VBUS–V_PP5V<

V_{PP_5V_RCP}. Measure V_VBUS–V_PP5V

V_{PP_5V_RCP}

10

20

VBUS to GND through

10mΩ, C_VBUS=0

t_{iOS_PP_5V}

response time to VBUS short circuit

1.15

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UNIT

ZHCSMU5A –JULY 2020 –REVISED DECEMBER 2020

6.8 PP_5V Power Switch Characteristics (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

Enable PP_5V, I_RpDefbeing

drawn from PP5V,

configure V_OVP4RCPto

setting 2, ramp V_VBUSfrom

t_{PP_5V_ovp}

response time to V_VBUS> V_OVP4RCP4V to 20V at 100 V/ms,

4.5

µs

C_PP5V= 2.5 µF, measure

time from OVP detection

until reverse current < 100

mA

response time to V_PP5V

V_{PP5V_UVLO}, PP_VBUS is deemed off

when V_VBUS< 0.8V

<

R_L= 100 Ω, no external

capacitance on VBUS

t_{PP_5V_uvlo}

4

V_PP5V=5.5V, I_RpDefbeing

drawn from PP5V, enable

PP_5V, configure V_OVP4RCP

to setting 2, ramp V_VBUS

from 4V to 21.5V at 10

response time to V_PP5V

V_VBUS+V_{PP_5V_RCP}

<

t_{PP_5V_rcp}

0.7

µs

V/µs, measure V_PP5V

C_PP5V= 104 µF,

.

C_VBUS=10µF, measure time

from RCP detection until

reverse current < 100 mA.

t_ILIM

t_ON

Current limit deglitch time

5.1

3.3

ms

from enable signal to VBUS at 90%

of final value

R_L= 100Ω, V_PP5V= 5V,

C_L=0

2.3

0.30

1.2

4.3

0.6

from disable signal to VBUS at 10%

of final value

R_L= 100Ω, V_PP5V= 5V,

C_L=0

t_OFF

t_RISE

t_FALL

0.45

1.7

ms

VBUS from 10% to 90% of final value

R_L= 100Ω, V_PP5V= 5V,

C_L=0

2.2

VBUS from 90% to 10% of initial

value

R_L= 100Ω, V_PP5V= 5V,

C_L=0

0.06

0.1

0.14

6.9 Power Path Supervisory

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

OVP detected when V_VBUS

V_OVP4RCP(rising)

>

V_OVP4RCP

VBUS over voltage protection

5.54

5.8

6.08

falling

5.44

3.9

5.94

4.3

V

rising

4.1

4.0

0.1

V_{PP5V_UVLO}

Voltage required on PP5V

VBUS discharge current

falling

3.8

4.2

V

hysteresis

I_DSCH

V_VBUS= 22V, measure I_VBUS

4

15

mA

6.10 CC Cable Detection Parameters

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Type-C Source (Rp pull-up)

Unattached CCy open circuit

voltage while Rp enabled, no load

V_{OC_3.3}

V_{OC_5}

1.85

2.95

V

V_{LDO_3V3}> 2.302 V, R_CC= 47 kΩ

V_PP5V> 3.802 V, R_CC= 47 kΩ

Attached CCy open circuit voltage

while Rp enabled, no load

8

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6.10 CC Cable Detection Parameters (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_CCy= 5.5V, V_CCx= 0V,

V_{LDO_3V3_UVLO}< V_{LDO_3V3}< 3.6 V,

V_PP5V= 3.8 V , measure current

into CCy

10

Unattached reverse current on

CCy

I_Rev

µA

V_CCy= 5.5V, V_CCx= 0V,

V_{LDO_3V3_UVLO}< V_{LDO_3V3}< 3.6 V,

V_PP5V= 0, T_J≤85^oC, measure

current into CCy

10

I_RpDef

I_Rp1.5

current source - USB Default

current source - 1.5A

0 < V_CCy< 1.0 V, measure I_CCy

64

80

96

µA

4.75 V < V_PP5V< 5.5 V, 0 < V_CCy

1.5 V, measure I_CCy

<

166

180

194

4.75 V < V_PP5V< 5.5 V, 0 < V_CCy

2.45 V, measure I_CCy

I_Rp3.0

current source - 3.0A

304

330

356

µA

6.11 CC VCONN Parameters

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

V_PP5V=5V, I_L= 250 mA,

R_{PP_CABLE}

Rdson of the VCONN path

measure resistance from PP5V

to CCy

1.2

Ω

V_PP5V=5V, R_L=10mΩ , measure

I_LIMVC

short circuit current limit

540

600

660

10

mA

µA

I_CCy

VCONN disabled, T_J≤85 ^oC,

V_CCy= 5.5 V, V_PP5V=0 V,

V_VBUS=5V, LDO forced to draw

from VBUS, measure I_CCy

Reverse leakage current

through VCONN FET

I_CC2PP5V

Over-voltage protection

threshold for PP_CABLE

V_{VC_OVP}

V_PP5Vrising

5.6

60

5.9

6.2

340

470

V

_PP5V≥4.9 V, V_CCy= V_PP5V

,

200

mV

Reverse current protection

threshold for PP_CABLE,

sourcing VCONN through CCx

V_CCxrising

V_{VC_RCP}

V

_PP5V≥4.9 V, V_CCy≤ 4 V,

210

340

1.3

mV

ms

V_CCxrising

t_VCILIM

Current clamp deglitch time

Time to disable PP_CABLE

t_{PP_CABLE_FSD}

after V_PP5V> V_{VC_OVP}or V_CCx- C_L=0

V_PP5V> V_{VC_RCP}

0.5

µs

from disable signal to CCy at

10% of final value

t_{PP_CABLE_off}

t_{iOS_PP_CABLE}

I_L= 250 mA, V_PP5V= 5V, C_L=0

100

200

2

300

µs

V_PP5V=5V, for short circuit R_L=

10mΩ.

response time to short circuit

6.12 Thermal Shutdown Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

°C

Temperature rising

hysteresis

145

160

20

175

T_{SD_MAIN}

Temperature shutdown threshold

°C

Temperature controlled shutdown Temperature rising

threshold. The PP_5V and

135

150

165

°C

PP_CABLE power paths have

T_{SD_PP5V}

local sensors that disables them

when this temperature is

exceeded.

hysteresis

10

°C

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6.13 Input/Output (I/O) Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CHG_HI, CTL, EN

GPIO_VIH

GPIOx high-Level input voltage V_{LDO_3V3}= 3.3V

GPIOx low-level input voltage V_{LDO_3V3}= 3.3V

GPIOx input hysteresis voltage V_{LDO_3V3}= 3.3V

1.3

V

GPIO_VIL

0.54

GPIO_HYS

0.09

–1

50

V

GPIO_ILKG

GPIO_RPD

GPIOx leakage current

GPIOx internal pull-down

GPIOx input deglitch

V_GPIOx= 3.45 V

1

µA

pull-down enabled

100

20

150

kΩ

GPIO_DG

ns

Status Outputs

GPIO_VOL

GPIOx output low voltage

V_{LDO_3V3}= 3.3V, I_GPIOx=2mA

V_ADCINx= 3.45 V, V_{VIN_3V3}= 3.3

0.4

1

V

ADCIN1, ADCIN2

ADCIN_ILKG

ADCINx leakage current

µA

ms

–1

time from LDO_3V3 going high

until ADCINx is read for

configuration

t_BOOT

10

6.14 BC1.2 Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{DX_SRC}

Source voltage

0.55

250

25

0.6

0.65

400

125

V

C

_{USB_P}≤600 pF

V_{DX_ILIM}

VDX_SRC current limit

Sink Current

µA

I_{DX_SNK}

75

V

_{USB_P}≥250 mV

_{USB_N}≥250 mV

I_{DX_SNK}

Sink Current

25

0.5 V ≤V_{USB_P}≤0.7 V, 25 µA ≤

_{USB_N}≤175 µA

R_{DCP_DAT}

Dedicated Charging Port Resistance

200

Ω

I

6.15 I2C Requirements and Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I2C_EC_IRQ

OD_VOL_IRQ

OD_LKG_IRQ

Low level output voltage

Leakage Current

I_OL= 2 mA

0.4

1

V

Output is Hi-Z, V_{I2Cx_IRQ}= 3.45 V

µA

–1

SDA and SCL Common Characteristics (Slave)

V_IL

V_IH

V_HYS

V_OL

I_LEAK

I_OL

t_f

Input low signal

V_{LDO_3V3}=3.3V,

0.54

V

Input high signal

V_{LDO_3V3}=3.3V,

1.3

Input hysteresis

V_{LDO_3V3}=3.3V

0.165

V

Output low voltage

I_OL=3 mA

0.36

3

V

Input leakage current

Max output low current

Fall time from 0.7*V_DDto 0.3*V_DD

I2C pulse width surpressed

pin capacitance (internal)

Voltage on pin = V_{LDO_3V3}

V_OL=0.4 V

µA

mA

ns

pF

–3

15

20

12

V_OL=0.6 V

80

150

50

V_DD= 1.8V, 10 pF ≤C_b≤400 pF

V_DD= 3.3V, 10 pF ≤C_b≤400 pF

t_f

t_SP

C_I

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6.15 I2C Requirements and Characteristics (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤V_{VIN_3V3}≤3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Capacitive load for each bus line

(external)

C_b

400

pF

SDA and SCL Standard Mode Characteristics (Slave)

f_SCLS

Clock frequency for slave

Valid data time

V_DD= 1.8V or 3.3V

100

kHz

µs

Transmitting Data, V_DD= 1.8V or

3.3V, SCL low to SDA output valid

t_VD;DAT

3.45

Transmitting Data, V_DD= 1.8V or

3.3V, ACK signal from SCL low to

SDA (out) low

t_VD;ACK

Valid data time of ACK condition

3.45

µs

SDA and SCL Fast Mode Characteristics (Slave)

f_SCLS

Clock frequency for slave

V_DD= 1.8V or 3.3V

100

400

0.9

kHz

µs

Transmitting data, V_DD= 1.8V,

SCL

t_VD;DAT

Valid data time

low to SDA output valid

Transmitting data, V_DD= 1.8V or

3.3V, ACK

signal from SCL low to SDA (out)

low

t_VD;ACK

Valid data time of ACK condition

0.9

µs

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6.16 Typical Characteristics

0.55

0.525

0.5

40

38

36

34

32

30

28

26

24

0.475

0.45

0.425

0.4

0.375

0.35

-20

0

20

40

60

T_J(^oC)

80

100

120

140

-20

0

20

40

60

T_J(^oC)

80

100

120

140

D004

D003

图6-2. PP_CABLEx Rdson vs. Temperature

图6-1. PP_5Vx Rdson vs. Temperature

5.8

5.798

5.796

5.794

5.792

5.79

-20

0

20

40

60

T_J(^oC)

80

100

120

140

D008

图6-3. V_OVP4RCPvs. Temperature

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7 Parameter Measurement Information

t

f

t

r

t

SU;DAT

70 %

30 %

70 %

30 %

SDA

cont.

t

HD;DAT

VD;DAT

t

f

t

HIGH

t

r

70 %

30 %

70 %

30 %

70 %

30 %

SCL

30 %

cont.

t

HD;STA

t

LOW

th

9

clock

1 / f

S

SCL

st

1

clock cycle

t

BUF

SDA

SCL

t

VD;ACK

t

SU;STO

SU;STA

HD;STA

SP

70 %

30 %

Sr

P

S

th

9

clock

002aac938

图7-1. I²C Slave Interface Timing

I_LIM5V, I_LIMVC

t_{iOS_PP_5V}, t_{iOS_PP_CABLE}

图7-2. Short-Circuit Response Time for Internal Power Paths PP_5V and PP_CABLE

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8 Detailed Description

8.1 Overview

The TPS25814 is a fully-integrated USB Type-C Source management device providing cable plug and

orientation detection for USB Type-C receptacle. The TPS25814 may also control an attached super-speed

multiplexer to simultaneously support USB data .

The TPS25814 is divided into several main sections: the cable plug and orientation detection circuitry, the port

power switches, the power management circuitry and the digital core.

The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug

insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and

orientation detection, a description of its features and more detailed circuitry, see the Cable Plug and Orientation

Detection.

The port power switches provide power to the VBUS pin and also to the CC1 or CC2 pins based on the detected

plug orientation. For a high-level block diagram of the port power switches, a description of its features and more

detailed circuitry, see the Power Paths.

The TPS25814 has a I²C slave port to be controlled by host processor (see the I²C Interface).

The TPS25814 also integrates a thermal shutdown mechanism and runs off of accurate clocks provided by the

integrated oscillator.

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8.2 Functional Block Diagram

Current Sense

5.0V

PP5V

VBUS

OTSD

thermal

sense

V_{PP5V_UVLO}

V_{VBUS_UVLO}

3.3V

Current Sense

VIN_3V3

CC1

Current

Limit

LDO_1V5

Power

Supply

CC2

Current

Sense

LDO_3V3

Charge Pump

Gate Control

CC Cable

Detect &

OVP

ADCIN1

ADCIN2

POL

Control Logic

I2C_EC_SDA

I2C_EC_SCL

I2C_EC_IRQ

SINK

FAULT

CTL

DEBUG

CHG_HI

EN

GPIO_RPD

USB_N

USB_P

BC 1.2

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8.3 Feature Description

8.3.1 Power Paths

The TPS25814 has internal power paths: PP_5V and PP_CABLE. Each power path is described in detail in this

section.

8.3.1.1 Internal Sourcing Power Paths

图 8-1 shows the TPS25814 internal sourcing power paths. The TPS25814 features two internal 5-V sourcing

power paths. The path from PP5V to VBUS is called PP_5V. The path from PP5V to CCx is called PP_CABLE.

Each path contains current clamping protection, overvoltage protection, UVLO protection and temperature

sensing circuitry. PP_5V may conduct up to 3 A continuously, while PP_CABLE may conduct up to 315 mA

continuously. When disabled, the blocking FET protects the PP5V rail from high-voltage that may appear on

VBUS.

3A

Fast current clamp, I_LIM5V

VBUS

Temp

Sensor

PP_5V Gate Control and Sense

PP_5V

PP_CABLE

CC1 Gate Control

T_{SD_PP5V}

Fast current limit, I_VCON

CC1

CC2 Gate Control

Temp

Sensor

PP5V

CC2

图8-1. Port Power Switches

8.3.1.1.1 PP_5V Current Clamping

The current through the internal PP_5V path are current limited to I_LIM5V. The I_LIM5Vvalue is configured by the

CHG_HI pin as well as ADCIN1 and ADCIN2 pin strapping. When the current through the switch exceeds I_LIM5V

,

the current limiting circuit activates within t_{iOS_PP_5V}and the path behaves as a constant current source. If the

duration of the overcurrent event exceeds t_ILIM, the PP_5V switch is disabled.

8.3.1.1.2 PP_5V Local Overtemperature Shut Down (OTSD)

When PP_5V clamps the current, the temperature of the switch will begin to increase. When the local

temperature sensors of PP_5V or PP_CABLE detect that T_J>T_{SD_PP5V}the PP_5V switch is disabled and the

affected port enters the USB Type-C ErrorRecovery state.

8.3.1.1.3 PP_5V OVP

When the voltage on a port's VBUS pin exceeds V_OVP4RCPwhile PP_5V is enabled, then PP_5V is disabled

within t_{PP_5V_ovp}and the port enters into the Type-C ErrorRecovery state.

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8.3.1.1.4 PP_5V UVLO

If the PP5V pin voltage falls below its undervoltage lock out threshold (V_{PP5V_UVLO}) while PP_5V is enabled, then

PP_5V is disabled within t_{PP_5V_uvlo}and the port that had PP_5V enabled enters into the Type-C ErrorRecovery

state.

8.3.1.1.5 PP_5Vx Reverse Current Protection

If V_VBUS- V_PP5V> V_{PP_5V_RCP}, then the PP_5V path is automatically disabled within t_{PP_5V_rcp}. If the RCP

condition clears, then the PP_5V path is automatically enabled within t_ON

.

8.3.1.1.6 PP_CABLE Current Clamp

When enabled and providing VCONN power the TPS25814 PP_CABLE power switch clamps the current to

I_VCON. When the current through the PP_CABLE switch exceeds I_VCON, the current clamping circuit activates

within t_{iOS_PP_CABLE}and the switch behaves as a constant current source.

8.3.1.1.7 PP_CABLE Local Overtemperature Shut Down (OTSD)

When PP_CABLE clamps the current, the temperature of the switch will begin to increase. When the local

temperature sensors of PP_5V or PP_CABLE detect that T_J>T_{SD_PP5V}the PP_CABLE switch is disabled and

latched off within t_{PP_CABLE_off}. The port then enters the USB Type-C ErrorRecovery state.

8.3.1.1.8 PP_CABLE UVLO

If the PP5V pin voltage falls below its undervoltage lock out threshold (V_{PP5V_UVLO}), then the PP_CABLE switch

is automatically disabled within t_{PP_CABLE_off}

.

8.3.2 Cable Plug and Orientation Detection

图 8-2 shows the plug and orientation detection block at each CCy pin (CC1, CC2). Each pin has identical

detection circuitry.

I_RpDef

I_Rp1.5

I_Rp3.0

VREF1

VREF2

VREF3

CCy

R_SNK

图8-2. Plug and Orientation Detection Block

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8.3.2.1 Configured as a Source

When configured as a source, the TPS25814 detects when a cable or a Sink is attached using the CC1 and CC2

pins. When in a disconnected state, the TPS25814 monitors the voltages on these pins to determine what, if

anything, is connected. See USB Type-C Specification for more information.

表8-1 shows the Cable Detect States for a Source.

表8-1. Cable Detect States for a Source

CC1

CC2

CONNECTION STATE

RESULTING ACTION

Continue monitoring both CCy pins for attach. Power is not applied to VBUS or

VCONN.

Open

Open Nothing attached

Open Sink attached

Rd

Monitor CC1 for detach. Power is applied to VBUS but not to VCONN (CC2).

Monitor CC2 for detach. Power is applied to VBUS but not to VCONN (CC1).

Open

Rd

Sink attached

Powered Cable-No UFP

attached

Monitor CC2 for a Sink attach and CC1 for cable detach. Power is not applied to

VBUS or VCONN (CC1).

Ra

Open

Ra

Open

Powered Cable-No UFP

attached

Monitor CC1 for a Sink attach and CC2 for cable detach. Power is not applied to

VBUS or VCONN (CC1).

Ra

Rd

Ra

Rd

Ra

Provide power on VBUS and VCONN (CC1) then monitor CC2 for a Sink detach.

CC1 is not monitored for a detach.

Powered Cable-UFP Attached

Powered Cable-UFP attached

Provide power on VBUS and VCONN (CC2) then monitor CC1 for a Sink detach.

CC2 is not monitored for a detach.

Rd

Debug Accessory Mode

attached

Rd

Sense either CCy pin for detach.

Audio Adapter Accessory

Mode attached

Ra

When a TPS25814 port is configured as a Source, a current I_RpDefis driven out each CCy pin and each pin is

monitored for different states. When a Sink is attached to the pin a pull-down resistance of Rd to GND exists.

The current I_RpDefis then forced across the resistance Rd generating a voltage at the CCy pin. The TPS25814

applies I_RpDefuntil it closes the switch from PP5V to VBUS, at which time it may change to I_Rp1.5Aor I_Rp3.0A

.

When the CCy pin is connected to an active cable VCONN input, the pull-down resistance is different (Ra). In

this case the voltage on the CCy pin will be lower and the TPS25814 recognizes it as an active cable.

The voltage on CCy is monitored to detect a disconnection depending upon which Rp current source is active.

When a connection has been recognized and the voltage on CCy subsequently rises above the disconnect

threshold for t_CC, the system registers a disconnection.

8.3.3 Overvoltage Protection (CC1, CC2)

The TPS25814 detects when the voltage on the CC1 or CC2 pin is too high or there is reverse current into the

PP5V pin and takes action to protect the system. The protective action is to disable PP_CABLE within

t_{PP_CABLE_FSD}and disable the USB PD transmitter.

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max(V_CC1, V_CC2) - V_PP5V

V_{VC_RCP}

PP5V

CC1

V_{VC_OVP}

Control Logic

Disable PP_CABLE

V_{PHY_OVP}

CC2

V_{PHY_OVP}

图8-3. Overvoltage and Reverse Current Protection for CC1 and CC2

8.3.4 Default Behavior Configuration (ADCIN1, ADCIN2)

The ADCINx pins must be externally tied to the LDO_3V3 pin via a resistive divider as shown in the following

figure. At power-up the ADC converts the ADCINx voltage and the digital core uses these two values to

determine the I²C slave address.

LDO_3V3

Mux and

ADC

Dividers

ADCINx

图8-4. ADCINx Resistor Divider

The device behavior is determined in several ways depending upon the decoded value of the ADCIN1 and

ADCIN2 pins. The following table shows the decoded values for different resistor divider ratios. See Pin

Strapping to Configure Default Behavior for details on how the ADCINx configurations determine default device

behavior. See I²C Address Setting for details on how ADCINx decoded values affects default I²C slave address.

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表8-2. Decoding of ADCIN1 and ADCIN2 Pins

DIV = R_DOWN/ (R_UP+ R_DOWN

)

ADCINx Decoded Value

Without Using

R_UPor R_DOWN

MIN

Target

MAX

0.0228

0.0722

0.1425

0.2372

0.3671

0.7064

0.9060

1.0

ADCINx[2]

ADCINx[1]

ADCINx[0]

0

0.0114

tie to GND

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.0229

0.0723

0.1425

0.2373

0.3672

0.7065

0.9061

0.0475

0.1074

0.1899

0.3022

0.5368

0.8062

0.9530

N/A

tie to LDO_1V5

N/A

tie to LDO_3V3

8.3.5 BC 1.2 (USB_P, USB_N)

The TPS25814 supports BC 1.2 as a Downstream Port using the hardware shown in the following figure.

RDCP_DAT

USB_P

USB_N

VDX_SRC

IDX_SNK

图8-5. BC1.2 Hardware Components

8.3.6 Digital Interfaces

The TPS25814 contains several different digital interfaces which may be used for communicating with other

devices. The available interfaces include one I²C Slave, and additional inputs and outputs.

8.3.6.1 Fault Indicators ( FAULT)

When the PP_5Vx power path is clamping the current, the FAULT pin is asserted. It is de-asserted when the sink

is unplugged or when the TPS25814 enters the Error Recovery state due to an OTSD event.

8.3.6.2 Sink Attachment Indicator ( SINK)

When the TPS25814 detects a valid sink attachment it asserts the SINK pin. The pin is de-asserted when the

sink is detached or the TPS25814 enters the Error Recovery state due to an OTSD event.

8.3.6.3 Polarity Indicator ( POL)

When the SINK pin is asserted, the TPS25814 will also assert the POL pin if CC2 is connected to the CC wire in

the plug. This pin will be de-asserted upon detachment of the sink. POL can connect to the FLIP pin of the

TUSB1046 for example.

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8.3.6.4 Power Management ( CHG_HI)

The TPS25814 will adjust its current advertisement and its current limit when the CHG_HI pin changes state.

When the CHG_HI pin is high, the TPS25814 will limit its current advertisement to the minimum current value.

When the pin is low, the maximum current is advertised. The ADCIN2 pin is used to configure the minimum and

maximum current (see Pin Strapping to Configure Default Behavior). To enable this behavior, the ADCIN1 must

be set to enable SPM (see Pin Strapping to Configure Default Behavior). Note that until the SINK pin is asserted,

the TPS25814 will set its Type-C current advertisement to USB default current.

表8-3. CHG_HI usage

ADCIN1[0]

CHG_HI pin state

Current Advertisement and Current Limit

1

0

Low

Maximum Current (1.5 A or 3.0 A depending on ADCIN2)

Minimum Current (USB default or 1.5 A depending on ADCIN2)

Maximum Current (1.5 A or 3.0 A depending on ADCIN2)

High

High or Low

8.3.6.5 Battery Charging Control (CTL)

The system can control the mode of the BC 1.2 charging used. The TPS25814 will implement the Dedicated

Charging Port (DCP) mode or the Charging Data Port (CDP) mode.

表8-4. BC 1.2 Mode Control (CTL)

CTL pin state

Low

ADCIN2[0] Decoded Value

BC 1.2 Charging Mode

0 or 1

CDP

DCP

High

0

1

High

DCP Auto Mode1

8.3.6.6 Debug Accessory Detection ( DEBUG)

If the TPS25814 detects the attachment of a Type-C debug accessory (Rd, Rd), then it will assert the DEBUG

pin low. Otherwise this pin is Hi-Z.

8.3.6.7 Disable the Port (EN)

The system may force the TPS25814 to disable the port by forcing the EN pin low. This forces the TPS25814

into the Type-C Error Recovery state. Note that the TPS25814 has an internal pull-down on this pin

(GPIO_RPD).

8.3.6.8 I²C Interface

The TPS25814 features an I²C interface that each use an I²C I/O driver like the one shown in 图 8-6. This I/O

consists of an open-drain output and in input comparator with de-glitching.

50ns

I2C_DI

Deglitch

I2C_SDA/SCL

I2C_DO

图8-6. I²C Buffer

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8.3.7 I²C Interface

The TPS25814 has an I²C slave interface port: I2C_EC . I²C port I2C_EC is comprised of the I2C_EC_SDA,

I2C_EC_SCL, and I2C_EC_IRQ pins. These interfaces provide general status information about the TPS25814,

as well as the ability to control the TPS25814 behavior, and providing information about connections detected at

the USB-C receptacle.

表8-5. I²C Summary

I2C Bus

Type

Typical Usage

I2C_EC

Slave

Connect to an Embedded Controller (EC).

8.3.7.1 I²C Interface Description

The TPS25814 supports Standard and Fast mode I²C interfaces. The bidirectional I²C bus consists of the serial

clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up resistor.

Data transfer may be initiated only when the bus is not busy.

A master sending a Start condition, a high-to-low transition on the SDA input and output, while the SCL input is

high initiates I²C communication. After the Start condition, the device address byte is sent, most significant bit

(MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/

output during the high of the ACK-related clock pulse. On the I²C bus, only one data bit is transferred during

each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period as

changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a

Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high.

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a

slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must

generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to

ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this

event, the transmitter must release the data line to enable the master to generate a Stop condition.

图8-7 shows the start and stop conditions of the transfer. 图8-8 shows the SDA and SCL signals for transferring

a bit. 图8-9 shows a data transfer sequence with the ACK or NACK at the last clock pulse.

SDA

SCL

S

P

Start Condition

Stop Condition

图8-7. I²C Definition of Start and Stop Conditions

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SDA

SCL

Data Line

Change

图8-8. I²C Bit Transfer

Data Output

by Transmitter

Nack

Data Output

by Receiver

SCL From

Master

Ack

1

2

8

9

S

Clock Pulse for

Acknowledgement

Start

Condition

图8-9. I²C Acknowledgment

8.3.7.2 I²C Clock Stretching

The TPS25814 features clock stretching for the I²C protocol. The TPS25814 slave I²C port may hold the clock

line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The

master communicating with the slave must not finish the transmission of the current bit and must wait until the

clock line actually goes high. When the slave is clock stretching, the clock line remains low.

The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for

standard 100-kbps I²C) before pulling the clock low again.

Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.

8.3.7.3 I²C Address Setting

The host should only use I2C_EC_SCL/SDA for loading a patch bundle. Once the boot process is complete,

each port has a unique slave address on the I2C_EC_SCL/SDA bus as selected by the ADCINx pins.

表8-6. I²C Default Slave Address for I2C_EC_SCL/SDA.

ADCIN1 Decoding

Slave Address

ADCIN1[1] ADCIN1[0]

Bit 7

Bit 6

Bit 5

Bit 4 Bit 3

Bit 2

Bit 1

Bit 0

R/W

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

8.3.7.4 Unique Address Interface

The Unique Address Interface allows for complex interaction between an I²C master and a single TPS25814.

The I²C Slave sub-address is used to receive or respond to Host Interface protocol commands. 图 8-10 and 图

8-11 show the write and read protocol for the I²C slave interface, and a key is included in 图 8-12 to explain the

terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated here in part.

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1

S

7

1

8

1

8

1

8

1

Unique Address

Wr

A

Register Number

A

Byte Count = N

A

Data Byte 1

A

8

1

8

1

Data Byte 2

A

Data Byte N

A

P

图8-10. I²C Unique Address Write Register Protocol

1

S

7

1

8

1

7

1

8

1

Unique Address

Wr

A

Register Number

A

Sr

Unique Address

Rd

A

Byte Count = N

A

8

1

8

1

8

1

Data Byte 1

A

Data Byte 2

A

Data Byte N

A

1

P

图8-11. I²C Unique Address Read Register Protocol

1

7

1

A

x

8

1

A

x

1

S

Slave Address

Wr

Data Byte

P

S

Start Condition

SR

Rd

Wr

x

Repeated Start Condition

Read (bit value of 1)

Write (bit value of 0)

Field is required to have the value x

Acknowledge (this bit position may be 0 for an ACK or

1 for a NACK)

A

P

Stop Condition

Master-to-Slave

Slave-to-Master

Continuation of protocol

图8-12. I²C Read/Write Protocol Key

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8.4 Device Functional Modes

8.4.1 Pin Strapping to Configure Default Behavior

During the boot procedure, the device will read the ADCINx pins and set the configurations based on the table

below.

表8-7. Device Configuration using ADCIN1

ADCIN1 Decoded Value ⁽¹⁾

I²C Address Index ⁽²⁾SPM Enabled

ADCIN1[2]

ADCIN1[1]

ADCIN1[0]

0

1

0

1

0

1

0

1

0

1

0

1

#1

#2

#3

#4

#1

#2

#3

#4

0

1

no

yes

(1) See 表8-6 to see the exact meaning of I²C Address Index.

(2) See 表8-2 for how to configure a given ADCINx decoded value.

表8-8. Device Configuration using ADCIN2

ADCIN2 Decoded Value ⁽¹⁾

Maximum

Current

Minimum Current⁽²⁾

DCP Mode

ADCIN2[2]

ADCIN2[1]

ADCIN2[0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DCP

1.5A

DCP Auto Mode 1

DCP

USB Default

3A

1.5A

3A

DCP Auto Mode 1

DCP

DCP Auto Mode 1

DCP

1.5A

DCP Auto Mode 1

(1) See 表8-2 for how to configure a given ADCINx decoded value.

(2) Requires SPM to be enabled via ADCIN1.

8.4.2 Power States

The TPS25814 may operate in one of three different power states: Active, Idle, or Sleep. The Modern Standby

mode is a special case of the Idle mode. The functionality available in each state is summarized in the following

table. The device will automatically transition between the three power states based on the circuits that are

active and required, see the following figure. In the Sleep State the TPS25814 will detect a Type-C connection.

Transitioning between the Active mode to the Idle mode requires a period of time (T) without any of the following

activity:

• Change in CC status.

• GPIO input event.

• I²C transactions.

• Voltage alert.

• Fault alert.

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图8-13. Flow Diagram For Power States

表8-9. Power Consumption States.

Modern Standby Source

Active Source Mode⁽¹⁾

Idle Source Mode⁽²⁾

Sleep Mode⁽³⁾

Mode⁽⁴⁾

enabled

disabled

Rd

PP_5V

enabled

Rd

disabled

open

PP_CABLE

external CC1 termination Rd

external CC2 termination open

open

(1) This mode is used for: I_{VIN_3V3,ActSrc}

(2) This mode is used for: I_{VIN_3V3,IdlSrc}

(3) This mode is used for: I_{VIN_3V3,SleepSrc}

(4) This mode is used for: P_MstbySrc

8.4.3 Schottky for Current Surge Protection

To prevent the possibility of large ground currents into the TPS25814 during sudden disconnects due to

inductive effects in a cable, it is recommended that a Schottky diode be placed from VBUS to ground as shown

in 图8-14.

PP5V

VBUS

GND

图8-14. Schottky for Current Surge Protection

8.4.4 Thermal Shutdown

The TPS25814 features a central thermal shutdown as well as independent thermal sensors for each internal

power path. The central thermal shutdown monitors the overall temperature of the die and disables all functions

except for supervisory circuitry when die temperature goes above a rising temperature of T_{SD_MAIN}. The

temperature shutdown has a hysteresis of T_{SDH_MAIN}and when the temperature falls back below this value, the

device resumes normal operation.

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The power path thermal shutdown monitors the temperature of each internal PP5V-to-VBUS power path and

disables both power paths and the VCONN power path when either exceeds T_{SD_PP5V}. Once the temperature

falls by at least T_{SDH_PP5V}the path can be configured to resume operation or remain disabled until re-enabled by

firmware.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The TPS25814 is a Type-C DFP controller that supports all Type-C DFP required functions. The TPS25814 Only

applies power to VBUS when it detects that a UFP is attached and removes power when it detects the UFP is

detached. The device exposes its identity via its CC pin advertising its current capability based on the CHG_HI

pin settings. The TPS25814 also limits its advertised current internally and provides robust protection to a fault

on the system VBUS power rail.

After a connection is established by the TPS25814, the device is capable of providing VCONN to power circuits

in the cable plug on the CC pin that is not connected to the CC wire in the cable. VCONN is internally current

limited and is supplied by PP5V.

The TPS25814 is also capable of supporting BC 1.2 compliant charging schemes of a Charging Data Port (CDP)

and a Dedicated Charging Port (DCP). The CTL pin changes which charging modes are activated to the

connected portable device.

The following design procedure can be used to implement a full featured Type-C DFP.

9.2 Typical Application

9.2.1 Type C DFP Port Implementation with Embedded Controller

图 9-1 shows a Type-C DFP implementation where the TPS25814 is connected to an embedded controller. The

embedded controller will have the ability to communicate with the TPS25814 via I²C, as well as change the

charge current advertisement and BC 1.2 charging scheme.

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图9-1. Type C DFP Port Implementation

9.2.1.1 Detailed Design Procedure

9.2.1.1.1 Type-C Connector VBUS Capacitors

The first level of protection starts at the Type-C connector and the VBUS pin capacitors. These capacitors help

filter out high frequency noise but can also help absorb short voltage transients. Each VBUS pin should have a

10-nF capacitor rated at or above 25 V and placed as close to the pin as possible. The GND pin on the

capacitors should have very short path to GND on the connector. The derating factor of ceramic capacitors

should be taken into account as they can lose more than 50% of their effective capacitance when biased. Adding

the VBUS capacitors can help reduce voltage spikes by 2 V to 3 V.

9.2.1.1.2 VBUS Schottky and TVS Diodes

Schottky diodes are used on VBUS to help absorb large GND currents when a Type-C cable is removed while

drawing high current. The inductance in the cable will continue to draw current on VBUS until the energy stored

is dissipated. Higher currents could cause the body diodes on IC devices connected to VBUS to conduct. When

the current is high enough it could damage the body diodes of IC devices. Ideally, a VBUS Schottky diode should

have a lower forward voltage so it can turn on before any other body diodes on other IC devices. Schottky

diodes on VBUS also help during hard shorts to GND which can occur with a faulty Type-C cable or damaged

Type-C PD device. VBUS could ring below GND which could damage devices hanging off of VBUS. The

Schottky diode will start to conduct once VBUS goes below the forward voltage. When the TPS25814 is the only

device connected to VBUS, place the Schottky Diode close to the VBUS pin of the TPS25814.

TVS Diodes help suppress and clamp transient voltages. Most TVS diodes can fully clamp around 10 ns and can

keep the VBUS at their clamping voltage for a period of time. Looking at the clamping voltage of TVS diodes

after they settle during a transient will help decide which TVS diode to use. The peak power rating of a TVS

diode must be able to handle the worst case conditions in the system.

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9.2.1.1.3 VBUS Snubber Circuit

VBUS

4.7 …F

3.48Ω

1 …F

GND

图9-2. VBUS Snubber

Another method of clamping the USB Type-C VBUS is to use a VBUS RC Snubber. An RC Snubber is smaller

than a TVS diode, and typically more cost effective as well. An RC Snubber works by modifying the

characteristic of the total RLC response in the USB Type-C cable hot-plug from being under-damped to critically-

damped or over-damped. So rather than clamping the overvoltage directly, it changes the hot-plug response

from under-damped to critically-damped, so the voltage on VBUS does not ring at all; so the voltage is limited,

but without requiring a clamping element like a TVS diode.

However, the USB Type-C and Power Delivery specifications limit the range of capacitance that can be used on

VBUS for the RC snubber. VBUS capacitance must have a minimum 1 µF and a maximum of 10 µF. The RC

snubber values chosen support up to 4 m USB Type-C cable (maximum length allowed in the USB Type-C

specification) being hot plugged, is to use 4.7-μF capacitor in series with a 3.48-Ω resistor. In parallel with the

RC Snubber a 1-μF capacitor is used, which always ensures the minimum USB Type-C VBUS capacitance

specification is met. This circuit is shown in 图9-2.

9.2.1.2 Application Curves

图9-3. VBUS Short to Ground (Zoomed In)

图9-4. VBUS Short to Ground (Zoomed Out)

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10 Power Supply Recommendations

10.1 3.3-V Power

10.1.1 VIN_3V3 Input Switch

The VIN_3V3 input is the main supply of the TPS25814 device. The VIN_3V3 switch is a uni-directional switch

from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3 to VIN_3V3. This switch is on

when the 3.3 V supply is available. The recommended capacitance C_{VIN_3V3}(see the Recommended

Capacitance in the Specifications section) should be connected from the VIN_3V3 pin to the GND pin ).

10.2 1.5-V Power

The internal circuitry is powered from 1.5 V. The 1.5-V LDO steps the voltage down from LDO_3V3 to 1.5 V. The

1.5-V LDO provides power to all internal low-voltage digital circuits which includes the digital core, and memory.

The 1.5-V LDO also provides power to all internal low-voltage analog circuits. Connect the recommended

capacitance C_{LDO_1V5}(see the Recommended Capacitance in the Specifications section) from the LDO_1V5 pin

to the GND pin.

10.3 Recommended Supply Load Capacitance

The Recommended Capacitance in the Specifications section lists the recommended board capacitances for the

various supplies. The typical capacitance is the nominally rated capacitance that must be placed on the board as

close to the pin as possible. The maximum capacitance must not be exceeded on pins for which it is specified.

The minimum capacitance is minimum capacitance allowing for tolerances and voltage derating ensuring proper

operation.

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11 Layout

11.1 Layout Guidelines

Proper routing and placement will maintain signal integrity for high speed signals and improve the heat

dissipation from the TPS25814 power path. The combination of power and high speed data signals are easily

routed if the following guidelines are followed. It is a best practice to consult with board manufacturing to verify

manufacturing capabilities.

11.1.1 Top TPS25814 Placement and Bottom Component Placement and Layout

When the TPS25814 is placed on top and its components on bottom the solution size will be at its smallest.

11.2 Layout Example

Follow the differential impedances for Super / High Speed signals defined by their specifications (DisplayPort -

AUXN/P and USB2.0). All I/O will be fanned out to provide an example for routing out all pins, not all designs will

utilize all of the I/O on the TPS25814.

图11-1. Example Schematic

11.3 Component Placement

Top and bottom placement is used for this example to minimize solution size. The TPS25814 is placed on the

top side of the board and the majority of its components are placed on the bottom side. When placing the

components on the bottom side, it is recommended that they are placed directly under the TPS25814. When

placing the VBUS and PPHV capacitors it is easiest to place them with the GND terminal of the capacitors to

face outward from the TPS25814 or to the side since the drain connection pads on the bottom layer should not

be connected to anything and left floating. All other components that are for pins on the GND pad side of the

TPS25814 should be placed where the GND terminal is underneath the GND pad.

The CC capacitors should be placed on the same side as the TPS25814 close to the respective CC1 and CC2

pins. Do NOT via to another layer in between the CC pins to the CC capacitor, placing a via after the CC

capacitor is recommended.

The ADCIN1/2 voltage divider resistors can be placed where convenient.

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The figures below show the placement in 2-D and 3-D.

图11-2. Top View Layout

图11-3. Bottom View Layout

图11-4. Top View 3-D

图11-5. Bottom View 3-D

11.4 Routing and View Placement

On the top side, create pours for PP5V and VBUS. Connect PP5V and VBUS from the top layer to the bottom

layer using at least 6, 8-mil hole and 16-mil diameter vias. See 图 11-6 for the recommended via sizing. The via

placement and copper pours are highlighted in 图11-7.

图11-6. Recommended Minimum Via Sizing

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图11-7. Via Placement - Top Layer

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图11-8. Via Placement - Bottom Layer

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图11-9. Routing - Top Layer

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图11-10. Routing - Bottom Layer

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12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.2 Documentation Support

12.2.1 Related Documentation

• USB-PD Specifications

• USB Power Delivery Specification

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RSM 32

4 x 4, 0.4 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224982/A

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PACKAGE OUTLINE

RSM0032B

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

B

4.1

3.9

A

0.45

0.25

0.15

PIN 1 INDEX AREA

DETAIL

OPTIONAL TERMINAL

TYPICAL

4.1

3.9

(0.1)

SIDE WALL DETAIL

OPTIONAL METAL THICKNESS

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

2.8 0.05

2X 2.8

(0.2) TYP

4X (0.45)

28X 0.4

9

16

SEE SIDE WALL

DETAIL

8

17

EXPOSED

THERMAL PAD

2X

SYMM

33

2.8

24

0.25

32X

1

SEE TERMINAL

DETAIL

0.15

0.1

C A B

25

32

PIN 1 ID

(OPTIONAL)

0.05

SYMM

0.45

0.25

32X

4219108/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RSM0032B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.8)

SYMM

32

25

32X (0.55)

1

32X (0.2)

24

(

0.2) TYP

VIA

(1.15)

SYMM

33

(3.85)

28X (0.4)

17

8

(R0.05)

TYP

9

16

(1.15)

(3.85)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219108/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RSM0032B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.715)

4X ( 1.23)

(R0.05) TYP

25

32

32X (0.55)

1

24

32X (0.2)

(0.715)

(3.85)

33

SYMM

28X (0.4)

17

8

METAL

TYP

16

9

SYMM

(3.85)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 33:

77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219108/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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型号：	TPS25814RSMR
厂家：	TEXAS INSTRUMENTS
描述：	具有集成拉电流电源开关的 USB Type-C® 控制器 \| RSM \| 32 \| -40 to 105 开关控制器电源开关
文件：	总44页 (文件大小：2610K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS25814RSMR [TI]

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