TPS25840QWRHBTQ1 [TI]
具有 STB 保护和电缆补偿功能的 USB-A SDP/CDP 充电端口转换器 | RHB | 32 | -40 to 125;
| 型号： | TPS25840QWRHBTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 STB 保护和电缆补偿功能的 USB-A SDP/CDP 充电端口转换器 | RHB | 32 | -40 to 125 CD 开关 输出元件 转换器 |
| 文件： | 总63页 (文件大小：5969K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS25840-Q1, TPS25842-Q1
ZHCSK92E –SEPTEMBER 2019 –REVISED MARCH 2022
TPS2584x-Q1 具有电缆补偿功能的汽车类USB Type-A BC1.2、5V 3.5A 输出、
36V 输入同步降压稳压器
• ±8kV 接触放电和±15kV 空气放电
• 故障标志报告
• 具有可润湿侧翼的32 引脚QFN 封装
1 特性
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：–40°C 至+125°C，TA
– HBM ESD 分类等级H2
– CDM ESD 分类等级C5
• 提供功能安全
2 应用
• 汽车信息娱乐系统
• USB 媒体中心
• USB 充电器端口
– 有助于进行功能安全系统设计的文档
• 同步降压直流/直流稳压器
3 说明
– 输入电压范围：4.5V 至36V
– 输出电流：3.5A
– 5.1V 输出电压，精度为±1%
– 电流模式控制
– 频率可调节：300 kHz 至2.2 MHz
– 与外部时钟频率同步
TPS2584x-Q1 是 USB Type-A BC1.2 充电解决方案，
其中包括一个同步直流/直流转换器。凭借电缆压降补
偿，不管负载电流如何变化，Vbus 都保持恒定，确保
即使在重负载期间也能以合适的电流和电压为连接的便
携式设备充电。
– 具有扩频频谱抖动的FPWM
– 内置补偿功能，便于使用
• 符合USB-IF 标准
TPS2584x-Q1 包括可实现 DP 和 DM 直通的高带宽模
拟开关。
TPS25840-Q1 还在 VBUS、DM_IN 和 DP_IN 引脚上
集成了电池短路保护。这些引脚可承受最高 18V 的电
压。TPS25842-Q1 不支持数据线 (Dx) 对 VBAT 短路保
护。
– 符合USB BC1.2 规范的CDP/SDP 模式
• 针对USB 电源和通信进行了优化
– 用户可编程的USB 电流限制
– 高达1.5V 的电缆压降补偿
– DP 和DM 上的高带宽数据开关
– 可用于进行系统更新的客户端模式
• 集成式保护
器件信息(1)
器件型号
TPS25840-Q1
封装
封装尺寸（标称值）
超薄四方扁平无
引线(VQFN)
(32)
5.00mm x 5.00mm
– VBUS 对VBAT 短路保护
– DP_IN 和DM_IN VBAT 短路保护
超薄四方扁平无
引线(VQFN)
(32)
（仅TPS25840-Q1）
– DP_IN 和DM_IN VBUS 短路保护
– 符合IEC 61000-4-2 标准的DP_IN、DM_IN
TPS25842-Q1
5.00mm x 5.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
CBOOT
100
95
90
85
80
75
VIN
BOOT
L
RSNS
IN
SW
CSP
RSET
EN/UVLO
RT/SYNC
CSN/OUT
VCC
TPS2584x-Q1
LS_GD
Optional
FAULT
70
VIN = 6V
VIN = 13.5V
BUCK_ST
CTRL1
CTRL2
65
60
VIN = 18V
VIN = 36V
BUS
DP_IN
DM_IN
DP_OUT
DM_OUT
INT
0.1
1
OUT Current (A)
4
A001
IMON ILIMIT
AGND PGND
降压效率与输出电流间的关系(fsw = 400 kHz)
TPS2584x-Q1 简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEG3
TPS25840-Q1, TPS25842-Q1
ZHCSK92E –SEPTEMBER 2019 –REVISED MARCH 2022
www.ti.com.cn
Table of Contents
10.3 Feature Description.................................................20
10.4 Device Functional Modes........................................36
11 Application and Implementation................................ 38
11.1 Application Information............................................38
11.2 Typical Application.................................................. 38
12 Power Supply Recommendations..............................48
13 Layout...........................................................................48
13.1 Layout Guidelines................................................... 48
13.2 Ground Plane and Thermal Considerations............49
13.3 Layout Example...................................................... 50
14 Device and Documentation Support..........................51
14.1 Documentation Support.......................................... 51
14.2 Related Links.......................................................... 51
14.3 接收文档更新通知................................................... 51
14.4 支持资源..................................................................51
14.5 Trademarks.............................................................51
14.6 Electrostatic Discharge Caution..............................51
14.7 术语表..................................................................... 51
15 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Device Comparison Table...............................................4
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings........................................ 6
8.2 ESD Ratings............................................................... 6
8.3 Recommended Operating Conditions.........................7
8.4 Thermal Information....................................................8
8.5 Electrical Characteristics.............................................8
8.6 Timing Requirements................................................ 11
8.7 Switching Characteristics..........................................12
8.8 Typical Characteristics..............................................13
9 Parameter Measurement Information..........................18
10 Detailed Description....................................................19
10.1 Overview.................................................................19
10.2 Functional Block Diagram.......................................20
Information.................................................................... 51
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (February 2022) to Revision E (March 2022)
Page
• Added the thermal information for RHB0032AA package.................................................................................. 8
Changes from Revision C (December 2021) to Revision D (February 2022)
Page
• Added RHB0032AA package to the data sheet..................................................................................................4
Changes from Revision B (August 2020) to Revision C (December 2021)
Page
• Added additional description for Fault pin, for better signal quality under some sensitive application............... 4
Changes from Revision A (May 2020) to Revision B (August 2020)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 向特性部分添加了功能安全链接........................................................................................................................ 1
Changes from Revision * (September 2019) to Revision A (May 2020)
Page
• Changed Layout description for clarity............................................................................................................. 48
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5 说明（续）
此同步降压稳压器具有电流模式控制并采用内部补偿，因此简化了设计。RT 引脚上有一个电阻器，可用于在
300kHz 和2.2MHz 之间设置开关频率。在低于 400kHz 的频率下运行可实现更高的系统效率。在高于 2.1MHz 的
频率下运行则可以避开AM 无线电频带，并且能够使用较小的电感器。
TPS2584x-Q1 集成了传统器件所需的电气特性，这些器件使用USB 数据线来确定充电配置。
内含一个精密电流感应放大器，用于实现用户可编程电缆压降补偿和电流限制调整。电缆补偿可使降压稳压器输
出电压随负载电流线性改变，以抵消由于汽车电缆布线中的导线电阻引起的压降，从而帮助便携式设备在重载下
实现最佳电流和电压充电。无论负载电流如何，在连接的便携式器件上测得的 VBUS 电压都保持大致恒定，这
样，便携式器件的电池充电器就能够保持最佳工作状态。
USB 规范要求 USB 充电端口满足电流限制，但也留下了合理的自由空间，允许系统设计人员基于系统要求选择
过流保护级别。TPS2584x-Q1 使用了一种新颖的双阈值电流限制电路，允许系统设计者对降压稳压器的平均电流
限制保护进行编程，或者在 CSN/OUT 和 BUS 引脚之间使用一个外部 NMOS 来对电流限制进行调整。由于实施
了NFET，TPS2584x-Q1 降压稳压器可在USB 端口上存在过流故障期间为其他负载提供5V 输出。
保护特性包括逐周期电流限制、断续短路保护、欠压锁定、VBUS 过压和过流保护、数据线(Dx) 对VBUS 短路保
护以及裸片过热保护。
TPS25840-Q1 包括可实现 DP 和 DM 直通的高带宽模拟开关，支持数据线 (Dx) 对 VBAT 短路保护。TPS25842-
Q1 不支持数据线(Dx) 对VBAT 短路保护。
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6 Device Comparison Table
DP AND DM
SWITCHES
DP/DM Short to
BAT
PART NUMBER
PACKAGE
DCP AUTO
NTC INPUT
TPS25840-Q1
TPS25842-Q1
VQFN (32)
VQFN (32)
No
No
Yes
Yes
No
No
Yes
No
7 Pin Configuration and Functions
A1
A4
1
24
FAULT
IN
1
24
FAULT
IN
IN
BUCK_ST
N/C
IN
IN
2
3
4
5
6
7
8
23
22
21
20
19
18
17
BUCK_ST
N/C
2
3
4
5
6
7
8
23
22
21
20
19
18
17
IN
EN
VCC
EN
VCC
Thermal Pad
Thermal Pad
CTRL1
CTRL2
DP_OUT
DM_OUT
INT
CTRL1
CTRL2
DP_OUT
DM_OUT
INT
N/C
N/C
DP_IN
DM_IN
DP_IN
DM_IN
A2
A3
As of 11/14/2017
图7-2. TPS25840QCWRHBRQ1,
NOTES:
1) A1, A2, A3, and A4 are corner anchors for enhanced package stress
performance.
2) A1, A2, A3, and A4 are electrically connected to the thermal pad.
3) A1, A2, A3, and A4 PCB lands should be electrically isolated or
electrically connected to thermal pad and PGND.
TPS25842QCWRHBRQ1 Package 32-Pin (VQFN)
Top View (2)
图7-1. TPS25840QWRHBRQ1,
TPS25842QWRHBRQ1 Package 32-Pin (VQFN) Top
View (1)
表7-1. Pin Functions
PIN
NAME
TYPE(3)
I/O
DESCRIPTION
NO.
Analog ground terminal. Ground reference for internal references and logic. All electrical
parameters are measured with respect to this pin. Connect to system ground on PCB.
AGND
BOOT
16
G
P
-
Boot-strap capacitor connection for HS FET driver. Connect a high quality 100-nF capacitor
from this pin to the SW pin.
32
BUS
CSN/OUT
CSP
15
13
14
5
A
P
P
A
A
A
A
A
A
I
I
I
I
I
VBUS discharge input. Connect to VBUS on USB Connector.
Negative input of current sense amplifier, also buck output for internal voltage regulation.
Positive input of current sense amplifier.
CTRL1
CTRL2
DM_IN
DM_OUT
DP_IN
Logic-level control inputs for device and system configuration (see 表10-6).
Logic-level control inputs for device and system configuration (see 表10-6).
DM data line. Connect to USB connector.
6
17
8
DM data line. Connect to USB host controller.
18
7
DP data line. Connect to USB connector.
DP_OUT
DP data line. Connect to USB host controller.
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表7-1. Pin Functions (continued)
PIN
TYPE(3)
I/O
DESCRIPTION
NAME
NO.
Enable pin. Do not float. High = on, Low = off. Can be tied to VIN. Precision enable input
allows adjustable UVLO by external resistor divider.
EN/UVLO
FAULT
4
A
A
Active LOW open-drain output. Asserted during fault conditions (see 表10-4). TI
recommends series about 1-k ohm damping resistor for better signal quality.
24
O
ILIMIT
IMON
12
11
A
A
External resistor used to set the current-limit threshold (see 表10-2).
External resistor used to set the max cable comp voltage at full load current.
Input Supply to regulator. Connect high-quality bypass capacitors directly to this pin and
PGND.
IN
1, 2, 3
23
P
A
I
Active Low open-drain output. After BUCK_ST assert, the Buck converter begins to start
up. At the same time, DP and DM data switch turn on accordingly.
BUCK_ST
O
External NMOS gate driver. If TPS2584x-Q1 configured under average current limit mode,
LS_GD pin must be pulled up through a 2.2-kΩresistor (see Current Limit Sensing using
RILIMIT).
LS_GD
10
A
25, 26,
27
Power ground terminal. Connect to system ground and AGND. Connect to bypass
capacitor with short wide traces.
PGND
N/C
G
-
19, 22
Make no electrical connection.
Resistor Timing or External Clock input. An internal amplifier holds this terminal at a fixed
voltage when using an external resistor to ground to set the switching frequency. If the
terminal is pulled above the PLL upper threshold, a mode change occurs and the terminal
becomes a synchronization input. The internal amplifier is disabled and the terminal is a
high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier
is re-enabled and the operating mode returns to resistor frequency programming.
RT/SYNC
9
A
28, 29,
30, 31
Switching output of the regulator. Internally connected to source of the HS FET and drain of
the LS FET. Connect to power inductor.
SW
INT
P
A
P
20
21
For internal circuit, must connect a 5.1-K resistor to AGND.
Output of internal bias supply. Used as supply to internal control circuits. Connect a high
quality 2.2-µF capacitor from this pin to GND.
VCC
(1) For package drawing please refer to RHB0032R at the end of the data sheet.
(2) For package drawing please refer to RHB0032AA at the end of the data sheet.
(3) A = Analog, P = Power, G = Ground.
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8 Specifications
8.1 Absolute Maximum Ratings
Voltages are with respect to GND (unless otherwise noted)(1)
PARAMETER
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–3.5
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
IN to PGND
40
OUT to PGND
EN to AGND
CSP to AGND
20
VIN + 0.3
20
Input voltage
CSN to AGND
20
V
BUS to AGND
18
RT/SYNC to AGND
6
CTRL1 or CTRL2 to AGND
AGND to PGND
6
0.3
SW to PGND
VIN + 0.3
SW to PGND (less than 10 ns transients)
BOOT to SW
40
6
Output voltage
Voltage range
V
V
VCC to AGND
6
LS_GD
18
18
7
TPS25840-Q1: DP_IN, DM_IN to AGND
TPS25842-Q1: DP_IN, DM_IN to AGND
DP_OUT, DM_OUT to AGND
FAULT, BUCK_ST, INT to AGND
ILIMIT or IMON to AGND
6
6
6
Pin positive source current,
IVCC
VCC Source Current
5
mA
A
Internally
Limited
Pin positive sink current, ISNK FAULT, BUCK_ST
DP_IN to DP_OUT, or DM_IN to DM_OUT in SDP, CDP, or
Client Mode
I/O current
100
mA
–100
TJ
Junction temperature
Storage temperature
-40
150
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Rating can cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
8.2 ESD Ratings
VALUE
±2000(2)
±750(3)
UNIT
Human body model (HBM), per AEC Q100-002(1)
Corner pins (1, 8, 9, 17, 25 and 32)
Charged device model (CDM), per
AEC Q100-011
V(ESD) Electrostatic discharge
Other pins
±750(3)
V
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air-gap discharge
DP_IN, DM_IN pins
DP_IN, DM_IN pins
±8000(4)
±15000(4)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) The passing level per AEC-Q100 Classification H2.
(3) The passing level per AEC-Q100 Classification C5.
(4) Surges per IEC61000-4-2, 1999 applied between DP_IN, DM_IN and output ground of the TPS2584x-Q1 evaluation module.
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8.3 Recommended Operating Conditions
Voltages are with respect to GND (unless otherwise noted)
MIN
4.5
0
NOM
MAX UNIT
IN to PGND
EN
36
VIN
5.5
3.6
VCC when driven from external regulator
DP_IN, DM_IN
0
VI
Input voltage
0
DP_OUT, DM_OUT
0
3.6
VCC
VCC
VCC
6.5
V
CTRL1, CTRL2
0
RT/SYNC when driven by external clock
FAULT, BUCK_ST
0
VPU
VO
Pull up voltage
Output voltage
0
CSN/OUT
0
Buck regulator output current
0
3.5
A
IO
Output current
DP_IN to DP_OUT or DM_IN to DM_OUT Continuous
current in SDP, CDP or Client Mode
30
–30
mA
ISNK
II
Sink current
FAULT, BUCK_ST
10
200
Input current
Continuous current into the CSP pin
RIMON, RILIMIT
µA
kΩ
°C
REXT
TJ
External resistnace
0
100
Operating junction temperature
125(1)
–40
(1) Operating at junction temperatures greater than 125°C is possible, however lifetime will be degraded.
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8.4 Thermal Information
TPS2584x-Q1
THERMAL METRIC(1)
RHB0032R (VQFN)
RHB0032AA (VQFN)
UNIT
32 PINS
28.7
17.6
7.2
32 PINS
29.4
18.6
9.7
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
0.2
ΨJT
7.2
9.7
ΨJB
RθJC(bot)
1
2.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS
=
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ωunless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTATE (IN PIN)
VIN
IQ
Operating input voltage range
4.5
36
V
VEN/UVLO = VIN, CTRL1 = CTRL2 =
VCC, VCSN = 8 V, INT pull down
resistance = 5.1 kΩ
Operating quiescent current (non
switching)
700
10
990
µA
Shutdown quiescent current;
measured at IN pin.
ISD
EN= 0
16
µA
ENABLE and UVLO (EN/UVLO PIN)
EN/UVLO input level required to turn
on internal LDO
VEN/UVLO_VCC_H
VEN/UVLO_VCC_L
VEN/UVLO_H
VEN/UVLO rising threshold
VEN/UVLO falling threshold
VEN/UVLO rising threshold
1.14
V
V
V
EN/UVLO input level required to turn
off internal LDO
0.3
EN/UVLO input level required to turn
on state machine
1.140
1.200
1.260
VEN/UVLO_HYS
ILKG_EN/UVLO
INTERNAL LDO
VBOOT_UVLO
Hysteresis
VEN/UVLO falling threshold
VEN/UVLO = 3.3 V
90
mV
uA
Enable input leakage current
0.5
Bootstrap voltage UVLO threshold
2.2
5
V
V
Internal LDO output voltage appearing
on VCC pin
VCC
4.75
3.4
5.25
3.8
6 V ≤VIN ≤36 V
VCC_UVLO_R
Rising UVLO threshold
Hysteresis
3.6
V
VCC_UVLO_HYS
600
mV
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE BUCK AVG CURRENT LIMITING
VCSN = 5 V, RSET = 300 Ω, RILIMIT
13 kΩ, RIMON = 13 kΩ, -40°C ≤TJ ≤
125°C
=
Current limit voltage buck regulator
control loop
(VCSP –VCSN/
43.5
42.5
20
46
46
48.5
49.5
25
mV
mV
mV
)
OUT
VCSN = 5 V, RSET = 300 Ω, RILIMIT
13 kΩ, RIMON = 13 kΩ, -40°C ≤TJ ≤
150°C
=
Current limit voltage buck regulator
control loop
(VCSP –VCSN/
)
OUT
VCSN = 5 V, RSET = 300 Ω, RILIMIT
26.1 kΩ, RIMON = 13 kΩ, -40°C ≤TJ
≤125°C
=
Current limit voltage buck regulator
control loop
(VCSP –VCSN/
22.5
)
OUT
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8.5 Electrical Characteristics (continued)
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS
=
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ωunless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCSN = 5 V, RSET = 300 Ω, RILIMIT
26.1 kΩ, RIMON = 13 kΩ, -40°C ≤TJ
≤150°C
=
Current limit voltage buck regulator
control loop
(VCSP –VCSN/
19
22.5
26
mV
)
OUT
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE EXTERNAL NFET CURRENT LIMITING
VCSN = 5 V, RSET = 300 Ω, RILIMIT
6.8 kΩ, RIMON = 13 kΩ, -40°C ≤TJ
≤125°C
=
(VCSP –VCSN/
Current limit voltage NFET control loop
Current limit voltage NFET control loop
Current limit voltage NFET control loop
Current limit voltage NFET control loop
40
38.5
18
43
43
21
21
46
47.5
24
mV
mV
mV
mV
)
OUT
VCSN = 5 V, RSET = 300 Ω, RILIMIT
6.8 kΩ, RIMON = 13 kΩ, -40°C ≤TJ
≤150°C
=
(VCSP –VCSN/
)
OUT
VCSN = 5 V, RSET = 300 Ω, RILIMIT
13.7 kΩ, RIMON = 13 kΩ, -40°C ≤TJ
≤125°C
=
(VCSP –VCSN/
)
OUT
VCSN = 5 V, RSET = 300 Ω, RILIMIT
13.7 kΩ, RIMON = 13 kΩ, -40°C ≤TJ
≤150°C
=
(VCSP –VCSN/
17
25
)
OUT
CURRENT LIMIT - BUCK REGULATOR PEAK CURRENT LIMIT
IL-SC-HS
IL-SC-LS
IL-NEG-LS
High-side current limit
4.6
3.5
5.4
4
6.2
4.5
A
A
A
Low-side current limit
Low-side negative current limit
–3.1
–2.1
–1.3
CABLE COMPENSATION VOLTAGE
(VCSP –VCSN) = 46 mV, RSET = 300
Ω, RILIMIT = 13 kΩ, RIMON = 13 kΩ
VIMON
VIMON
VIMON
Cable compensation voltage
0.935
0.435
1
0.5
1.8
1.065
0.565
V
V
V
(VCSP –VCSN) = 23 mV, RSET = 300
Ω, RILIMIT = 13 kΩ, RIMON = 13 kΩ
Cable compensation voltage
Cable compensation voltage (internal (VCSP –VCSN) = 46 mV, RSET = 300
clamp)
Ω, RILIMIT = 13 kΩ, RIMON = open
BUCK OUTPUT VOLTAGE (CSN/OUT PIN)
INT pulldown resistance = 5.1kΩ,
RIMON = 0 Ω, RILIMIT = 0 Ω
VCSN/OUT
Output voltage
5.05
5.10
5.15
1
V
INT pulldown resistance = 5.1kΩ,
RIMON = 0 Ω, RILIMIT = 0 Ω
VCSN/OUT
Output voltage accuracy
%
–1
Overvoltage level on CSN/OUT pin
which buck regulator stops switching
VCSN/OUT_OV
VCSN/OUT rising
7.1
7.5
500
2
7.9
V
mV
V
VCSN/OUT_OV_HYS Hysteresis
CSN / OUT pin voltage required to
trigger short circuit hiccup mode
VHC
VIN = VOUT + VDROP, VOUT = 5.1V,
IOUT = 3A
VDROP
Dropout voltage ( VIN-VOUT
)
150
mV
BUCK REGULATOR INTERNAL RESISTANCE
RDS-ON-HS
RDS-ON-HS
RDS-ON-HS
RDS-ON-LS
RDS-ON-LS
RDS-ON-LS
High-side MOSFET ON-resistance
High-side MOSFET ON-resistance
High-side MOSFET ON-resistance
Low-side MOSFET ON-resistance
Low-side MOSFET ON-resistance
Low-side MOSFET ON-resistance
Load = 3 A, TJ = 25°C
40
40
40
35
35
35
45
68
75
41
60
68
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
Load = 3 A, -40°C ≤TJ ≤125°C
Load = 3 A, -40°C ≤TJ ≤150°C
Load = 3 A, TJ = 25C
Load = 3 A, -40°C ≤TJ ≤125°C
Load = 3 A, -40°C ≤TJ ≤150°C
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8.5 Electrical Characteristics (continued)
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS
=
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ωunless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
NFET GATE DRIVE (LS_GD PIN)
VCSN/OUT = 5.1 V, CG = 1000 pF (see
图9-2)
VLS_GD
NFET gate drive output voltage
9.5
11
12.5
V
ILS_DR_SRC
ILS_DR_SNK
NFET gate drive output source current VCSN/OUT = 5.1 V, CG = 1000 pF
2
3
4
µA
µA
NFET gate drive output sink current
VCSN/OUT = 5.1 V, CG = 1000 pF
VCSN/OUT rising
20
35
50
VCSN/OUT rising threshold for LS_GD
operation
VLS_GD_UVLO_R
2.85
3
3.15
V
VLS_GD_UVLO_HYS Hysteresis
80
mV
BUS DISCHARGE (BUS PIN)
Rising threshold for BUS pin
overvoltage protection
VBUS_OV
VBUS rising
6.6
7
7.3
V
VBUS_OV_HYS
RBUS_DCHG_18V
RBUS_DCHG_8V
FAULT, BUCK_ST
VOL
Hysteresis
180
29
mV
kΩ
kΩ
Discharge resistance for BUS
Discharge resistance for BUS
VBUS = 18V, measure leakage current
VBUS = 8V, measure leakage current
35
FAULT Output low voltage
FAULT Off-state leakage
ISNK_PIN = 0.5 mA
VPIN = 5.5 V
250
1
mV
µA
IOFF
VOL
BUCK_ST Output low voltage
BUCK_ST Off-state leakage
ISNK_PIN = 0.5 mA
VPIN = 5.5 V
250
1
mV
µA
IOFF
CTRL1, CTRL2 - LOGIC INPUTS
VIH
VIL
Rising threshold voltage
1.48
1.30
180
2
V
V
Falling threshold voltage
Hysteresis
0.85
VHYS
IIN
mV
µA
Input current
1
–1
DP_IN AND DM_IN OVERVOLTAGE PROTECTION
Rising threshold for Dx_IN overvoltage
VDx_IN_OV
protection
DP_IN or DM_IN rising
3.7
3.9
100
94
4.15
V
Hysteresis
mV
kΩ
VDx_IN = 18V, measure leakage
current
RDx_IN_DCHG_18V
RDx_IN_DCHG_5V
Discharge resistance for Dx_IN
Discharge resistance for Dx_IN
VDx_IN = 5V, measure leakage
current
416
kΩ
HIGH-BANDWIDTH ANALOG SWITCH
VDP_OUT = VDM_OUT = 0 V, IDP_IN
IDM_IN = 30 mA
=
RDS_ON
DP and DM switch on-resistance
DP and DM switch on-resistance
3.4
4.3
6.3
7.7
Ω
Ω
Ω
Ω
pF
pF
VDP_OUT = VDM_OUT = 2.4 V, IDP_IN
IDM_IN = –15 mA
=
=
RDS_ON
Switch resistance mismatch between VDP_OUT = VDM_OUT = 0 V, IDP_IN
=
0.05
0.05
6.7
0.15
0.15
|ΔRDS_ON
|ΔRDS_ON
CIO_OFF
CIO_ON
|
DP and DM channels
IDM_IN = 30 mA
VDP_OUT = VDM_OUT = 2.4 V, IDP_IN
IDM_IN = –15 mA
Switch resistance mismatch between
DP and DM channels
|
VEN = 0 V, VDP_IN = VDM_IN = 0.3 V,
Vac = 0.03 VPP , f = 1 MHz
DP/DM switch off-state capacitance
DP/DM switch on-state capacitance
VDP_IN = VDM_IN = 0.3 V, Vac = 0.03
VPP, f = 1 MHz
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8.5 Electrical Characteristics (continued)
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS
=
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ωunless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OIRR
Off-state isolation
VEN = 0 V, f = 250 MHz
9
dB
dB
XTALK
On-state cross-channel isolation
f = 250 MHz
29
VEN = 0 V, VDP_IN = VDM_IN = 3.6 V,
VDP_OUT = VDM_OUT = 0 V,
measure IDP_OUT and IDM_OUT
Off-state leakage current, DP_OUT
and DM_OUT
Ilkg(OFF)
0.1
1.5
µA
BW
800
MHz
Bandwidth (–3 dB)
RL = 50 Ω
CHARGING DOWNSTREAM PORT (CDP) DETECT
VDP_IN = 0.6 V, –250 µA < IDM_IN < 0
µA
VDM_SRC
DM_IN CDP output voltage
0.5
0.6
0.7
0.4
V
DP_IN rising lower window threshold
for VDM_SRC activation
VDAT_REF
VDAT_REF
VLGC_SRC
0.36
0.38
50
V
mV
V
Hysteresis
DP_IN rising upper window threshold
for VDM_SRC deactivation
0.8
40
0.84
0.88
100
VLGC_SRC_HYS
IDP_SINK
Hysteresis
100
70
mV
µA
DP_IN sink current
VDP_IN = 0.6 V
RT/SYNC THRESHOLD (RT/SYNC PIN)
RT/SYNC high threshold for external
Amplitude of SYNC clock AC signal
(measured at SYNC pin)
VIH_RT/SYNC
3.5
V
V
clock synchronization
RT/SYNC low threshold for external
clock synchronization
Amplitude of SYNC clock AC signal
(measured at SYNC pin)
VIL_RT/SYNC
0.8
THERMAL SHUTDOWN
Shutdown threshold
Recovery threshold
160
140
°C
°C
TSD
Thermal shutdown
8.6 Timing Requirements
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS
=
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ωunless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
MIN NOM MAX UNIT
SYNC (RT/SYNC PIN) WITH EXTERNAL CLOCK
Switching frequency using external clock on
RT/SYNC pin
fSYNC
300
2300 kHz
fSYNC = 400 kHz, VRT/SYNC > VIH_RT/SYNC
VRT/SYNC < VIL_RT/SYNC
,
TSYNC_MIN
TLOCK_IN
Minimum SYNC input pulse width
PLL lock time
100
100
ns
µs
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8.7 Switching Characteristics
Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS
=
15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ωunless otherwise stated. Minimum and maximum limits are specified
through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SOFT START
TSS
The time of internal reference to
increase from 0 V to 1.0 V
Internal soft-start time
3
5
7
ms
HICCUP MODE
NOC
Number of cycles that LS current limit
is tripped to enter Hiccup mode
128
118
Cycles
ms
TOC
Hiccup retry delay time
SW (SW PIN)
TON_MIN
Minimum turnon-time
105
7.5
ns
µs
Maximum turnon-time, HS timeout in
dropout
TON_MAX
TOFF_MIN
Dmax
Minimum turnoff time
80
98
ns
%
Maximum switch duty cycle
TIMING RESISTOR AND INTERNAL CLOCK
Switching frequency range using RT
fSW_RANGE
300
2300
kHz
mode
Switching frequency
Switching frequency
360
400
440
kHz
kHz
RT = 49.9 kΩ
RT = 8.87 kΩ
fSW
1953
2100
2247
Frequency span of spread spectrum
operation
FSSS
±6
%
NFET DRIVER
VOUT = 5.1 V, NFET = CSD87502Q2,
time from LS_GD 10% to 90%
tr
VLS_DR rise time
VLS_DR fall time
1000
100
µs
µs
VOUT = 5.1 V, NFET = CSD87502Q2,
time from LS_GD time 90% to 10%
tf
CURRENT LIMIT - EXTERNAL NFET CONNECTED BETWEEN CSN/OUT AND BUS, LS_GD CONNECTED TO FET GATE
tOC_HIC_ON
tOC_HIC_OFF
ON-time during hiccup mode
OFF-time during hiccup mode
2
ms
ms
263
FAULT DUE TO VBUS OC, VBUS OV, DP OV, DM OV
tDEGLA
Asserting deglitch time
5.5
5.5
8.2
8.2
11.5
11.5
ms
ms
tDEGLD
De-asserting deglitch time
BUCK_ST
tDEGLA
Asserting deglitch time
88
150
220
ms
HIGH-BANDWIDTH ANALOG SWITCH
tpd
Analog switch propagation delay
Analog switch skew between opposite
transitions of the same port (tPHL
tPLH
0.14
0.02
ns
ns
tSK
–
)
DP_IN and DM_IN overvoltage
protection response time
tOV_Dn
2
µs
Deglitch time from Vcc > 4V to DP /
DM data switch turn on
tST_DEG_Dn
88
150
220
ms
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8.8 Typical Characteristics
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
717
714
711
708
705
702
699
696
32
28
24
20
16
12
8
-40C
25C
125C
150C
-40C
25C
150C
4
0
4
8
12
16
Input Voltage (V)
20
24
28
32
36
40
0
4
8
12
16
Input Voltage (V)
20
24
28
32
36
40
D001
D003
VCSN = 8 V
图8-1. Non-Switching Quiescent Current
EN = 0 V
图8-2. Shutdown Quiescent Current
INT = 5.1 kΩ
1.225
1.2
3.9
3.75
3.6
UP
DN
UP
DN
1.175
1.15
1.125
1.1
3.45
3.3
3.15
3
1.075
1.05
2.85
-50
-25
0
25
Temperature (C)
50
75
100
125
150
-60
-30
0
30
Temperature (C)
60
90
120
150
180
D004
D005
图8-3. Precision Enable Threshold
图8-4. VIN UVLO Threshold
5.1
5.07
5.04
5.01
4.98
4.95
4.92
4.89
5.16
5.14
5.12
5.1
-40C
25C
125C
150C
Vin = 6V
Vin = 13.5V
Vin = 36V
5.08
5.06
5.04
0
4
8
12
16
Input Voltage (V)
20
24
28
32
36
40
-50
-25
0
25
Temperature (C)
50
75
100
125
150
D005
D006
图8-5. VCC vs Input Voltage
RIMON = 0 Ω
图8-6. VCSN/OUT Voltage vs Junction Temperature
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8.8 Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
6.2
6
80
72
64
56
48
40
32
24
-40C
25C
150C
5.8
5.6
5.4
5.2
5
Vin = 6V
Vin = 13.5V
Vin = 36V
4.8
0
4
8
12
16
Input Voltage (V)
20
24
28
32
36
40
-50
-25
0
25
Temperature (C)
50
75
100
125
150
D006
D008
图8-7. High-side Current Limit vs Input Voltage
图8-8. High-side MOSFET on Resistance vs Junction
Temperature
60
55
50
45
40
35
30
25
420
414
408
402
396
390
384
378
Vin = 6V
Vin = 13.5V
Vin = 36V
-50
-25
0
25
Temperature (C)
50
75
100
125
150
-50
-25
0
25
Temperature (C)
50
75
100
125
150
D009
D010
图8-9. Low-side MOSFET on Resistance vs Junction
RT = 49.9 kΩ
Temperature
图8-10. Switching Frequency vs Junction Temperature
2400
4.2
1A
2A
3A
Rlimit = 13kW
Rlimit = 26.1kW
2100
1800
1500
1200
900
3.6
3
2.4
1.8
1.2
0.6
0
600
300
0
5
10
15
20
Input voltage (V)
25
30
35
40
-50
-25
0
25
Temperature (C)
50
75
100
125
150
D011
D012
RT = 8.87 kΩ
图8-11. Switching Frequency vs VIN Voltage
RSNS = 15 mΩ
RSET = 300 Ω
图8-12. Buck Average Current Limit vs Junction Temperature
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8.8 Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
4.2
3.6
3
4.8
4.4
4
Rlimit = 6.8kW
Rlimit = 13.7kW
Vin = 6V
Vin = 13.5V
Vin = 36V
2.4
1.8
1.2
0.6
0
3.6
3.2
2.8
2.4
2
-50
-25
0
25
50
75
Temperature (C)
100
125
150
-50
-25
0
25
50
75
Temperature (C)
100
125
150
D013
D013
图8-14. LS_GD Gate Source Current vs Junction Temperature
RSNS = 15 mΩ
RSET = 300 Ω
图8-13. External FET Current Limit vs Junction Temperature
13
1.35
Vin = 6V
Vin = 13.5V
Vin = 36V
Load Current = 3 A
Load Current = 1.5 A
12.5
12
1.2
1.05
0.9
11.5
11
0.75
0.6
10.5
10
0.45
0.3
9.5
-50
-25
0
25
50
75
Temperature (C)
100
125
150
-50
-25
0
25
50
75
Temperature (C)
100
125
150
D013
D014
VCSN/OUT = 5.1 V
RIMON = 0 kΩ
RSNS = 15 mΩ
RSET = 300 Ω
RIMON = 13 kΩ
图8-15. LS_GD Gate Voltage vs Junction Temperature
图8-16. Cable Compensation Voltage vs Junction Temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
7.5
7.35
7.2
7.05
6.9
6.75
6.6
6.45
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Load Current (A)
3
-50
-25
0
25
50
75
Temperature (C)
100
125
150
D014
D016
图8-18. VBUS Overvoltage Protection Threshold vs Junction
RSNS = 15 mΩ
RSET = 300 Ω
RIMON = 13 kΩ
Temperature
图8-17. Cable Compensation Voltage vs Load Current
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8.8 Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
4.3
4.2
4.1
4
4.3
4.2
4.1
4
3.9
3.8
3.7
3.6
3.9
3.8
3.7
3.6
-50
-25
0
25
Temperature (C)
50
75
100
125
150
-50
-25
0
25
Temperature (C)
50
75
100
125
150
D017
D018
图8-19. DP_IN Overvoltage Protection Threshold vs Junction
图8-20. DM_IN Overvoltage Protection Threshold vs Junction
Temperature
Temperature
Measured on TPS25830-Q1 EVM with 10-cm cable
Measured source with 10-cm cable
图8-22. Through the TPS2584x-Q1 Data Switch
图8-21. Bypassing the TPS2584x-Q1 Data Switch
图8-23. Data Transmission Characteristics vs Frequency
图8-24. Off-state Data-Switch Isolation vs Frequency
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8.8 Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
图8-25. On-state Cross-channel Isolation vs Frequency
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9 Parameter Measurement Information
IOS
90%
tr
tf
VLS_GD
I(OUT)
10%
t(IOS)
图9-2. NFET Gate Drive Rise and Fall Time
图9-1. Short-Circuit Parameters
0.5m AWG28
0.5m AWG28
0.5m AWG28
10cm AWG18
Manually Hot-short
PSIL079
18V
OUT
DP_IN
DM_IN
27 mF
35V
GND
GND
图9-3. Short-to-Battery System Test Setup
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10 Detailed Description
10.1 Overview
The TPS2584x-Q1 devices are full-featured solutions for implementing a compact USB charging port with
support for Type-A BC1.2 standards. Both devices contain an efficient 36-V buck regulator power source
capable of providing up to 3.5 A of output current at 5.10 V (nominal). System designers can optimize efficiency
or solution size through careful selection of switching frequency over the range of 300 to 2200 kHz with sufficient
margin to operate above or below the AM radio frequency band. In all versions the buck regulator operates in
forced PWM mode ensuring fixed switching frequency regardless of load current. Spread-spectrum feature aid
reducing harmonic peaks of the switching frequency potentially simplifying EMI filter design and easing
compliance.
Current sensing via a precision high-side current sense amplifier enables an accurate, user programmable
overcurrent limit setting; and programmable linear cable compensation to overcome IR losses when powering
remote USB ports.
The CTRL1 and CTRL2 pins set the operating mode for the TPS2584x-Q1 device. The device can support CDP,
SDP or Client configurations.
The TPS25840-Q1 integrates high band-width (800 MHz) USB switches, includes short to VBAT and short to
VBUS protection as well as IEC61000-4-2 electrostatic discharge clamps to protect the host from potentially
damaging overvoltage conditions.
The TPS25842-Q1 integrates high band-width (800 MHz) USB switches, includes short to VBUS protection as
well as IEC61000-4-2 electrostatic discharge clamps, but does not support short to VBAT protection.
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10.2 Functional Block Diagram
10.3 Feature Description
10.3.1 Buck Regulator
The following operating description of the TPS2584x-Q1 refers to the Functional Block Diagram and the
waveforms in 图 10-1. TPS2584x-Q1 is a step-down synchronous buck regulator with integrated high-side (HS)
and low-side (LS) switches (synchronous rectifier). The TPS2584x-Q1 supplies a regulated output voltage by
turning on the HS and LS NMOS switches with controlled duty cycle. During high-side switch ON time, the SW
pin voltage swings up to approximately VIN, and the inductor current iL increase with linear slope (VIN – VOUT) /
L. When the HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot-through
dead time. Inductor current discharges through the LS switch with a slope of –VOUT / L. The control parameter
of a buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side switch ON time and TSW is
the switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle
D. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage: D = VOUT / VIN.
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VSW
VIN
D = tON/ TSW
tON
tOFF
t
0
-VD
TSW
iL
ILPK
IOUT
DiL
t
0
图10-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The TPS2584x-Q1 employs fixed frequency peak current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, makes it easy to design, and provides stable operation with almost any combination of
output capacitors. TPS2584x-Q1 operates in FPWM mode for low output voltage ripple, tight output voltage
regulation, and constant switching frequency.
10.3.2 Enable/UVLO
The voltage on the EN/UVLO pin controls the ON or OFF operation of TPS2584x-Q1. An EN/UVLO pin voltage
higher than VEN/UVLO-VOUT-H is required to start the internal regulator (Assume 5.1-k pull down resister on INT
pin). The EN/UVLO pin is an input and can not be left open or floating. The simplest way to enable the operation
of the TPS2584x-Q1 is to connect the EN to VIN. This action allows self-start-up of the TPS2584x-Q1 when VIN
is within the operation range.
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EN
VEN/UVLO-H
VEN/UVLO-H œ VEN/UVLO-HYS
VEN-VCC-H
VEN-VCC-L
VCC
5V
0
VCSN/OUT
VCSN/OUT
0
图10-2. Precision Enable Behavior
Many applications benefit from the employment of an enable divider RENT and RENB (图 10-3) to establish a
precision system UVLO level for the TPS2584x-Q1. System UVLO can be used for sequencing, ensuring reliable
operation, or supply protection, such as a battery discharge level. To ensure the USB port VBUS is within the 5-V
operating range as required for USB compliance (for the latest USB specifications and requirements, refer to
USB.org), TI suggests that the RENT and RENB resistors be chosen such that the TPS2584x-Q1 enables when
VIN is approximately 6 V. Considering the drop out voltage of the buck regulator and IR loses in the system, 6 V
provides adequate margin to maintain VBUS within USB specifications. If system requirements such as a warm
crank (start) automotive scenario require operation with VIN < 6 V, the values of RENT and RENB can be
calculated assuming a lower VIN. An external logic signal can also be used to drive EN/UVLO input when a
microcontroller is present and it is desirable to enable or disable the USB port remotely for other reasons.
IN
RENT
EN
RENB
图10-3. System UVLO by Enable Divider
UVLO configuration using external resistors is governed by the following equations:
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(1)
(2)
Example:
VIN(ON) = 6 V (user choice)
RENB = 5 kΩ(user choice)
RENT = [(VIN(ON) / VEN/UVLO_H) –1] × RENB= 19.6 kΩ. Choose standard 20 kΩ.
Therefore, VIN(OFF) = 6 V × [1 –(0.09 V / 1.2 V)] = 5.55 V
A typical start-up waveform is shown in 图10-4. The rise time of DCDC VBUS voltage is about 5 ms.
EN,
5V/Div
VIN
5V/Div
VBUS,
5V/Div
VCC,
5V/Div
40ms/Div
图10-4. Typical Start-up Behavior, VIN = 13.5 V, RIMON = 12.6 kΩ
For TPS2584x-Q1, the pin voltage must meet the requirement below during startup. See 图10-5.
• VBUS < 0.8 V (typical)
• VDX_OUT < 2.2 V (typical)
• VDX_IN < 1.5 V (typical)
After the 150-ms deglitch time, no additional requirement on these pins. In real application, BUCK_ST pin can be
used to configure the timing sequence.
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VIN
EN
VCC
Dx_OUT
Must < 2.2V
5}v[š ꢀꢁŒꢂ
VBUS must < 0.8V
VBUS
deglitch time
150ms (typ)
DP/DM
ON
Date Switch
OFF
BUCK_ST
图10-5. TPS2584x-Q1 Pin Voltage Requirement During Startup
10.3.3 Switching Frequency and Synchronization (RT/SYNC)
The switching frequency of the TPS2584x-Q1 can be programmed by the resistor RT from the RT/SYNC pin and
GND pin. Use Equation 3 to determine the RT resistance for a given switching frequency.
-1.0483
RFREQ kW = 26660ì ƒ
kHz
SW
(3)
70
65
60
55
50
45
40
35
30
25
20
15
10
5
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Switching Frequency (kHz)
D024
图10-6. RT Set Resistor vs Switching Frequency
表10-1 lists typical RT resistors values.
表10-1. Setting the Switching Frequency With RT
SWITCHING FREQUENCY (kHz)
RT (kΩ)
68.1
300
400
49.9
39.2
500
19.1
1000
1500
2000
2100
12.4
9.31
8.87
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表10-1. Setting the Switching Frequency With RT (continued)
SWITCHING FREQUENCY (kHz)
RT (kΩ)
8.45
2200
TPS2584x-Q1 switching action can be synchronized to an external clock from 300 kHz to 2.3 MHz. The RT/
SYNC pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be
synchronized by AC coupling a positive edge into the RT/SYNC pin. The AC coupled peak-to-peak voltage at the
RT/SYNC pin must exceed the SYNC amplitude threshold of 3.5 V (typical) to trip the internal synchronization
pulse detector, and the minimum SYNC clock ON and OFF time must be longer than 100 ns (typical). When
using a low impedance signal source, the frequency setting resistor, RT, is connected in parallel with an AC
coupling capacitor, CCOUP, to a termination resistor, RTERM (for example: 50 Ω). The two resistors in series
provide the default frequency setting resistance when the signal source is turned off. A 10-pF ceramic capacitor
can be used for CCOUP. 图10-7 show the device synchronized to an external clock.
CCOUP
RT
PLL
PLL
Lo-Z
Clock
Hi-Z
Clock
Source
RTERM
RT
RT/SYNC
RT/SYNC
Source
图10-7. Synchronize to External Clock
To avoid AM radio frequency brand and maintain proper regulation when minimum ON-time or minimum OFF-
time is reached, the TPS2584x-Q1 implement frequency foldback scheme depends on VIN voltage. Refer to
Figure 8-10.
• When 8 V < VIN ≤19 V, the switching frequency of TPS2584x-Q1 is determined by RT resistor or external
sync clock.
• When VIN ≤8 V, the switching frequency of TPS2584x-Q1 is set to default 420 kHz, regardless of RT
resistor setting or external sync clock.
• When VIN > 19 V, the switching frequency of TPS2584x-Q1 is set to default 420 kHz, regardless of RT
resistor setting or external sync clock.
figure 10-8, figure 10-9 and Figure 10-10 show the device switching frequency and behavior under different VIN
voltage and RT = 8.87 kΩ.
Figure 10-11, Figure 10-12 and Figure 10-13 show the device switching frequency and behavior under different
VIN voltage and synchronized to an external 2.1-M system clock.
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VIN,
10V/Div
VIN,
10V/Div
SW,
10V/Div
SW,
10V/Div
Inductor Current,
5A/Div
Inductor Current,
5A/Div
1us/Div
1us/Div
VIN = 7.5 V
L = 2.2 uH
ILOAD = 3 A
VIN = 13.5 V
L = 2.2 uH
ILOAD = 3 A
图10-8. Switching Frequency When RT = 8.87 kΩ 图10-9. Switching Frequency When RT = 8.87 kΩ
VIN, 5V/Div
VIN,
10V/Div
SW,
10V/Div
Sync, 2V/Div
SW,
5V/Div
Inductor Current,
5A/Div
Inductor Current,
2A/Div
1us/Div
1us/Div
VIN = 20 V
L = 2.2 uH
ILOAD = 3 A
VIN = 7.5 V
L = 2.2 uH
ILOAD = 3 A
图10-10. Switching Frequency When RT = 8.87 kΩ 图10-11. Synchronizing to External 2.1-MHz Clock
VIN, 10V/Div
VIN, 5V/Div
Sync, 2V/Div
Sync, 2V/Div
SW,
10V/Div
SW,
10V/Div
Inductor Current,
2A/Div
Inductor Current,
2A/Div
1us/Div
1us/Div
VIN = 20 V
L = 2.2 uH
ILOAD = 3 A
VIN = 13.5 V
L = 2.2 uH
ILOAD = 3 A
图10-13. Synchronizing to External 2.1-MHz Clock
图10-12. Synchronizing to External 2.1-MHz Clock
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10.3.4 Spread-Spectrum Operation
To reduce EMI, the TPS2584x-Q1 introduce frequency spread spectrum. The spread spectrum is used to
eliminate peak emissions at specific frequencies by spreading emissions across a wider range of frequencies
than a part with fixed frequency operation. In most systems, low frequency conducted emissions from the first
few harmonics of the switching frequency can be easily filtered. A more difficult design criterion is reduction of
emissions at higher harmonics which fall in the FM band. These harmonics often couple to the environment
through electric fields around the switch node. The TPS2584x-Q1 devices use ±6% spread of switching
frequencies with 1/256 swing frequency.
The spread spectrum function is only available when using the TPS2584x-Q1 internal oscillator. If the RT/SYNC
pin is synchronized to an external clock, the spread spectrum function turns off.
10.3.5 VCC, VCC_UVLO
The TPS2584x-Q1 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The
nominal voltage for VCC is 5 V. The VCC pin is the output of an LDO and must be properly bypassed. A high
quality ceramic capacitor with a value of 2.2 µF to 4.7 µF, 10 V or higher rated voltage must be placed as close
as possible to VCC and grounded to the PGND ground pin. The VCC output pin must not be loaded with more
than 5 mA, or shorted to ground during operation. Shorting VCC to ground during operation can cause damage to
the TPS2584x-Q1.
10.3.6 Minimum ON-time, Minimum OFF-time
Minimum ON-time, TON_MIN, is the smallest duration of time that the HS switch can be on. TON_MIN is typically
105 ns in the TPS2584x-Q1. Minimum OFF-time, TOFF_MIN, is the smallest duration that the HS switch can be
off. TOFF_MIN is typically 80 ns in the TPS2584x-Q1. In CCM (FPWM) operation, TON_MIN and TOFF_MIN limit the
voltage conversion range given a selected switching frequency.
The minimum duty cycle allowed is:
(4)
And the maximum duty cycle allowed is:
(5)
Given fixed TON_MIN and TOFF_MIN, the higher the switching frequency the narrower the range of the allowed duty
cycle.
10.3.7 Internal Compensation
The TPS2584x-Q1 is internally compensated as shown in 图10-14. The internal compensation is designed such
that the loop response is stable over the specified operating frequency and output voltage range. The
TPS2584x-Q1 is optimized for transient response over the range 300 kHz ≤fsw ≤2300 kHz.
10.3.8 Bootstrap Voltage (BOOT)
The TPS2584x-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is
0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or
higher for stable performance overtemperature and voltage.
10.3.9 RSNS, RSET, RILIMIT and RIMON
The programmable current limit threshold and full-scale cable compensation voltage are determined by the
values of the RSNS, RSET, RILIMIT and RIMON resistors. Refer to 图10-14.
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• RSNS is the current sense resistor. The recommended voltage across RSNS under current limit must be
approximately 50 mV as a compromise between accuracy and power dissipation. For example, if current
limiting is desired for IOUT(MAX) ≥3.3 A, then RSNS = 0.05 V / 3.3 A = 0.01515 Ω. Choose a standard value of
15 mΩ.
• RSET determines the input current to the transconductance amplifier and current mirror. The amplifier
balances the voltage to be equal to that across RSNS. Choose a RSET value to produce an ISET current
between 75–180 µA at the desired IOUT(MAX). Considering 50 mV across RSET, a value of 300 Ωprovides
approximately 166 µA of ISET current to the amplifier and mirror circuit. Care must be taken to limit the ISET
current below 200 µA to avoid saturating the internal amplifier circuit.
• RILIMIT in conjuction with the 0.5 × ISET current produces a voltage on the ILIMIT pin which is proportional to
the load current flowing in RSNS. For details on setting the current limit, see Current Limit Sensing Using
RILIMIT
.
• RIMON in conjuction with the 0.5 × ISET current produces a voltage on the IMON pin which is proportional to
the load current flowing in RSNS. For details on setting the current limit, see Cable Compensation.
(1): VSNS = ILOAD x RSNS
ILOAD
(2): VSNS ~= VSET
(by op amp)
(3): ISET = VSET / RSET = VSNS / RSET
RSNS
+ 50mV -
RSET
CSP
CSN/OUT
RT
RM
RB
+
Low Offset
Amp
œ
IMON
ILIMIT
IIMON = 0.5 x ISET
ISET
+
RIMON
œ
RS = RT
IILIMIT = 0.5 x ISET
RILIMIT
œ
+
1V
Soft
Start
œ
+
+
VCOMP
1V
VILIMIT = 1V (current limit by Buck)
VILIMIT = 0.49V (current limit by NFET)
LS_GD
œ
+
0.49V
BUS
图10-14. Current Limit and Cable Compensation Circuit
10.3.10 Overcurrent and Short Circuit Protection
For maximum versatility, TPS2584x-Q1 includes both a precision, programmable current limit as well cycle-by-
cycle current limit to protect the USB port from extreme overload conditions. In most applications, the RILIMIT
resistor in conjunction with the selection of RSNS and RSET determines the overload threshold. The cycle-by-
cycle current limit serves as a backup means of protection in the event RILMIT is shorted to ground, disabling the
programmable current limit function.
In some applications, the setting of TPS2584x-Q1 over-current need meets MFi requirement. For more details,
please refer to the How to Pass MFi Overcurrent Protection Test With USB Charger and Switch Device
application report.
10.3.10.1 Current Limit Setting using RILIMIT
Refer to 图10-14. The TPS2584x-Q1 can establish current limit by two methods.
• Using external a single or back-to-back N-Channel MOFETs between CSN/OUT and BUS: a voltage of 0.49
V on the ILIMIT pin initiates current limiting using the external MOSFET by decreasing the LS_GD voltage
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causing the FET to operate in the saturation region. To protect the MOSFETs from damage a hiccup timer
limits the duty cycle to prevent thermal runaway. Refer to the Specifications for MOSFET hiccup timing.
• Buck average current limit: no MOSFET, CSN/OUT connected to BUS. The LS_GD must be pulled up
through a 2.2-kΩresistor. In this configuration, a voltage of 1 V across RILIMIT on the ILIMIT pin initiates
average current limiting of the buck regulator.
The 2-level current limit is described below:
• With external MOSFET 图10-15:
– Isolating a fault on the USB port from other loads connected to the CSP output of the TPS2584x-Q1. In
some applications, it can be useful to power additional circuitry (for example: USB HUB) from the output of
the TPS2584x-Q1 and maintain operation of these circuits in the event of a short circuit downstream of the
BUS pin. To prevent triggering the MOSFET current limit below the programmed ILIMIT threshold, external
circuits must be supplied after the inductor and before the current sense resistor, RSNS
.
– After RSNS and RSET are determined and the full load ISET current is known, the resistor value, RILIMIT, can
be determined by:
(6)
– In most cases, the recommended voltage across RSNS under current limit must be approximately 50 mV
as a compromise between accuracy and power dissipation. While in some application, RILIMIT is the only
resistor that can be changed to achieve different current limit. Typical RILIMIT resistors value are listed in 表
10-2 given the condition RSNS = 15 mΩand RSET = 300 Ω
表10-2. Setting the Current Limit with RILIMIT
RILIMIT (kΩ)
Current-Limit Threshold (mA)
With External MOSFET
Without External MOSFET
700
26.1
12.7
11.3
7.15
6.49
5.62
5.11
53.6
26.1
22.6
14.7
13
1500
1700
2700
3000
3400
3800
11.5
10.5
• Buck Average Current Limit 图10-16:
1. CSN/OUT connected directly to BUS, LS_GD must be pulled up through 2.2-kΩresistor. The TPS2584x-
Q1 can operate as a stand-alone USB charging port. In this configuration, the internal buck regulator
operates with average current limiting as programmed by the ILIMIT pin, potentially producing less heat
compared to N-channel MOSFET current limiting
2. After RSNS and RSET are determined and the full load ISET current is known, the resistor value RILIMIT can
be determined by:
(7)
3. 表10-2 lists Typical RILIMIT resistors values given the condition RSNS = 15 mΩand RSET = 300 Ω.
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CBOOT
CBOOT
To auxillary
loads
VIN
VIN
BOOT
BOOT
L
L
RSNS
IN
RSNS
IN
SW
RSET
EN/UVLO
RT/SYNC
EN/UVLO
RT/SYNC
CSP
RSET
CSP
CSN/OUT
CSN/OUT
VCC
VCC
TPS2584x-Q1
TPS2584x-Q1
2.2kΩ
LS_GD
FAULT
BUCK_ST
CTRL1
FAULT
LS_GD
BUS
BUCK_ST
CTRL1
BUS
CTRL2
CTRL2
DP_OUT
DM_OUT
DP_IN
DM_IN
DP_OUT
DM_OUT
DP_IN
DM_IN
INT
IMON ILIMIT
AGND PGND
INT
IMON ILIMIT
AGND PGND
图10-16. Buck Average Current Limit
图10-15. Current Limit With External MOSFET
10.3.10.2 Buck Average Current Limit Design Example
To start the procedure, the ILOAD(MAX), RSNS and RSET, must be known.
1. Determine ILIMIT, usually chose ILIMIT= ILOAD(MAX) / (1 –10%).
2. Determine RSNS to achieve 50 mV at current limit. For 3-A load current, choose ILIMIT = 3.3A. RSNS = (0.05
V / 3.3 A) = 15 mΩ.
3. Choose RSET = 300 Ω
4. According to 方程式7, RLIMIT = 300 / (0.5 × ( 3.3 X 0.015 + 0.0007)) = 11.95 kΩ.
5. Choose standard 11.8 kΩ.
10.3.10.3 External MOSFET Gate Drivers
The TPS2584x-Q1 has integrated NFET gate drivers, and can support current limit with external NFET. Refer to
图10-15.
The LS_GD pin of TPS2584x-Q1 can source 3-uA (typical) current to enhance the external MOSFET. A 6.2-V
clamp between LS_GD and CSN/OUT pin limits the gate-to-source voltage. During DCDC start up, the LS_GD
gate drivers begin to source current after VCSN/OUT reach 3 V. If the VCSN/OUT > 7.5 V or VBUS > 7 V is under
overvoltage condition, the LS_GD turns off immediately with 35-uA (typical) sink current.
If load current above NFET current limit threshold, LS_GD also turns off the NFET after 2 ms (typical) and enters
hiccup mode to protect NFET from thermal issue. Refer to Figure 11-24 for application waveform.
In real application, if VBUS short to VBAT function is needed, 20 V back-to-back NFET is suggested in circuit
design.
10.3.10.4 Cycle-by-Cycle Buck Current Limit
The buck regulator cycle-by-cycle current limit on both the peak and valley of the inductor current. Hiccup mode
is activated if a fault condition persists to prevent over-heating.
High-side MOSFET overcurrent protection is implemented by the nature of the Peak Current Mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. for more
details, refer to the Functional Block Diagram. The peak current of HS switch is limited by a clamped maximum
peak current threshold IHS_LIMIT which is constant. So the peak current limit of the high-side switch is not affected
by the slope compensation and remains constant over the full duty cycle range.
The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor
current begins to ramp down. The LS switch is not turned OFF at the end of a switching cycle if its current is
above the LS current limit ILS_LIMIT. The LS switch is kept ON so that the inductor current keeps ramping down,
until the inductor current ramps below the LS current limit ILS_LIMIT. Then the LS switch is turned OFF and the HS
switch is turned on after a dead time. This is somewhat different than the more typical peak current limit, and
results in Equation 8 for the maximum load current.
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(8)
If VCSN/OUT < 2-V typical due to a short circuit for 128 consecutive cycles, hiccup current protection mode is
activated. In hiccup mode, the regulator is shut down and kept off for 118 ms typically, then TPS2583x-Q1 go
through a normal re-start with soft start again. If the short-circuit condition remains, hiccup repeats until the fault
condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions, prevents
over-heating and potential damage to the device and serves as a backup to the programmable current limit. See
Current Limit Setting Using RILIMIT. After the output short is removed, the hiccup delay is passed and the output
voltage recovers normally as shown in Figure 11-21.
10.3.11 Overvoltage, IEC and Short-to-Battery Protection
The TPS25840-Q1 integrates OVP and short to battery protection on VBUS, DM_IN and DP_IN pins. These pins
can withstand voltage up to 18 V, and can protect upstream processor or Hub data line when overvoltage or
short to battery condition occurs. Refer to 图9-3 for the short-to-battery test setup.
The TPS2584x-Q1 also integrates IEC ESD cell on DP_IN and DM_IN pins.
For more detailed TPS2584x-Q1 short-to-battery consideration and test report, please refer to the TPS2583x-Q1
and TPS2584x-Q1 Short-to- Battery Application application report.
10.3.11.1 VBUS and VCSN/OUT Overvoltage Protection
The TPS25840-Q1 integrates overvoltage protection on both BUS and CSN/OUT pin to meet different
application requirement.
BUS pin can withstand up to 18 V, and the OVP threshold is 7-V typical. After overvoltage is detected on BUS
pin, the LS_GD turns off immediately. Also, FAULT asserts after 8-ms deglitch time. After the excessive voltage
is removed, the LS_GD turns on again and FAULT deasserts.
CSN/OUT pin can withstand up to 20 V, and the OVP threshold is 7.5-V typical. After overvoltage is detected on
CSN/OUT pin, the buck converter stops regulation. Also, LS_GD turns off immediately. After the excessive
voltage is removed, the buck converter resumes and the LS_GD turns on again.
CBOOT
CBOOT
To auxillary
loads
VIN
VIN
BOOT
BOOT
L
L
RSNS
RSNS
IN
IN
SW
CSP
RSET
EN/UVLO
RT/SYNC
EN/UVLO
RT/SYNC
RSET
CSP
CSN/OUT
CSN/OUT
VCC
VCC
TPS2584x-Q1
TPS2584x-Q1
2.2kΩ
LS_GD
FAULT
FAULT
BUCK_ST
CTRL1
LS_GD
BUS
BUCK_ST
0.22uF
0.22uF
CTRL1
CTRL2
RBUS= 10Ω
RBUS= 100Ω
BUS
CTRL2
DP_OUT
DM_OUT
DP_IN
DM_IN
DP_OUT
DM_OUT
DP_IN
DM_IN
INT
IMON ILIMIT
AGND PGND
INT
IMON ILIMIT
AGND PGND
图10-17. Current Limit With External MOSFET
图10-18. Buck Average Current Limit
As shown in 图 10-17, TPS25840-Q1 is configured in external FET current limit mode. When short-to-battery
occurs on BUS_Connector, the external MOSFET turns off immediately after BUS pin detect over voltage. The
FAULT signal assertd after 8-ms deglitch time. See Figure 11-28. With Back-to-back FET, the TPS2583x-Q1 can
withstand short-to-battery event even when Vin is off. TI recommends a 10-Ω 0805 resistor between BUS pin
and BUS_Connector.
As shown in 图 10-18, TPS25840-Q1 is configured in buck average current limit mode. When short-to-battery
occurs on BUS_Connector, the buck regulator stops switching after CSN/OUT pin detect overvoltage. The
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FAULT signal also asserts after 8-ms deglitch time. TI recommends a 100-Ω0805 resistor between BUS pin and
BUS_Connector in buck average current limit mode.
10.3.11.2 DP_IN and DM_IN Protection
DP_IN and DM_IN protection consists of IEC ESD and overvoltage protection.
The DP_IN and DM_IN pins integrate an IEC ESD cell to provide ESD protection up to ±15-kV air discharge and
±8-kV contact discharge per IEC 61000-4-2 (for test conditions, see the ESD Ratings section). The IEC ESD
performance of the TPS2584x-Q1 device depends on the capacitance connected from BUS pin to GND. TI
recommends placing a A 0.22-µF capacitor close to the BUS pin
The ESD stress seen at DP_IN and DM_IN is impacted by many external factors like the parasitic resistance and
inductance between ESD test points and the DP_IN and DM_IN pins. For air discharge, the temperature and
humidity of the environment can cause some difference, so the IEC performance must always be verified in the
end-application circuit.
Overvoltage protection (OVP) is provided for short-to-VBUS or short-to-battery conditions in the vehicle harness,
preventing damage to the upstream USB transceiver or hub. When the voltage on DP_IN or DM_IN exceeds 3.9
V (typical), the TPS25840-Q1 device immediately turns off DP/DM switch and responds to block the high-voltage
reverse connection to DP_OUT and DM_OUT. FAULT signal asserts after 8-ms deglitch time. See Figure 11-30.
For DP_IN and DM_IN, when OVP is triggered, the device turns on an internal discharge path with 416-kΩ
resistance to ground. On removal of the overvoltage condition, the pin automatically turns off this discharge path
and returns to normal operation by turning on the previously affected analog switch.
10.3.12 Cable Compensation
When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to
the load. Cable droop compensation linearly increases the voltage at the CSN/OUT pin of TPS2584x-Q1 as load
current increases with the objective of maintaining VBUS_CON (the bus voltage at the USB connector) at 5 V,
regardless of load conditions. Most portable devices charge at maximum current when 5 V is present at the USB
connector. 图 10-19 provides an example of resistor drops encountered when designing an automotive USB
system with a remote USB connector location.
图10-19. Automotive USB Resistances
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5.x
V(DROP)
VOUT with compensation
VBUS with compensation
VBUS without compensation
3
1
2
Output Current (A)
图10-20. Voltage Drop
The TPS2584x-Q1 detects the load current and increases the voltage at the CSN/OUT pin to compensate the IR
drop in the charging path according to the gain set by the RSNS, RSET, and RIMON resistors as described in RSNS
RSET, RILIMIT, and RIMON
,
.
The amount of cable droop compensation required can be estimated by the following equation: ΔVOUT = (RSNS
+ RDSON_NFET + RWIRE) IBUS × RIMON is then chosen by RIMON = (ΔVOUT × RSET × 2) / (IBUS × RSNS), Where
ΔVOUT is the desired cable droop compensation voltage at full load.
In most cases, the recommended voltage across RSNS must be 50 mV. See the RSNS, RSET, RILIMIT, and RIMON
section. In type-C application, typical RIMON resistors value are listed in 表 10-3 given the condition full load
current = 3 A, RSNS = 15 mΩand RSET = 300 Ω.
表10-3. Setting the Cable Compensation Voltage with RIMON
Cable Compensation Voltage at 3-A Full Load (V)
RIMON (kΩ)
0.3
0.6
0.9
1.2
1.5
4.02
8.06
12.1
16.2
20
备注
The maximum cable compensation voltage in TPS2584x-Q1 is 1.5 V.
10.3.12.1 Cable Compensation Design Example
To start the procedure, the RSNS, RDSON_NFET and wire resistance RWIRE must be known.
1. Determine RSNS to achieve 50 mV at full current. For 3.3 A (3-A load current plus at approximately 10% for
overcurrent threshold). RSNS = (0.05 V / 3.3 A) = 15 mΩ.
2. RDSON_NFET = 50 mΩ
3. RWIRE = 200 mΩ
4. ΔVOUT = (RSNS + RDSON_NFET + RWIRE) × IBUS = (0.015 + 0.05 + 0.2) × 3 = 0.795 V
5. Choose RSET = 300 Ω
6. RIMON = (ΔVOUT * RSET × 2) / (IBUS × RSNS) = (0.795 × 300 × 2) / (3 × 0.015) = 10.6 kΩ
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10.3.13 USB Port Control
The TPS25840-Q1 and TPS25842-Q1 include DP_IN, DM_IN pins for automatic or host facilitated USB port
power management of a Type-A downstream facing connector. For details on configuring the TPS2584x-Q1, see
Device Functional Modes.
10.3.14 FAULT Response
The device features an active-low, open-drain fault output. Connect a 100-kΩ pullup resistor from FAULT to
VCC or other suitable I/O voltage. FAULT can be left open or tied to GND when not used.
表10-4 summarizes the conditions that generate a fault and actions taken by the device.
表10-4. Fault and Warning Conditions
EVENT
CONDITION
ACTION
The device regulates current at ISNS either by external NFET
or by the buck regulator control loop.
When current limiting by external NFET, there is NO fault
indicator assertion under minor overload conditions.
When current limiting by buck average current, there is NO
fault indicator assertion under minor overload conditions.
Hard shorts during average buck current limiting can trigger
buck hiccup operation. The FAULT indicator asserts
immediately after NOC cycles in and persists for TOC as
specified in Cycle-by-Cycle Buck Current Limit.
NFET or Buck average current limit
implemented. See Current Limit Sensing
Overcurrent on OUT
using RILIMIT
.
ICSN/OUT > programmed ISNS
.
The device turns on the BUS discharge path in the event of
an overvoltage conditions and turns off the LS_GD
immediately. The FAULT indicator asserts and de-asserts
with an 8-ms deglitch.
Overvoltage on BUS
VBUS > VBUS_OV
The device immediately shuts off the USB data switches.
The FAULT indicator asserts and de-asserts with an 8-ms
deglitch.
Overvoltage on the data lines DP_IN or DM_IN > VDx_IN_OV
10.3.15 USB Specification Overview
Universal Serial Bus specifications provide critical physical and electrical requirements to electronics
manufacturers of USB capable equipment. Adherence to these specifications during product development
coupled with standardized compliance testing assures very high degrees of interoperability amongst USB
products in the market. Since its inception in the mid 1990s, USB has undergone a number of revisions to
enhance utility and extend functionality. For the most up to date standards, please consult the USB
Implementers Forum (USB-IF).
All USB ports are capable of providing a 5-V output making them a convenient power source for operating and
charging portable devices. USB specification documents outline specific power requirements to ensure
interoperability. In general, a USB 2.0 port host port is required to provide up to 500 mA; a USB 3.0 or USB 3.1
port is required to provide up to 900 mA; ports adhering to the USB Battery Charging 1.2 Specification provide
up to 1500 mA; and newer Type-C ports can provide up to 3000 mA. Though USB standards governing power
requirements exist, some manufacturers of popular portable devices created their own proprietary mechanisms
to extend allowed available current beyond the 1500 mA maximum per BC 1.2. While not officially part of the
standards maintained by the USB-IF, these proprietary mechanisms are recognized and implemented by
manufacturers of USB charging ports.
The TPS2584x-Q1 device supports the most-common USB-charging schemes BC1.2 in popular hand-held
media and cellular devices.
The BC1.2 specification includes three different port types:
• Standard downstream port (SDP, supported)
• Charging downstream port (CDP, supported)
• Dedicated charging port (DCP, NOT supported)
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BC1.2 defines a charging port as a downstream-facing USB port that provides power for charging portable
equipment. Under this definition, CDP and DCP are defined as charging ports.
表10-5 lists the difference between these port types.
表10-5. Operating Modes Table
MAXIMUM ALLOWABLE CURRENT
DRAWN BY PORTABLE EQUIPMENT (A)
PORT TYPE
SUPPORTS USB2.0 COMMUNICATION
SDP (USB 2.0)
SDP (USB 3.0 and 3.1)
CDP
YES
YES
YES
NO
0.5
0.9
1.5
1.5
DCP
10.3.16 Device Power Pins (IN, CSN/OUT, and PGND)
The IN pins are the input power path to the TPS2584x-Q1 devices. The internal LDO and buck regulator high
side switch are supplied from the IN pins. The CSN/OUT pin connects to the negative terminal of the current
sense amplifier and the internal voltage feedback network. This pin must be connected to the output LC filter for
proper operation. PGND is the power ground return. For optimum performance, ensure the IN pin is properly
bypassed to PGND with adequate bulk and high-frequency bypass capacitance located as close to these pins as
possible.
10.3.17 Thermal Shutdown
The device has an internal overtemperature shutdown threshold, TSD to protect the device from damage and
overall safety of the system. When device temperature exceeds TSD, the LD_GD pin is pulled low, and the buck
regulator stops switching. The device attempts to power-up when die temperature decreases by approximately
20°C.
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10.4 Device Functional Modes
10.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the TPS2584x-Q1. When VEN is below 1.2 V (typical), the
device is in shutdown mode. The TPS2584x-Q1 also employs VIN and VCC undervoltage lock out protection. If
VIN or VCC voltage is below their respective UVLO level, the regulator is turned off.
10.4.2 Active Mode
The TPS2584x-Q1 is in Active Mode when VEN is above the precision enable threshold, VIN and VCC are above
their respective UVLO levels. The simplest way to enable the TPS2584x-Q1 is to connect the EN pin to VIN pin.
This connection allows self startup when the input voltage is in the operating range of 3.8 V to 36 V and a UFP
detection is made. For details on setting these operating levels, refer to VCC, VCC_UVLO and Enable/UVLO.
In Active Mode, the TPS2584x-Q1 buck regulator operates with Forced Pulse Width Modulation (FPWM), also
referred to as Forced Continuous Conduction Mode (FCCM). This operation ensures the buck regulator
switching frequency remains constant under all load conditions. FPWM operation provides low output voltage
ripple, tight output voltage regulation, and constant switching frequency. Built-in spread-spectrum modulation
aids in distributing spectral energy across a narrow band around the switching frequency programmed by the
RT/SYNC pin. Under light load conditions the inductor current is allowed to go negative. A negative current limit
of IL_NEG is imposed to prevent damage to the regulator's low side FET. During operation the TPS2584x-Q1
synchronized to any valid clock signal on the RT/SYNC input.
10.4.3 Device Truth Table (TT)
The device truth table (表 10-6) lists all valid combinations for the two control pins (CTRL1 and CTRL2). The
TPS2584x-Q1 devices monitor the CTRL inputs and transitions to whichever charging mode it is commanded.
表10-6. Truth Table
CURRENT LIMIT
DEVICE(S)
CTRL1
CTRL2
USB MODES
BUCK REGULATOR
LS_GD
SETTING
0
0
1
1
0
1
0
1
Buck Hiccup Only
Buck Hiccup Only
Client Mode(1)
Client Mode(1)
SDP Mode
ON
ON
ON
ON
OFF
OFF
TPS2584x-Q1
See Current Limit
Sensing using RILIMIT
CDP Mode
(1) TPS2584x-Q1: USB data switches ON during client mode.
10.4.4 USB Port Operating Modes
10.4.4.1 Standard Downstream Port (SDP) Mode —USB 2.0, USB 3.0, and USB 3.1
An SDP is a traditional USB port that follows USB 2.0, USB 3.0 or USB 3.1 protocol. A USB 2.0 SDP supplies a
minimum of 500 mA per port and supports USB 2.0 communications. A USB 3.x SDP supplies a minimum of 900
mA per port and supports USB 3.0 or USB 3.1 communications. For both types, the host controller must be
active to allow charging.
10.4.4.2 Charging Downstream Port (CDP) Mode
A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5 A per port. A CDP provides power
and meets the USB 2.0 requirements for device enumeration. USB-2.0 communication is supported, and the
host controller must be active to allow charging. The difference between CDP and SDP is the host-charge
handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and
allows for additional current draw by the client device.
The CDP handshaking process occurs in two steps. During step one, the portable equipment outputs a nominal
0.6-V output on the D+ line and reads the voltage input on the D– line. The portable device detects the
connection to an SDP if the voltage is less than the nominal data-detect voltage of 0.3 V. The portable device
detects the connection to a CDP if the D– voltage is greater than the nominal data detect voltage of 0.3 V and
optionally less than 0.8 V.
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The second step is necessary for portable equipment to determine whether the equipment is connected to a
CDP or a DCP. The portable device outputs a nominal 0.6-V output on the D– line and reads the voltage input
on the D+ line. The portable device concludes the equipment is connected to a CDP if the data line being read
remains less than the nominal data detects voltage of 0.3 V. The portable device concludes it is connected to a
DCP if the data line being read is greater than the nominal data detect voltage of 0.3 V.
10.4.4.3 Client Mode
The TPS2584x-Q1 device integrates client mode as shown in 图 10-21. The external MOSFET power switch is
OFF and only the data analog switch is ON. This mode can be used by automotive USB system manufacturers
and OEMs for factory-only software programming with the USB port.
L
RSNS
ON
BOOT
IN
SW
Buck Regulator
LS_GD
NFET
ON
RSET
LOW
OFF
ON
CSP
USB Switches
CSN/OUT
LS_GD
TPS25840/2-Q1
LOW
OFF
BUS
DM_IN
DP_IN
SW
SW
DM_OUT
DP_OUT
图10-21. Client-mode Equivalent Circuit
10.4.5 High-bandwidth Data-line Switches
The TPS2584x-Q1 device passes the D+ and D– data lines through the device to enable monitoring and
handshaking while supporting the charging operation. A wide-bandwidth signal switch allows data to pass
through the device without corrupting signal integrity. The data-line switches are turned on in any of the CDP,
SDP, or client operating modes. The EN input must be at logic high for the data line switches to be enabled.
For more detailed USB2.0 data line consideration and eye diagram test report, please refer to the How to
Improve USB2.0 Eye Diagram Using Long USB Cable application report.
备注
• The data switches are ON while in CDP mode, even during CDP handshaking.
• The data line switches are OFF if EN/UVLO is low.
• The data line switches are OFF during External FET Current limit conditions.
• The data switches are only for a USB-2.0 differential pair. In the case of a USB-3.0 host, the super-
speed differential pairs must be routed directly to the USB connector without passing through the
TPS2584x device.
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11 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
11.1 Application Information
The TPS2584x-Q1 is a step down DC-to-DC regulator and USB charge port controller. TheTPS2584x-Q1 is
typically used in automotive systems to convert a DC voltage from the vehicle battery to 5-V DC with a maximum
output current of 3 A. The following design procedure can be used to select components for the TPS2584x-Q1.
11.2 Typical Application
The TPS2584x-Q1 only requires a few external components to convert from a wide voltage range supply to a 5-
V output for powering USB devices. 图11-1 shows a basic schematic.
CBOOT
CSNS(FLT)
0.1 ꢁF
0.1 ꢁF
VIN
6 V to 18 V
BOOT (32)
L
RSNS
IN (1, 2, 3)
RENT
20 kꢀ
SW (28, 29, 30, 31)
10 ꢁH
CCSP
0.015 ꢀ
CIN(HF)
CIN(BULK)
CIN
RSET
+
5*22 ꢁF
EN/UVLO (4)
CSP (14)
RENB
300 ꢀ
10 ꢁF
0.1 ꢁF
5 kꢀ
CSN/OUT (13)
LS_GD (10)
CCSN/OUT
2.2 kꢀ
VCC (21)
0.1 ꢁF
CVCC
CVCC(HF)
0.22 ꢁF
100 ꢀ
2.2 ꢁF
0.1 ꢁF
BUS (15)
RPU
DM_IN (17)
DP_IN (18)
CTRL1 (5)
CTRL2 (6)
100 kꢀ
RPU
100 kꢀ
RPU
RT/SYNC (9)
IMON (11)
FAULT (24)
BUCK_ST (23)
INT (20)
100 kꢀ
RPU
RIMON
1 ꢁF
CBUS
ILIMIT (12)
12.7 kꢀ
100 kꢀ
RRT
49.9 kꢀ
RILIMIT
AGND (16)
5.1 kꢀ
11.8 kꢀ
PGND (25, 26, 27)
DM_OUT (8)
DP_OUT (7)
图11-1. Application Circuit
The integrated buck regulator of TPS2584x-Q1 is internally compensated and optimized for a reasonable
selection of external inductance and capacitance. The external components have to fulfill the needs of the
application, but also the stability criteria of the device's control loop. 表 11-2 can be used to simplify the output
filter component selection.
11.2.1 Design Requirements
To begin the design process, a few parameters must be known:
• Cable compensation: Total resistance including cable resistance, contact resistance of connectors,
TPS2584x-Q1 current sense resistor and external NFET rDS(on) (if used). Refer to 图10-19 for examples of
resistance in an automotive application.
• The maximum continuous output current for the charging port. The minimum current-limit setting of
TPS2584x-Q1 device must be higher than this current.
For this example, use the parameters listed in 表11-1 as the input parameters.
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表11-1. Design Example Parameters
PARAMETER
Input Voltage, VIN
VALUE
13.5-V typical, range from 6 V to 18 V
Output Voltage, VOUT
5.1 V
3.0 A
Maximum Output Current IOUT(MAX)
Transient Response 0.3 A to 3 A
Output Voltage Ripple
5%
50 mV
400 mV
400 kHz
300 mΩ
3.3 A
Input Voltage Ripple
Switching Frequency fSW
Cable Resistance for Cable Compensation
Current Limit by Buck Average
表11-2. L, and COUT Typical Values
VOUT without
Cable
fSW
CIN + CHF
L
Current Limit
CCSP
CCSN/OUT
CBUS
Compensation
400 kHz
400 kHz
2100 kHz
5.10 V
5.10 V
5.10 V
1 × 10 µF + 1 × 100 nF
1 × 10 µF + 1 × 100 nF
1 × 10 µF + 1 × 100 nF
10 µH
10 µH
2.2 µH
Buck Avg
Ext. NFET
Buck Avg
5 × 22 µF
5 × 22 µF
2 × 22 µF
100 nF
100 nF
100 nF
1 to 4.7 µF
1 to 4.7 µF
1 to 4.7 µF
1. Inductance value is calculated based on VIN = 18 V.
2. All the COUT values are after derating.
11.2.2 Detailed Design Procedure
11.2.2.1 Output Voltage
The output voltage of TPS2584x-Q1 is internally fixed at 5.10 V. Cable compensation can be used to increase
the voltage on the CSN/OUT pin linearly with increasing load current. For more details on output voltage
variation versus load current, refer to Cable Compensation. If cable compensation is not desired, use a 0-Ω
RIMON resistor.
11.2.2.2 Switching Frequency
The recommended switching frequency of the TPS2584x-Q1 is in the range of 300–400 kHz for best efficiency.
Choose RRT = 49.9 kΩfor 400-kHz operation. Refer to 表10-1 to choose a different switching frequency.
11.2.2.3 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current and the rated current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Because the ripple current increases with
the input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 10 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of
KIND must be 20% to 40%. During an instantaneous short or over current operation event, the RMS and peak
inductor current can be high. The inductor current rating must be higher than the current limit of the device.
VOUT ì V
- VOUT
(
)
IN_MAX
DiL =
VIN_MAX ìL ì fSW
(9)
V
- VOUT
VOUT
IN_MAX
LMIN
=
ì
IOUT ìKIND
V
IN_MAX ì fSW
(10)
In general, choose lower inductance in switching power supplies because it usually corresponds to faster
transient response, smaller DCR, and reduced size for more compact designs. But too low of an inductance can
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generate too large of an inductor current ripple such that over current protection at the full load can be falsely
triggered. Too low of an inductance also generates more conduction loss and inductor core loss. Larger inductor
current ripple also implies larger output voltage ripple with same output capacitors. With peak current mode
control, TI recommends to have a larger inductor current ripple. A larger peak current ripple improves the
comparator signal to noise ratio.
For this design example, choose KIND = 0.3, the minimum inductor value is calculated to be 8.7 µH. Choose the
nearest standard 10 μH ferrite inductor with a capability of 4 A RMS current and 6-A saturation current.
11.2.2.4 Output Capacitor Selection
The value of the output capacitor, and its ESR, determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements, rather than the
output voltage ripple. Equation 11 can be used to estimate a lower bound on the total output capacitance, and an
upper bound on the ESR, required to meet a specified load transient.
K2
12
»
…
…
ÿ
DIOUT
fSW ∂ DVOUT ∂K
COUT
í
∂
(
1- D
)
∂
(
1+ K
)
+
∂
(
2 - D
)
Ÿ
Ÿ
⁄
(
2 + K
)
∂ DVOUT
ESR Ç
K2
1
»
ÿ
≈
’
2∂ DIOUT 1+ K +
∂∆1+
÷
÷
…
Ÿ
∆
12
(1- D)
…
«
◊Ÿ
⁄
VOUT
D =
V
IN
(11)
where
• ΔVOUT = output voltage transient
• ΔIOUT = output current transient
• K = Ripple factor from Inductor Selection
After the output capacitor and ESR have been calculated, Equation 12 can be used to check the peak-to-peak
output voltage ripple, Vr.
1
Vr @ DIL ∂ ESR2 +
2
8∂ fSW ∂COUT
(12)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
For this example, we require a ΔVOUT of ≤ 250 mV for an output current step of ΔIOUT = 2.7 A. Equation 11
gives a minimum value of 86 µF and a maximum ESR of 0.08 Ω. Assuming a 20% tolerance and a 10% bias de-
rating, we arrive at a minimum capacitance of 110 µF. This can be achieved with a bank of 5 × 22-µF, 10-V,
ceramic capacitors in the 1210 case size. More output capacitance can be used to improve the load transient
response. Ceramic capacitors can easily meet the minimum ESR requirements. In some cases an aluminum
electrolytic capacitor can be placed in parallel with the ceramics to help build up the required value of
capacitance.
In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and Bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help to reduce high frequency noise. Small case size ceramic capacitors in the range
of 1 nF to 100 nF can be very helpful in reducing voltage spikes on the output caused by inductor and board
parasitics.
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The maximum value of total output capacitance must be limited to about 10 times the design value, or 1000 µF,
whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the
regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-
up at full load and loop stability must be performed.
11.2.2.5 Input Capacitor Selection
The TPS2584x-Q1 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. A high-quality ceramic capacitor type X5R or X7R with sufficient voltage ratings
are recommended. To compensate the derating of ceramic capacitors, TI recommends a voltage rating of twice
the maximum input voltage. The bulk capacitance selection depends upon a number of factors: long leads from
the automotive battery to the IN pin of TPS2584x-Q1, cold or warm engine crank requirements, and so forth. The
bulk capacitor is used to dampen voltage spike due to the lead inductance of the cable or the trace. For this
design, one 10-μF, 50-V, X7R ceramic capacitors are used. Use a 0.1 μF for high-frequency filtering and place
it as close as possible to the device pins. Consider adding additional bulk capacitance for operation through low
VIN warm-crank profiles is required by the vehicle OEM.
11.2.2.6 Bootstrap Capacitor Selection
Every TPS2584x-Q1 design requires a bootstrap capacitor (CBOOT). The recommended capacitor is 0.1 μF and
rated 10 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap
capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.
11.2.2.7 VCC Capacitor Selection
The VCC pin is the output of an internal LDO for TPS2584x. The LDO supplies gate charge to the LS buck
switch and is the supply to the digital state-machine and analog USB circuitry. To insure stability of the device,
place a minimum of 2.2 μF, 10 V, X7R capacitor from this pin to ground. In addition a 0.1-μF high frequency
decoupling capacitor is highly recommended.
11.2.2.8 Enable and Under Voltage Lockout Set-Point
The system enable and undervoltage lockout (UVLO) is adjusted using the external voltage divider network of
RENT and RENB. The EN/UVLO has two thresholds, one for power up when the input voltage is rising and one
for power down or brown outs when the input voltage is falling. The following equations can be used to
determine the VIN(ON) and VIN(OFF) levels.
(13)
(14)
VIN(ON) = 6 V (user choice)
RENB = 5 kΩ(user choice)
RENT = [(VIN(ON) / (VEN/UVLO_H) –1] × RENB
RENB = [(6 V / 1.2 V) –1] × 5 kΩ= 20 kΩ. Choose standard 20 kΩ.
Therefore VIN(OFF) = 6 V × [1 –(0.09 V / 1.2 V)] = 5.55 V
11.2.2.9 Current Limit Set-Point
The TPS2584x-Q1 provides an accurate current limit to protect the USB port from overload based upon the
values of RSNS, RSET and RILIMIT. The design process is the same regardless of whether buck average current
limiting or external NFET current limiting is chosen. The only difference is the current limit threshold voltage on
the ILIMIT pin.
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• RSNS is the current sense resistor. The recommended voltage across RSNS under current limit must be
approximately 50 mV as a compromise between accuracy and power dissipation. For example, if current
limiting is desired for IOUT(MAX) ≥3.3 A, then RSNS = 0.05 V / 3.3 A = 0.01515 Ω. Choose a standard value of
15 mΩ.
• RSET determines the input current to the transconductance amplifier and current mirror. The amplifier
balances the voltage to be equal to that across RSNS. Choose a RSET value to produce an ISET current
between 75 –180 µA at the desired IOUT(MAX). Considering 50 mV across RSET, a value of 300 Ωprovides
approximately 166 µA of ISET current to the amplifier and mirror circuit. Care must be taken to limit the ISET
current below 200 µA to avoid saturating the internal amplifier circuit.
• Buck average current limiting occurs when VILIMIT = 1 V. RILIMIT is calculated as 1 V × 300 Ω/ [ 0.5 × (3.3 A ×
15 mΩ+ 0.7 mV) ] = 11.95 kΩ. A standard 11.8 kΩvalue is chosen.
11.2.2.10 Cable Compensation Set-Point
From 表11-1 the total cable resistance to be accounted for is 300 mΩ.
1. From Current Limit Set-Point RSNS and RSET have been determined as 15 mΩand 300 Ω, respectively.
2. RWIRE = 300 mΩ
3. ΔVOUT = (RSNS + RWIRE) × IBUS = (0.015 + 0.3) × 3 = 1.0395 V
4. RIMON = (ΔVOUT × RSET × 2) / (IBUS × RSNS) = (1.0395 × 300 × 2) / (3.3 × 0.015) = 12.6 kΩ. A standard
value of 12.7 kΩis selected.
11.2.2.11 FAULT Resistor Selection
The FAULT pins are open-drain output flags. The pins can be connected to the TPS2584x-Q1 VCC pin with 100
kΩ resistors, or connected to another suitable I/O voltage supply if actively monitored by a USB HUB or MCU.
The pins can be left floating if unused.
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11.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 10 µH, COUT_CSP = 66 µF,
COUT_CSN = 0.1 µF, CBUS = 1 µF, TA = 25 °C.
100
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
VIN = 6V
VIN = 13.5V
VIN = 18V
VIN = 36V
VIN = 8.5V
VIN = 13.5V
VIN = 18V
0.1
1
OUT Current (A)
4
0.1
1
OUT Current (A)
4
A001
A002
VOUT = 5.1 V
fSW = 400 kHz
VOUT = 5.1 V
fSW = 2100 kHz
图11-2. Buck Only Efficiency
图11-3. Buck Only Efficiency
100
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
VIN = 6V
VIN = 13.5V
VIN = 18V
VIN = 36V
VIN = 8.5V
VIN = 13.5V
VIN = 18V
0.1
1
OUT Current (A)
4
0.1
1
OUT Current (A)
4
A003
A004
VOUT = 5.1 V
fSW = 400 kHz
VOUT = 5.1 V
fSW = 2100 kHz
RSENS = 15 mΩ
RSENS = 15 mΩ
图11-4. Efficiency With Sense Resistor
图11-5. Efficiency With Sense Resistor
0.4
0.1
VIN = 6V
VIN = 13.5V
VIN = 18V
Load = 1A
Load = 2A
Load = 3A
0.08
0.06
0.04
0.02
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.02
-0.04
0
0.5
1
1.5
OUT Current (A)
2
2.5
3
A005
6
9
12
15
18
21
24
VIN Voltage (V)
27
30
33
36
A006
VOUT = 5.1 V
fSW = 400 kHz
VOUT = 5.1 V
fSW = 400 kHz
图11-6. Load Regulation
图11-7. Line Regulation
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VBUS,
200mV/Div
VBUS,
200mV/Div
Load Current,
2A/Div
Load Current,
2A/Div
200us/Div
200us/Div
VOUT = 5.1 V ILOAD = 0 A to 3.5A
VOUT = 5.1 V
ILOAD = 0.75 A to
2.25A
RIMON = 0 Ω
RIMON = 0 Ω
图11-8. Load Transient Without Cable
图11-9. Load Transient Without Cable
Compensation
Compensation
VBUS,
500mV/Div
VBUS,
500mV/Div
Load Current,
2A/Div
Load Current,
2A/Div
2ms/Div
2ms/Div
ILOAD = 0 A to 3.5A
ILOAD = 0.75 A to
2.25A
RIMON = 13 kΩ
RIMON = 13 kΩ
图11-10. Load Transient With Cable Compensation
图11-11. Load Transient With Cable Compensation
6
5.5
5
SW,
5V/Div
4.5
4
VBUS,
10mV/Div (AC coupled)
Load = 0A
Load = 1A
Load = 2A
Load = 3A
Load = 3.5A
3.5
3
4
4.5
5
5.5 6
Input Voltage (V)
6.5
7
7.5
2us/Div
A007
RIMON = 13 kΩ
图11-12. Dropout Characteristic
图11-13. 3.5-A Output Ripple
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SW,
5V/Div
SW,
5V/Div
VBUS,
10mV/Div (AC coupled)
VBUS,
10mV/Div (AC coupled)
2us/Div
2us/Div
RIMON = 13 kΩ
RIMON = 13 kΩ
图11-14. 100-mA Output Ripple
图11-15. No Load Output Ripple
EN,
5V/Div
EN,
5V/Div
VIN
5V/Div
VIN
5V/Div
VBUS,
5V/Div
VBUS,
5V/Div
VCC,
5V/Div
VCC,
5V/Div
40ms/Div
10ms/Div
VIN = 0 V to 13.5 V
ILOAD = 3A
VIN = 13.5 V to 0 V
ILOAD = 3A
INT = 5.1 kΩ
INT = 5.1 kΩ
图11-16. Startup Relate to VIN
图11-17. Shutdown Relate to VIN
EN, 5V/Div
EN,
5V/Div
VIN
5V/Div
VIN, 5V/Div
VBUS, 2V/Div
VBUS,
2V/Div
VCC, 2V/Div
VCC,
5V/Div
40ms/Div
40ms/Div
EN = 0V to 5V
ILOAD = 3A
EN = 5V to 0V
ILOAD = 3A
INT = 5.1 kΩ
INT = 5.1 kΩ
图11-18. Startup Relate to EN
图11-19. Shutdown Relate to EN
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EN, 10V/Div
EN, 10V/Div
FAULT, 2V/Div
Short removed
FAULT, 2V/Div
VBUS, 2V/Div
VBUS, 2V/Div
Load Current,
5A/Div
Load Current, 5A/Div
40ms/Div
100ms/Div
EN to High
VBUS = GND
RLIMIT = 13 kΩ
RLIMIT = 13 kΩ
图11-20. Enable into Short Without External FET 图11-21. Short Circuit Recovery Without External
FET
EN, 10V/Div
EN, 10V/Div
FAULT, 2V/Div
FAULT, 2V/Div
VBUS, 1V/Div
1Ω load removed
Load Current, 2A/Div
VBUS, 1V/Div
Load Current, 2A/Div
100ms/Div
100ms/Div
EN to High
VBUS = GND
RLIMIT = 13 kΩ
RLIMIT = 13 kΩ
图11-22. Enable Into 1-ΩLoad Without External
图11-23. 1-ΩLoad Recovery Without External FET
FET
EN, 10V/Div
EN, 10V/Div
FAULT, 2V/Div
Short removed
FAULT, 2V/Div
VBUS, 2V/Div
VBUS, 2V/Div
Load Current, 2A/Div
Load Current, 2A/Div
100ms/Div
100ms/Div
EN to High
VBUS = GND
RLIMIT = 6.8 kΩ
RLIMIT = 6.8 kΩ
图11-25. Short Circuit Recovery With External FET
图11-24. Enable Into Short With External FET
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EN, 10V/Div
EN, 10V/Div
FAULT, 2V/Div
FAULT, 2V/Div
VBUS, 2V/Div
VBUS hot short to
GND
VBUS hot short to
GND
VBUS, 2V/Div
Load Current, 2A/Div
Load Current, 5A/Div
1ms/Div
2ms/Div
RLIMIT = 13 kΩ
RLIMIT = 6.8 kΩ
图11-26. VBUS Hot Short to GND Without External
图11-27. VBUS Hot Short to GND With External
FET
FET
FAULT, 2V/Div
FAULT, 2V/Div
VBUS, 5V/Div
VBUS short to 18V BAT
VBUS, 5V/Div
2ms/Div
20ms/Div
NO LOAD
NO LOAD
INT = 5.1 kΩ
INT = 5.1 kΩ
图11-28. VBUS Short to BAT With External FET
图11-29. VBUS Short to BAT Recovery With
External FET
FAULT, 2V/Div
FAULT, 2V/Div
VBUS, 5V/Div
DP, 5V/Div
DP short to 18V BAT
DP, 5V/Div
2ms/Div
20ms/Div
NO LOAD
NO LOAD
INT = 5.1 kΩ
INT = 5.1 kΩ
图11-30. DP Short to BAT
图11-31. DP Short to BAT Recovery
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12 Power Supply Recommendations
The TPS2584x-Q1 is designed to operate from an input voltage supply range between 6 V and 36 V. This input
supply must be able to withstand the maximum input current and maintain a stable voltage. The resistance of the
input supply rail must be low enough that an input current transient does not cause a high enough drop at the
TPS2584x-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply
is located more than a few inches from the TPS2584x-Q1, additional bulk capacitance can be required in
addition to the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF
electrolytic capacitor is a typical choice.
13 Layout
13.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines help users design a PCB with
the best power conversion performance, thermal performance, and minimized generation of unwanted EMI. For
more detailed EMC design consideration and test report, please see the PCB Layout and Parameters
Recommendation for TPS2583X EMC Performance application report.
1. Input capacitor: The input bypass capacitor, CIN, must be placed as close as possible to the IN and PGND
pins. Grounding for both the input and output capacitors must consist of localized top side planes that
connect to the PGND pin and PAD. A combination of different values and packages of capacitors can help
improve the EMC performance (for example: 10 μF + 0.1 μF + 2.2 nF). Besides, the distance between the
input filter section and the output power section must be at least 15mm to prevent the output high-frequency
signal from coupling into the input filter. A 10-µF cap cross VIN and PGND pin on top of SW is suggested for
TPS2584x-Q1.
2. VCC bypass capacitor: Place bypass capacitors for VCC close to the VCC pin and ground the bypass
capacitor to device ground.
3. Use a ground plane in one of the middle layers as noise shielding and heat dissipation path.
4. Connect the thermal pad to the ground plane. The QFN package has a thermal pad (PAD) connection that
must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection. The integrity of
this solder connection has a direct bearing on the total effective RθJA of the application.
5. Make VIN, VOUT and ground bus connections as wide as possible. This action reduces any voltage drops on
the input or output paths of the converter and maximizes efficiency.
6. Provide enough PCB area for proper heat sinking. As stated in the section, enough copper area must be
used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature. Make
the top and bottom PCB layers with 2-ounce copper and no less than one ounce. Use an array of heat-
sinking vias to connect the thermal pad (PAD) to the ground plane on the bottom PCB layer. If the PCB
design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer
heat-spreading ground planes.
7. The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load
current without excessive heating. Short, thick traces or copper pours (shapes) bring a high current
conduction capacity to minimize parasitic resistance, but also cause a larger parasitic capacitance. Thus a
balance must be found between smaller parasitic resistance and larger parasitic capacitance. And the
current path must be kept straight forward to the inductor, otherwise the L-shaped or T-shaped path makes a
sudden change of the impedance which causes signal reflection and impacts the performance of EMC. The
output capacitors must be placed close to the VOUT end of the inductor and closely grounded to PGND pin
and exposed PAD. Besides, do not punch vias on SW lines. Using shielded inductors or molded inductors to
reduce high-frequency radiation.
8. Sense and Set Resistors: The RSNS and RSET resistors connect to the current sense amplifier inputs at the
CSP and CSN/OUT pins. For best current limit and cable compensation accuracy; short, parallel traces give
the best performance. If it is not possible to place RSNS and RSET near the CSP and CSN/OUT pins, TI
recommends that the traces from sense resistor be routed in parallel and of similar lengths. A small filter
capacitor in parallel with RSNS and a small filter capacitor from CSN/OUT to AGND help decouple noise.
9. RILIMIT and RIMON resistors must be placed as close as possible to the ILIMIT and IMON pins and connected
to AGND. If needed, these components can be placed on the bottom side of the PCB with signals routed
through small vias.
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10. Trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: Route these traces as micro-strips with nominal
differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the reference
GND plane devoid from cuts or splits above the differential pairs to prevent impedance discontinuities.
11. FAULT are open-drain outputs. They can be connected to the VCC pin via pull-up resistors. Suggested
resistor value is 100 kΩ.
12. The area enclosed by current loop of input side and output side must be as small as possible; the area
enclosed by the BOOT circuit must be as small as possible.
13. Power ground PGND and the signal ground AGND must be separated in the actual PCB layout.
13.2 Ground Plane and Thermal Considerations
TI recommends to use one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. Ground plane also provides a quiet reference potential for the control circuitry. The
PGND pins must be connected to the ground plane using vias right next to the bypass capacitors. PGND pin is
connected to the source of the internal LS switch. The PGND net contains noise at switching frequency and can
bounce due to load variations. PGND trace, as well as VIN and SW traces, must be constrained to one side of
the ground plane. The other side of the ground plane contains much less noise and must be used for sensitive
routes. AGND and PGND must be connected under the QFN package PAD.
TI recommends to provide adequate device heat sinking by using the PAD of the IC as the primary thermal path.
Use a minimum 2 row, 2 column "+" array of 12 mil thermal vias to connect the PAD to the system ground plane
heat sink. The vias must be evenly distributed under the PAD. Use as much copper as possible, for system
ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper
thickness for the four layers, starting from the top of 2 oz, 1 oz, 1 oz, 2 oz. Four layer boards with enough copper
thickness provide low current conduction impedance, proper shielding and lower thermal resistance.
The thermal characteristics of the TPS2584x-Q1 are specified using the parameter, θJA, which characterize the
junction temperature of silicon to the ambient temperature in a specific system. Although the value of θJA is
dependent on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one can use the following relationship:
TJ = PD x θJA + TA
(15)
where
TJ = Junction temperature is in °C
PD = VIN × IIN × (1 –Efficiency) –1.1 × IOUT 2 × DCR in Watt
DCR = Inductor DC parasitic resistance in Ω
θJA = Junction to ambient thermal resistance of the device in °C/W
TA = Ambient temperature in °C
θJA is highly related to PCB size and layout, as well as environmental factors such as heat sinking and air flow.
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TPS25840-Q1, TPS25842-Q1
ZHCSK92E –SEPTEMBER 2019 –REVISED MARCH 2022
www.ti.com.cn
13.3 Layout Example
EMI Filter
VIN
CHF
CIN
PGND
USB Connector
A4
9
8
7
6
5
4
3
2
1
A1
32
RT
BT
LS_GD 10
IMON 11
31
30
SW
ILIM 12
CSN/OUT 13
CSP 14
29
28
27
BUS 15
26 PGND
CFILT
AGND 16
A3
25
A2
17
18
19
20
21
22
23
24
RSET
CFILT
COUT
CFILT
CFILT
COUT
VBUS
RSNS
RBUS
COUT
Top Trace/Plane
Inner GND Plane
Top
Inner GND Plane
Signal Layers
VIA to Signal Layer
VIA to GND Planes
VIA to Strap
Power and GND
图13-1. Layout Example
Copyright © 2022 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: TPS25840-Q1 TPS25842-Q1
TPS25840-Q1, TPS25842-Q1
ZHCSK92E –SEPTEMBER 2019 –REVISED MARCH 2022
www.ti.com.cn
14 Device and Documentation Support
14.1 Documentation Support
14.1.1 Related Documentation
• Texas Instruments, How to Improve USB2.0 Eye Diagram Using Long USB Cable application report
• Texas Instruments, TPS2583x-Q1 and TPS2584x-Q1 Short-to- Battery Application application report
• Texas Instruments, How to Pass MFi Overcurrent Protection Test With USB Charger and Switch Device
application report
• Texas Instruments, PCB Layout and Parameters Recommendation for TPS2583X EMC Performance
application report
14.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
表14-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TPS25840-Q1
TPS25842-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
14.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
14.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
14.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
14.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
14.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: TPS25840-Q1 TPS25842-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS25840QCWRHBRQ1
TPS25840QWRHBRQ1
TPS25840QWRHBTQ1
TPS25842QCWRHBRQ1
TPS25842QWRHBRQ1
TPS25842QWRHBTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
5000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
T25840
SN
SN
T25840
T25840
T25842
T25842
T25842
250
RoHS & Green
5000 RoHS & Green
3000 RoHS & Green
NIPDAU
SN
250
RoHS & Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Mar-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS25840QCWRHBRQ1 VQFN
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
5000
3000
250
330.0
330.0
180.0
330.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.25
5.25
5.3
5.3
5.25
5.25
5.3
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
TPS25840QWRHBRQ1
TPS25840QWRHBTQ1
VQFN
VQFN
TPS25842QCWRHBRQ1 VQFN
5000
3000
250
TPS25842QWRHBRQ1
TPS25842QWRHBTQ1
VQFN
VQFN
5.25
5.25
5.25
5.25
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS25840QCWRHBRQ1
TPS25840QWRHBRQ1
TPS25840QWRHBTQ1
TPS25842QCWRHBRQ1
TPS25842QWRHBRQ1
TPS25842QWRHBTQ1
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
5000
3000
250
367.0
367.0
213.0
367.0
367.0
213.0
367.0
367.0
191.0
367.0
367.0
191.0
35.0
38.0
35.0
35.0
38.0
35.0
5000
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032R
VQFN - 1 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
0.5
0.3
0.3
0.2
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
5.1
4.9
0.1 MIN
(0.05)
A
-
A
2
0
.
0
0
0
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
3.7 0.1
2X 3.5
8X (0.2)
(0.2) TYP
A2
9
16
A3
28X 0.5
8
17
8X (0.375)
A
A
2X
33
SYMM
3.5
EXPOSED
THERMAL PAD
SEE TERMINAL
DETAIL
1
24
A4
0.3
32X
A1
0.2
32
25
PIN 1 ID
(OPTIONAL)
0.1
C A B
SYMM
0.5
0.3
32X
0.05
4223771/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032R
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.7)
(R0.05)
TYP
SYMM
8X (0.575)
32X (0.6)
32
25
8X (0.2)
A4
A1
32X (0.25)
1
24
4X
(0.97)
(
0.2) TYP
VIA
33
SYMM
4X
(4.8)
(1.26)
28X (0.5)
(2.225)
TYP
8
17
A2
A3
9
16
4X
(0.97)
4X (1.26)
(4.8)
(2.225) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223771/A 06/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032R
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.26 TYP)
9X ( 1.06)
32
8X (0.575)
8X (0.2)
32X (0.6)
25
32X (0.25)
33
1
24
(1.26)
TYP
(R0.05) TYP
SYMM
(4.8)
(2.225)
TYP
28X (0.5)
8
17
METAL
TYP
9
16
SYMM
(4.8)
(2.225) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33
74% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:18X
4223771/A 06/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RHB0032AA
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
0.07 MIN
(0.13)
SECTION A-A
A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
3.7 0.1
2X 3.5
(0.2) TYP
9
16
EXPOSED
THERMAL PAD
28X 0.5
8
(0.16) TYP
17
2X
A
A
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
PIN 1 ID
32
25
SYMM
0.5
0.3
(0.25)
TYP
32X
4227186/A 10/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032AA
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.7)
SYMM
25
32
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.97)
(0.63)
TYP
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(0.63) TYP
(0.97)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4227186/A 10/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032AA
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9X ( 1.06)
(1.26)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(1.26)
SYMM
33
(4.8)
METAL
TYP
17
8
(R0.05) TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
74% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4227186/A 10/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TPS25842-Q1
USB Type-A SDP/CDP 汽车充电端口转换器电缆补偿Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS25842QCWRHBRQ1
USB Type-A SDP/CDP 汽车充电端口转换器电缆补偿 | RHB | 32 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS25842QWRHBRQ1
USB Type-A SDP/CDP 汽车充电端口转换器电缆补偿 | RHB | 32 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS25842QWRHBTQ1
USB Type-A SDP/CDP 汽车充电端口转换器电缆补偿 | RHB | 32 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS25846-Q1
具有客户端模式支持的 USB BC1.2 5V 3.5A 输出、36V 输入同步降压转换器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS25846QCWRHBRQ1
具有客户端模式支持的 USB BC1.2 5V 3.5A 输出、36V 输入同步降压转换器 | RHB | 32 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS25846QWRHBRQ1
具有客户端模式支持的 USB BC1.2 5V 3.5A 输出、36V 输入同步降压转换器 | RHB | 32 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS25846QWRHBTQ1
具有客户端模式支持的 USB BC1.2 5V 3.5A 输出、36V 输入同步降压转换器 | RHB | 32 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS25850-Q1
具有可编程电流限制和热管理功能的双路 3A USB Type-C 充电端口控制器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS25850QRPQRQ1
具有可编程电流限制和热管理功能的双路 3A USB Type-C 充电端口控制器 | RPQ | 25 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS25851-Q1
具有甩负荷和插头极性检测功能的 2.2MHz 双路 3A USB Type-C® 充电端口控制器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
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TPS25851QRPQRQ1
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