TPS25865-Q1 [TI]
具有甩负荷功能的双路 2.4A USB Type-A 充电端口控制器;
| 型号： | TPS25865-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有甩负荷功能的双路 2.4A USB Type-A 充电端口控制器 控制器 |
| 文件： | 总53页 (文件大小：3506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS25865-Q1, TPS25864-Q1
ZHCSMS4B –NOVEMBER 2020 –REVISED SEPTEMBER 2021
TPS25864-Q1 和TPS25865-Q1 具有热管理和电缆补偿功能的低EMI 双USB Type-
A 充电端口转换器
• 符合USB-IF 标准
1 特性
– 自动DCP 模式：
• 符合面向汽车应用的AEC-Q100 标准：
• 符合BC1.2 和YD/T 1591 2009 要求的短路
模式
– 温度等级1：TA 范围–40°C 至+125°C
– HBM ESD 分类等级H2
• 1.2V 模式
– CDM ESD 分类等级C5
• 2.7V 分压器3 模式
• 针对超低EMI 要求进行了优化：
• 甩负荷和可编程TA
• 器件TJ 范围：–40°C 至+150°C
– 符合CISPR25 5 类标准
– HotRod™ 封装可更大限度地减少开关节点振铃
– 展频可降低峰值发射
2 应用
• 同步降压稳压器
• 汽车USB 充电端口
• 汽车USB 媒体中心
– 400kHz 下的高效率：VIN = 13.5V、IPA_BUS
2.4A 且IPB_BUS = 2.4A 时效率为95.2%
– 18mΩ/10mΩ 低RDS(ON) 降压稳压器MOSFET
– 工作电压范围：5.5V 至26V，可承受36V 输入
– 频率可调节：200kHz 至800kHz (TPS25865-
Q1)
=
3 说明
TPS2586x-Q1 是一款集成式 USB 充电端口解决方
案，其中包括一个同步高效直流/直流转换器，而且它
还集成了检测和控制功能，用于在双 Type-A 端口上实
施USB 电池充电规范1.2。
– 频率可调节：200kHz 至3MHz (TPS25864-Q1)
– 具有展频频谱抖动的FPWM
器件信息(1)
– 可选输出电压：5.1V、5.17V、5.3V、5.4V
• 内部电源路径：
器件型号
封装
封装尺寸（标称值）
3.50mm × 4.50mm
3.50mm × 4.50mm
TPS25865-Q1
TPS25864-Q1
VQFN-HR (25)
VQFN-HR (25)
– 7mΩ/7mΩ 低RDS(ON) 内部USB 功率MOSFET
– 具有高精度的USB 端口的电流限制： 2.73A 下
为±10%
(1) 如需了解所有不同可用选件的详细器件型号，请参阅数据表末
尾的可订购产品附录。
– OUT：用于辅助负载的5.1V、200mA 电源
• 线路压降补偿：2.4A 负载下为90mV
100
95
90
85
80
75
70
VIN=6V
400KHz
65
60
VIN=13.5V 400KHz
VIN=18V 400KHz
0.1
1
2
3
4
4.8
Load Current(A)
简化版原理图TPS25864-Q1、TPS25865-Q1
效率与输出电流间的关系
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFP2
TPS25865-Q1, TPS25864-Q1
ZHCSMS4B –NOVEMBER 2020 –REVISED SEPTEMBER 2021
www.ti.com.cn
Table of Contents
10.2 Functional Block Diagram.......................................18
10.3 Feature Description.................................................19
10.4 Device Functional Modes........................................30
11 Application and Implementation................................ 31
11.1 Application Information............................................31
11.2 Typical Applications.................................................31
12 Power Supply Recommendations..............................40
13 Layout...........................................................................40
13.1 Layout Guidelines................................................... 40
13.2 Layout Example...................................................... 41
13.3 Ground Plane and Thermal Considerations............41
14 Device and Documentation Support..........................43
14.1 接收文档更新通知................................................... 43
14.2 支持资源..................................................................43
14.3 Trademarks.............................................................43
14.4 Electrostatic Discharge Caution..............................43
14.5 术语表..................................................................... 43
15 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Device Comparison Table...............................................4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings ....................................... 7
8.2 ESD Ratings .............................................................. 7
8.3 Recommended Operating Conditions ........................8
8.4 Thermal Information ...................................................9
8.5 Electrical Characteristics ............................................9
8.6 Timing Requirements ............................................... 11
8.7 Switching Characteristics .........................................12
8.8 Typical Characteristics..............................................13
9 Parameter Measurement Information..........................16
10 Detailed Description....................................................17
10.1 Overview.................................................................17
Information.................................................................... 44
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (March 2021) to Revision B (September 2021)
Page
• 添加了TPS25864-Q1 信息.................................................................................................................................1
Changes from Revision * (November 2020) to Revision A (March 2021)
Page
• 向特性部分添加了EMI 要求要点....................................................................................................................... 1
• 已更新文档标题...................................................................................................................................................1
• Added 图11-3 to the Application Curves section............................................................................................. 35
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5 说明（续）
TPS2586x-Q1 是一款用于双USB 端口应用的高度集成的USB Type-A 充电控制器。
TPS2586x-Q1 集成了一个具有内部功率 MOSFET 的单片、同步、整流、降压开关模式转换器和两个具有充电端
口自动检测功能的 USB 限流开关。TPS2586x-Q1 提供了一种紧凑型解决方案，可在宽输入电源电压范围内实现
出色的负载和线路调节。该同步降压稳压器具有峰值电流模式控制，而且采用了内部补偿，可简化设计。对于
TPS25865-Q1，FREQ 引脚上有一个电阻器，可用于在 200kHz 和800kHz 之间设置开关频率。对于TPS25864-
Q1，FREQ 引脚上有一个电阻器，可用于在 200kHz 和 3MHz 之间设置开关频率。在低于 400kHz 的频率下运行
可实现更高的系统效率，在高于 2.1MHz 的频率下运行则可以避开 AM 无线电频带，并且能够使用较小的电感
器。
TPS2586x-Q1 集成了标准电池充电（1.2 版），可提供 Type-A USB 器件（利用 USB 数据线信号来确定USB 端
口的拉电流能力）所需的电气特性。TPS2586X-Q1 还集成了一个 OUT 电源开关，可为辅助负载提供最大
200mA 的电流。由于系统集成度高且占用空间小，该器件特别适用于双端口应用。由于系统集成度高且占用空间
小，该器件特别适用于双端口应用。
TPS2586x-Q1 支持智能热管理。USB 输出电压可以根据温度检测通过 TS 引脚进行调节。TPS2586x-Q1 必须在
TS 引脚上连接一个 NTC 热敏电阻以监控环境温度或 PCB 板温度，具体取决于 NTC 热敏电阻在 USB 充电模块
或PCB 板中的放置位置。选择不同的NTC 热敏电阻和底部串联电阻可以改变甩负荷的温度阈值。
TPS2586x-Q1 具有四种可选的 USB 输出电压设置：5.1V、5.17V、5.3V 和 5.4V。TPS2586x-Q1 集成了一个精
密电流检测放大器，用于实现电缆压降补偿和USB 端口电流限制。电缆补偿仅在输出电压设置为 5.17V 时可用。
电缆补偿电压在 2.4A 输出电流时为 90mV。电缆补偿可使降压稳压器输出电压随负载电流线性改变，以抵消由于
汽车电缆布线中的导线电阻引起的压降，从而帮助便携式设备在重载下实现最佳电流和电压充电。无论负载电流
如何，在连接的便携式器件上测得的总线电压都保持大致恒定，这样，便携式器件的电池充电器就能够保持理想
工作状态。
TPS2586x-Q1 针对 USB 充电和系统运行提供多种安全特性，包括外部负热敏电阻监控、逐周期电流限制、断续
短路保护、欠压锁定、BUS 过流、OUT 过流以及裸片过热保护。
该器件系列可提供25 引脚3.5mm × 4.5mm QFN 封装。
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6 Device Comparison Table
DEVICE NUMBER
TPS25864-Q1
TPS25865-Q1
Type-A ports number
Dual
Yes
Dual
Yes
NTC Thermistor Input (TS)
DC/DC converter switching frequency range
BC1.2 DCP
200 kHz to approximately 3 MHz
200 kHz to approximately 800 kHz
Yes
Yes
Yes
Yes
Yes
Apple or Samsung charging scheme
Cable compensation
Yes
Yes(1)
Selectable output voltage
External clock synchronization
Yes
Yes, range 200 kHz to approximately 3
MHz
Yes, range 200 kHz to approximately 800
kHz
Adjustable output short current limit
FPWM/PFM
Yes
Yes
FPWM
FPWM
DCDC always ON (EN pull High)
Spread spectrum
Yes
No
Yes
Yes
Package
QFN-25 3.5 mm × 4.5 mm
QFN-25 3.5 mm × 4.5 mm
(1) VSET short to GND to set 5.17-V output voltage. Compensation voltage is 90 mV when either USB port A or USB port B output 2.4-A
current.
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7 Pin Configuration and Functions
PGND SW
IN
BOOT
21
VSET
1
24
23
22
TS
BIAS
EN/UV
2
20
3
FREQ/SYNC
PB_DP
19
18
PA_DP
4
5
PA_DM
PB_DM
PGND
CFG3
NC
17
16
25
11
6
7
AGND
CFG1
15
14
NC
8
10
12
9
13
CFG2
PB_BUS
OUT
PA_BUS SENSE
图7-1. TPS2586x-Q1 RPQ Package 25-Pin (QFN) Top View
表7-1. Pin Functions for TPS2586x-Q1 RPQ Package
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
Output Voltage Setting. Short to GND to set the 5.17-V output voltage. Float or pull up to
VSENSE to set 5.1-V output voltage. Tie to GND through a 40.2-KΩ resistor to set 5.3-V
output voltage. Tie to GND through a 80.6-KΩ resistor to set 5.4-V output voltage.
VSET
1
A
TS
2
3
A
P
Temperature Sense terminal. Connect the TS input to the NTC thermistor.
Input of internal bias supply. Must connect to the SENSE pin directly. Power the internal
circuit.
BIAS
PA_DP
PA_DM
AGND
CFG1
NC
4
5
A
A
P
A
A
A
P
D+ data line. Connect to USB Port A connector.
D- data line. Connect to USB Port A connector.
Analog ground terminal. Connect AGND to PGND.
Configuration pin. For internal circuit, must connect a 5.1-KΩresistor to AGND.
Makes no electrical connection.
6
7
8, 14
9
CFG2
Configuration pin. For internal circuit, must connect a 11.8-KΩresistor to AGND.
Port A BUS output.
PA_BUS
SENSE
PB_BUS
OUT
10
Output Voltage Sensing. External load on this pin is strictly prohibited. Connect to the
other side of the external inductor.
11
12
13
15
P
P
P
A
Port B BUS output.
Output pin. Provide 5.1-V voltage to power external load with maximum 200-mA capability.
The voltage follows the VSET setting.
CFG3
Configuration pin. For internal circuit, must connect a 5.1-KΩresistor to AGND.
Power Ground terminal. Connected to the source of LS FET internally. Connect to system
ground, AGND, and the ground side of the CIN and COUT capacitors. The path to CIN must
be as short as possible.
PGND
16, 24, 25
P
PB_DM
PB_DP
17
18
A
A
D- data line. Connect to USB port B connector.
D+ data line. Connect to USB port B connector.
Switching Frequency Program and External Clock Input. Connect a resistor from FREQ to
GND to set the switching frequency.
FREQ/ SYNC
EN/UV
19
20
A
A
Enable pin. Precision enable controls the regulator switching action. Do not float. High =
on, Low = off. Can be tied to SENSE directly. Precision enable input allows adjustable
UVLO by external resistor divider if tie to IN pin.
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表7-1. Pin Functions for TPS2586x-Q1 RPQ Package (continued)
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
Bootstrap capacitor connection. Internally, the BOOT is connected to the cathode of the
boost-strap diode. Connect the 0.1-μF bootstrap capacitor from SW to BOOT.
BOOT
21
P
Input power. Connected to external DC supply. Expected range of bypass capacitors is 1
μF to 10 μF, connect from IN to PGND. Can withstand up to 36 V without damage but
operating is suspended if VIN is above the 26-V OVP threshold.
IN
22
23
P
P
Switching output of the regulator. Internally connected to source of the HS FET and drain
of the LS FET. Connect to output inductor.
SW
(1) A = Analog, P = Power, G = Ground.
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8 Specifications
8.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of -40°C to +150°C and AGND = PGND (unless otherwise
noted)(1)
PARAMETER
IN to PGND
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
-0.3
MAX
40(2)
35
6
UNIT
IN to SW
BIAS, SENSE to PGND
EN to AGND
Input voltage
V
11
6
FREQ/SYNC to AGND
VSET to AGND
6
AGND to PGND
0.3
35
35
6
–0.3
–0.3
–3.5
–0.3
–0.3
–0.3
–0.3
–0.3
–35
-40
SW to PGND
SW to PGND (less than 10 ns transients)
BOOT to SW
Output voltage
Voltage range
V
V
PA_BUS, PB_BUS, OUT to PGND
CFG1, CFG2, CFG3 to AGND
DP, DM to AGND
6
6
6
Voltage range
I/O current
TJ
TS to AGND
6
V
DP to DM in BC1.2 DCP Mode
Junction temperature
Storage temperature
35
150
150
mA
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VIN rising slew rate below 20V/ms if in 0-V to 40-V transient, room temperature, maximum 500-uF cap at SENSE.
8.2 ESD Ratings
VALUE
±2000(2)
±750(3)
±750(3)
UNIT
Human body model (HBM), per AEC Q100-002(1)
V(ESD) Electrostatic discharge
Corner pins
V
Charged device model (CDM), per
AEC Q100-011
Other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) The passing level per AEC-Q100 Classification H2.
(3) The passing level per AEC-Q100 Classification C5
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8.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of -40°C to 150°C. Voltages are with respect to GND (unless
otherwise noted)
MIN
NOM
MAX UNIT
IN to PGND
5.5
26
EN
0
VSENSE
VI
Input voltage
V
TS
0
VSENSE
3.3
FREQ/SYNC when driven by external clock
0
VO
Output voltage
Output current
PA_BUS, PB_BUS, OUT
5
5.5
V
A
A
PA_BUS, PB_BUS
0
0
2.4
OUT
0.2
IO
DP to DM Continuous current in BC1.2 DCP Mode
15 mA
–15
0
RVSET
100
kΩ
kΩ
uF
REXT
External resistnace
External capacitance
RFREQ
0
100
CEXT
TJ
CBOOT
0.1
Operating junction temperature
150
°C
–40
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8.4 Thermal Information
TPS2586x-Q1
THERMAL METRIC(1) (2)
RPQ (VQFN)
25 PINS
37.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
17.2
8.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJT
8.8
ΨJB
RθJC(bot)
20.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Power rating at a specific ambient temperature TA should be determined with a maximum junction temperature of 150 °C.
8.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW = 400
kHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE (IN PIN)
Shutdown quiescent current;
measured at IN pin.
ISD
IQ
34
63
200
uA
µA
VEN/UV = 0, -40℃≤TJ ≤85℃
VEN = VSENSE, CFG1&CFG3 = open,
-40℃≤TJ ≤85℃
Operating quiescent current (DCDC
disable)
Voltage on VIN pin when buck
regulator stops switching
VOVLO_R
26.6
1.26
27.5
0.5
28.4
V
V
VOVLO_HYS
Hysteresis
ENABLE AND UVLO (EN/UVLO PIN)
Rising threshold for not in External
UVLO
VEN/UVLO_R
VEN/UV rising threshold
VEN/UVLO falling
1.3
1.34
V
VEN/UVLO_HYS
BOOTSTRAP
VBTST_UVLO
RBOOT
Hysteresis
100
mV
Bootstrap voltage UVLO threshold
Bootstrap pull-up resistence
2.2
7.7
V
VSENSE - BOOT = 0.1 V
Ω
BUCK REGULATOR
IL-SC-HS
IL-SC-LS
IL-NEG-LS
IZC
High-side current limit
BOOT - SW = 5 V
SENSE = 5 V
10.2
8.5
-7
11.4
10
12.6
11.5
-3
A
A
A
A
Low-side current limit
Low-side negative current limit
Zero current detector threshold
SENSE = 5 V
-5
0.01
CFG1 or CFG3 pulldown resistance =
5.1KΩ, VSET float or pull up to
VSENSE, TJ = 25℃
-1%
-1%
5.1
+1%
+1%
V
V
CFG1 or CFG3 pulldown resistance =
5.1KΩ, VSET short to AGND, TJ =
25℃
5.17
VSENSE
BUCK Output voltage
CFG1 or CFG3 pulldown resistance =
5.1KΩ, RVSET = 40.2KΩ, TJ = 25℃
-1%
-1%
5.3
5.4
+1%
+1%
V
V
CFG1 or CFG3 pulldown resistance =
5.1KΩ, RVSET = 80.6KΩ, TJ = 25℃
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8.5 Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW = 400
kHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CFG1 or CFG3 pulldown resistance =
Rd, -40℃≤TJ ≤150℃
VSENSE
BUCK Output voltage accuracy
2
%
V
–2
VSENSE rising, CFG1 or CFG3 pull
down resistance = 5.1KΩ
SENSE input level to enable DCDC
switching
VDCDC_UVLO_R
VDCDC_UVLO_HYS
VDROP
3.85
4
0.4
300
18
4.15
VSENSE falling, CFG1 or CFG3 pull
down resistance = 5.1KΩ
Hysteresis
V
VIN = VSENSE + VDROP, VSENS = 5.1 V,
IPA_BUS = 2.4A, IPB_BUS = 2.4A
Dropout voltage ( VIN-VSENSE
)
mV
mΩ
mΩ
IPA_BUS = 2.4 A, IPB_BUS = 2.4 A, BOOT
- SW = 5 V, -40℃≤TJ ≤150℃
RDS-ON-HS
RDS-ON-LS
High-side MOSFET ON-resistance
Low-side MOSFET ON-resistance
34
IPA_BUS = 2.4 A, IPB_BUS = 2.4 A,
VSENSE = 5 V, -40℃≤TJ ≤150℃
9.5
18.5
POWER SWITCH AND CURRENT LIMIT
USB Load Switch MOSFET ON-
resistance
IPA_BUS = 2.4 A, IPB_BUS = 2.4 A; -40℃
≤TJ ≤150℃
RDS-ON_USB
RDS-ON_OUT
VUSBLS_UVLO_R
6.8
230
4.1
11.73
4.25
mΩ
OUT Load Switch MOSFET ON-
resistance
IOUT = 0.3 A
mΩ
Voltage on SENSE pin that will enable
the USB Load Switch
3.95
V
VUSBLS_UVLO_HYS Hysteresis
200
4376
4376
2735
2735
450
mV
mA
mA
mA
mA
mA
3938
4157
2461
2598
390
4814
4595
3009
2872
495
BUS output short-circuit secondary
current limit
IOS_HI
TJ = 25℃
IOS_BUS
IOS_OUT
BUS output short-circuit current limit
OUT output short-circuit current limit
TJ = 25℃
Short circuit current limit
CABLE COMPENSATION VOLTAGE
IPA_BUS or IPB_BUS = 2.4A, VSET= GND
(set 5.17V output)
VDROP_COM
Cable compensation voltage
70
90
70
110
200
mV
BC 1.2 DOWNSTREAM CHARGING PORT
RDPM_SHORT
DIVIDER 3 MODE
VDP_DIV3
DP and DM shorting resistance
Ω
DP output voltage
2.57
2.57
24
2.7
2.7
30
2.84
2.84
36
V
V
VDM_DIV3
DM output voltage
DP output impedance
DM output impedance
RDP_DIV3
IDP_IN = –5 µA
IDM_IN = –5 µA
kΩ
kΩ
RDM_DIV3
24
30
36
1.2-V MODE
VDP_1.2V
DP output voltage
1.12
1.12
84
1.2
1.2
1.26
1.26
126
126
V
V
VDM_1.2V
DM output voltage
DP output impedance
DM output impedance
RDP_1.2V
100
100
IDP_IN = –5 µA
IDM_IN = –5 µA
kΩ
kΩ
RDM_1.2V
84
FREQ/SYNC THRESHOLD
FREQ/SYNC high threshold for
Amplitude of SYNC clock AC signal
(measured at FREQ/SYNC pin)
VIH_FREQ/SYNC
2
V
V
external clock synchronization
FREQ/SYNC low threshold for
external clock synchronization
Amplitude of SYNC clock AC signal
(measured at FREQ/SYNC pin)
VIL_FREQ/SYNC
0.8
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8.5 Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW = 400
kHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEMPERATURE SENSING
VWARN_HIGH Temperature warning threshold rising As percentage to VSENSE
VWARN_HYS
TEST CONDITIONS
MIN
TYP
MAX UNIT
0.475
0.5
0.1
0.525
0.683
V/V
V/V
Hysteresis
As percentage to VSENSE
As percentage to VSENSE
As percentage to VSENSE
Temperature Hot assert threshold
rising to reduce SENS voltage
VHOT_HIGH
VHOT_HYS
VR_VSENS
0.618
0.65
0.1
V/V
V/V
V
Hysteresis
VSENSE voltage decay when
Temperature Hot assert
TS pin voltage rise above 0.65 *
VSENSE
4.77
THERMAL SHUTDOWN
TLS_SD USB Load Switch Over Temperature
Shutdown threshold
Recovery threshold
Shutdown threshold
Recovery threshold
160
150
166
154
°C
°C
°C
°C
TSD
Thermal shutdown
8.6 Timing Requirements
Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)
MIN NOM MAX UNIT
BUS DISCHARGE
POWER SWITCH TIMING
Deglitch time for USB power switch current
limit enable
tIOS_HI_DEG
tIOS_HI_RST
tr_USB
USB port enter overcurrent
1.228 2.048 2.867 ms
MFI OCP reset timing
9.6
16 22.4 ms
CL = 1 µF, RL = 100 Ω(measured from 10%
to 90% of final value)
PA_BUS, PB_BUS voltage rise time
PA_BUS, PB_BUS voltage fall time
1.67
ms
ms
CL = 1 µF, RL = 100 Ω(measured from 90%
to 10% of final value)
tf_USB
0.49
ton_USB
toff_USB
PA_BUS, PB_BUS voltage turnon-time
PA_BUS, PB_BUS voltage turnoff-time
2.59
2.07
ms
ms
CL = 1 µF, RL = 100 Ω
CL = 1 µF, RL = 100 Ω
PA_BUS, PB_BUS short-circuit response
time
tIOS_USB
tr_OUT
1
us
CL = 1 µF, RL = 1 Ω
CL = 1 µF, RL = 100 Ω(measured from 10%
to 90% of final value)
OUT voltage rise time
OUT voltage fall time
0.12
0.16
0.2 0.28 ms
0.22 0.28 ms
CL = 1 µF, RL = 100 Ω(measured from 90%
to 10% of final value)
tf_OUT
ton_OUT
OUT voltage turnon-time
OUT voltage turnoff-time
OUT short-circuit response time
0.6
1.1 1.65 ms
0.54 0.62 ms
CL = 1 µF, RL = 100 Ω
CL = 1 µF, RL = 100 Ω
CL = 1 µF, RL = 1 Ω
toff_OUT
0.45
tIOS_OUT
1.4
4
us
HICCUP MODE
OUT, PA_BUS, PB_BUS output hiccup mode
ON time
THICP_ON
THICP_OFF
OC, VOUT, VPA_BUS, VPB_BUS drop 10%
2.94
367
4.1 5.42 ms
524 715 ms
OUT, PA_BUS, PB_BUS output hiccup mode OC, OUT, PA_BUS, PB_BUS connect to
OFF time
GND
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MAX UNIT
8.7 Switching Characteristics
Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SW (SW PIN)
TON_MIN
Minimum turnon-time
84
6
ns
µs
Maximum turnon-time, HS timeout in
dropout
TON_MAX
TOFF_MIN
Dmax
Minimum turnoff time
81
98
ns
%
Maximum switch duty cycle
TIMING RESISTOR AND INTERNAL CLOCK
Switching frequency range using
fSW_RANGE
200
200
800
kHz
kHz
9 kΩ≤RFREQ≤99 kΩ
FREQ mode (TPS25865-Q1)
Switching frequency range using
fSW_RANGE
3000
9 kΩ≤RFREQ≤99 kΩ
FREQ mode (TPS25864-Q1)
228
360
253
400
278
440
kHz
kHz
kHz
RFREQ = 80.6 kΩ
RFREQ = 49.9 kΩ
RFREQ = 8.45 kΩ
fSW
Switching frequency
fSW
Switching frequency (TPS25864-Q1)
1980
2200
2420
Frequency span of spread spectrum
operation
FSSS
±6
%
EXTERNAL CLOCK(SYNC)
Switching frequency using external
fFREQ/SYNC
clock on FREQ/SYNC pin (TPS25865-
Q1)
200
200
800
kHz
kHz
Switching frequency using external
clock on FREQ/SYNC pin (TPS25864-
Q1)
fFREQ/SYNC
3000
fSYNC = 400kHz, VFREQ/SYNC
>
TSYNC_MIN
TLOCK_IN
Minimum SYNC input pulse width
PLL lock time
VIH_FREQ/SYNC, VFREQ/SYNC < VIL_FREQ/
100
100
ns
µs
SYNC
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8.8 Typical Characteristics
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 3.3 µH, CSENSE = 141 µF, CPA_BUS
= 1 µF, CPB_BUS = 1 µF, TA = 25 °C.
70
60
50
40
30
20
1.36
1.34
1.32
1.3
-40C
25C
150C
Vin = 5.5V
Vin = 13.5V
Vin = 26V
1.28
1.26
4
8
12
16 20
Input Voltage (V)
24
28
32
-50
-25
0
25
Temperature (C)
50
75
100
125
150
图8-2. Precision Device Enable Threshold
VEN/EULVO = 0 V
图8-1. Shutdown Quiescent Current
5.2
5.19
5.18
5.17
5.16
5.15
5.14
5.46
Vin = 5.5V
Vin = 13.5V
Vin = 26V
Vin = 5.5V
Vin = 13.5V
Vin = 26V
5.44
5.42
5.4
5.38
5.36
5.34
-50
-25
0
25
Temperature (C)
50
75
100
125
150
-50
-25
0
25
Temperature (C)
50
75
100
125
150
VSET = GND
RVSET = 80.6 kΩ
图8-3. VSENSE Voltage vs Junction Temperature
图8-4. VSENSE Voltage vs Junction Temperature
3.94
11.7
-40C
25C
Vin = 5.5V
Vin = 13.5V
Vin = 26V
3.96
3.98
4
150C
11.6
11.5
11.4
11.3
11.2
4.02
4.04
4.06
-50
-25
0
25
Temperature (C)
50
75
100
125
150
4
8
12
16
Input Voltage (V)
20
24
28
图8-6. High-side Current Limit vs Input Voltage
VEN/EULVO = VSENSE
图8-5. DCDC UVLO Threshold
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8.8 Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 3.3 µH, CSENSE = 141 µF, CPA_BUS
= 1 µF, CPB_BUS = 1 µF, TA = 25 °C.
10.3
10.2
10.1
10
40
35
30
25
20
15
-40C
25C
150C
Vin = 5.5V
Vin = 13.5V
Vin = 26V
9.9
9.8
4
8
12
16
Input Voltage (V)
20
24
28
-50
-25
0
25
Temperature (C)
50
75
100
125
150
图8-7. Low-side Current Limit vs Input Voltage
IPA_BUS = 2.4 A
IPB_BUS = 2.4 A
图8-8. High-side MOSFET on Resistance vs Junction
Temperature
18
16
14
12
520
Vin = 5.5V
Vin = 13.5V
Vin = 26V
500
480
460
440
420
400
10
Vin = 5.5V
Vin = 13.5V
Vin = 26V
8
-50
-25
0
25
Temperature (C)
50
75
100
125
150
-50
-25
0
25
Temperature (C)
50
75
100
125
150
图8-10. OUT Power Switch Current Limit vs Junction
IPA_BUS = 2.4 A
IPB_BUS = 2.4 A
Temperature
图8-9. Low-side MOSFET on Resistance vs Junction
Temperature
100
96
92
88
84
80
9.6
8.8
8
7.2
6.4
Vin = 5.5V
Vin = 13.5V
Vin = 26V
5.6
4.8
-50
-25
0
25
Temperature (C)
50
75
100
125
150
-50
-25
0
25
Temperature (C)
50
75
100
125
150
图8-12. USB Power Switch On Resistance vs Junction
IPA/B_BUS = 2.4 A
VSET = GND
Temperature
图8-11. Cable Compensation Voltage vs Junction Temperature
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8.8 Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 3.3 µH, CSENSE = 141 µF, CPA_BUS
= 1 µF, CPB_BUS = 1 µF, TA = 25 °C.
400
360
320
280
240
200
160
424
416
408
400
392
384
376
Vin = 5.5V
Vin = 13.5V
Vin = 26V
Vin = 5.5V
Vin = 13.5V
Vin = 26V
-50
-25
0
25
Temperature (C)
50
75
100
125
150
-50
-25
0
25
Temperature (C)
50
75
100
125
150
图8-13. OUT Power Switch On Resistance vs Junction
RFREQ = 49.9 kΩ
Temperature
图8-14. Switching Frequency vs Junction Temperature
0.72
0.7
4.82
4.8
4.78
4.76
4.74
4.72
4.7
0.68
0.66
0.64
0.62
0.6
-50
-25
0
25
Temperature (C)
50
75
100
125
150
-50
-25
0
25
Temperature (C)
50
75
100
125
150
图8-15. TS Temperature Hot Threshold vs Junction
图8-16. SENSE Voltage in Temperature Hot vs Junction
Temperature
Temperature
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9 Parameter Measurement Information
OUT
90%
R(L)
tr
C(L)
tf
V(OUT)
10%
图9-1. OUT Rise-Fall Test Load Figure
图9-2. Power-On and Power-Off Timing
V(EN)
50%
50%
5 V
ton
toff
t(DCHG)
V(OUT)
90%
V(OUT)
0 V
10%
图9-3. OUT Discharge During Mode Change
图9-4. Enable Timing, Active-High Enable
IOS
I(OUT)
t(IOS)
图9-5. Output Short-Circuit Parameters
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10 Detailed Description
10.1 Overview
The TPS2586x-Q1 is a full-featured solution for implementing a compact USB charging port with support BC1.2
standards. The device contain an efficient buck regulator power source. For dual Type-A ports, the TPS2586x-
Q1 is capable of providing up to 5 A of output current at 5.17 V (nominal), 2.4 A for each Type-A port, 200 mA for
the OUT pin. The TPS2586x-Q1 is an automotive-focused USB charging controller and offers a robust solution,
so TI recommends to add adequate protection (TVS3300 equivalent or better but auto qualified) on the IN pin to
protect systems from high-power transients or lightning strikes.
System designers can optimize efficiency or solution size through careful selection of switching frequency in the
range of 200 kHz–2400 kHz with sufficient margin to operate above or below the AM radio frequency band.
TPS2586x-Q1 protects itself with internal thermal sensing circuits that monitor the operating temperature of the
junction and disables operation if the temperature exceeds the Thermal Shutdown threshold, so in high ambient
temperature application, the 5-A output current capability is not assured. In the TPS2586x-Q1, the buck regulator
operates in forced PWM mode, ensuring fixed switching frequency regardless of load current. Spread-spectrum
frequency dithering reduces harmonic peaks of the switching frequency, potentially simplifying EMI filter design
and easing compliance.
Current sensing through a precision FET current sense amplifier on the USB port enables an accurate
overcurrent limit setting and linear cable compensation to overcome IR losses when powering remote USB ports.
The TPS2586x-Q1 includes a TS input for user-programmable thermal protection using a negative temperature
coefficient (NTC) resistor.
The device can support the legacy Battery Charging Specification Rev 1.2 (BC1.2) DCP mode with an auto-
detect feature to charge not only BC1.2-compliant handheld devices, but also popular phones and tablets that
incorporate their own propriety charging algorithm.
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10.2 Functional Block Diagram
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10.3 Feature Description
10.3.1 Power-Down or Undervoltage Lockout
The device is in low power mode if the IN terminal voltage is less than VUVLO, so the part is considered dead
and all the terminals are high impedance. Once the IN voltage rises above the VUVLO threshold, the IC enters
sleep mode or active mode, depending on the EN/UVLO voltage.
The voltage on the EN/UVLO pin controls the ON/OFF operation of the TPS2586x-Q1. An EN/UVLO pin voltage
higher than VEN/UVLO-H is required to start the internal regulator. The internal USB monitoring circuitry is on when
VIN is within the operation range and the EN/UVLO threshold is cleared.
The EN/UVLO pin is an input and cannot be left open or floating. The simplest way to enable the operation of the
TPS2586x-Q1 is to connect EN to SENSE. This connection allows self-startup of the TPS2586x-Q1 when VIN is
within the operation range. Note that you cannot connect the EN to IN pin directly for self-startup.
Many applications benefit from the employment of enable dividers RENT and RENB to establish a precision
system UVLO level for the TPS2586x-Q1 shown in 图 10-1. The system UVLO can be used for sequencing,
ensuring reliable operation, or supply protection, such as a battery discharge level. To ensure the USB port VBUS
is within the 5-V operating range as required for USB compliance (for the latest USB specifications and
requirements, refer to USB.org), TI suggests that the RENT and RENB resistors be chosen such that the
TPS2586x-Q1 enables when VIN is approximately 6 V. Considering the dropout voltage of the buck regulator and
IR losses in the system, 6 V provides adequate margin to maintain VBUS within USB specifications. If system
requirements, such as a warm crank (start) automotive scenario, require operation with VIN < 6 V, the values of
RENT and RENB can be calculated assuming a lower VIN. An external logic signal can also be used to drive the
EN/UVLO input when a microcontroller is present and it is desirable to enable or disable the USB port remotely
for other reasons.
IN
RENT
EN
RENB
图10-1. System UVLO by Enable Divider
UVLO configuration using external resistors is governed by the following equations:
VIN ON
≈
’
÷
◊
(
)
RENT
=
- 1 ì R
∆
÷
ENB
∆
VEN/UVLO _H
«
(1)
(2)
≈
’
VEN/UVLO _HYS
VIN OFF = VIN ON ì 1 -
∆
÷
÷
(
)
(
)
∆
VEN/UVLO _H
«
◊
For example:
VIN(ON) = 6 V
RENT = 20 kΩ
RENB = [(VEN-VOUT-H) / (VIN(ON) –VEN)] × RENT
(3)
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RENB = 5 kΩ
Therefore, VIN(OFF) = 5.5 V
10.3.2 Input Overvoltage Protection (OVP) - Continuously Monitored
The operation voltage range of the TPS2586x-Q1 is up to 26 V. If the input source applies an overvoltage, the
buck regulator HSFET/LSFET turns off immediately. Thus, the USB ports and OUT pin loses their power as well.
Once the overvoltage returns to a normal voltage, the buck regulator continues switching and provides power on
the USB ports and OUT pin.
During the overvoltage condition, the internal regulator regulates the SENSE voltage at 5 V, so the SENSE
always has power for the internal bias circuit and external NTC pullup reference.
10.3.3 Buck Converter
The following operating description of the TPS2586x-Q1 refers to the Functional Block Diagram.
The TPS2586x-Q1 integrates a monolithic, synchronous, rectified, step-down, switch-mode converter with
internal power MOSFETs and USB current-limit switches with charging ports auto-detection. The TPS2586x-Q1
offers a compact solution that achieves up to 5 A of continuous output current with excellent load and line
regulation over a wide input supply range. The TPS2586x-Q1 supplies a regulated output voltage by turning on
the high-side (HS) and low-side (LS) NMOS switches with controlled duty cycle. During high-side switch ON
time, the SW pin voltage swings up to approximately VIN. The inductor current, iL, increases with linear slope
(VIN – VOUT ) / L. When the HS switch is turned off by the control logic, the LS switch is turned on after an anti-
shoot-through dead time. Inductor current discharges through the LS switch with a slope of –VOUT / L. The
control parameter of a buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side switch
ON time and TSW is the switching period, shown in 图 10-2. The regulator control loop maintains a constant
output voltage by adjusting the duty cycle D. In an ideal buck converter, where losses are ignored, D is
proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN.
VSW
D = tON/ TSW
VIN
tON
tOFF
t
0
-VD
TSW
iL
ILPK
IOUT
DiL
t
0
图10-2. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The TPS2586x-Q1 operates in a fixed-frequency, peak-current-mode control to regulate the output voltage. A
voltage feedback loop is used to get accurate DC voltage regulation by adjusting the peak current command
based on voltage offset. The peak inductor current is sensed from the high-side switch and compared to the
peak current threshold to control the ON time of the high-side switch. The voltage feedback loop is internally
compensated, which allows for fewer external components, making it easy to design, and provides stable
operation with a reasonable combination of output capacitors. The TPS2586x-Q1 operates in FPWM mode for
low output voltage ripple, tight output voltage regulation, and constant switching frequency.
10.3.4 FREQ/SYNC
The switching frequency of the TPS2586x-Q1 can be programmed by the resistor, RFREQ, from the FREQ/SYNC
pin and AGND pin. To determine the FREQ resistance for a given switching frequency, use 方程式4:
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-1.0483
RFREQ kW = 26660ì ƒ
kHz
SW
(4)
70
65
60
55
50
45
40
35
30
25
20
15
10
5
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Switching Frequency (kHz)
D024
图10-3. FREQ Set Resistor vs Switching Frequency
The normal method of setting the buck regulator switching frequency is by selecting an appropriate value FREQ
resistor. The typical FREQ resistors value are listed in 表 10-1. Please note that TPS25865-Q1 can only support
frequency up to 800 kHz.
表10-1. Setting the Switching Frequency With FREQ
SWITCHING FREQUENCY (KHz)
FREQ (KΩ)
80.6
253
400
49.9
19.1
1000
2100
2200
8.87
8.45
The FREQ/SYNC pin can be used to synchronize the internal oscillator to an external clock. The internal
oscillator can be synchronized by AC coupling a positive edge into the FREQ/SYNC pin. When using a low
impedance signal source, the frequency setting resistor, FREQ, is connected in parallel with an AC coupling
capacitor, CCOUP, to a termination resistor, RTERM (for example, 50 Ω). The two resistors in series provide the
default frequency setting resistance when the signal source is turned off. A 10-pF ceramic capacitor can be used
for CCOUP. The AC coupled peak-to-peak voltage at the FREQ/SYNC pin must exceed the SYNC amplitude
threshold of 1.2 V (typical) to trip the internal synchronization pulse detector, and the minimum SYNC clock
HIGH and LOW time must be longer than 100 ns (typical). A 2.5 V or higher amplitude pulse signal coupled
through a 1-nF capacitor, CSYNC, is a good starting point. 图 10-4 shows the device synchronized to an external
system clock. The external clock must be off before startup to allow proper startup sequencing.
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CCOUP
RT
PLL
PLL
Lo-Z
Hi-Z
Clock
Source
FREQ/
FREQ/
SYNC
Clock
RTERM
RT
SYNC
Source
图10-4. Synchronize to External Clock
TPS25864-Q1 switching action can be synchronized to an external clock from 200 KHz to 3 MHz. TPS25865-Q1
switching action can be synchronized to an external clock from 200 KHz to 800 kHz. Note the higher switching
frequency results in more power loss on IC, causing the junction temperature and also the board temperature
rising. Then, the device can enter load shedding under high ambient temperature.
10.3.5 Bootstrap Voltage (BOOT)
The TPS2586x-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is
100 nF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended for stable performance over temperature and voltage. The BOOT rail has a UVLO to protect the
chip from operation with too little bias and is typically 2.2 V. If the BOOT capacitor voltage drops below the UVLO
threshold, the device initiates a charging sequence using the low-side FET before attempting to turn on the high-
side device.
10.3.6 Minimum ON-Time, Minimum OFF-Time
Minimum ON-time, TON_MIN, is the smallest duration of time that the HS switch can be on. TON_MIN is typically 84
ns in the TPS2586x-Q1. Minimum OFF-time, TOFF_MIN, is the smallest duration that the HS switch can be off.
TOFF_MIN is typically 81 ns in the TPS2586x-Q1. In CCM (FPWM) operation, TON_MIN and TOFF_MIN limit the
voltage conversion range given in a selected switching frequency.
The minimum duty cycle allowed is:
DMIN = TON_MIN × fSW
(5)
And the maximum duty cycle allowed is:
DMAX = 1 –TOFF_MIN × fSW
(6)
Given fixed TON_MIN and TOFF_MIN, the higher the switching frequency, the narrower the range of the allowed
duty cycle.
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size, and efficiency. The maximum operation supply voltage can be found by:
VOUT
V
=
IN_MAX
f
ì TON_MIN
SW
(7)
At lower supply voltage, the switching frequency is limited by TOFF_MIN. The minimum VIN can be approximated
by:
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VOUT
V
=
IN_MIN
1- f
ì TOFF _MIN
SW
(8)
Considering power losses in the system with heavy load operation, VIN_MAX is higher than the result calculated in
方程式7.
If minimum ON-time or minimum OFF-time do not support the desired conversion ratio, frequency is reduced,
automatically allowing regulation to be maintained during load dump and with very low dropout during cold crank
even with high operating-frequency setting.
10.3.7 Internal Compensation
The TPS2586x-Q1 is internally compensated. The internal compensation is designed such that the loop
response is stable over the specified operating frequency and output voltage range. TPS25865-Q1 is optimized
for transient response over the range of 200 kHz ≤ fsw ≤ 800 kHz.TPS25864-Q1 is optimized for transient
response over the range of 200 kHz ≤fsw ≤3 MHz.
10.3.8 Selectable Output Voltage (VSET)
The TPS2586x-Q1 provides four different output voltage options. The voltage can be set by an external resistor
across the VSET pin. The normal method of setting the buck output voltage is by selecting an appropriate value
VSET resistor as shown in 表10-2.
表10-2. VSET Configuration vs BUS Output Voltage
VSET CONFIGURATION
Float or pull up to VSENSE
Short to GND
VSENSE
5.1 V
5.17 V
5.3 V
RVSET = 40.2 KΩ
5.4 V
RVSET = 80.6 KΩ
Note that the VSET has an internal weak 20-µA current source to overdrive the pin to SENSE. If this pin is
floated, the voltage on this pin approaches the SENSE voltage, and sets the output voltage to 5.1 V. TI does not
recommend to float this pin if there is external noise from the PCB board because the noise interferes with the
VSET internal logic block.
10.3.9 Current Limit and Short Circuit Protection
For maximum versatility, the TPS2586x-Q1 includes both a precision, fixed current limit as well cycle-by-cycle
current limit to protect the USB port from extreme overload conditions. The cycle-by-cycle current limit serves as
a backup means of protection.
10.3.9.1 USB Switch Current Limit
Because the TPS2586x-Q1 integrates two USB current-limit switches, it provides current limit to prevent USB
port overheating. The USB current limit threshold is fixed at 2.73 A with a maximum ±10% variation
overtemperature on each USB port to follow the Type-A specification. The TPS2586x-Q1 provides built-in soft-
start circuitry that controls the rising slew rate of the output voltage to limit inrush current and voltage surges.
The TPS2586x-Q1 engages the two-level current limit scheme, which has one typical current limit, IOS_BUS, and
the secondary current limit, IOS_HI. The secondary current limit, IOS_HI, is 1.6x the primary current limit,
IOS_BUS.The secondary current limit acts as the current limit threshold for a deglitch time, tIOS_HI_DEG, then the
USB power switch current limit threshold is set back to IOS_BUS
.
The secondary current limit, IOS_HI, allows the USB port pull out a larger current for a short time during transient
overload conditions, which can bring benefits for USB port special overload testing like MFi OCP. In a normal
application, once the device is powered on and USB port is not in UVLO, the USB port current limit threshold is
overridden by the secondary current limit, IOS_HI, so the USB port can output as high as a 1.6 × IOS_BUS current
for typically 2 ms. After the deglitch time, tIOS_HI_DEG, the current limit threshold is set back to the typical current
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with IOS_BUS. The secondary current limit threshold does not resume until after the tIOS_HI_RST deglitch time,
which is typically 16 ms. If there is an inrush current higher than the IOS_HI threshold, the current limit is set back
to IOS_BUS immediately, without waiting for a tIOS_HI_DEG
.
The TPS2586x-Q1 responds to overcurrent conditions by limiting output current to IOS_BUS as shown in previous
equation. When an overload condition occurs, the device maintains a constant output current and the output
voltage reduces accordingly. Three possible overload conditions can occur:
• The first condition is when a short circuit or overload is applied to the USB output when the device is powered
up or enabled. There can be inrush current and once it triggers the approximate 8-A threshold. A fast turnoff
circuit is activated to turn off the USB power switch within tIOS_USB before the current limit control loop is able
to respond (shown in 图10-5). After the fast turnoff is triggered, the USB power switch current-sense
amplifier is over-driven during this time and momentarily disables the internal N-channel MOSFET to turn off
USB port. The current-sense amplifier then recovers and ramps the output current with a soft start. If the USB
port is still in overcurrent condition, the short circuit and overload hold the output near zero potential with
respect to ground and the power switch ramps the output current to IOS_BUS. If the overcurrent limit condition
lasts longer than 4.1 ms, the corresponding USB channel enters hiccup mode with 524 ms of off-time and 4.1
ms of on-time.
IBUS
IOS_BUS
t
hiccup OFF
hiccup ON
tIOS
图10-5. Response Time to BUS Short-Circuit
• The second condition is the load current increases above IOS_BUS but below the IOS_HI setting. The device
allows the USB port to output this large current for tIOS_HI_DEG, without limiting the USB port current to
IOS_BUS. After the tIOS_HI_DEG deglitch time, the device limits the output current to IOS_BUS and works in a
constant current-limit mode. If the load demands a current greater than IOS_BUS, the USB output voltage
decreases to IOS_BUS × RLOAD for a resistive load, which is shown in 图10-6. If the overcurrent limit condition
lasts longer than 4.1 ms, the corresponding USB channel enters hiccup mode with 524 ms of off-time and 4.1
ms of on-time. Another USB channel still works normally.
I
BUS(A)
V
BUS(V)
5
IOS_HI
IOS_BUS
0
hiccup OFF
hiccup OFF
hiccup ON
hiccup ON
tIOS_HI_DEG
t
图10-6. BUS Overcurrent Protection
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• The third condition is the load current increases just over the IOS_HI setting. In this case, the load current does
not trigger the fast turnoff. The USB power switch current limit threshold is set back to the primary current
limit, IOS_BUS, immediately. If the load still demands a current greater than IOS_BUS, the USB output voltage
decreases to IOS_BUS × RLOAD for a resistive load, which is shown in 图10-7. If the overcurrent limit condition
lasts longer than 4.1 ms, the corresponding USB channel enters hiccup mode with 524 ms of off-time and 4.1
ms of on-time. Another USB channel still works normally.
I
BUS(A)
V
BUS(V)
5
IOS_HI
IOS_BUS
0
hiccup OFF
hiccup OFF
hiccup ON
hiccup ON
t
图10-7. BUS Overcurrent Protection: Two-Level Current Limit
The TPS2586x-Q1 thermal cycles if an overload condition is present long enough to activate thermal limiting in
any of the previously mentioned cases. Thermal limiting turns off the internal NFET and starts when the NFET
junction temperature exceeds 160°C (typical). The device remains off until the NFET junction temperature cools
10°C (typical) and then restarts. This extra thermal protection mechanism can help prevent further junction
temperature rise, which can cause the device to turn off due to junction temperature exceeding the main thermal
shutdown threshold, TSD
.
10.3.9.2 Interlocking for Two-Level USB Switch Current Limit
The TPS2586x-Q1 has two USB ports. Because the secondary current limit, IOS_HI, is 1.6x of the primary current
limit, IOS_BUS, if the two USB ports pull out large current at the same time, then the DC-DC regulator is
overloaded, and DC-DC regulator output voltage can be crashed. To avoid these potential issues, the
TPS2586x-Q1 adopts the interlocking scheme to manage the current limits of the two USB ports.
For interlocking, if one USB port current is beyond the primary current limit threshold, IOS_BUS, then another USB
port current limit threshold is overridden to the primary current limit, IOS_BUS, immediately. With this control
scheme, the TPS2586x-Q1 only allows one USB port to output a large current, which can be as high as 1.6x of
the primary current limit, IOS_BUS, at the same time. Ensure the DC-DC regulator has enough energy to sustain
its output voltage.
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10.3.9.3 Cycle-by-Cycle Buck Current Limit
There is a buck regulator cycle-by-cycle current limit on both the peak and valley of the inductor current.
High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. The peak
current of HS switch is limited by a clamped maximum peak current threshold, IHS_LIMIT, which is constant. The
peak current limit of the high-side switch is not affected by the slope compensation and remains constant over
the full duty cycle range.
The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor
current begins to ramp down. The LS switch does not turn OFF at the end of a switching cycle if its current is
above the LS current limit, ILS_LIMIT. The LS switch is kept ON so that the inductor current keeps ramping down
until the inductor current ramps below the LS current limit, ILS_LIMIT. Then, the LS switch is turned OFF and the
HS switch is turned on after a dead time. This action is somewhat different than the more typical peak current
limit and results in 方程式9 for the maximum load current.
V
IN - VOUT
(
)
ì
VOUT
IOUT _MAX = ILS _LIMIT
+
2ì fSW ìL
V
IN
(9)
10.3.9.4 OUT Current Limit
The TPS2586x-Q1 can provide 200-mA current at the OUT pin to power the auxiliary loads, such as USB HUB,
LEDs. The input of the OUT power switch comes from the buck regulator output, so the OUT voltage is the same
with the SNESE voltage but deducts the OUT RDS-ON voltage loss.
If the OUT current reaches the current limit level, the OUT pin MOSFET works in a constant current-limit mode.
If the overcurrent limit condition lasts longer than 4.1 ms, it enters hiccup mode with 4.1 ms of on-time and 524
ms of off-time.
10.3.10 Cable Compensation
When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to
the load. In the vehicle from the voltage regulator output VOUT to VBUS (input voltage of portable device), the total
resistance of PCB trace, connector, and cable resistances causes an IR drop at the portable device input, so the
charging current of most portable devices is less than their expected maximum charging current. The voltage
drop is shown in 图10-8.
5.x
V(DROP)
VOUT with compensation
VBUS with compensation
VBUS without compensation
3
1
2
Output Current (A)
图10-8. Voltage Drop
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To handle this case, the TPS2586x-Q1 has a built-in cable compensation function where the droop
compensation linearly increases the voltage at the SENSE pin of the TPS2586x-Q1 as load current increases, to
maintain a fairly constant output voltage at the load-side voltage.
For the TPS2586x-Q1, the internal comparator compares the current-sense output voltage of the two current-
limit switches and uses the larger current-sense output voltage to compensate for the line drop voltage. The
cable compensation amplitude increases linearly as the load current increases. The cable compensation also
has an upper limitation. The cable compensation at output currents greater than 2.4 A is 90 mV and is shown in
图 10-9. Note the cable compensation only works when you short the VSET to GND. For the other VSET
configuration, the cable compensation is not available.
VSENSE
5.26V
5.17V
IPA/B_BUS
2.4A
图10-9. Dual Ports Cable Compensation
10.3.11 Thermal Management With Temperature Sensing (TS) and OTSD
The TS input pin allows for user-programmable thermal protection (for the TS pin thresholds, see the Electrical
Characteristics section). The TS input pin threshold is ratiometric with VSENSE. The external resistor divider
setting, VTS, must be connected to the TPS2586x-Q1 SENSE pin to achieve accurate results (refer to the 图
10-10).
VSENSE
RSER
VSENSE
RPARA
RNTC
RB
TS
CC override
(3A -> 1.5A)
Vth9 ≈ 0.5 x VSENSE
Vhys ≈ 500mV
TS_TEMP_HOT
Vth9 ≈ 0.65 x VSENSE
Vhys ≈ 500mV
图10-10. TS Input
If the overtemperature condition happens, causing VTS = 0.65 × VSENSE, the TPS2586x-Q1 reduces the BUCK
regulator output voltage to 4.77 V.
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If the Overtemperature condition persists, causing TJ to reach the OTSD threshold, then the device thermal
shuts down.
The NTC thermistor must be placed near the hottest point on the PCB. In most cases, this placement is close to
the SW node of the TPS2586x-Q1, near the buck inductor.
10.3.12 Thermal Shutdown
The device has an internal overtemperature shutdown threshold, TSD, to protect the device from damage and
overall safety of the system. When the device temperature exceeds TSD, the device is turned off when thermal
shutdown activates. Once the die temperature falls below 154°C (typical), the device re-initiates the power-up
sequence controlled by the internal soft-start circuitry.
10.3.13 USB Specification Overview
All USB ports are capable of providing a 5-V output, making them a convenient power source for operating and
charging portable devices. USB specification documents outline specific power requirements to ensure
interoperability. In general, a USB 2.0 port host port is required to provide up to 500 mA; a USB 3.0 or USB 3.1
port is required to provide up to 900 mA; ports adhering to the USB Battery Charging 1.2 Specification provide
up to 1500 mA; newer Type-C ports can provide up to 3000 mA. Though USB standards governing power
requirements exist, some manufacturers of popular portable devices created their own proprietary mechanisms
to extend allowed available current beyond the 1500-mA maximum per BC 1.2. While not officially part of the
standards maintained by the USB-IF, these proprietary mechanisms are recognized and implemented by
manufacturers of USB charging ports.
The TPS2586x-Q1 device supports four of the most-common USB-charging schemes found in popular hand-
held media and cellular devices:
• USB Battery Charging Specification BC1.2 DCP mode
• Chinese Telecommunications Industry Standard YD/T 1591-2009
• Divider 3 mode
• 1.2-V mode
10.3.14 USB Port Operating Modes
10.3.14.1 Dedicated Charging Port (DCP) Mode
A DCP only provides power and does not support data connection to an upstream port. As shown in the
following sections, a DCP is identified by the electrical characteristics of the data lines. TPS2586x-Q1 only
emulates one state, DCP-auto state. In the DCP-auto state, the device charge-detection state machine is
activated to selectively implement charging schemes involved with the shorted, Divider 3 and 1.2-V modes. The
shorted DCP mode complies with BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591-2009,
whereas the Divider 3 and 1.2-V modes are employed to charge devices that do not comply with the BC1.2 DCP
standard.
10.3.14.1.1 DCP BC1.2 and YD/T 1591-2009
Both standards specify that the D+ and D– data lines must be connected together with a maximum series
impedance of 200 Ω, as shown in 图10-11.
VBUS
5 V
D–
200 Ω
(ma x.)
D+
GND
图10-11. DCP Supporting BC1.2 and YD/T 1591-2009
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10.3.14.1.2 DCP Divider-Charging Scheme
The device supports Divider 3, as shown in 图10-12. In the Divider 3 charging scheme, the device applies 2.7 V
and 2.7 V to D+ and D–data lines.
VBUS
5 V
D–
D+
2.7 V
2.7 V
GND
图10-12. Divider 3 Mode
10.3.14.1.3 DCP 1.2-V Charging Scheme
The DCP 1.2-V charging scheme is used by some hand-held devices to enable fast charging at 2 A. The
TPS2586x-Q1 device supports this scheme in DCP-auto state before the device enters BC1.2 shorted mode. To
simulate this charging scheme, the D+ and D– lines are shorted and pulled up to 1.2 V for a fixed duration.
Then the device moves to DCP shorted mode as defined in the BC1.2 specification and as shown in 图10-13.
VBUS
5 V
200 Ω (ma x.) D–
D+
1.2 V
GND
图10-13. 1.2-V Mode
10.3.14.2 DCP Auto Mode
The TPS2586x-Q1 device integrates an auto-detect state machine that supports all the DCP charging schemes
as shown in 图 10-14. The auto-detect state machine starts in the Divider 3 scheme. If a BC1.2 or YD/T
1591-2009 compliant device is attached, the TPS2586x-Q1 device responds by turning the power switch back
on without output discharge and operating in 1.2-V mode briefly before entering BC1.2 DCP mode. Then, the
auto-detect state machine stays in that mode until the device releases the data line, in which case, the auto-
detect state machine goes back to the Divider 3 scheme. When a Divider 3-compliant device is attached, the
TPS2586x-Q1 device stays in the Divider 3 state.
5 V
S1
Divider 3 Mode
VBUS
S1, S2: ON
S3, S4: OFF
DM_IN
DP_IN
GND
D–
D+
S2
S3
S4
Shorted Mode
S4 ON
S1, S2, S3: OFF
GND
1.2-V Mode
S1, S2: OFF
S3, S4: ON
2.7 V 2.7 V 1.2 V
图10-14. DCP Auto Mode
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10.4 Device Functional Modes
10.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the TPS2586x-Q1. When VEN is below 1.2 V (typical), the
device is in shutdown mode. The TPS2585x-Q1 also employs VIN overvoltage lock out protection and VSENSE
undervoltage lock out protection. If VIN voltage is above its respective OVLO level, VOVLO, or VSENSE voltage is
below its respective UVLO level, VDCDC_UVLO, the DC/DC converter turns off.
10.4.2 Active Mode
The TPS2586x-Q1 is in active mode when VEN is above the precision enable threshold and VSENSE is above its
respective UVLO levels. The simplest way to enable the TPS2586x-Q1 is to connect the EN pin to SENSE pin.
This connection allows self startup when the input voltage is in the operating range (5.5 V to 26 V) and a UFP
detection is made.
In active mode, the TPS25865-Q1 buck regulator does not operate unless CFG1/3 resistors are attached, the
TPS25854-Q1 buck regulator operates even though CFG1/3 resistors are not attached. Then the buck regulator
operates with Forced Pulse Width Modulation (FPWM), also referred to as Forced Continuous Conduction Mode
(FCCM). This operation ensures the buck regulator switching frequency remains constant under all load
conditions. FPWM operation provides low output voltage ripple, tight output voltage regulation, and constant
switching frequency. Built-in spread-spectrum modulation aids in distributing spectral energy across a narrow
band around the switching frequency programmed by the FREQ/SYNC pin. Under light load conditions the
inductor current is allowed to go negative. A negative current limit of IL-NEG-LS is imposed to prevent damage to
the regulator's low side FET. During operation, the TPS2586x-Q1 synchronizes to any valid clock signal on the
FREQ/SYNC input.
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11 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
11.1 Application Information
The TPS2586x-Q1 is a step down DC-to-DC regulator and USB charge port controller. The TPS2586x-Q1 is
typically used in automotive systems to convert a DC voltage from the vehicle battery to 5-V DC with a maximum
output current of 5 A in dual Type-A ports applications. The TPS2586x-Q1 engages a high efficiency buck
converter, letting the device operate at as high as 85°C ambient temperature with full load. The following design
procedure can be used to select components for the TPS2586x-Q1.
11.2 Typical Applications
The TPS2586x-Q1 only requires a few external components to convert from a wide voltage range supply to a 5-
V output to power USB devices. 图 11-1 shows the TPS2586x-Q1 typical application schematic for Dual Type-A
charging ports under 400-kHz operating frequency.
图11-1. TPS2586x-Q1 Typical Application Circuit for 400-KHz fSW
As a quick start guide, 表 11-1 provides typical component values for some of the most common configurations.
The values given in 表 11-1 are typical. Other values can be used to enhance certain performance criterion as
required by the application. The integrated buck regulator of TPS2586x-Q1 is internally compensated and
optimized for a reasonable selection of external inductance and capacitance. The external components have to
fulfill the needs of the application, but also the stability criteria of the control loop of the device.
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表11-1. L and COUT Typical Values
VOUT WITHOUT CABLE
COMPENSATION
fSW
L
CHF + CIN
CBOOT
RATED COUT
400 KHZ
2.1 MHz
5.17 V
5.17 V
3.3 µH
1 × 100 nF + 1 × 47 µF
1 × 100 nF + 1 × 22 µF
1 × 100 nF
1 × 100 nF
3 × 47 µF
3 × 22 µF
0.68 µH
1. The inductance value is calculated based on max VIN = 18 V.
2. All the COUT values are after derating and use low ESR ceramic capacitors.
3. The COUT is the buck regulator output capacitors at the SENSE pin.
11.2.1 Design Requirements
The detailed design procedure is described based on a design example. For this design example, use the
parameters listed in 表11-2 as the input parameters.
表11-2. Design Example Parameters
Input voltage, VIN
13.5-V typical, range from 8 V to 18 V
Output voltage, VSENSE
Maximum output current
Switching frequency, fSW
5.17 V
5 A
400 KHz
11.2.2 Detailed Design Procedure
11.2.2.1 Output Voltage Setting
The output voltage of TPS2586x-Q1 is programmed by the VSET pin, and if short VSET to GND sets the output
voltage at 5.17 V and enables the cable compensation function, the output voltage increases linearly with
increasing load current. Refer to List item for more details on output voltage setting. Cable compensation can be
used to increase the voltage on the SENSE pin linearly with increasing load current. Refer to List
item.referenceTitle for more details on cable compensation setting. If cable compensation is not desired, use a
0-ΩRIMON resistor.
11.2.2.2 Switching Frequency
The recommended switching frequency of the TPS2586x-Q1 is in the range of 250 KHz–400 KHz for high
efficiency. Choose RFREQ = 49.9 kΩ for 400-KHz operation. To choose a different switching frequency, refer to
表10-1.
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence, a
more compact design. In automotive USB charging applications, switching frequency tends to operate at either
400 kHz below the AM band, or 2.1 MHz above the AM band. In this example, 400 kHz is chosen.
11.2.2.3 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current, and the rated current. The
inductance is based on the desired peak-to-peak ripple current, ΔiL. Because the ripple current increases with
the input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use 方
程式 11 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current of the device. A reasonable value of KIND must be
20% to 40%. Note that when selecting the ripple current for applications with much smaller maximum load than
the maximum available from the device, the maximum device current must still be used. During an instantaneous
short or overcurrent operation event, the RMS and peak inductor current can be high. The inductor current rating
must be higher than the current limit of the device.
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VOUT ì V
- VOUT
(
)
IN_MAX
DiL =
VIN_MAX ìL ì fSW
(10)
(11)
V
- VOUT
VOUT
IN_MAX
LMIN
=
ì
IOUT ìKIND
V
IN_MAX ì fSW
In general, choose lower inductance in switching power supplies because it usually corresponds to faster
transient response, smaller DCR, and reduced size for more compact designs. Too low of an inductance can
generate too large of an inductor current ripple such that overcurrent protection at the full load can be falsely
triggered. This low inductance also generates more conduction loss and inductor core loss. Larger inductor
current ripple also implies larger output voltage ripple with the same output capacitors. With peak current mode
control, TI recommends to not have too small of an inductor current ripple. A larger peak current ripple improves
the comparator signal to noise ratio.
For this design example, choose KIND = 0.3, and find an inductance of approximately 3.58 µH. Select the next
standard value of 3.3 μH.
11.2.2.4 Output Capacitor Selection
The output capacitor or capacitors, COUT, must be chosen with care because it directly affects the steady state
output voltage ripple, loop stability, and the voltage overshoot/undershoot during load current transients.
The value of the output capacitor and its ESR, determine the output voltage ripple and load transient
performance. The output capacitor is usually limited by the load transient requirements rather than the output
voltage ripple if the system requires tight voltage regulation with presence of large current steps and fast slew
rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor
current can slew up to the appropriate level. The control loop of the regulator usually needs four or more clock
cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the
current difference for four clock cycles to maintain the output voltage within the specified range. 表 11-3 can be
used to find output capacitors for a few common applications. In this example, good transient performance is
desired giving 3 × 47-µF ceramic as the output capacitor.
表11-3. Selected Output Capacitor
FREQUENCY
400 KHz
COUT
SIZE and COST
TRANSIENT PERFORMANCE
3 × 47-µF ceramic
Small size
Good
Minimum
Good
400 KHz
2 × 47-µF ceramic
Small size
400 KHz
Larger size, low cost
4 × 22 µF + 1 × 260 µF, < 50-mΩ electrolytic
1 × 4.7 µF + 2 × 10 µF + 1 × 260 µF, < 50-
400 KHz
Lowest cost
Minimum
mΩ electrolytic
2.1 MHz
2.1 MHz
2.1 MHz
3 × 22 µF ceramic
2 × 47 µF ceramic
2 × 22 µF ceramic
Small size
Small size
Good
Better
Smallest size
Minimum
11.2.2.5 Input Capacitor Selection
The TPS2586x-Q1 device requires a high frequency input decoupling capacitor or capacitors, depending on the
application. A high-quality ceramic capacitor type X5R or X7R with sufficient voltage rating is recommended. The
ceramic input capacitors provide a low impedance source to the converter in addition to supplying the ripple
current and isolating switching noise from other circuits. The typical recommended value for the high frequency
decoupling capacitor is 10 μF of ceramic capacitance. This capacitance must be rated for at least the maximum
input voltage that the application requires; preferably twice the maximum input voltage. This capacitance can be
increased to help reduce input voltage ripple, maintain the input voltage during load transients, or both. In
addition, a small case size 100-nF ceramic capacitor must be used at IN and PGND, immediately adjacent to the
converter. This action provides a high frequency bypass for the control circuits internal to the device. For this
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example a 10-μF, 50-V, X7R (or better) ceramic capacitor is chosen, and the 100-nF ceramic capacitor must
also be rated at 50 V with an X7R or better dielectric.
Additionally, an electrolytic capacitor on the input in parallel with the ceramics can be required, especially if long
leads from the automotive battery to the IN pin of the TPS2586x-Q1, cold or warm engine crank requirements,
and so forth. The moderate ESR of this capacitor is used to provide damping to the voltage spike due to the lead
inductance of the cable or the trace.
11.2.2.6 Bootstrap Capacitor Selection
The TPS2586x-Q1 design requires a bootstrap capacitor (CBOOT). The recommended capacitor is 100 nF and
rated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap
capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. The bootstrap capacitor
must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.
11.2.2.7 Undervoltage Lockout Set-Point
The system undervoltage Lockout (UVLO) is adjusted using the external voltage divider network of RENT and
RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down
or brownouts when the input voltage is falling. 方程式12 can be used to determine the VIN UVLO level.
RENT + RENB
RENB
V
= VENH ì
IN_RISING
(12)
The EN rising threshold (VENH) for the TPS2586x-Q1 is set to be 1.3 V (typical). Choose 10 kΩ for RENB to
minimize input current from the supply. If the desired VIN UVLO level is at 6 V, then the value of RENT can be
calculated using 方程式13:
V
≈
’
IN_RISING
RENT
=
-1 ìR
∆
∆
÷
ENB
÷
VENH
«
◊
(13)
方程式 13 yields a value of 36.1 kΩ. The resulting falling UVLO threshold equals 5.5 V and can be calculated by
方程式14, where EN hysteresis (VEN_HYS) is 0.1 V (typical).
RENT + RENB
RENB
V
= VENH - VEN_HYS
(
ì
)
IN_FALLING
(14)
Note that it cannot connect EN to IN pin directly for self-startup. Because the voltage rating of EN pin is 11 V,
tying it to VIN directly damages the device. The simplest way to enable the operation of the TPS2586x-Q1 is to
connect the EN to VSENSE. This connection allows the automatic startup when VIN is within the operation range.
11.2.2.8 Cable Compensation Set-Point
The TPS2586x-Q1 must short the VSET pin to ground to enable the cable compensation. With that setting, the
buck regulator increases its output voltage linearly as the load current increases, and the voltage compensation
at the currents of the USB ports greater than 2.4 A is 90 mV.
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11.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 13.5 V, fSW = 400 kHz, L = 3.3 µH, CSENSE = 141 µF, CPA_BUS
= 1 µF, CPB_BUS = 1 µF, TA = 25 °C.
Level[dBuV]
100
95
90
85
80
75
70
VIN=6V
VIN=13.5V
VIN=18V
VIN=26V
65
PA_BUS = 2.4A,
PB_BUS = 2.4A
fSW = 400 kHz
L = 3.3 uH
60
0.1
1
6
Load Current(A)
图11-3. 400-khz EMI Results (Without CM Filter)
VSET = GND
fSW = 400 kHz
L = 3.3 uH
图11-2. Buck Only Efficiency
0.4
Level[dBuV]
VIN=6V
VIN=13.5V
0.2
VIN=18V
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
Load = 6A
fSW = 2100 kHz
L = 0.68 uH
3
0
6
图11-4. 2.1-Mhz EMI Results (Without CM Filter)
Load Current(A)
VSET = GND
fSW = 400 kHz
图11-5. Load Regulation
Load=2A
0.1
Load=4A
Load=6A
-0.1
VPA_BUS
200mV/Div
-0.3
-0.5
-0.7
-0.9
-1.1
-1.3
-1.5
IPA_BUS
1A/Div
5
12
18
26
Input Voltage(V)
200.0us/Div
VSET = GND
fSW = 400 kHz
图11-6. Line Regulation
VSET =
VSENSE
IPA_BUS = 0 A to 2.4 A IPB_BUS = 2.4 fSW = 400
KHZ
A
图11-7. Load Transient Without Cable
Compensation
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VPB_BUS
200mV/Div
VPB_BUS
200mV/Div
IPB_BUS
1A/Div
IPB_BUS
1A/Div
200.0us/Div
200.0us/Div
VSET =
VSENSE
IPB_BUS = 0 A to 2.4 A IPA_BUS = 2.4 fSW = 400
kHZ
VSET =
VSENSE
IPB_BUS = 0.75 A to IPA_BUS = 0 A
2.25 A
fSW = 400
kHZ
A
图11-8. Load Transient Without Cable
图11-9. Load Transient Without Cable
Compensation
Compensation
VPB_BUS
200mV/Div
VPB_BUS
200mV/Div
IPB_BUS
1A/Div
IPB_BUS
1A/Div
200us/Div
200us/Div
VSET = IPB_BUS = 0.75 A to
GND 2.25 A
IPA_BUS = 0 A fSW = 400
kHZ
VSET =
GND
IPB_BUS = 0 A to 2.4 A IPA_BUS = 2.4 fSW = 400
kHZ
A
图11-11. Load Transient With Cable Compensation
图11-10. Load Transient With Cable Compensation
5.2
Load=2A
Load=4A
Load=6A
5.15
SW
5V/Div
5.1
5.05
5.0
4.95
VPA_BUS
50mV/Div
4.9
5.5
10.5
15.5
20.5
26
Input Voltage(V)
1us/Div
图11-12. Dropout Characteristic
VSET = GND IPA_BUS = 2.4 IPB_BUS = 2.4 fSW = 400 kHZ
A
A
图11-13. 4.8-A Output Ripple
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SW
5V/Div
SW
5V/Div
VPA_BUS
50mV/Div
VPA_BUS
50mV/Div
1us/Div
1us/Div
VSET =
GND
IPA_BUS = 0.1 A IPB_BUS = 0 A fSW = 400 kHZ
VSET = GND IPA_BUS = 0 A IPB_BUS = 0 A fSW = 400 kHZ
图11-15. No Load Output Ripple
图11-14. 100-mA Output Ripple
EN
5V/Div
EN
5V/Div
VIN
5V/Div
VIN
5V/Div
VPA_BUS
5V/Div
VPA_BUS
5V/Div
VSENSE
5V/Div
VSENSE
5V/Div
50ms/Div
20ms/Div
VIN = 0 V to 13.5
IPA_BUS = 2.4 A
VIN = 13.5 V to 0 V
IPA_BUS = 2.4 A
图11-16. Startup Relate to VIN
图11-17. Shutdown Relate to VIN
EN
5V/Div
EN
5V/Div
VIN
2V/Div
VIN
5V/Div
VPB_BUS
5V/Div
VPB_BUS
5V/Div
VSENSE
5V/Div
VSENSE
5V/Div
50ms/Div
50ms/Div
EN = 0 V to 5 V
IPB_BUS = 2.4 A
EN = 5 V to 0 V
IPB_BUS = 2.4 A
图11-18. Startup Relate to EN
图11-19. Shutdown Relate to EN
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EN
5V/Div
EN
5V/Div
VPB_BUS
2V/Div
VPB_BUS
2V/Div
VPA_BUS
2V/Div
VPA_BUS
2V/Div
IPB_BUS
2A/Div
IPB_BUS
2A/Div
200.0ms/Div
200.0ms/Div
EN to High
PA_BUS = GND
PB_BUS = GND
图11-21. Short Circuit Recovery
图11-20. Enable Into Short
EN
5V/Div
EN
5V/Div
VPB_BUS
2V/Div
VPB_BUS
2V/Div
VPA_BUS
2V/Div
VPA_BUS
2V/Div
IPB_BUS
2A/Div
IPB_BUS
2A/Div
400.0ms/Div
400.0ms/Div
EN to High
PA_BUS = 1 Ω
PB_BUS = 1 Ω
图11-23. 1-ΩLoad Recovery
图11-22. Enable Into 1-ΩLoad
EN
5V/Div
EN
5V/Div
VOUT
2V/Div
VPB_BUS
2V/Div
VPA_BUS
2V/Div
IOUT
500mA/Div
5ms/Div
IPB_BUS
5A/Div
PA/B_BUS NO
LOAD
OUT = 5.1 Ω
2ms/Div
图11-25. OUT short to 5.1-ΩLoad
图11-24. VBUS Hot Short to GND
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EN
5V/Div
VTS
2V/Div
VOUT
2V/Div
VPA_BUS
5V/Div
VPA_BUS
2V/Div
IOUT
500mA/Div
SW
10V/Div
100.0ms/Div
5ms/Div
VTS = 0 V to 4 V
OUT = GND
PA/B_BUS NO
LOAD
图11-27. Thermal Sensing - NTC Temperature HOT
Behavior
图11-26. OUT Hot Short to GND
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12 Power Supply Recommendations
The input supply must be able to withstand the maximum input current and maintain a stable voltage. The
resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the TPS2586x-Q1 supply voltage that it causes a false UVLO fault triggering and system reset. If
the TPS2586x-Q1 is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. An additional bulk capacitance can be required in addition to the ceramic input
capacitors. The amount of bulk capacitance is not critical, but a 100-μF electrolytic capacitor is a typical choice.
The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input
test, the output capacitors discharge through the internal parasitic diode found between the VIN and SW pins of
the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If
this scenario is considered likely, then a Schottky diode between the input supply and the output must be used.
13 Layout
13.1 Layout Guidelines
The PCB layout of any bulk converter is critical to the optimal performance of the design. Bad PCB layout can
disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB
layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,
the EMI performance of the converter is dependent on the PCB layout to a great extent. The following guidelines
will help users design a PCB with the best power conversion performance, thermal performance, and minimized
generation of unwanted EMI.
1. The input bypass capacitor, CIN, must be placed as close as possible to the IN and PGND pins. The high
frequency ceramic bypass capacitors at the input side provide a primary path for the high di/dt components
of the pulsing current. Use a wide VIN plane on a lower layer to connect both of the VIN pairs together to the
input supply. Grounding for both the input and output capacitors must consist of localized top-side planes
that connect to the PGND pin and PAD.
2. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.
3. Use wide traces for the CBOOT capacitor. Place the CBOOT capacitor as close to the device with short, wide
traces to the BOOT and SW pins.
4. The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load
current without excessive heating. Short, thick traces or copper pours (shapes) must be used for a high
current conduction path to minimize parasitic resistance. The output capacitors must be placed close to the
VSENSE end of the inductor and closely grounded to PGND pin and exposed PAD.
5. RFREQ resistors must be placed as close as possible to the FREQ pins and connected to AGND. If needed,
these components can be placed on the bottom side of the PCB with signals routed through small vias, and
the traces need far away from noisy nets like SW, BOOT.
6. Make VIN, VSENSE, and ground bus connections as wide as possible. This action reduces any voltage drops
on the input or output paths of the converter and maximizes efficiency.
7. Provide enough PCB area for proper heat sinking. Enough copper area must be used to ensure a low RθJA
commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB
layers with 2-ounce copper; and no less than 1 ounce. If the PCB design uses multiple copper layers
(recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes. Note
,
that the package of this device dissipates heat through all pins. Wide traces must be used for all pins except
where noise considerations dictate minimization of area.
8. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.
If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-
spreading ground planes. Ensure enough copper area is used for heat-sinking to keep the junction
temperature below 150°C.
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13.2 Layout Example
EMI Filter
USB
PGND
BATT
PGND
L
CIN
CIN
VIN
RBOOT
20
19
18
17
16
14
15
13
21
22
C
BOOT
RBOOT
12
11
VIN
SW
PB_BUS
SENSE
23
24 PGND
PA_BUS 10
USB
8
9
2
3
4
5
6
7
1
L
VSENSE
PGND
Top Trace/Plane
Inner GND Plane
Top
Inner GND Plane
VIA to Signal Layer
VIA to GND Planes
VIA to Strap
Signal Layers
Power and GND
图13-1. Layout Example
13.3 Ground Plane and Thermal Considerations
TI recommends to use one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. Ground plane also provides a quiet reference potential for the control circuitry. The
AGND and PGND pins must be connected to the ground plane using vias right next to the bypass capacitors.
The PGND pin is connected to the source of the internal low-side MOSFET switch, and also connected directly
to the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and
can bounce due to load variations. The PGND trace, as well as VIN and SW traces, must be constrained to one
side of the ground plane. The other side of the ground plane contains much less noise and must be used for
sensitive routes.
TI recommends to provide adequate device heat sinking by using the PAD of the IC as the primary thermal path.
Use a minimum 4 × 2 array of 12-mil thermal vias to connect the PAD to the system ground plane heat sink. The
vias must be evenly distributed under the PAD. Use as much copper as possible, for system ground plane, on
the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the
four layers, starting from the top of 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough copper thickness
provide low current conduction impedance, proper shielding, and lower thermal resistance.
The thermal characteristics of the TPS2586x-Q1 are specified using the parameter θJA, which characterizes the
junction temperature of silicon to the ambient temperature in a specific system. Although the value of θJA is
dependent on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one can use the following relationship:
TJ = PD × θJA + TA
(15)
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where
• TJ = Junction temperature in °C
• PD = VIN × IIN × (1 –Efficiency) –1.1 × IOUT 2 × DCR in Watt
• DCR = Inductor DC parasitic resistance in Ω
• θJA = Junction-to-ambient thermal resistance of the device in °C/W
• TA = Ambient temperature in °C
The maximum operating junction temperature of the TPS2586x-Q1 is 150°C. θJA is highly related to PCB size
and layout, as well as environmental factors such as heat sinking and air flow.
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14 Device and Documentation Support
14.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
14.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
14.3 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
14.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
14.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TPS25865-Q1 TPS25864-Q1
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS25864QRPQRQ1
TPS25865QRPQRQ1
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RPQ
RPQ
25
25
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-45 to 125
-40 to 125
T25864
T25865
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS25864QRPQRQ1
TPS25865QRPQRQ1
VQFN-
HR
RPQ
RPQ
25
25
3000
3000
330.0
12.4
3.8
4.8
1.18
8.0
12.0
Q1
VQFN-
HR
330.0
12.4
3.8
4.8
1.18
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS25864QRPQRQ1
TPS25865QRPQRQ1
VQFN-HR
VQFN-HR
RPQ
RPQ
25
25
3000
3000
367.0
367.0
367.0
367.0
38.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
RPQ0025A
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
A
B
PIN 1 INDEX AREA
4.6
4.4
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
1.0
0.8
SEATING PLANE
0.08 C
0.05
0.00
1.325 0.1
0.75
0.55
PINS 7,8,14 & 15
0.975
0.775
4X
2X 1
8X (0.25)
10
EXPOSED
THERMAL PAD
SYMM
(DIM A) TYP
12
9
13
1.45
1.25
3X
0.65 0.1
PKG
25
2X 4
0.7
0.5
PINS 3 &19
PIN 1 ID
20X 0.5
0.3
24X
0.2
1
21
24
22
0.1
C A B
1.8
1.6
0.725
0.525
PINS 2 & 20
3X
0.05
0.9
0.7
PINS 4-6 & 16-18
4224966/B 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RPQ0025A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.1)
(3.05)
(1.325)
4X (1.075)
4X (0.675)
3X
(1.9)
SYMM
24
22
4X (0.575)
21
2X (0.825)
1
4X (0.25)
2X (0.8)
20X (0.5)
6X (1)
(1.5)
PKG
25
(0.65)
(R0.05) TYP
(1.675)
20X (0.25)
4X (0.85)
SEE SOLDER MASK
DETAIL
13
9
10
12
3X
(1.55)
(2.9)
(3.075)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224966/B 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RPQ0025A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.1)
(3.05)
4X (1.075)
4X (0.675)
SYMM
6X (0.85)
22
24
4X (0.575)
21
1
2X (0.825)
4X (0.25)
20X (0.5)
2X (0.8)
(2.025)
6X (1)
(0.975)
2X
(0.563)
PKG
25
2X (0.325)
(1.237)
2X (0.65)
26X (0.25)
(2.112)
4X (0.85)
13
9
(R0.05) TYP
10
12
6X
(0.675)
EXPOSED METAL
TYP
(0.763)
(2.9)
(3.075)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 25
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224966/B 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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