TPS25921LDR [TI]
具有闭锁故障响应功能的 4.5V 至 18V、90mΩ、0.4A 至 1.6A 电子保险丝 | D | 8 | -40 to 85;
| 型号： | TPS25921LDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有闭锁故障响应功能的 4.5V 至 18V、90mΩ、0.4A 至 1.6A 电子保险丝 | D | 8 | -40 to 85 电子 光电二极管 |
| 文件： | 总38页 (文件大小：1928K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS25921A, TPS25921L
ZHCSCQ0 –AUGUST 2014
TPS25921x 具有精密限流和过压保护功能的 4.5V - 18V 熔丝
1 特性
3 说明
1
•
•
•
•
•
•
•
4.5V - 18V 工作电压，最大绝对值 20V
TPS25921 是一款具有全套保护功能的紧凑型多功能
熔丝。 它具有较宽的工作电压，可实现对多种常用直
流 (DC) 总线的控制。 室温下限流精度达 ±2%，这种
优异的精度使得 TPS25921 成为多种系统保护应用的
理想选择。
90mΩ RDS(ON)（典型值）
0.4A 至 1.6A 可调电流限值
ILIMIT 为 1A 且温度为 25°C 时限流精度达 ±2%
±3% 过压、欠压阈值
可编程的 dVO/dt 控制
而且它还具有过流保护、过压保护和欠压保护等多种可
编程功能，能够对负载、电源和器件提供保护。欠压和
过压条件下的阈值精度为 3%，无需监控电路即可确保
对总线电压进行严密控制。 此外，还针对系统状态监
视和下游负载控制提供了故障标志输出 (FLT)。
热关断故障输出、欠压闭锁 (UVLO) 和过压保护
(OVP)
•
•
•
•
-40°C 至 125°C 的结温范围
自动重试和闭锁型号
UL2367 认证正在处理中
UL60950 - 单点故障测试期间安全
对于热插拔电路板，TPS25921 提供了浪涌电流控制
和可编程的输出斜坡速率。 为实现设计灵活性的最大
化，可使用软启动 (SS) 引脚处的电容器编程设定输出
斜坡速率。
2 应用范围
•
•
•
•
•
•
•
大型家用电器，家用电器
机顶盒、数字化视频光盘 (DVD) 和游戏机
硬盘 (HDD) 和固态硬盘 (SSD)
智能仪表，气体分析仪
智能负载开关
器件信息(1)
部件号
TPS25921A
TPS25921L
封装
封装尺寸（标称值）
SOIC
4.90mm x 3.91mm
USB 开关
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
电源适配器器件
4 应用电路原理图
4.5 to 18 V
V(IN)
Load
IN
OUT
12V 短路响应
FLTb
90mOꢀ
V(OUT)
ENUV
OVP
FLT
V(IN)
I_IN
SS
ILIM
GND
TPS25921x
TIME = 20 ms/div
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCE1
TPS25921A, TPS25921L
ZHCSCQ0 –AUGUST 2014
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
10 Applications and Implementation...................... 18
10.1 Application Information.......................................... 18
10.2 Typical Application ................................................ 18
11 System Examples................................................ 25
应用范围................................................................... 1
说明.......................................................................... 1
应用电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
7.1 Absolute Maximum Ratings ...................................... 3
7.2 Handling Ratings ...................................................... 3
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Characteristics ........................................... 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Typical Characteristics.............................................. 7
Parametric Measurement Information ............... 11
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 17
11.1 Protection and Current Limiting for Primary-Side
Regulated Power Supplies....................................... 25
11.2 Precision Current Limiting in Intrinsic Safety
Applications.............................................................. 26
11.3 Smart Load Switch................................................ 27
12 Power Supply Recommendations ..................... 28
12.1 Transient Protection.............................................. 28
12.2 Output Short-Circuit Measurements ..................... 29
13 Layout................................................................... 30
13.1 Layout Guidelines ................................................. 30
13.2 Layout Example .................................................... 30
14 器件和文档支持 ..................................................... 31
14.1 相关链接................................................................ 31
14.2 Trademarks........................................................... 31
14.3 Electrostatic Discharge Caution............................ 31
14.4 术语表 ................................................................... 31
15 机械封装和可订购信息 .......................................... 31
8
9
5 修订历史记录
日期
修订版本
注释
2014 年 8 月
*
最初发布。
2
Copyright © 2014, Texas Instruments Incorporated
TPS25921A, TPS25921L
www.ti.com.cn
ZHCSCQ0 –AUGUST 2014
6 Pin Configuration and Functions
SOIC (D) 8 PIN PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
OVP
ILIM
GND
SS
FLT
ENUV
IN
OUT
Pin Functions
NAME
NUMBER
DESCRIPTION
GND
SS
1
2
Ground.
A capacitor from this pin to GND sets the ramp rate of output voltage at device turn-on.
Input for setting programmable undervoltage lockout threshold. An undervoltage event will open internal FET and
assert FLT to indicate power-failure. When pulled to GND, resets the thermal fault latch in TPS25921L.
ENUV
3
IN
4
5
Power Input and supply voltage of the device.
Power Output of the device.
OUT
Fault event indicator, goes low to indicate fault condition due to Undervoltage, Overvoltage, and Thermal shutdown
event. A nuisance fast trip does not trigger fault. It is an open drain output.
FLT
ILIM
OVP
6
7
8
A resistor from this pin to GND will set the overload and short circuit limit.
Input for setting programmable overvoltage protection threshold. An overvoltage event will open the internal FET and
assert FLT to indicate overvoltage.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE(2)
MIN
UNIT
MAX
20
22
7
IN, OUT, ENUV, OVP, FLT
–0.3
V
Input voltage range
IN (10 ms Transient)
ILIM, SS
SS
–0.3
5
mA
mA
Sink current
FLT
100
Source current
ILIM, SS, FLT
Internally Limited
Internally Limited
Maximum junction temperature, TJ
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
7.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
-65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
–2
2
V(ESD)
Electrostatic discharge
kV
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
–0.5
0.5
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2014, Texas Instruments Incorporated
3
TPS25921A, TPS25921L
ZHCSCQ0 –AUGUST 2014
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN TYP
MAX UNIT
IN
4.5
18
OUT, OVP, ENUV, FLT
0
18
V
Input voltage range
SS
0
6
ILIM
0
3.3
Resistance
ILIM
OUT
SS
35.7 95.3
158
kΩ
µF
nF
°C
0.1
1
1
External capacitance
1000
125
Operating junction temperature range, TJ
–40
25
7.4 Thermal Characteristics(1)
TPS2592xx
SOIC (8) PINS
120.8
THERMAL METRIC
UNIT
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
65.5
51.8
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
17.4
ψJB
61.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014, Texas Instruments Incorporated
TPS25921A, TPS25921L
www.ti.com.cn
ZHCSCQ0 –AUGUST 2014
7.5 Electrical Characteristics
Conditions (unless otherwise noted) are –40°C ≤ TJ ≤ 125°C, 4.5 V ≤ V(IN) ≤ 18 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3
kΩ, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages are referenced to GND (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT
V(IN)
Operating Input Voltage
UVLO Threshold, Rising
UVLO Hysteresis
4.5
4.10
168
18
4.40
279
V
V(UVR)
V(UVHys)
IQ( ON)
IQ( OFF)
4.26
224
V
mV
mA
mA
Supply Current, Enabled
Supply Current, Disabled
V(ENUV) = 2 V, V(IN) = 12 V
0.22
0.08
0.41
0.58
0.20
V(ENUV) = 0 V, V(IN) = 12 V
0.132
OVERVOLTAGE PROTECTION (OVP) INPUT
Overvoltage Threshold Voltage,
V(OVPR)
Rising
1.35
1.39
1.43
V
Overvoltage Threshold Voltage,
V(OVPF)
Falling
1.30
1.34
0
1.37
100
V
I(OVP)
OVP Input Leakage Current
0V ≤ V(OVP) ≤ 18 V
–100
nA
ENABLE AND UNDERVOLTAGE LOCKOUT (ENUV) INPUT
V(ENR)
V(ENF)
ENUV Threshold voltage, rising
ENUV Threshold voltage, falling
1.36
1.30
1.39
1.34
1.42
1.37
V
V
ENUV Threshold voltage to reset
thermal fault, falling
V(ENF_RST)
IEN
0.5
0.61
0
0.8
V
EN Input leakage current
0 ≤ V(ENUV) ≤ 18 V
–100
100
nA
SOFT START: OUTPUT RAMP CONTROL (SS)
I(SS)
SS charging current
V(SS) = 0 V
0.9
60
1.04
70
1.2
85
µA
Ω
R(SS)
SS discharging resistance
SS maximum capacitor voltage
SS to OUT gain
V(ENUV) = 0 V, I(SS) = 10 mA sinking
V(SSmax)
GAIN(SS)
5.5
V
ΔV(OUT)/ΔV(SS)
4.81
4.86
4.92
V/V
CURRENT LIMIT PROGRAMMING (ILIM)
I(ILIM)
ILIM Bias current
6
0.284
0.394
0.98
10
0.368
0.471
1.0
16
0.452
0.547
1.02
µA
A
R(ILIM) = 35.7 kΩ, (V(IN) - V(OUT)) = 1 V
R(ILIM) = 45.3 kΩ, (V(IN) - V(OUT)) = 1 V
R(ILIM) = 95.3 kΩ, (V(IN) - V(OUT)) = 1 V, TA = TJ= 25°C
R(ILIM) = 95.3 kΩ, (V(IN) - V(OUT)) = 1 V
R(ILIM) = 150 kΩ, (V(IN) - V(OUT)) = 1 V
Current Limit(1)
0.93
1.0
1.062
1.7
ILIMIT
1.43
1.57
R(ILIM) = SHORT, Shorted resistor current limit
R(ILIM) = OPEN, Open resistor current limit
(Single Point Failure Test: UL60950)
0.12
0.257
0.406
R(ILIM) = 35.7 kΩ, (V(IN) - V(OUT)) = 12 V
R(ILIM) = 45.3 kΩ, (V(IN) - V(OUT)) = 12 V
R(ILIM) = 95.3 kΩ, (V(IN) - V(OUT)) = 12 V
R(ILIM) = 150 kΩ, (V(IN) - V(OUT)) = 12 V
0.275
0.376
0.837
1.219
0.356
0.45
0.438
0.522
0.964
1.46
IOS
Short-circuit current limit(1)
A
0.9
1.34
0.0142 x
I(FASTRIP)
V(ILIMopen)
Fast-Trip comparator threshold
R(ILIM) in kΩ
R(ILIM)
+
A
V
0.36
ILIM Open resistor detect threshold V(ILIM) Rising, R(ILIM) = OPEN
2.81
3.0
3.25
MOSFET – POWER SWITCH
–40°C ≤ TJ ≤ 85°C
–40°C ≤ TJ ≤ 125°C
55
55
87
87
120
135
FET ON resistance(2)
RDS(on)
mΩ
PASS FET OUTPUT (OUT)
Ilkg(OUT)
V(ENUV) = 0 V, V(OUT) = 0 V (Sourcing)
V(ENUV) = 0V, V(OUT) = 300 mV (Sinking)
–2
5
0
7
1
OUT Bias current in off state
µA
Isink(OUT)
10
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
(2) The limits for these parameters are specified based on design and characterization data, and are not tested during production.
Copyright © 2014, Texas Instruments Incorporated
5
TPS25921A, TPS25921L
ZHCSCQ0 –AUGUST 2014
www.ti.com.cn
Electrical Characteristics (continued)
Conditions (unless otherwise noted) are –40°C ≤ TJ ≤ 125°C, 4.5 V ≤ V(IN) ≤ 18 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3
kΩ, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages are referenced to GND (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FAULT FLAG (FLT): ACTIVE LOW
R(FLT)
I(FLT)
THERMAL SHUT DOWN (TSD)
FLT Pull down Resistance
Device in fault condition, V(ENUV) = 0V, I(FLT) = 100mA
Device not in fault condition, V(FLT) = 0V, 18V
22
26
0
32
Ω
FLT Input Leakage Current
–0.5
0.5
µA
T(TSD)
TSD Threshold, rising(3)
TSD Hysteresis(3)
155
20
°C
°C
T(TSDhys)
TPS25921L
TPS25921A
LATCHED
Thermal fault: Latched or Auto Retry
AUTO-
RETRY
(3) The limits for these parameters are specified based on design and characterization data, and are not tested during production.
7.6 Timing Requirements
Conditions (unless otherwise noted) are –40°C ≤ TJ ≤ 125°C, V(IN)= 12 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3 kΩ, CSS
OPEN, FLT = OPEN. Positive current into terminals. All voltages are referenced to GND (unless otherwise noted). Refer to
Figure 26 for the timing diagrams
=
MIN
TYP
MAX
UNIT
ENABLE AND UNDERVOLTAGE LOCKOUT (ENUV) INPUT
tOFF(dly)
Turn Off delay
Turn-On delay
ENUV ↓ to V(OUT)
↓
8
µs
µs
ENUV ↑ to V(OUT) = 1V,
C(SS) = OPEN
96
14.5 +
0.5 x (
70p +
tON(dly)
ENUV ↑ to V(OUT) = 1V,
C(SS) > 0.39nF, [C(dVdT) in nF]
C(SS)
)
OVERVOLTAGE PROTECTION (OVP) INPUT
tOVP(dly) OVP Disable delay OVP↑ to V(OUT)
SOFT START: OUTPUT RAMP CONTROL (SS)
↓
8
µs
ENUV ↑ to V(OUT) = 11.7 V, with C(SS) = open ,
C(OUT) = 2.2 µF
0.2
2.1
0.26
3
0.33
3.6
tSS
Output ramp time
ms
ENUV ↑ to V(OUT) = 11.7 V, with C(SS) = 1 nF, C(OUT)
= 2.2 µF
CURRENT LIMIT PROGRAMMING (ILIM)
Fast-Trip comparator
delay
tFASTRIP(dly)
I(OUT) > I(FASTRIP)
3
µs
THERMAL SHUT DOWN (TSD)
Retry Delay after TSD
TPS25921A Only, V(IN) = 12 V
TPS25921A Only, V(IN) = 4.5 V
150
100
ms
ms
tTSD(dly)
recovery, TJ < [T(TSD)
-
20oC]
6
Copyright © 2014, Texas Instruments Incorporated
TPS25921A, TPS25921L
www.ti.com.cn
ZHCSCQ0 –AUGUST 2014
7.7 Typical Characteristics
Conditions (unless otherwise noted) are –40°C ≤ TJ ≤ 125°C, V(IN)= 12 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3 kΩ, C(OUT)
= 2.2 μF, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise
noted). For all oscilloscope waveforms TA = 25°C.
4.4
4.3
4.2
4.1
4
0.6
0.5
0.4
0.3
0.2
0.1
0
V(UVR)
V(UVF)
TA = -40qC
TA = 25qC
TA = 85qC
TA = 125qC
3.9
-50
-25
0
25
50
75
100
125
150
4
6
8
10
12
14
16
18
Temperature (qC)
Input Voltage (V)
D001
D002
Figure 1. UVLO Threshold Voltage vs Temperature
Figure 2. Input Supply Current vs Supply Voltage During
Normal Operation
250
200
150
100
50
1.4
1.38
1.36
1.34
1.32
1.3
TA = 25qC
TA = 125qC
V(ENR), V(OVPR)
V(ENF), V(OVPF)
0
0
5
10
15
20
-50
-25
0
25
50
75
100
125
150
Input Voltage (V)
Temperature (qC)
D003
D004
Figure 3. Input Supply Current vs Supply Voltage at
Shutdown
Figure 4. ENUV and OVP Threshold Voltage vs Temperature
1.2
1.15
1.1
0.8
0.7
0.6
0.5
0.4
1.05
1
0.95
0.9
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (qC)
Temperature (qC)
D007
D006
Figure 6. SS Pin Charging Current vs Temperature
Figure 5. EN Threshold Voltage to Reset Fault Latch vs
Temperature
Copyright © 2014, Texas Instruments Incorporated
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TPS25921A, TPS25921L
ZHCSCQ0 –AUGUST 2014
www.ti.com.cn
Typical Characteristics (continued)
Conditions (unless otherwise noted) are –40°C ≤ TJ ≤ 125°C, V(IN)= 12 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3 kΩ, C(OUT)
= 2.2 μF, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise
noted). For all oscilloscope waveforms TA = 25°C.
5
4.95
4.9
1k
100
10
4.85
4.8
TA = -40qC
TA = 25qC
TA = 85qC
TA = 125qC
4.75
1
-50
-25
0
25
50
75
100
125
150
1
10
100
Temperature (qC)
Soft Start Capacitor (nF)
D008
D009
Figure 7. GAIN(SS) vs Temperature
Figure 8. Output Ramp Time vs C(SS)
2.5
2
0.275
0.27
0.265
0.26
1.5
1
0.255
0.25
0.5
ILIMIT
I(FASTRIP)
0
-50
-25
0
25
50
75
100
125
150
20
40
60
80
100
120
140
160
Temperature (qC)
R(ILM) Resistor (k:)
D010
D011
C(SS) = Open
Figure 9. Output Ramp Time vs Temperature
Figure 10. Current Limit vs Current Limit Resistor
2.4
2
25
20
15
10
5
35.7 k:
45.3 k:
95.3 k:
150 k:
1.6
1.2
0.8
0.4
0
0
-50
-25
0
25
50
75
100
125
150
0
0.25
0.5
0.75
Current Limit (A)
1
1.25
1.5
1.75
Temperature (qC)
D013
D012
Figure 12. Current Limit vs Temperature Across R(ILIM)
Figure 11. Current Limit Accuracy vs Current Limit
8
Copyright © 2014, Texas Instruments Incorporated
TPS25921A, TPS25921L
www.ti.com.cn
ZHCSCQ0 –AUGUST 2014
Typical Characteristics (continued)
Conditions (unless otherwise noted) are –40°C ≤ TJ ≤ 125°C, V(IN)= 12 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3 kΩ, C(OUT)
= 2.2 μF, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise
noted). For all oscilloscope waveforms TA = 25°C.
0.28
0.27
0.26
0.25
0.24
0
R(ILIM) = Short
R(ILIM) = Open
-5
-10
-15
-20
-25
0
5
10
15
20
25
-60
-30
0
30
60
90
120
150
Power Dissipation (W)
Temperature (qC)
D014
D015
PD = [V(IN)
-
V(OUT)]*ILIMIT
Figure 14. Current Limit for R(ILIM) = Open and Short vs
Temperature
Figure 13. Current Limit Normalized (%) vs Power
Dissipation in the Device PD
135
120
105
90
100000
o
TA = -40 C
TA =25oC
10000
1000
100
10
T
= 85oC
A
TA = 125oC
75
1
60
0.1
0.1
1
10
100
45
-50
-25
0
25
50
75
100
125
150
C014
Power Dissipation (W)
Temperature (qC)
D016
Taken on 1-Layer board, 2oz.(0.08-mm thick) with GND plane
area: 14 cm2 (bottom)
Figure 15. RDS(ON) vs Temperature
Figure 16. Thermal Shutdown Time vs Power Dissipation
C(SS) = Open
C(OUT) = 4.7 nF
C(SS) = 1nF
C(OUT) = 4.7 nF
Figure 17. Turn ON with Enable
Figure 18. Turn ON with Enable
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Typical Characteristics (continued)
Conditions (unless otherwise noted) are –40°C ≤ TJ ≤ 125°C, V(IN)= 12 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3 kΩ, C(OUT)
= 2.2 μF, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise
noted). For all oscilloscope waveforms TA = 25°C.
R(FLT) = 100 kΩ
R(FLT) = 100 kΩ
Figure 19. EN Turn ON Delay : EN ↑ to Output Ramp ↑
Figure 20. EN Turn OFF Delay : EN ↓ to Fault ↓
RL = 12 Ω
R(FLT) = 100 kΩ
RL = 12 Ω
R(FLT) = 100 kΩ
Figure 21. OVP Turn OFF delay: OVP ↑ to Fault ↓
Figure 22. OVP Turn ON delay: OVP ↓ to Output Ramp ↑
Figure 23. Hot-Short: Fast Trip Response and Current
Regulation
Figure 24. Hot-Short: Fast Trip Response (Zoomed)
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8 Parametric Measurement Information
5V
V(OUT)
VEN
10%
1V
5V
90%
90%
VEN
V(OUT)
time
0
time
0
tOFF(dly)
tON(dly)
5V
I(FASTRIP)
V(OVP)
50%
ILIMIT
I(IN)
90%
V(OUT)
0
time
0
time
tFASTRIP(dly)
tOVP(dly)
Figure 25. Timing Diagrams
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9 Detailed Description
9.1 Overview
TPS25921 is a smart eFuse with enhanced built-in protection circuitry. It provides robust protection for all
systems and applications powered from 4.5 V to 18 V.
For hot-plug-in boards, the device provides in-rush current control and programmable output ramp-rate.
TPS25921 integrates overcurrent and short circuit protection. The precision overcurrent limit helps to minimize
over design of the input power supply, while the fast response short circuit protection immediately isolates the
load from input when a short circuit is detected. The device allows the user to program the overcurrent limit
threshold between 0.4 A and 1.6 A via an external resistor. The device provides precise monitoring of voltage
bus for brown-out and overvoltage conditions and asserts fault for downstream system. Its threshold accuracy of
3% ensures tight supervision of bus, eliminating the need for a separate supply voltage supervisor chip.
TPS25921 is designed to protect systems such as White Goods, STBs, DTVs, Smart Meters and Gas Analyzers.
The additional features include:
•
•
•
Over temperature protection to safely shutdown in the event of an overcurrent event
Fault reporting for brown-out and overvoltage faults
A choice of latched or automatic restart mode
9.2 Functional Block Diagram
OUT
IN
4
5
Current
Sense
OVP
90m:
8
OVP
1.39V
1.34V
Charge
Pump
+
+
ENUV
I to V
3
EN
1.39V
1.34V
FLT
6
Thermal
Shutdown
TSD
GATE
CONTROL
SWEN
S
SWEN
Fault
Logic
Q
26:
R
Retry Timer
(TPS25921A Only)
+
0.61V
10uA
+
1PA
ILIMIT
ILIM
SS
7
+
2
1
4.8x
+
70pF
Fast Trip
Comp
SWEN
GND
70:
I(FASTRIP)
TPS25921x
12
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9.3 Feature Description
9.3.1 Enable and Adjusting Undervoltage Lockout (UVLO)
The ENUV pin controls the ON/OFF state of the internal FET. A voltage V(ENUV) < V(ENF) on this pin turns off the
internal FET, thus disconnecting IN from OUT.
Toggling the ENUV pin below V(ENF_RST) resets the TPS25921L that has latched off due to a fault condition. The
internal de-glitch delay on ENUV falling edge is kept low for quick detection of power failure. For applications
where a higher de-glitch delay on ENUV is desired, or when the supply is particularly noisy, it is recommended to
use an external filter capacitor from the ENUV terminal to GND.
The undervoltage lockout threshold can be programmed by using an external resistor divider from the supply IN
terminal to the ENUV terminal to GND as shown in Figure 26. When an undervoltage or input power fail event is
detected, the internal FET is quickly turned off, and FLT is asserted. If the undervoltage lockout function is not
needed, the ENUV pin should be connected to the IN terminal. The ENUV terminal should not be left floating.
TPS25921 also implements internal undervoltage lockout (UVLO) circuitry on the IN pin. The device gets
disabled when the IN terminal voltage falls below internal UVLO Threshold V(UVF)
.
V(IN)
IN
TPS25921x
R1
ENUV
+
EN
1.39V
R2
1.34V
OVP
+
OVP
1.39V
R3
1.34V
GND
Figure 26. UVLO and OVP Thresholds Set By R1, R2 and R3
9.3.2 Overvoltage Protection (OVP)
TPS25921 incorporates circuits to protect the system during overvoltage conditions. A resistor divider, connected
from the supply to OVP terminal to GND (as shown in Figure 26), programs the overvoltage threshold. A voltage
more than V(OVPR) on the OVP pin turns off the internal FET and protects the downstream load. This pin should
be tied to GND when not used.
9.3.3 Hot Plug-in and In-Rush Current Control
TPS25921 is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot"
power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets of
the system power. A slew rate controlled startup (SS) also helps to eliminate conductive and radiated
interference. An external capacitor from the SS pin to GND defines the slew rate of the output voltage at power-
on (as shown in Figure 27). The equation governing slew rate at start-up is shown in Equation 1 :
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Feature Description (continued)
TPS25921x
1 PA
SS
C(SS)
70 :
SWEN
C(INT)
GND
Figure 27. Output Ramp Up Time tdVdT is Set by C(dVdT)
(C
(SS)
+ C
(INT)
)
dV
(OUT)
I
=
x
(SS)
Gain
(SS)
dt
(1)
Where:
•
I(SS) = 1 µA (typical)
space
dV
(OUT)
•
•
dt
= Desired output slew rate
GAIN(SS) = ΔV(OUT)/ΔV(SS) gain = 4.85
The total ramp time (tSS) of V(OUT) for 0 to V(IN) can be calculated using Equation 2:
4
t
= 20.6 x 10 x V
x
C
(
(SS)
+ 0.07
)
SS
(IN)
(2)
(3)
The inrush current, I(INRUSH) can be calculated as
V
(IN)
I
= C x
(OUT)
(INRUSH)
t
SS
The SS pin can be left floating to obtain a predetermined slew rate (tSS) on the output. When terminal is left
floating, the device sets an internal ramp rate of ~50V/ms for output (V(OUT)) ramp.
Figure 36 and Figure 37 illustrate the inrush current control behavior of the device. For systems where load is
present during start-up, the current never exceeds the overcurrent limit set by R(ILIM) resistor for the application.
For defining appropriate charging time/rate under different load conditions, refer to the Setting Output Voltage
Ramp time (tSS) section.
9.3.4 Overload and Short Circuit Protection :
At all times load current is monitored by sensing voltage across an internal sense resistor. During overload
events, current is limited to the current limit (ILIMIT) programmed by R(ILIM) resistor
-3
I
= 10.73 x 10 x R
- 0.018
LIMIT
(ILIM)
(4)
(5)
I
+ 0.018
-3
LIMIT
R
=
(ILIM)
10.73 x 10
•
•
ILIMIT is overload current limit in Ampere
R(ILIM) is the current limit programming resistor in kΩ
TPS25921 incorporates two distinct overcurrent protection levels: the current limit (ILIMIT) and the fast-trip
threshold (I(FASTRIP)). The fast trip and current limit operations are shown in Figure 28.
Bias current on ILIM pin directly controls current-limiting behavior of the device, and PCB routing of this node
must be kept away from any noisy (switching) signals.
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Feature Description (continued)
9.3.4.1 Overload Protection
For overload conditions, the internal current-limit amplifier regulates the output current to ILIMIT. The output
voltage droops during current limit regulation, resulting in increased power dissipation in the device. If the device
junction temperature reaches the thermal shutdown threshold (T(TSD)), the internal FET is turned off. Once in
thermal shutdown, The TPS25921L version stays latched off, whereas TPS25921A commences an auto-retry
cycle tTSD(dly) ms after TJ < [T(TSD) - 20°C]. During thermal shutdown, the fault pin FLT pulls low to signal a fault
condition. Figure 40 and Figure 41 illustrate overload behavior.
9.3.4.2 Short Circuit Protection
During a transient short circuit event, the current through the device increases very rapidly. As current-limit
amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator, with a threshold I(FASTRIP). When the current through the internal FET exceeds I(FASTRIP) (I(OUT)
>
I(FASTRIP)), this comparator shuts down the pass device within 3 µs and terminates the rapid short-circuit peak
current. The I(FASTRIP) threshold is dependent on programmed overload current limit and function of R(ILIM). See
Equation 6 for the calculation.
-2
I
= 1.42 x 10 x R
+ 0.36
(FASTRIP)
(ILIM)
where
•
•
I(FASTRIP) is fast trip current limit in Ampere
R(ILIM) is the current limit resistor in kΩ
(6)
The fast-trip circuit holds the internal FET off for only a few microseconds, after which the device attempts to turn
back on normally, allowing the current-limit loop to regulate the output current to ILIMIT. Then, device behaves
similar to overload condition. Figure 42 through Figure 44 illustrate the behavior of the system when the current
exceeds the fast-trip threshold.
9.3.4.3 Start-Up with Short on Output
During start-up into a short circuit current is limited to ILIMIT. Figure 45 and Figure 46 illustrate start-up with a
short on the output. This feature helps in quick fault isolation and hence ensures stability of the DC bus.
9.3.4.4 Constant Current Limit Behavior during Overcurrent Faults
When power dissipation in the internal FET [PD = (V(IN) - V(OUT)) × I(OUT)] > 2 W, there is a ~1 to 20 % thermal fold
back in the current limit value so that the regulated current drops from ILIMIT to IOS. Eventually, the device shuts
down due to over temperature.
I(FASTRIP)
I(FASTRIP) = 1.42 x 10-2 x R(ILIM) + 0.36
ILIMIT
Thermal Foldback
1-20%
IOS
Figure 28. Overcurrent Protection Levels
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Feature Description (continued)
9.3.5 FAULT Response
The FLT open-drain output is asserted (active low) during undervoltage, overvoltage and thermal shutdown
conditions. The FLT signal remains asserted until the fault condition is removed and the device resumes normal
operation. During thermal shutdown, TPS25921L version stays latched off, whereas TPS25921A commences an
auto-retry cycle tTSD(dly) millisecond after TJ < [T(TSD) - 20°C]. For TPS25921L, thermal fault latch can be reset by
cycling the ENUV pin below V(ENF_RST) threshold. A nuisance fast trip does not trigger fault.
Connect FLT with a pull up resistor to Input or Output voltage rail. FLT may be left open or tied to ground when
not used.
9.3.6 IN, OUT and GND Pins
The IN pin should be connected to the power source. A ceramic bypass capacitor close to the device from IN to
GND is recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V – 18 V.
The OUT pin should be connected to the load. V(OUT) in the ON condition, is calculated using the Equation 7
V
= V
(IN)
-
R
x I
DS(ON) (OUT)
(
)
(OUT)
(7)
where, RDS(ON) is the ON resistance of the internal FET.
GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference
unless otherwise specified.
9.3.7 Thermal Shutdown:
Internal over temperature shutdown disables/turns off the FET when TJ > 155°C (typical). The TPS25921L
version latches off the internal FET, whereas TPS25921A commences an auto-retry cycle tTSD(dly) milliseconds
after TJ drops below [T(TSD) - 20°C]. During the thermal shutdown, the fault pin FLT is pulled low to signal a fault
condition.
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9.4 Device Functional Modes
9.4.1 Shutdown Control
The internal FET and hence the load current can be remotely switched off by taking the ENUV pin below its 1.34
V threshold with an open collector or open drain device as shown in Figure 29. Upon releasing the ENUV pin the
device turns on with soft-start cycle.
V(IN)
IN
TPS25921x
R1
ENUV
+
EN
1.39V
from µC
R2
1.34V
GND
Figure 29. Shutdown Control
9.4.2 Operational Overview of Device Functions
The Table 1 below elucidates the device functionality for various conditions
Table 1. Operational Overview of Device Functions
Device
TPS25921
Inrush ramp controlled by capacitor at SS pin
Inrush limited to ILIMIT level as set by R(ILIM)
If TJ > T(TSD) device shuts off
Start Up
Current is limited to I(LIM) level as set by R(ILIM)
Power dissipation increases as V(IN) - V(OUT) grows
Device turns off when TJ > T(TSD)
Overcurrent Response
Short-Circuit Response
‘L' Version remains off
'A' Version will attempt restart tTSD(dly) ms after TJ < [T(TSD) -20°C]
Fast shut off when I(LOAD) > I(FASTRIP)
Quick restart and current limited to ILIMIT, follows standard startup cycle
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10 Applications and Implementation
10.1 Application Information
The TPS25921x is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It
operates from 4.5 V to 18 V with programmable current limit, overvoltage and undervoltage protection. The
device aids in controlling the in-rush current and provides precise current limiting during overload conditions for
systems such as White Goods, Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The
device also provides robust protection for multiple faults on the sub-system rail.
The following design procedure can be used to select component values for the device.
Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. Additionally, a spreadsheet design tool TPS25921 Design Calculator is available on web folder.
This section presents a simplified discussion of the design process.
10.2 Typical Application
10.2.1 Precision Current Limiting and Protection for White Goods
V(IN) 4.5 to 18 V
V(OUT)
IN
OUT
(Note 1)
CIN
0.1µF
R1
470kOꢀ
COUT
100µF
90mOꢀ
R4
ENUV
OVP
R2
53kOꢀ
Fault Monitor
FLT
SS
ILIM
GND
CSS
1nF
R3
47kOꢀ
TPS25921x
RILIM
95.3kO
(1) CIN: Optional and only for noise suppression.
Figure 30. Typical Application Schematics: eFuse for White Goods
10.2.1.1 Design Requirements
Table 2. Design Parameters
DESIGN PARAMETER
Input voltage range, V(IN)
EXAMPLE VALUE
12 V
8 V
Undervoltage lockout set point, V(UV)
Overvoltage protection set point , V(OV)
Load at Start-Up , RL(SU)
17 V
24 Ω
1 A
Current limit, ILIMIT
Load capacitance , C(OUT)
100 µF
85°C
Maximum ambient temperatures , TA
18
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10.2.1.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS25921A and TPS25921L.
10.2.1.2.1 Step by Step Design Procedure
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
•
•
•
•
•
Normal input operation voltage
Maximum output capacitance
Maximum current Limit
Load during start-up
Maximum ambient temperature of operation
This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
10.2.1.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
The R(ILIM) resistor at the ILIM pin sets the over load current limit, this can be set using Equation 5.
1 + 0.018
R
=
= 94.8 kW
(ILIM)
-3
10.73 x 10
(8)
Choose closest standard value: 95.3 kΩ, 1% standard value resistor.
10.2.1.2.3 Undervoltage Lockout and Overvoltage Set Point
The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using the external voltage divider
network of R1, R2 and R3 as connected between IN, ENUV, OVP and GND pins of the device. The values
required for setting the undervoltage and overvoltage are calculated solving Equation 9 and Equation 10.
R
3
R +R +R
V
=
x V
(OV)
(OVPR)
1
2
3
(9)
R
+R
2
3
R +R +R
V
=
x V
(UV)
(ENR)
1
2
3
(10)
For minimizing the input current drawn from the power supply {I(R123) = V(IN)/(R1 + R2 + R3)}, it is recommended to
use higher values of resistance for R1, R2 and R3.
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, I(R123) must be chosen to be 20x greater than the leakage
current expected.
From the device electrical specifications, V(OVPR) = 1.40 V and V(ENR) = 1.40 V. For design requirements, V(OV) is
17 V and V(UV) is 8 V. To solve the equation, first choose the value of R3 = 47 kΩ and use Equation 9 to solve for
(R1 + R2) = 523.71 kΩ. Use Equation 10 and value of (R1 + R2) to solve for R2 = 52.88 kΩ and finally R1= 470.83
kΩ.
Using the closest standard 1% resistor values gives R1 = 470 kΩ, R2 = 53 kΩ, and R3 = 47 kΩ.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the
rising threshold, V(UV). This is calculated using Equation 11.
V(PFAIL) = 0.96 x V(UV)
(11)
Power fail threshold set is : 7.68 V
10.2.1.2.4 Setting Output Voltage Ramp time (tSS
)
For a successful design, the junction temperature of device should be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor C(SS) needed is calculated considering the two possible cases:
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10.2.1.2.4.1 Case1: Start-up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-up
During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and
the power dissipated decreases as well. Typical ramp-up of output voltage V(OUT) with inrush current limit of 0.5A
and power dissipated in the device during start-up is shown in Figure 31. The average power dissipated in the
device during start-up is equal to area of triangular plot (red curve in Figure 32) averaged over tSS
.
7
14
12
10
8
Input Current
Power Dissipation
Output Voltage
6
5
4
3
2
1
0
6
4
2
0
0
20
40
60
80
100
Start-Up Time, tSS (%)
C013
V(IN) = 12 V
C(SS) = 1 nF
C(OUT)=100 µF
V(IN) = 12 V
C(SS) = 1 nF
C(OUT)=100 µF
Figure 32. PD(INRUSH) Due to Inrush Current
Figure 31. Start-up Without Load
For TPS25921 device, the inrush current is determined as,
V
dV
(IN)
I = C x
=> I
(INRUSH)
= C x
(OUT)
dT
t
SS
(12)
(13)
Power dissipation during start-up is:
P
= 0.5 x V x I
(IN) (INRUSH)
D(INRUSH)
Equation 13 assumes that load does not draw any current until the output voltage has reached its final value.
10.2.1.2.4.2 Case 2: Start-up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-up
When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a
resistive load RL(SU) during start-up, load current ramps up proportionally with increase in output voltage during
tSS time. Typical ramp-up of output voltage, load current and power dissipation in the device is shown in
Figure 33 and power dissipation with respect to time is plotted in Figure 34. The additional power dissipation
during start-up phase is calculated as follows.
æ
ö
÷
÷
÷
t
ç
(V - V )(t) = V
(IN)
x ç1-
I
O
ç
ç
è
÷
ø
t
SS
(14)
æ
ç
ç
ç
ç
ö
V
÷
÷
÷
÷
÷
t
(IN)
I (t) =
x
L
R
t
SS
ç
è
L(SU) ø
(15)
Where RL(SU) is the load resistance present during start-up. Average energy loss in the internal FET during
charging time due to resistive load is given by:
tss
æ
ç
ç
ç
ö
÷
÷
÷
÷
÷
æ
ç
ç
è
ö
÷
÷
÷
V
t
t
(IN)
ç
W
=
V
x ç1 -
x
x
dt
t
(IN)
ç
ç
è
ò
÷
ø
t
R
t
SS
L(SU)
SS ø
0
(16)
20
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2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
14
12
10
8
Power Dissipation
Load Current
Output Voltage
6
4
2
0
0
10
20
30
40
50
60
70
80
90 100
Start-Up Time, tSS (%)
C013
V(IN) = 12 V
C(SS) = 1 nF
RL(SU) = 24 Ω
V(IN) = 12 V
C(SS) = 1 nF ,
C(OUT)=100 µF
RL(SU) = 24 Ω
Figure 34. PD(LOAD) in Device during Start-up with Load
Figure 33. Start-up With Load
On solving Equation 16 the average power loss in the internal FET due to load is:
2
V
æ
ö
÷
÷
ø
1
6
(IN)
÷
x
÷
ç
P
=
ç
D(LOAD)
ç
è
R
L(SU)
(17)
(18)
(19)
Total power dissipated in the device during startup is:
P
=
P + P
D(INRUSH) D(LOAD)
D(STARTUP)
Total current during startup is given by:
I
=
I
+ I (t)
(STARTUP)
(INRUSH) L
If I(STARTUP) > ILIMIT, the device limits the current to ILIMIT and the current limited charging time is determined by:
é
ê
ê
ê
ê
ê
ê
ê
ë
ù
ö
æ
ç
ç
ç
ç
ç
ç
ç
ç
ç
çI
÷
ú
÷
÷
ú
÷
I
I
(INRUSH)
÷
ú
÷
(LIMIT)
÷
ú
÷
÷
t
=
C
x R
L(SU)
x
-1+LN
SS(current-limited)
(OUT)
V
I
ú
(IN)
÷
(INRUSH)
÷
-
ú
÷
(LIMIT)
ç
÷
ú
÷
L(SU) ø
û
R
ç
è
(20)
The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as
shown in Figure 35.
100000
o
TA = -40 C
TA =25oC
10000
T
= 85oC
A
TA = 125oC
1000
100
10
1
0.1
0.1
1
10
100
C014
Power Dissipation (W)
Figure 35. Thermal Shutdown Limit Plot
For the design example under discussion,
Select ramp-up capacitor C(SS) = 1nF, using Equation 2.
4
= 20.6 x 10 x 12 x 1 + 0.07 = 2.64 ms
t
(
)
SS
(21)
21
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The inrush current drawn by the load capacitance (C(OUT)) during ramp-up using Equation 3.
æ
ç
ö
÷
ø
12
-6
I
=
100 x 10
x
= 0.454 A
(INRUSH)
(
)
-3
è 2.64 x 10
(22)
(23)
The inrush Power dissipation is calculated, using Equation 13.
P
= 0.5 x 12 x 0.454 = 2.72 W
D(INRUSH)
For 2.72 W of power loss, the thermal shut down time of the device should not be less than the ramp-up time tSS
to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 35 at
TA = 85°C, for 2.72 W of power the shutdown time is ~170 ms. So it is safe to use 2.64 ms as start-up time
without any load on output.
Considering the start-up with load 24 Ω, the additional power dissipation, when load is present during start up is
calculated, using Equation 17.
1
12 x 12
æ
ö
æ
ö
P
=
x
= 1 W
D(LOAD)
ç
÷
ç
÷
6
24
è
ø
è
ø
(24)
(25)
The total device power dissipation during start up is:
P
= 2.72 + 1 = 3.72 W
D(STARTUP)
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 3.72 W is close to 60 ms. It is
safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and
input voltage. So it is well within acceptable limits to use the 1 nF capacitor with start-up load of 24 Ω.
If there is a need to decrease the power loss during start-up, it can be done with increase of C(SS) capacitor.
To illustrate, choose C(SS) = 4.7 nF as an option and recalculate:
4
= 20.6 x 10 x 12 x 4.7 + 0.07 = 11.8 ms
t
(
)
SS
(26)
æ
ç
ö
÷
ø
12
-6
I
=
100 x 10
x
= 0.102 A
(INRUSH)
(
)
-3
è11.8 x 10
(27)
(28)
P
= 0.5 x 12 x 0.102 = 0.61 W
D(INRUSH)
1
6
12 x 12
24
æ
ö
æ
ö
P
=
x
= 1 W
D(LOAD)
ç
÷
ç
÷
è
ø
è
ø
(29)
(30)
P
= 0.61+ 1 = 1.61 W
D(STARTUP)
From thermal shutdown limit graph at TA = 85°C, the shutdown time for 1.61 W power dissipation is ~1000 ms,
which increases the margins further for shutdown time and ensures successful operation during start up and
steady state conditions.
The spreadsheet tool available on the web can be used for iterative calculations.
10.2.1.2.5 Support Component Selections - R4 and CIN
Reference to application schematics, R4 is required only if FLT is used; The resistor serves as pull-up for the
open-drain output driver. The current sunk by this pin should not exceed 100 mA (refer to the Absolute Maximum
Ratings table). CIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise.
Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for C(IN)
.
22
Copyright © 2014, Texas Instruments Incorporated
TPS25921A, TPS25921L
www.ti.com.cn
ZHCSCQ0 –AUGUST 2014
10.2.1.3 Application Curves
Figure 36. Hot-Plug Start-Up: Output Ramp Without Load
on Output
Figure 37. Hot-Plug Start-Up: Output Ramp With 24 Ω Load
at Start Up
Figure 38. Overvoltage Shutdown
Figure 39. Overvoltage Recovery
Figure 40. Over Load: Step Change in Load from 19 Ω to 9
Ω Back
Figure 41. Overload Condition: Auto Retry and Recovery -
TPS25921A
Copyright © 2014, Texas Instruments Incorporated
23
TPS25921A, TPS25921L
ZHCSCQ0 –AUGUST 2014
www.ti.com.cn
Figure 42. Hot Short: Fast Trip and Current Regulation
Figure 43. Hot Short: Latched - TPS25921L
Figure 44. Hot Short: Auto-Retry and Recovery from Short
Circuit - TPS25921A
Figure 45. Hot Plug-in with Short on Output: Latched -
TPS25921L
Figure 46. Hot Plug-in with Short on Output: Auto-Retry - TPS25921A
24
Copyright © 2014, Texas Instruments Incorporated
TPS25921A, TPS25921L
www.ti.com.cn
ZHCSCQ0 –AUGUST 2014
11 System Examples
The TPS25921 provides a simple solution for current limiting, inrush current control and supervision of power
rails for wide range of applications operating at 4.5 V to 18 V and delivering up to 1.5 A.
11.1 Protection and Current Limiting for Primary-Side Regulated Power Supplies
Primary side regulated power supplies and adapters are dominant today in many of the applications such as
Smart-phones, Portable hand-held devices, White Goods, Set-Top-Box and Gaming consoles. These supplies
provide efficient, low cost and low component count solutions for power needs ranging from 5W to 30W. But,
these come with drawbacks of
•
•
•
No secondary side protection for immediate termination of critical faults such as short circuit and over voltage
Do not provide precise current limiting for overload transients
Have poor output voltage regulation for sudden change in AC input voltages - triggering output overvoltage
condition
Many of the above applications require precise output current limiting and secondary side protection, driving the
need for current sensing in the secondary side. This needs additional circuit implementation using precision
operational amplifiers. This increases the complexity of the solution and also results in sensing losses The
TPS25921 with its integrated low-ohmic N-channel FET provides a simple and efficient solution. Figure 47 shows
the typical implementation using TPS25921.
VDC
V(OUT)
VAC(IN)
Rectifier + Noise
Filter
TPS25921
ILIM
R1
R2
OVP
CO
CB
RILIM
UCC287xx
Primary Regulated
Fly-back Controller
Rs
Figure 47. Current Limiting and Protection for AC-DC Power Supplies
During short circuit conditions, the internal fast comparator of TPS25921 turns OFF the internal FET in less than
3 µs (typical) as soon as current exceeds I(FASTRIP), set by the current limit R(ILIM) resistor. The OVP comparator
with 3% precision helps in quick isolation of the load from the input when inputs exceeds the set V(OVPR)
Figure 42 and Figure 38 shows short circuit and overvoltage response waveforms of implementation using
TPS25921. In addition to above, the TPS25921 provides inrush current limit when output is hot-plugged into any
of the system loads.
Copyright © 2014, Texas Instruments Incorporated
25
TPS25921A, TPS25921L
ZHCSCQ0 –AUGUST 2014
www.ti.com.cn
11.2 Precision Current Limiting in Intrinsic Safety Applications
Intrinsic safety (IS) is becoming prominent need for safe operation of electrical and electronic equipment in
hazardous areas. Intrinsic safety requires that equipment is designed such that the total amount of energy
available in the apparatus is simply not enough to ignite an explosive atmosphere. The energy can be electrical,
in the form of a spark, or thermal, in the form of a hot surface.
This calls for precise current limiting and precision shutdown of the circuit for over voltage conditions ensuring
that set voltage and current limits are not exceeded for wide operating temperature range and variable
environmental conditions. Applications such as Gas Analyzers, Medical equipment (such as
electrocardiographs), Portal Industrial Equipment, Cabled Power distribution systems and hand-held motor
operated tools need to meet these critical safety standards.
The TPS25921 device can be used as simple protection solution for each of the internal rails. Figure 48 shows
the typical implementation using TPS25921.
LO
V(IN)
V(OUT)
Sync Buck
DC-DC Converter
TPS25921
R1
R2
ILIM
OVP
CO
CB
RILIM
V(IN)
V(OUT)
TPS25921
LDO
R1
R2
ILIM
OVP
CO
CB
RILIM
Figure 48. Precision current Limit and Protection of Internal Rails
26
Copyright © 2014, Texas Instruments Incorporated
TPS25921A, TPS25921L
www.ti.com.cn
ZHCSCQ0 –AUGUST 2014
11.3 Smart Load Switch
A smart load switch is a series FET used for switching of the load (resistive or inductive). It also provides
protection during fault conditions. Typical discrete implementation is shown in Figure 49. Discrete solutions have
higher component count and require complex circuitry to implement each of the protection fault needs.
TPS25921 can be used as a smart power switch for applications ranging from 4.5 V to 18 V. TPS25921 provides
programmable soft start, programmable current limits, over-temperature protection, a fault flag, and under-
voltage lockout.
Enable
EN
V(IN)
V(IN)
Load
Load
TPS25921
ILIM
OVP
R1
R2
R1
Over Current
Protection
Cs
UVLO
OVP
RILIM
R2
Q2
Enable
Figure 49. Smart Load Switch Implementation
Figure 49 shows typical implementation and usage as load switch. This configuration can be used for driving a
solenoid and FAN control. It is recommended to use a freewheeling diode across the load when load is highly
inductive.
Figure 50 shows load switching waveforms using TPS25921 for 12 V Bus
Figure 50. Smart Load Switch (100 Hz Operation)
Copyright © 2014, Texas Instruments Incorporated
27
TPS25921A, TPS25921L
ZHCSCQ0 –AUGUST 2014
www.ti.com.cn
12 Power Supply Recommendations
The device is designed for supply voltage range of 4.5 V ≤ VIN ≤ 18 V. If the input supply is located more than a
few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power supply
should be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.
12.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include
•
•
•
•
Minimizing lead length and inductance into and out of the device
Using large PCB GND plane
Schottky diode across the output to absorb negative spikes
A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with Equation 31.
L
(IN)
V
= V x I x
(IN) (LOAD)
SPIKE(Absolute)
C
(IN)
(31)
Where:
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current,
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 51.
4.5 to 18 V
OUT
IN
IN
OUT
(Note 1)
CIN
90mOꢀ
ENUV
OVP
(Note 1)
(Note 1)
FLT
SS
ILIM
GND
TPS25921x
(1) Optional components needed for suppression of transients
Figure 51. Circuit Implementation With Optional Protection Components
28
Copyright © 2014, Texas Instruments Incorporated
TPS25921A, TPS25921L
www.ti.com.cn
ZHCSCQ0 –AUGUST 2014
12.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
Copyright © 2014, Texas Instruments Incorporated
29
TPS25921A, TPS25921L
ZHCSCQ0 –AUGUST 2014
www.ti.com.cn
13 Layout
13.1 Layout Guidelines
•
For all applications, a 0.01-uF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated/minimized.
•
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 52 for a PCB layout example.
•
•
•
High current carrying power path connections should be as short as possible and should be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground should be
a copper plane or island on the board.
Locate all TPS25921x support components: R(ILIM), CSS, and resistors for FLT, ENUV and OVP, close to their
connection pin. Connect the other end of the component to the GND pin of the device with shortest trace
length.
•
The trace routing for the RILIM and CSS components to the device should be as short as possible to reduce
parasitic effects on the current limit and soft start timing. These traces should not have any coupling to
switching signals on the board.
•
•
OVP and ENUV signal traces should be routed with sufficient spacing from FLT signal trace, to avoid
spurious coupling of FLT switching, during fault conditions.
Protection devices such as TVS, snubbers, capacitors, or diodes should be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it should be physically close to the OUT pins.
•
Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.
13.2 Layout Example
Top layer
Bottom Layer: GND plane (Optional)
Via to top layer ground plane (only for two layer board)
Ground
1
2
3
4
8
7
6
5
OVP
ILIM
GND
SS
(Note 1)
(Note 1)
FLT
ENUV
IN
OUT
Output
Input
(1) Optional: Needed only to suppress the transients caused by inductive load switching.
Figure 52. Board Layout
30
Copyright © 2014, Texas Instruments Incorporated
TPS25921A, TPS25921L
www.ti.com.cn
ZHCSCQ0 –AUGUST 2014
14 器件和文档支持
14.1 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
Table 3. 相关链接
部件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TPS25921A
TPS25921L
14.2 Trademarks
14.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
15 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
Copyright © 2014, Texas Instruments Incorporated
31
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Copyright © 2014, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS25921AD
TPS25921ADR
TPS25921LD
TPS25921LDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
25921A
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
25921A
25921L
25921L
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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