TPS259461ARPWR [TI]
TPS25946xx 2.7â23 V, 5.5-A, 28-mΩ eFuse With Bidirectional Current Support;
| 型号： | TPS259461ARPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS25946xx 2.7â23 V, 5.5-A, 28-mΩ eFuse With Bidirectional Current Support |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS25946
SLVSGA8A – MAY 2021 – REVISED AUGUST 2021
TPS25946xx 2.7–23 V, 5.5-A, 28-mΩ eFuse With Bidirectional Current Support
1 Features
3 Description
•
Wide operating input voltage range: 2.7 V to 23 V
– 28-V absolute maximum
Integrated back-to-back FETs with low On-
Resistance: RON = 28.3 mΩ (typ)
– Bi-directional current flow during ON state
– Reverse current blocking during OFF state
Fast overvoltage protection
– Adjustable Overvoltage Lockout (OVLO) with
1.2-μs (typ) response time
The TPS25946xx family of eFuses is a highly
integrated circuit protection and power management
solution in
a
small package. The devices
•
provide multiple protection modes using very few
external components and are a robust defense
against overloads, short-circuits, voltage surges and
excessive inrush current. With integrated back-to-
back FETs, the device allows bi-directional current
flow during ON state, while blocking current flow in
both directions during OFF state, making it well suited
for USB OTG (On-The-Go) applications.
•
•
Overcurrent protection in forward direction with
load current monitor output (ILM)
– Active current limit response
– Adjustable threshold (ILIM): 0.5 A to 6 A
Output slew rate and inrush current can be adjusted
using a single external capacitor. Loads are protected
from input overvoltage conditions by cutting off the
output if input exceeds an adjustable overvoltage
threshold. The devices respond to output overload by
actively limiting the current. The output current limit
threshold as well as the transient overcurrent blanking
timer are user adjustable. The current limit control pin
also functions as an analog load current monitor.
•
±10% accuracy for ILIM > 1 A
– Adjustable transient blanking timer (ITIMER) to
allow peak currents up to 2 × ILIM
– Output load current monitor accuracy: ±6%
(IOUT ≥ 1 A)
Fast-trip response for short-circuit protection on
OUT pin
•
•
– 500-ns (typ) response time
The devices are available in a 2-mm × 2-mm,
10-pin HotRod QFN package for improved thermal
performance and reduced system footprint.
– Adjustable (2 × ILIM) and fixed thresholds
Active high enable input with adjustable
Undervoltage Lockout threshold (UVLO)
Adjustable output slew rate control (dVdt)
Overtemperature protection
Digital Indication Options:
– Power Good indication (PG) with adjustable
threshold (PGTH) or
The devices are characterized for operation over a
junction temperature range of –40°C to +125°C.
•
•
•
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
TPS25946xxRPW
QFN (10)
2 mm × 2 mm
– Supply Good (SPLYGD) and Fault (FLT)
indications
UL 2367 recognition (pending)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
•
IEC 62368 CB certification (pending)
Small footprint: QFN 2 mm × 2 mm, 0.45-mm pitch
VBUS
VSYS
IN
OUT
2 Applications
•
•
•
•
•
•
USB On-The-Go (OTG)
Smartphones
Tablets
Digital cameras
Point of sales terminals
Wireless chargers
COUT
PGTH
EN/UVLO
OVLO
VLOGIC
TPS259460x
PG
ITIMER dVdt
ILM
GND
RILM
CITIMER
CDVDT
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS25946
SLVSGA8A – MAY 2021 – REVISED AUGUST 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................7
7.6 Timing Requirements .................................................8
7.7 Switching Characteristics ...........................................9
7.8 Typical Characteristics..............................................10
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................16
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................27
9 Application and Implementation..................................28
9.1 Application Information............................................. 28
9.2 Typical Application.................................................... 28
10 Power Supply Recommendations..............................34
10.1 Transient Protection................................................34
10.2 Output Short-Circuit Measurements....................... 35
11 Layout...........................................................................36
11.1 Layout Guidelines................................................... 36
11.2 Layout Example...................................................... 37
12 Device and Documentation Support..........................38
12.1 Documentation Support.......................................... 38
12.2 Receiving Notification of Documentation Updates..38
12.3 Support Resources................................................. 38
12.4 Trademarks.............................................................38
12.5 Electrostatic Discharge Caution..............................38
12.6 Glossary..................................................................38
13 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (May 2021) to Revision A (August 2021)
Page
•
•
Added TPS259461 device variant to the document........................................................................................... 1
Updated Equation 9 and Equation 12 ..............................................................................................................31
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5 Device Comparison Table
PG
Output
SPLYGD
Output
Overvoltage
Part Number
Overcurrent
Response
Adjustable
PG Threshold
Response To
Fault
FLT Output
Response
TPS259460ARPW
Auto-Retry
Latch-Off
Auto-Retry
Latch-Off
Y
N
Y
N
N
Y
N
TPS259460LRPW
TPS259461ARPW
TPS259461LRPW
Adjustable
OVLO
Active Current
Limit
Y
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6 Pin Configuration and Functions
IN
OUT
1
EN/UVLO
10
ITIMER
ILM
OVLO
9
8
2
3
5
6
PG/
SPLYGD
GND
PGTH/
FLT
DVDT
7
4
Figure 6-1. TPS25946xx RPW Package 10-Pin QFN Top View
Table 6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Active High Enable for the device. A Resistor Divider on this pin from input supply to GND
can be used to adjust the Undervoltage Lockout threshold. Do not leave floating. Refer to
Section 8.3.1 for details.
Analog
Input
EN/UVLO
1
A Resistor Divider on this pin from supply to GND can be used to adjust the Overvoltage
Lockout threshold. This pin can also be used as an Active Low Enable for the device. Do
not leave floating. Refer to Section 8.3.2 for details.
Analog
Input
OVLO
PG
2
3
TPS259460x: Power Good indication. This is an Open Drain signal which is asserted
High when the internal powerpath is fully turned ON and PGTH input exceeds a certain
threshold. Refer to Section 8.3.8 for more details.
Digital
Output
TPS259461x: Input Supply Good indication. This is an Open Drain signal which is asserted
High when the input supply is valid and device has completed inrush sequence. Refer to
Section 8.3.9 for more details.
SPLYGD
Analog
Input
PGTH
FLT
TPS259460x: Power Good Threshold. Refer to Section 8.3.8 for more details.
4
Digital TPS259461x: Active low Fault event indicator. This is an Open Drain signal which will be
Output pulled low when a fault is detected. Refer to Section 8.3.7 for more details.
IN
5
6
Power Power Input/Output.
Power Power Input/Output.
OUT
Analog A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating
Output for the fastest turn on slew rate. Refer to Section 8.3.3.1 for details.
DVDT
GND
7
8
Ground This is the ground reference for all internal circuits and must be connected to system GND.
This is a dual function pin used to limit and monitor the output current. An external resistor
Analog from this pin to GND sets the output current limit threshold during start-up as well as
Output steady state. The pin voltage can also be used as analog output load current monitor
signal. Do not leave floating. Refer to Section 8.3.3.2 for more details.
ILM
9
A capacitor from this pin to GND sets the overcurrent blanking interval during which the
Analog output current can temporarily exceed set current limit (but lower than fast-trip threshold)
Output before the device overcurrent response takes action. Leave this pin open for fastest
response to overcurrent events. Refer to Section 8.3.3.2 for more details.
ITIMER
10
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Parameter
Pin
MIN
-0.3
MAX UNIT
VIN
Maximum Input Voltage Range, -40 ℃ ≤ TJ ≤ 125 ℃
Maximum Output Voltage Range, -40 ℃ ≤ TJ ≤ 125 ℃
Maximum Output Voltage Range, -10 ℃ ≤ TJ ≤ 125 ℃
Minimum Output Voltage Pulse (< 1 µs)
IN
28
min (28, VIN + 21)
min (28, VIN + 22)
V
–0.3
–0.3
–0.8
–0.3
–0.3
VOUT
OUT
VOUT,PLS
OUT
VEN/UVLO Maximum Enable Pin Voltage Range
EN/UVLO
OVLO
dVdt
6.5
6.5
V
V
VOVLO
VdVdT
VITIMER
VPG
Maximum OVLO Pin Voltage Range
Maximum dVdT Pin Voltage Range
Maximum ITIMER Pin Voltage Range
Maximum PG Pin Voltage Range (TPS259460x)
Maximum PGTH Pin Voltage Range (TPS259460x)
Maximum SPLYGD Pin Voltage Range (TPS259461x)
Maximum FLT Pin Voltage Range (TPS259461x)
Maximum ILM Pin Voltage Range
Internally Limited
Internally Limited
–0.3
V
ITIMER
PG
V
6.5
6.5
6.5
6.5
V
VPGTH
VSPLYGD
VFLTB
VILM
PGTH
SPLYGD
FLT
–0.3
V
–0.3
V
–0.3
V
ILM
Internally Limited
Internally Limited
Internally Limited
V
IMAX
Maximum Continuous Switch Current
Junction temperature
IN - OUT
A
TJ
°C
°C
°C
TLEAD
TSTG
Maximum Lead Temperature
300
150
Storage temperature
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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MAX UNIT
SLVSGA8A – MAY 2021 – REVISED AUGUST 2021
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
VIN
Input Voltage Range
Output Voltage Range
IN
2.7
23
V
V
V
V
V
V
V
V
V
V
Ω
A
°C
VOUT
OUT
min (23, VIN + 20)
VEN/UVLO Enable Pin Voltage Range
EN/UVLO
OVLO
dVdt
5 (1)
VOVLO
VdVdT
VPG
OVLO Pin Voltage Range
0.5
1.5
dVdt Capacitor Voltage Rating
VIN + 5 V
PG Pin Voltage Range (TPS259460x)
PGTH Pin Voltage Range (TPS259460x)
SPLYGD Pin Voltage Range (TPS259461x)
FLT Pin Voltage Range (TPS259461x)
ITIMER Pin Capacitor Voltage Rating
ILM Pin Resistance
PG
5
5
5
5
VPGTH
VSPLYGD
VFLTB
VITIMER
RILM
PGTH
SPLYGD
FLT
ITIMER
ILM
4
549
6650
5.5
IMAX
Continuous Switch Current, TJ ≤ 125 ℃
Junction temperature
IN - OUT
TJ
–40
125
(1) For supply voltages below 5 V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5 V, TI recommends
to use a pull-up resistor with a minimum value of 350 kΩ.
7.4 Thermal Information
TPS25946xx
THERMAL METRIC (1)
RPW (QFN)
10 PINS
41.7 (2)
74.5 (3)
1
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
ΨJT
ΨJB
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
20 (2)
27.6 (3)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device.
(3) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device.
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7.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V, RILM
=
549 Ω , dVdT = Open, ITIMER = Open, PGTH/FLT = Open, PG/SPLYGD = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
INPUT SUPPLY (IN)
VUVP(R)
VUVP(F)
IQ(ON)
IQ(OFF)
ISD
IN Supply UVP Rising threshold
IN Supply UVP Falling threshold
2.44
2.35
2.53
2.42
428
73
2.64
2.55
610
130
28.7
V
V
IN Supply Quiescent Current
µA
µA
µA
IN Supply disabled State Current (VSD(F) < VEN < VUVLO(F)
)
IN Supply Shutdown Current (VEN < VSD(F)
)
4.4
ON RESISTANCE (IN - OUT)
VIN = 12 V, IOUT = 3 A, TJ = 25 ℃
28.3
mΩ
mΩ
RON
2.7 ≤ VIN ≤ 23 V, IOUT = 3 A, –40 ℃ ≤ TJ ≤ 125 ℃
45
ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO)
VUVLO(R)
VUVLO(F)
VSD(F)
UVLO Rising threshold
1.183
1.076
0.45
1.20
1.09
0.74
1.223
1.116
V
V
UVLO Falling threshold
EN/UVLO Falling Threshold for lowest shutdown current
EN/UVLO leakage current
V
IENLKG
-0.1
0.1
µA
OVERVOLTAGE LOCKOUT (OVLO)
VOV(R)
VOV(F)
IOVLKG
OVLO Rising threshold
1.183
1.076
-0.1
1.20
1.09
1.223
1.116
0.1
V
V
OVLO Falling threshold
OVLO pin leakage current, 0.5 V < VOVLO < 1.5 V
µA
OVERCURRENT PROTECTION (OUT)
Overcurrent Threshold, RILM = 6.65 kΩ
0.425
0.850
1.800
3.960
5.400
0.500
1.007
2.028
4.452
6.068
0.575
1.150
2.200
4.840
6.600
A
A
A
A
A
Overcurrent Threshold, RILM = 3.32 kΩ
Overcurrent Threshold, RILM = 1.65 kΩ
Overcurrent Threshold, RILM = 750 Ω
Overcurrent Threshold, RILM = 549 Ω
ILIM
Circuit Breaker Threshold, ILM Pin Open (Single point
failure)
0.1
1.1
A
A
IFLT
Circuit Breaker Threshold, ILM Pin Shorted to GND (Single
point failure)
2.1
ISCGain
IFT
Scalable Fast Trip Threshold (ISC) : ILIM Ratio
Fixed Fast-trip current threshold
201
22.2
1.9
%
A
VFB
VOUT threshold to exit Current Limit Foldback
V
OVERCURRENT FAULT TIMER (ITIMER)
VINT
ITIMER pin internal pull-up voltage
2.3
2.57
15
2.72
V
kΩ
µA
V
RITIMER
IITIMER
ΔVITIMER
ITIMER pin internal pull-up resistance
ITIMER pin internal discharge current, IOUT > ILIM
ITIMER discharge differential voltage threshold
1.2
1.8
2.5
1.286
1.51
1.741
OUTPUT LOAD CURRENT MONITOR (ILM)
Analog Load Current Monitor Gain (IMON : IOUT), IOUT = 0.5 A
165
165
182
182
200
200
µA/A
µA/A
to 1 A, IOUT < ILIM
GIMON
Analog Load Current Monitor Gain (IMON : IOUT), IOUT = 1 A to
5.5 A, IOUT < ILIM
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7.5 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V, RILM
549 Ω , dVdT = Open, ITIMER = Open, PGTH/FLT = Open, PG/SPLYGD = Open. All voltages referenced to GND.
=
Test
Description
MIN
TYP
MAX
UNITS
Parameter
POWER GOOD INDICATION (PG) - TPS259460x OR SUPPLY GOOD INDICATION (SPLYGD) - TPS259461x
PG/SPLYGD pin voltage while de-asserted. VIN < VUVP(F)
VEN < VSD(F), Weak pull-up (IPG = 26 μA)
,
0.67
0.79
1
1
V
V
VPGD
PG/SPLYGD pin voltage while de-asserted, VIN < VUVP(F)
VEN < VSD(F), Strong pull-up (IPG = 242 μA)
,
PG/SPLYGD pin voltage while de-asserted, VIN > VUVP(R)
PG/SPLYGD Pin leakage current, PG/SPLYGD asserted
0
V
IPGLKG
0.9
3
µA
POWERGOOD THRESHOLD (PGTH) - TPS259460x
VPGTH(R)
VPGTH(F)
IPGTHLKG
PGTH Rising threshold
PGTH Falling threshold
PGTH leakage current
1.183
1.076
-0.1
1.20
1.09
1.223
1.116
0.3
V
V
µA
FAULT INDICATION (FLT) - TPS259461x
IFLTLKG
RFLTB
FLT pin leakage current
-1
1
µA
Ω
FLT pin pull-down resistance
12.3
OVERTEMPERATURE PROTECTION (OTP)
TSD
Thermal Shutdown Rising Threshold, TJ↑
154
10
°C
°C
TSDHYS
DVDT
IdVdt
Thermal Shutdown Hysteresis, TJ↓
dVdt Pin Charging Current
0.81
2.21
3.82
µA
7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
tOVLO
tLIM
Overvoltage lock-out response time
VOVLO > VOV(R) to VOUT
↓
1.2
µs
IOUT > 1.2 x ILIM & ITIMER expired to IOUT
settling to within 5 % of ILIM
Current limit response time
340
µs
tSC
Scalable fast-trip response time
Fixed fast-trip response time
Auto-Retry Interval after fault (TPS25946xA)
PG Assertion de-glitch
IOUT > 3 x ILIM to IOUT
IOUT > IFT to IOUT
↓
500
500
110
12
ns
ns
ms
µs
µs
tFT
↓
tRST
tPGA
tPGD
PG De-assertion de-glitch
12
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7.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the
turn on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from
the dVdt pin to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current
Control (dVdt) section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant
of the load capacitance (COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up
sequence where the supply is available in steady state condition and the load voltage is completely discharged before the
device is enabled.Typical Values are taken at TJ = 25°C unless specifically noted otherwise. RL = 100 Ω, COUT = 1 µF
CdVdt
3300 pF
=
PARAMETER
VIN
CdVdt = Open CdVdt = 1800 pF
UNIT
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
12.14
28.1
44.78
0.09
0.1
0.87
1.09
1.25
0.6
0.5
SRON
tD,ON
tR
Output Rising slew rate
0.61
V/ms
0.71
0.97
Turn on delay
Rise time
1.32
1.99
2.51
8.1
2.35
ms
ms
ms
µs
0.11
3.69
0.17
0.35
0.40
0.27
0.45
0.50
64.44
25.32
23.02
4.33
15.37
25.89
5.31
14.4
3.11
10.08
16.41
64.44
25.32
23.02
tON
Turn on time
Turn off delay
17.72
29.57
64.44
25.32
23.02
tD,OFF
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7.8 Typical Characteristics
30.9
30.6
30.3
30
480
460
440
420
400
380
360
340
IOUT (A)
1
3
4
5.5
VIN (V)
2.7
5
12
23
29.7
29.4
29.1
28.8
28.5
28.2
27.9
2.5
5
7.5
10
12.5 15
VIN (V)
17.5 20
22.5 25
-40
-20
0
20
40
TA (èC)
60
80
100 120 140
D007
D011
Figure 7-1. ON-Resistance vs Supply Voltage
Figure 7-2. IN Quiescent Current vs Temperature
95
14
VIN (V)
VIN (V)
2.7
5
12
23
2.7
5
12
90
85
80
75
70
65
60
55
12
10
8
23
6
4
2
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (èC)
TA (èC)
D014
D013
Figure 7-3. IN OFF State (UVLO) Current vs Temperature
Figure 7-4. IN Shutdown Current vs Temperature
1.204
VIN (V)
2.7
5
12
23
1.203
1.202
1.201
1.2
-40
-20
0
20
40
60
80
100 120 140
TA (C)
Figure 7-6. EN/UVLO Rising Threshold vs Temperature
Figure 7-5. IN Undervoltage Threshold vs Temperature
1.097
VIN (V)
2.7
0.825
VIN (V)
0.8
2.7
5
12
23
5
12
23
0.775
0.75
0.725
0.7
1.096
1.095
1.094
1.093
0.675
0.65
0.625
0.6
0.575
0.55
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
Figure 7-7. EN/UVLO Falling Threshold vs Temperature
Figure 7-8. EN/UVLO Shutdown Falling Threshold vs
Temperature
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7.8 Typical Characteristics (continued)
1.204
VIN (V)
2.7
1.097
1.096
1.095
1.094
1.093
VIN (V)
2.7
12
12
23
23
1.203
1.202
1.201
1.2
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
Figure 7-9. OVLO Rising Threshold vs Temperature
Figure 7-10. OVLO Falling Threshold vs Temperature
7000
6000
5000
4000
3000
2000
1000
0
18
Min
Max
12
6
0
-6
-12
-18
0.5
1
1.5
2
2.5
3
3.5
RILM (kW)
4
4.5
5
5.5
6
6.5
7
0
1000
2000
3000
ILIM (mA)
4000
5000
6000
D005
Figure 7-11. Overcurrent Threshold vs ILM Resistor
Figure 7-12. Overcurrent Threshold Accuracy (Across Process,
Voltage & Temperature)
203
10
VIN (V)
2.7
Min
8
6
Max
202.5
202
5
12
23
4
2
201.5
201
0
-2
-4
-6
-8
200.5
200
-40
-20
0
20
40
TA (C)
60
80
100 120 140
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
IOUT (A)
Figure 7-14. Scalable Fast-Trip Threshold: Current Limit
Threshold (ILIM) Ratio vs Temperature
Figure 7-13. Analog Current Monitor Gain Accuracy
26
1.518
VIN (V)
VIN (V)
25
24
23
22
21
20
19
18
17
2.7
5
12
23
2.7
5
12
23
1.516
1.514
1.512
1.51
1.508
1.506
1.504
1.502
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (èC)
TA (èC)
D030
D041
Figure 7-15. Steady State Fixed Fast-Trip Current Threshold vs Figure 7-16. ITIMER Discharge Differential Voltage Threshold vs
Temperature
Temperature
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7.8 Typical Characteristics (continued)
1.83
18.5
18
VIN (V)
2.7
5
12
23
VIN (V)
2.7
5
12
23
1.825
1.82
17.5
17
1.815
1.81
16.5
16
15.5
15
1.805
1.8
14.5
14
1.795
1.79
13.5
1.785
13
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (èC)
TA (èC)
D043
D044
Figure 7-17. ITIMER Discharge Current vs Temperature
Figure 7-18. ITIMER Internal Pull-Up Resistance vs Temperature
3
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
VIN (V)
2.7
5
12
23
VIN (V)
2.9
2.7
5
12
23
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
1.9
-40
-20
0
20
40
TA (èC)
60
80
100 120 140
-40
-20
0
20
40
TA (C)
60
80
100 120 140
D029
Figure 7-20. DVDT Charging Current vs Temperature
Figure 7-19. ITIMER Internal Pull-Up Voltage vs Temperature
0.9
IPG (A)
26
242
0.85
0.8
0.75
0.7
0.65
0.6
0.55
0.5
-40
-20
0
20
40
60
80
100 120 140
TA (C)
Figure 7-22. PG Low Voltage Without Input Supply vs
Temperature
Figure 7-21. PGTH Threshold vs Temperature
Figure 7-23. Time to Thermal Shut-Down During Inrush State
Figure 7-24. Time to Thermal Shut-Down During Steady State
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7.8 Typical Characteristics (continued)
VIN
VOUT
EN
IIN
VIN = 12 V, COUT = 30 μF, CdVdt = Open, VEN/UVLO stepped up
to 1.4 V
VEN/UVLO = 3.3 V, COUT = 30 μF, CdVdt = Open, VIN ramped up
to 12 V
Figure 7-25. Start Up with Enable
Figure 7-26. Start Up with IN Supply
EN
VOUT
PG
IIN
COUT = 220 μF, CdVdt = 10 nF, EN/UVLO connected to IN
through resistor ladder, 12 V hot-plugged to IN
VIN = 12 V, COUT = 470 μF, CdVdt = 3300 pF, VEN/UVLO stepped
up to 1.4 V
Figure 7-27. IN Hot-Plug
Figure 7-28. Inrush Current with Capacitive Load
VIN
VIN
VOUT
VOUT
PG
OVLO
IIN
COUT = 220 μF, IOUT = 4 A, VIN Overvoltage threshold set to
22 V, VIN ramped up from 20 V to 23 V
VIN = 12 V, COUT = 470 μF, ROUT = 5 Ω, CdVdt = 3300 pF,
VEN/UVLO stepped up to 1.4 V
Figure 7-30. Overvoltage Lockout Response
Figure 7-29. Inrush Current with Resistive and Capacitive Load
VIN
VOUT
VIN
VOUT
ITIMER
IIN
FLTb
IIN
VIN = 12 V, CITIMER = 2.2 nF, COUT = 470 μF, RILM = 549 Ω,
IOUT ramped from 4 A → 8 A→ 4 A within 1 ms
VIN = 12 V, CITIMER = 2.2 nF, COUT = 220 μF, RILM = 549 Ω,
IOUT stepped from 3 A → 9 A → 3 A within 5 ms
Figure 7-31. Transient Overcurrent Blanking Timer Response
Figure 7-32. Active Current Limit Response
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7.8 Typical Characteristics (continued)
VIN
VIN
VOUT
VOUT
IIN
FLTb
IOUT
VIN = 12 V, CITIMER = 2.2 nF, COUT = 220 μF, RILM = 549 Ω,
IOUT stepped from 3 A → 9 A
VIN = 12 V, RILM = 549 Ω, VEN/UVLO = 3.3 V, OUT stepped from
Open → Short-circuit to GND
Figure 7-33. Active Current Limit Response Followed by TSD
Figure 7-34. OUT Pin Short-Circuit During Steady State
VIN
VIN
VOUT
VOUT
PG
IIN
IOUT
VIN = 12 V, RILM = 549 Ω, VEN/UVLO = 3.3 V, OUT stepped from
Open → Short-circuit to GND
VIN = 5 V, COUT = Open, OUT short-circuit to GND, RILM = 750
Ω, VEN/UVLO stepped from 0 V to 3.3 V
Figure 7-35. OUT Pin Short-Circuit During Steady State
(Zoomed In)
Figure 7-36. Power Up with OUT Pin Short-Circuit to GND
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8 Detailed Description
8.1 Overview
The TPS25946xx is an eFuse with integrated power path that is used to ensure safe power delivery in a system.
The device starts its operation by monitoring the IN bus. When the input supply voltage (VIN) exceeds the
Undervoltage Protection threshold (VUVP), the device samples the EN/UVLO pin. A high level (> VUVLO) on
this pin enables the internal power path (BFET+HFET) to start conducting and allow current to flow in both
directions. When the IN supply voltage is insufficient (< VUVP) or the EN/UVLO is held low (< VUVLO), the internal
power path is turned off, thereby blocking current flow in both directions.
After a successful start-up sequence, the device now actively monitors its IN voltage and load current from
IN to OUT, and controls the internal HFET to ensure that the user adjustable overcurrent limit threshold (ILIM
)
is not exceeded and overvoltage spikes are cut-off once they cross the user adjustable overvoltage lockout
threshold (VOVLO). The device also provides fast protection against severe overcurrent during short-circuit events
on OUT pin. This keeps the system safe from harmful levels of voltage and current. At the same time, a user
adjustable overcurrent blanking timer allows the system to pass moderate transient peaks in the load current
profile without tripping the eFuse. This ensures a robust protection solution against real faults which is also
immune to transients, thereby ensuring maximum system uptime.
The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device
temperature (TJ) exceeds the recommended operating conditions.
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8.2 Functional Block Diagram
FFT
TPS259460x
353.9 mV
Temp Sense &
Overtemperature
protection
TSD
OUT
5
6
IN
INRUSH_DONE
2.8V
BFET
HFET
7
DVDT
CP
îXîí …A
+
UVPb
2.53V9
-
íôî …A/A
GHI
FFT
GHI
2.42V;
2x
1x
-
-
HFET Control
SC
OVLO
2
OVLOb
1.20V9
1.09V;
+
+
-
BFET Control
Current Limit
Amplifier
OC
+
1
EN/UVLO
UVLOb
+
9
ILM
1.20V9
-
1.09V;
SWEN
Short
Detect
INRUSH_DONE
-
SD
ILM Pin Short
+
0.74V;
PG_int
1.06 V; 2.57 V
INRUSH_DONE
+
SD
UVPb
R
S
/Q
Q
ITIMER_EXPIRED
PG_int
RETRY#
10
ITIMER
-
PG_int
TSD
FLT
OC
ILM Pin Short
íXô …A
8
GND
R
S
110 ms
TIMER#
RETRY#
Q
/Q
1.2V9
1.09V;
3
4
PG
PGTH
# Not applicable to Latch-off variants (TPS259460L)
Figure 8-1. TPS259460x Block Diagram
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FFT
TPS259461x
353.9 mV
Temp Sense &
Overtemperature
protection
TSD
OUT
5
6
7
IN
INRUSH_DONE
2.8V
BFET
HFET
DVDT
CP
îXîí …A
+
UVPb
2.53V9
-
íôî …A/A
GHI
FFT
GHI
2.42V;
2x
1x
-
-
HFET Control
SC
OVLO
2
OVLOb
UVLOb
1.20V9
1.09V;
+
+
-
BFET Control
Current Limit
Amplifier
OC
+
1
EN/UVLO
+
9
ILM
1.20V9
-
1.09V;
SWEN
Short
Detect
INRUSH_DONE
-
SD
ILM Pin Short
+
0.74V;
1.06 V; 2.57 V
RETRY#
+
SD
UVPb
R
S
/Q
Q
ITIMER_EXPIRED
110 ms
TIMER#
RETRY#
10
ITIMER
-
TSD
FLT
OC
ILM Pin Short
íXô …A
ITIMER_EXPIRED
8
GND
4
3
SPLYGD
FLT
# Not applicable to Latch-off variants (TPS259461L)
Figure 8-2. TPS259461x Block Diagram
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8.3 Feature Description
The TPS25946xx eFuse is a compact, feature rich power management device that provides detection, protection
and indication in the event of system faults.
8.3.1 Undervoltage Lockout (UVLO & UVP)
The TPS25946xx implements Undervoltage Protection on IN in case the applied voltage becomes too low for the
system or device to properly operate. The Undervoltage Protection has a default lockout threshold of VUVP which
is fixed internally. Also, the UVLO comparator on the EN/UVLO pin allows the Undervoltage Protection threshold
to be externally adjusted to a user defined value. The Figure 8-3 and Equation 1 show how a resistor divider can
be used to set the UVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/UVLO
R2
GND
Figure 8-3. Adjustable Undervoltage Protection
VUVLO x (R1 + R2)
VIN(UV)
=
(1)
8.3.2 Overvoltage Lockout (OVLO)
The TPS25946xx allows the user to implement Overvoltage Lockout to protect the load from input overvoltage
conditions. The OVLO comparator on the OVLO pin allows the Overvoltage Protection threshold to be adjusted
to a user defined value. Once the voltage at the OVLO pin crosses the OVLO rising threshold VOV(R), the device
turns off the power to the output. Thereafter, the devices wait for the voltage at the OVLO pin to fall below the
OVLO falling threshold VOV(F) before the output power is turned ON again. The rising and falling thresholds are
slightly different to provide hysterisis. The Figure 8-4 and Equation 2 show how a resistor divider can be used to
set the OVLO set point for a given voltage supply.
Power
Supply
IN
R1
OVLO
R2
GND
Figure 8-4. Adjustable Overvoltage Protection
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VOV x (R1 + R2)
VIN(OV)
=
(2)
While recovering from a OVLO event, the TPS25946xx starts up with inrush control (dVdt).
Input Overvoltage Event
Input Overvoltage Removed
IN
0
VOV(R)
VOV(F)
OVLO
tOVLO
0
dVdt Limited
Start-up
OUT
PG*
0
VL
0
tPGA
tPGD
VL
0
SPLYGD**
Time
* Applicable only to TPS259460x variants
** Applicable only to TPS259461x variants
Figure 8-5. TPS25946xx Overvoltage Lockout and Recovery
8.3.3 Inrush Current, Overcurrent, and Short Circuit Protection
TPS25946xx incorporates four levels of protection against overcurrent in forward direction (IN to OUT):
1. Adjustable slew rate (dVdt) for inrush current control
2. Adjustable threshold (ILIM) for overcurrent protection during start-up or steady-state
3. Adjustable threshold (ISC) for fast-trip response to severe overcurrent during start-up or steady-state
4. Fixed threshold (IFT) for fast-trip response to quickly protect against hard output short-circuits during steady-
state
8.3.3.1 Slew Rate (dVdt) and Inrush Current Control
During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large
inrush current. If the inrush current is not managed properly, it can damage the input connectors and/or cause
the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current
during turn on is directly proportional to the load capacitance and rising slew rate. Equation 3 can be used to find
the slew rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (COUT):
IINRUSH (mA)
SR (V/ms) =
C
OUT (µF)
(3)
A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during
turn on. The required CdVdt capacitance to produce a given slew rate can be calculated using Equation 4.
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2000
CdVdt (pF) =
SR (V/ms)
(4)
The fastest output slew rate is achieved by leaving the dVdt pin open.
Note
For CdVdt > 10 nF, TI recommends to add a 100-Ω resistor in series with the capacitor on the dVdt pin.
8.3.3.2 Active Current Limiting
The TPS25946xx responds to output overcurrent conditions by actively limiting the current after a user
adjustable transient fault blanking interval. When the load current exceeds the set overcurrent threshold (ILIM
)
set by the ILM pin resistor (RILM), but stays lower than the short-circuit threshold (2 × ILIM), the device starts
discharging the ITIMER pin capacitor using an internal 1.8-μA pull-down current. If the load current drops below
the overcurrent threshold before the ITIMER capacitor (CITIMER) discharges by ΔVITIMER, the ITIMER is reset
by pulling it up to VINT internally and the current limit action is not engaged. This allows short load transient
pulses to pass through the device without getting current limited. If the overcurrent condition persists, the CITIMER
continues to discharge and once it discharges by ΔVITIMER, the current limit starts regulating the HFET to actively
limit the current to the set overcurrent threshold (ILIM). At the same time, the CITIMER is charged up to VINT
again so that it is at its default state before the next overcurrent event. This ensures the full blanking timer
interval is provided for every overcurrent event. Equation 5 can be used to calculate the RILM value for a desired
overcurrent threshold.
3334
: ;
RILM À =
: ;
A
ILIM
(5)
Note
1. The device offers overcurrent protection only in forward direction i.e. from IN to OUT. There' i no
overcurrent protection from OUT to IN during ON state.
2. Leaving the ILM pin Open sets the current limit to nearly zero and results in the part entering
current limit with the slightest amount of loading at the output.
3. The current limit circuit employs a foldback mechanism. The current limit threshold in the foldback
region (0 V < VOUT < VFB) is lower than the steady state current limit threshold (ILIM).
4. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the
part shuts down. There’s a minimum current (IFLT) which the part allows in this condition before
the pin short condition is detected.
The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER
pin to ground. The CITIMER value needed to set the desired transient overcurrent blanking interval can be
calculated using Equation 6 below.
¿VITIMER (V) x CITIMER (nF)
tITIMER (ms) =
IITIMER (µA)
(6)
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Overload Removed
Persistent Output Overload ITIMER expired Thermal shutdown
Transient Overcurrent
Persistent Output Overload ITIMER expired
2 x ILIM
tLIM
tLIM
IOUT
ILIM
Current limiting
operation
Current limiting
operation
0
tITIMER
tITIMER
VINT
∆VITIMER
ITIMER
OUT
0
VIN
0
1.2 V
PGTH *
tPGD
tPGD
tPGA
0
VPG
PG *
0
VFLT
FLT **
0
TSD
TSDHYS
TJ
TJ
Time
* Applicable only to TPS259460x variants
** Applicable only to TPS259461x variants
Figure 8-6. TPS25946xx Active Current Limit Response
Note
1. Leave the ITIMER pin open to allow the part to limit the current with the minimum possible delay.
2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar
to ITIMER pin open condition), but increases the device current consumption. This is not a
recommended mode of operation.
3. Active current limiting based on RILM is active during startup. In case the startup current exceeds
ILIM, the device regulates the current to the set limit. However, during startup the current limit is
engaged without waiting for the ITIMER delay.
4. Increasing the CITIMER value extends the overcurrent blanking interval, but it also extends the
time needed for the CITIMER to recharge up to VINT. If the next overcurrent event occurs before
the CITIMER is recharged fully, it will take lesser time to discharge to the ITIMER expiry threshold,
thereby providing a shorter blanking interval than intended.
During active current limit, the output voltage will drop resulting in increased device power dissipation across the
HFET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the HFET is turned
off. Once the part shuts down due to TSD fault, it would either stay latched off (TPS25946xL variants) or restart
automatically after a fixed delay (TPS25946xA variants). See Overtemperature Protection (OTP) for more details
on device response to overtemperature.
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8.3.3.3 Short-Circuit Protection
During an short-circuit event on OUT pin, the current from IN to OUT increases very rapidly. When a severe
overcurrent condition is detected, the TPS25946xx triggers a fast-trip response to limit the current through
the device to a safe level. The internal fast-trip comparator employs a scalable threshold (ISC) which is equal
to 2 × ILIM. This enables the user to adjust the fast-trip threshold rather than using a fixed threshold which
can be too high for some low current systems. The device also employs a fixed fast-trip threshold (IFT) to
protect fast protection against hard short-circuits during steady state. The fixed fast-trip threshold is higher than
the maximum recommended user adjustable scalable fast-trip threshold. Once the current exceeds ISC or IFT,
the HFET is turned off completely within tFT. Thereafter, the devices tries to turn the HFET back on after a
short de-glitch interval (30 μs) in a current limited manner instead of a dVdt limited manner. This ensures that
the HFET has a faster recovery after a transient overcurrent event and minimizes the output voltage droop.
However, if the fault is persistent, the device will stay in current limit causing the junction temperature to rise
and eventually enter thermal shutdown. See Overtemperature Protection (OTP) section for details on the device
response to overtemperature.
Persistent Severe Overcurrent
Thermal Shutdown
Overcurrent Removed
Retry Timer Elapsed (1)
Transient Severe Overcurrent
Output Hard Short-circuit to ground
Thermal Shutdown
Short-circuit Removed
Retry Timer Elapsed (1)
VIN
IN
0
tFT
tSC
tSC
IFT
2 x ILIM
IOUT
ILIM
0
VIN
OUT
dVdt Limited
Start-up
dVdt Limited
Start-up
Current Limited
Start-up
0
tPGD
tPGD
tPGD
VPG
PG
0
tRST
tRST
TSD
TSDHYS
TJ
Time
(1) Applicable only to TPS259460A variants
Figure 8-7. TPS25946xx Short-Circuit Response
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8.3.4 Analog Load Current Monitor
The TPS25946xx allows the system to accurately monitor the load current by providing an analog current sense
output on the ILM pin which is proportional to the current through the FET from IN to OUT. The user can sense
the voltage (VILM) across the RILM to get a measure of the output load current.
VILM (µV)
IOUT (A) =
RILM :À; x GIMON (µA/A)
(7)
The waveform below shows the ILM signal response to a load step at the output.
VIN
VOUT
VILM
IIN
VIN = 12 V, COUT = 22 μF, RILM = 1150 Ω, IOUT varied dynamically between 0 A and 3.5 A
Figure 8-8. Analog Load Current Monitor Response
Note
1. The ILM pin is sensitive to capacitive loading. Careful design and layout is needed to ensure the
parasitic capacitive loading on the ILM pin is < 50 pF for stable operation.
2. The ILM pin can only report the current flowing from IN to OUT and not from OUT to IN.
8.3.5 Reverse Current Protection
The TPS25946xx has integrated back-to-back MOSFETs connected in a common drain configuration. When the
device is in powered down or disabled state, both the FETs are turned OFF, thereby blocking the current flow in
forward as well as reverse direction.
8.3.6 Overtemperature Protection (OTP)
The TPS25946xx monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD), thereby protecting the device from damage. The device will
not turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD – TSDHYS).
When the TPS25946xL (latch-off variant) detects thermal overload, it will be shut down and remain latched-off
until the device is power cycled or re-enabled. When the TPS25946xA (auto-retry variant) detects thermal
overload, it will remain off until it has cooled down by TSDHYS. Thereafter, it will remain off for an additional delay
of tRST after which it will automatically retry to turn on if it is still enabled.
Table 8-1. Thermal Shutdown
DEVICE
ENTER TSD
EXIT TSD
TJ < TSD – TSDHYS
VIN cycled to 0 V and then above VUVP(R) OR
EN/UVLO toggled below VSD(F)
TPS25946xL (Latch-Off)
TJ ≥ TSD
TJ < TSD – TSDHYS
VIN cycled to 0 V and then above VUVP(R) OR
TPS25946xA (Auto-Retry)
TJ ≥ TSD
EN/UVLO toggled below VSD(F) OR tRST timer
expired
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8.3.7 Fault Response and Indication (FLT)
The following table summarizes the device response to various fault conditions. Additionally, an active low
external fault indication (FLT) pin is available on the TPS259461x variants.
Table 8-2. Fault Summary
Event
Protection Response
Fault Latched Internally FLT Pin Status(1)
FLT Assertion Delay(1)
Overtemperature
Shutdown
Y
N
N
N
L
Undervoltage (UVP or
UVLO)
Shutdown
Shutdown
None
H
H
H
Input Overvoltage
Transient Overcurrent (ILIM
< IOUT < 2 × ILIM
)
Persistent Overcurrent
in forward direction (IN to
OUT)
Current Limit
N
N
L
tITIMER
OUT Pin Short-Circuit to
GND
Circuit Breaker followed by
Current Limit
H
ILM Pin Open
(During Steady State)
Shutdown
Shutdown
N
Y
L
L
tITIMER
tITIMER
ILM Pin Shorted to GND
(1) Applicable to TPS259461x variants only.
Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by
pulling the EN/UVLO pin voltage below VSD. This also resets the tRST timer for the TPS25946xA (auto-retry)
variants.
During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This is
true for both TPS25946xL (latch-off) & TPS25946xA (auto-retry) variants.
The TPS25946xA (auto-retry) variants restart automatically on expiry of the tRST timer after a fault.
8.3.8 Power Good Indication (PG)
The TPS259460x variants provide an active high digital output (PG) which serves as a power good indication
signal and is asserted high depending on the voltage at the PGTH pin along with the device state information.
The PG is an open-drain pin and needs to be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned
on in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush
sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time
(tPGA).
PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F) or the device
detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD
.
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Overload Event
Overcurrent blanking timer expired
Overload Removed
Device Enabled
VUVLO(R)
0
EN/UVLO
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
VIN
Active Current
limiting
OUT
0
VPGTH(R)
VPGTH(F)
PGTH*
0
VPG
PG*
tPGA
tPGD
tPGA
0
VPG
SPLYGD**
0
VIN
dVdt
0
VOUT + 2.8V
VHGate
0
tITIMER
ILIM
IINRUSH
0
IOUT
Time
* Applicable only to TPS259460x variants
** Applicable only to TPS259461x variants
Figure 8-9. TPS259460x PG Timing Diagram
Table 8-3. TPS259460x PG Indication Summary
Event
Protection Response
PG Pin Status
PG Delay
Undervoltage (UVP or UVLO)
Overvoltage (OVLO)
Shutdown
L
L (If PGTH pin voltage <
Shutdown
tPGD
VPGTH(F)
)
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Table 8-3. TPS259460x PG Indication Summary (continued)
Event
Protection Response
PG Pin Status
PG Delay
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
)
tPGA
tPGD
Steady State
NA
)
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
)
tPGA
tPGD
Transient overcurrent
NA
)
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
Persistent overload in forward
direction (IN to OUT)
)
tPGA
tPGD
Current Limiting
)
H (If PGTH pin voltage >
VPGTH(R)
)
tPGA
tPGD
OUT Pin Short-Circuit to GND
Fast trip followed by Current Limit
L (If PGTH pin voltage <
VPGTH(F)
)
L (If PGTH pin voltage <
VPGTH(F)
ILM Pin Open
Shutdown
Shutdown
Shutdown
tPGD
tPGD
tPGD
)
L (If PGTH pin voltage <
VPGTH(F)
ILM Pin Shorted to GND
Overtemperature
)
L (If PGTH pin voltage <
VPGTH(F)
)
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pull-down
in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply
which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the
pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize the sink current to keep
this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.
8.3.9 Input Supply Good Indication (SPLYGD)
The TPS259461x variants provide an active high digital output (SPLYGD) which is asserted to indicate when the
input supply is in a valid range (above UVP/UVLO and below OVLO thresholds) and the device has successfully
completed its inrush sequence. This pin can be used as a supply valid status indication to the downstream load
or system supervisor.
The SPLYGD pin is an open-drain signal which needs to be pulled up to an external supply.
After power up, SPLYGD pin is pulled low initially. The device initiates a inrush sequence in which the HFET is
turned on in a controlled manner. When the FET gate voltage has reached the full overdrive indicating that the
inrush sequence is complete and device is capable of delivering full power, the SPLYGD pin is asserted high.
Thereafter, the SPLYGD pin is de-asserted only if the input supply becomes invalid (below UVP/UVLO or above
OVLO thresholds). No load side events/faults have any control over the SPLYGD de-assertion.
Table 8-4. TPS259461x SPLYGD Indication Summary
Event
SPLYGD Pin
Undervoltage (UVP or UVLO)
Overvoltage (OVLO)
Inrush
L
L
L
H
Steady State
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Table 8-4. TPS259461x SPLYGD Indication Summary (continued)
Event
SPLYGD Pin
Overcurrent
H
H
H
H
H
OUT Pin Short-Circuit to GND
ILM Pin Open
ILM Pin Shorted to GND
Overtemperature
When there is no supply to the device, the SPLYGD pin is expected to stay low. However, there is no active
pull-down in this condition to drive this pin all the way down to 0 V. If the SPLYGD pin is pulled up to an
independent supply which is present even if the device is unpowered, there can be a small voltage seen on this
pin depending on the pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize
the sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external
circuits in this condition.
8.4 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS25946xx is a 2.7 V to 23 V, 5.5-A eFuse that is typically used for power rail protection applications.
The device operates from 2.7 V to 23 V with adjustable overvoltage and undervoltage protection. The device
provides ability to control inrush current and bidirectional current flow when enabled. The device can be used in
a variety of applications such as Smartphones, Tablets, Digital Cameras, Point of Sales terminals, USB On-The-
Go (OTG) enabled devices, Wireless Chargers etc.The design procedure explained in the subsequent sections
can be used to select the supporting component values based on the application requirement. Additionally, a
spreadsheet design tool TPS25946xx Design Calculator is available in the web product folder.
9.1.1 Single Device, Self-Controlled
VIN = 2.7 to 23 V
VIN = 2.7 to 23 V
VOUT
VOUT
IN
OUT
IN
OUT
VLOGIC
COUT
COUT
PGTH
EN/UVLO
OVLO
EN/UVLO
OVLO
VLOGIC
TPS259460x
TPS259461x
FLT
PG
SPLYGD
ITIMER dVdt
ILM
ITIMER dVdt
GND
GND
ILM
RILM
RILM
CITIMER
CDVDT
CITIMER
CDVDT
Figure 9-1. Single Device, Self-Controlled
Other Variations:
In a Host MCU controlled system, EN/UVLO or OVLO can also be driven from the host GPIO to control the
device.
ILM pin can be connected to the MCU ADC input for current monitoring purpose.
Note
TI recommends to keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation.
For TPS259460x variants, either VIN or VOUT can be used to drive the PGTH resistor divider depending on which
supply needs to be monitored for power good indication.
9.2 Typical Application
Smartphones come equipped with USB OTG functionality that allows their USB port to be used not only for
charging the phone battery but also allow the smartphone to act as a USB host and deliver power to external
accessories such as headphones, pen drives etc. Some smartphones also support a wireless charging path
which can also be used to wirelessly share power to other devices. TPS25946xx can be used as a bi-directional
power switch in such applications as shown in Figure 9-2.
For the USB power path, when an external charger is connected at the port, TPS25946xx provides a conduction
path from IN pin to OUT pin and the battery charger IC is configured to charge the battery and also power the
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internal circuits. TPS25946xx also provides overvoltage and overcurrent protection in this case. In another use
case scenario where an accessory such as headphone is connected to the USB port, the phone MCU will detect
this and the battery charger is configured in OTG boost mode to provide power from battery to the USB port. In
this case, the TPS25946xx also needs to be turned on to establish the power path from OUT to IN. Before that,
there needs to be a minimum voltage (VUVP(R)) available at the IN pin. An series diode and resistor is added in
parallel to the device to provide this initial bias voltage. Once MCU detects that the accessory is connected, it
enables the TPS25946xx and establishes a low impedance power path capable of delivering high power to the
accessory.
Similarly, the TPS25946xx also provides controlled bi-directional power flow in the wireless charging & power
share sub-system.
VBUS = 5 to 20 V
IN
OUT
SYS
System Load
VBUS
CBUS
PGTH
PG
BQ25898x
OVLO
TPS259460x
System MCU
EN/UVLO
ILM
PMID
BAT
ITIMER dVdt
GND
RILM
CITIMER
CDVDT
IN
OUT
Wireless
Charger
PGTH
PG
OVLO
TPS259460x
System MCU
EN/UVLO
ILM
ITIMER dVdt
GND
Current monitor ADC
RILM
CITIMER
CDVDT
Figure 9-2. Smartphone Power Path Example
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R5 11O
D1
VBUS = 5 to 20 V
VOUT
IN
OUT
SYS
System Load
VBUS
VLOGIC
R3
100kO
R1
470kO
COUT
47µF
D2*
TVS2200
CBUS
10µF
BQ25898x
OVLO
PG
TPS259460x
System
MCU
R2
44.2kO
R4
36.5kO
EN/UVLO
BAT
PGTH
ITIMER dVdt
ILM
GND
RILM
1050O
CITIMER
2.2nF
CDVDT
1100pF
* Optional circuit components needed for transient protection. Please refer to Transient Protection section for
details.
Figure 9-3. USB On-The-Go Port Protection Design Example
9.2.1 Design Requirements
Table 9-1. Design Parameters
PARAMETER
VALUE
9 V
Bus voltage during charging (VIN)
Overvoltage protection threshold during charging (VIN(OV)
)
14 V
Bus power good threshold (VPG
)
4.5 V
Max continuous charging current
3 A
Load transient blanking interval during charging (tITIMER
)
2 ms
Output capacitance (COUT
Output rise time (tR)
)
47 μF
5 ms
Overcurrent threshold (ILIM) during charging
3.25 A
100 mA
Start-up load current supported during USB OTG operation (ILOAD
)
Fault response
Auto-retry
9.2.2 Detailed Design Procedure
9.2.2.1 Device Selection
TPS259460A variant is selected after refering to the Device Comparison Table.
9.2.2.2 Setting Overvoltage Threshold
The supply overvoltage threshold is set using the resistors, R1 & R2, whose values can be calculated using
Equation 8:
VOV(R) x (R1 + R2)
VIN(OV)
=
(8)
Where VOV(R) is the OVLO rising threshold. Because R1, R2 leak the current from input supply VIN, these
resistors must be selected based on the acceptable leakage current from input power supply VIN. The current
drawn by R1, R2 from the power supply is IR12 = VIN / (R1 + R2). However, leakage currents due to external
active components connected to the resistor string can add error to these calculations. So, the resistor string
current, IR12, must be chosen to be 20 times greater than the leakage current expected on the OVLO pin.
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From the device electrical specifications, OVLO leakage current is 0.1 μA (maximum), VOV(R) = 1.2 V. From
design requirements, VIN(OV) = 14 V. To solve the equation, first choose the value of R1 = 470 kΩ and use the
above equation to solve for R2 = 44.06 kΩ.
Using the closest standard 1% resistor values, we get R1 = 470 kΩ, R2 = 44.2 kΩ.
9.2.2.3 Setting Output Voltage Rise Time (tR)
For a successful design, the junction temperature of device must be kept below the absolute maximum rating
during both dynamic (start-up) and steady-state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and inrush
current limit required with system capacitance to avoid thermal shutdown during start-up.
The slew rate (SR) needed to achieve the desired output rise time can be calculated as:
VIN (V)
9 V
SR (V/ms) =
=
= 1.8 V/ms
tR (ms) 5 ms
(9)
The CdVdt needed to achieve this slew rate can be calculated as:
2000
2000
1.8
:
;
CdVdt pF =
=
= 1111 pF
:
SR V/ms
;
(10)
Choose the nearest standard capacitor value as 1100 pF.
For this slew rate, the inrush current can be calculated as:
:
;
:
IINRUSH mA = SR (V/ms) x COUT µF = 1.8 x 47 = 84.6 mA
;
(11)
(12)
The average power dissipation inside the part during inrush can be calculated as:
: ;
IINRUSH A x VIN
: ;
V
0.085 x 9
: ;
PDINRUSH W =
=
= 0.38 W
For the given power dissipation, the thermal shutdown time of the device must be greater than the ramp-up time
tR to avoid start-up failure. Figure 9-4 shows the thermal shutdown limit, for 0.38 W of power, the shutdown time
is over 100 ms which is very large as compared to tR = 5 ms. Therefore, it is safe to use 5 ms as the startup time
for this application.
Figure 9-4. Thermal Shut-Down Plot During Inrush
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9.2.2.4 Setting Power Good Assertion Threshold
The Power Good assertion threshold can be set using the resistors R3 & R4 connected to the PGTH pin whose
values can be calculated as:
VPGTH(R) x (R3 + R4)
VPG =
R4
(13)
Because R3 and R4 leak the current from the output rail VOUT, these resistors must be selected to minimize the
leakage current. The current drawn by R3 and R4 from the power supply is IR34 = VOUT / (R3 + R4). However,
leakage currents due to external active components connected to the resistor string can add error to these
calculations. So, the resistor string current, IR34, must be chosen to be 20 times greater than the PGTH leakage
current expected. From the device electrical specifications, PGTH leakage current is 1 μA (max), VPGTH(R) = 1.2
V and from design requirements, VPG = 4.5 V. To solve the equation, first choose the value of R3 = 100 kΩ and
calculate R4 = 36.4 kΩ. Choose nearest 1% standard resistor value as R4 = 36.5 kΩ.
9.2.2.5 Setting Overcurrent Threshold (ILIM
)
The overcurrent protection (Circuit Breaker) threshold can be set using the RILM resistor whose value can be
calculated as:
3334
3334
: ;
RILM À =
=
= 1025.8 À
: ;
A
ILIM
3.25 A
(14)
Choose nearest 1% standard resistor value as 1050 Ω.
9.2.2.6 Setting Overcurrent Blanking Interval (tITIMER
)
The overcurrent blanking timer interval can be set using the CITIMER capacitor whose value can be calculated as:
tITIMER (ms) x IITIMER (µA)
2 x 1.8
1.51
CITIMER (nF) =
=
= 2.38 nF
¿VITIMER (V)
(15)
Choose nearest standard capacitor value as 2.2 nF.
9.2.2.7 Selecting External Bias Resistor (R5)
During OTG mode of operation, initially the TPS259460A is in OFF state. The initial bias voltage at the USB bus
provided by external diode (D1) and resistor (R5) can be calculated as:
: ; : ; : ; : ;
VBUS (V) = VOUT V F VF V F ILOAD A x R5 À
Where
VOUT = Voltage at OUT pin provided by the charger IC in OTG boost mode
VF = diode forward voltage drop
ILOAD = current drawn by USB powered peripheral initially
The bus voltage must be greater than VUVP(R) to ensure the TPS259460A can turn on and start delivering the full
load current demanded by the USB peripheral. Putting the value of VF = 0.4 V, VOUT (minimum) = 4.5 V, VUVP(R)
= 2.53 V, ILOAD = 100 mA gives maximum value of R5 = 15.7 Ω. Choose value as 11 Ω.
Initial power dissipation across R5 can be calculated as:
: ;
: ;
: ;
PD W = ILOAD A x ILOAD A x R5 À
: ;
For ILOAD = 100 mA and R5 = 11 Ω, the power dissipation in the resistor is 0.11 W. Choose a resistor with power
rating higher than this value for safe operation. A 0.25-W resistor must be suitable for this application.
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9.2.2.8 Selecting External Diode (D1)
1. Diode must have low forward voltage drop (VF) to give more headroom to voltage at IN pin above VUVP(R).
2. Diode must be able to support initial load current required by USB peripheral.
3. Diode must have small footprint.
9.2.3 Application Curve
VSYS
VBUS
EN
PG
Figure 9-5. Power Up in OTG Mode
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10 Power Supply Recommendations
The TPS25946xx devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 23 V. An input ceramic
bypass capacitor higher than 0.1 μF is recommended if the input supply is located more than a few inches from
the device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
10.1 Transient Protection
In the case of a short-circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
•
•
•
•
•
Minimize lead length and inductance into and out of the device.
Use a large PCB GND plane.
Connect a Schottky diode from the OUT pin ground to absorb negative spikes.
Connect a low ESR capacitor larger than 1 μF at the OUT pin very close to the device.
Use a low-value ceramic capacitor CIN = 1 μF to absorb the energy and dampen the transients. The capacitor
voltage rating must be at least twice the input supply voltage to be able to withstand the positive voltage
excursion during inductive ringing.
The approximate value of input capacitance can be estimated with Equation 16:
LIN
¨
VSPIKE(Absolute) = VIN + LOAD x
I
CIN
(16)
where
– VIN is the nominal supply voltage.
– ILOAD is the load current.
– LIN equals the effective inductance seen looking into the source.
– CIN is the capacitance present at the input.
•
•
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients
from exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude
of the transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive
energy dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which
can couple to the internal control circuits and cause unexpected behavior.
For applications such as USB-C ports where a powered cable can be plugged to the output of the device,
there can be excess voltage stress from OUT to IN which exceeds the absolute maximum rating of the
device. TI recommends to add a TVS diode from OUT to IN to clamp the voltage to a safe level.
The circuit implementation with optional protection components is shown in Figure 10-1.
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D3
D4
VOUT
VIN = 2.7 to 23 V
IN
OUT
R1
R2
COUT
D2
PG/
SPLYGD
EN/UVLO
OVLO
TPS25946xx
PGTH/
FLT
CIN
D1
ITIMER dVdt
GND
ILM
R3
RILM
CITIMER
CDVDT
Figure 10-1. Circuit Implementation with Optional Protection Components
10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in
results:
•
•
•
•
•
•
•
Source bypassing
Input leads
Circuit layout
Component selection
Output shorting method
Relative location of the short
Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like
those in this data sheet because every setup is different.
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11 Layout
11.1 Layout Guidelines
•
For all applications, a ceramic decoupling capacitor of 0.1 μF or greater is recommended between the IN
terminal and GND terminal.
•
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC.
•
•
High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible
trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate
ground plane island for the eFuse. This plane doesn't carry any high currents and serves as a quiet ground
reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the
system power ground plane using a star connection.
•
•
The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom PCB
layers using as possible. Adding thermal vias on the under the device further helps to minimize the voltage
gradient accross the IN and OUT pads and distribute current unformly through the device, which improves
the on-resistance and current sense accuracy.
Locate the following support components close to their connection pins:
– RILM
– CdVdT
– CITIMER
– Resistors for the EN/UVLO, OVLO and PGTH pins
•
Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the RILM, CITIMER and CdVdt components to the device must be as short as possible to reduce
parasitic effects on the current limit , overcurrent blanking interval and soft start timing. TI recommends to
keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. These traces must not have
any coupling to switching signals on the board.
•
•
Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the
PCB routing of this node must be kept away from any noisy (switching) signals.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, a protection Schottky diode is recommended to address negative transients due to
switching of inductive loads. TI also recommends to add a ceramic decoupling capacitor of 1 μF or greater
between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to
minimize the loop area formed by the Schottky diode/bypass-capacitor connection, the OUT pin and the GND
terminal of the IC.
Copyright © 2021 Texas Instruments Incorporated
36
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TPS25946
SLVSGA8A – MAY 2021 – REVISED AUGUST 2021
www.ti.com
11.2 Layout Example
Bottom Signal/GND layer
Top Power layer
6
OUT
5
IN
Figure 11-1. Layout Example
Copyright © 2021 Texas Instruments Incorporated
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TPS25946
SLVSGA8A – MAY 2021 – REVISED AUGUST 2021
www.ti.com
12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
TPS25946EVM eFuse Evaluation Board
TPS25946xx Design Calculator
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
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TPS25946
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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39
Product Folder Links: TPS25946
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS259460ARPWR
TPS259460LRPWR
TPS259461ARPWR
TPS259461LRPWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RPW
RPW
RPW
RPW
10
10
10
10
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2GKH
2HCH
2L6H
2L7H
Call TI | NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS259460ARPWR
TPS259460LRPWR
TPS259461ARPWR
TPS259461LRPWR
VQFN-
HR
RPW
RPW
RPW
RPW
10
10
10
10
3000
3000
3000
3000
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
VQFN-
HR
VQFN-
HR
VQFN-
HR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS259460ARPWR
TPS259460LRPWR
TPS259461ARPWR
TPS259461LRPWR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RPW
RPW
RPW
RPW
10
10
10
10
3000
3000
3000
3000
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
2.1
1.9
A
B
2.1
1.9
PIN 1 IDENTIFICATION
(0.1) TYP
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.45
PKG
4X
SQ (0.15) TYP
4X 0.475
4
2X 0.25
6
5
7
0.35
4X
4X 0.475
0.25
0.1
C A B
C
0.05
2.1
1.9
2X
2X 0.45
PKG
4X
0.3
0.2
0.1
0.05
C A B
C
1
10
0.3
0.2
PIN 1 ID
(OPTIONAL)
4X
0.5
0.3
0.35
0.25
8X
2X
0.1
C A B
C
0.1
C A B
0.05
0.05
C
4225183/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.45)
4X (0.475)
2X (0.25)
1
10
4X (0.25)
4X
(0.225)
PKG
2X
2X
(1.75)
(2.4)
4X (0.3)
4X (0.475)
7
4
4X
(0.65)
(R0.05) TYP
6
5
2X (0.3)
4X (0.25)
PKG
8X (0.6)
LAND PATTERN EXAMPLE
SCALE: 30X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225183/A 08/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.425)
4X (0.4625)
2X (0.25)
METAL TYP
1
10
4X (0.25)
4X
(0.63)
PKG
2X
(1.75)
4X (0.225)
4X (0.275)
4X
4X (0.4625)
(1.06)
7
4
4X
(0.65)
(R0.05)
TYP
6
5
4X (0.28)
4X (0.225)
PKG
8X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
PADS 1, 4,7 & 10: 93%; PADS 5 & 6: 82%
SCALE: 30X
4225183/A 08/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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