TPS259620DDAR [TI]
采用引线式封装、具有可选过压保护钳位的 2.7V 至 19V、85mΩ、0.13A 至 2A 电子保险丝 | DDA | 8 | -40 to 125;
| 型号： | TPS259620DDAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用引线式封装、具有可选过压保护钳位的 2.7V 至 19V、85mΩ、0.13A 至 2A 电子保险丝 | DDA | 8 | -40 to 125 电子 光电二极管 |
| 文件： | 总48页 (文件大小：4434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS2596
ZHCSJQ2A –MAY 2019–REVISED AUGUST 2019
具有精确电流监控器和快速过压保护功能的 TPS2596 2.7V 至 19V、
0.125A 至 2A、89mΩ 电子保险丝
1 特性
2 应用
1
•
宽输入电压范围：2.7V 至 19V
绝对最大值为 21V
•
•
能量计
UL 60335-1 15W LPC 在电器中的应用
–
•
•
低导通电阻：Ron = 89mΩ（典型值）
–
–
–
冰箱
带有可调节欠压锁定 (UVLO) 的高电平有效使能输
入
洗碗机
洗衣机和烘干机
•
可用过压保护选项：
•
•
机顶盒
–
快速过压钳位（3.8V、5.7V 和 13.8V 引脚可选
阈值），响应时间为 5μs（典型值）
IP 网络摄像头
–
可调节过压锁定 (OVLO)，响应时间为 1.3μs
（典型值）
3 说明
TPS2596xx 系列电子保险丝（集成式 FET 热插拔器
件）是采用小型封装且高度集成的电路保护和电源管理
解决方案。这些设备只需很少的外部组件即可提供多种
保护模式，能够非常有效地抵御过载、短路、电压浪涌
和过多浪涌电流。输出电流限制级别可通过单个外部电
阻设定。还可能通过测量整个电流限制电阻的压降实现
对输出负载电流的准确感应。对 浪涌电流有特别要求
的应用可以通过单个外部电容器设定输出转换率。对于
TPS25962x 型号，发生输入过压情况时，内部钳位电
路会将输出限制在一个安全的固定最大电压（引脚可
选），而无需外部组件。TPS25963x 型号使用户可以
设置指定的过压截止阈值。
•
配备负载电流监控器输出 (ILM) 的可调节电流限制
–
–
电流范围：0.125A 至 2A
电流限制准确度：
–
–
整个电流范围内为 ±10.4%（最大值）
在 1A 电流限制下为 ±5.5%（最大值）
•
•
•
•
•
•
•
不受电气快速瞬变干扰 (IEC 61000-4-4)
可调节的输出压摆率控制 (dVdt)
提供过热保护 (OTP)
故障指示引脚 (FLT)
UL2367 认证正在处理中
IEC 62368 CB 认证（正在申请中）
小尺寸：4.91mm × 3.9mm SOIC 封装
这些器件的额定工作结温范围为 –40°C 至 +125°C。
器件信息(1)
器件型号
TPS259620DDA
TPS259621DDA
TPS259630DDA
TPS259631DDA
封装
SOIC (8)
封装尺寸（标称值）
4.91mm x 3.9mm
4.91mm x 3.9mm
4.91mm x 3.9mm
4.91mm x 3.9mm
SOIC (8)
SOIC (8)
SOIC (8)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
TPS25963x 1KV EFT 响应
Power
Supply
IN
OUT
TPS25963x
VFLT
R1
R2
RFLT
EN/UVLO
Fault
FLT
ILM
CIN
COUT
IMON
OVLO
dVdt
ROUT
GND
RILM
R3
CdVdt
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSET8
TPS2596
ZHCSJQ2A –MAY 2019–REVISED AUGUST 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 25
Application and Implementation ........................ 27
9.1 Application Information............................................ 27
9.2 Typical Application ................................................. 27
9.3 System Examples ................................................... 31
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
器件比较表............................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements................................................ 8
7.7 Switching Characteristics.......................................... 8
7.8 Typical Characteristics............................................ 10
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
9
10 Power Supply Recommendations ..................... 34
10.1 Transient Protection.............................................. 34
10.2 Output Short-Circuit Measurements ..................... 35
11 Layout................................................................... 36
11.1 Layout Guidelines ................................................. 36
11.2 Layout Example .................................................... 37
12 器件和文档支持 ..................................................... 38
12.1 文档支持................................................................ 38
12.2 接收文档更新通知 ................................................. 38
12.3 社区资源................................................................ 38
12.4 商标....................................................................... 38
12.5 静电放电警告......................................................... 38
12.6 Glossary................................................................ 38
13 机械、封装和可订购信息....................................... 38
8
4 修订历史记录
Changes from Original (May 2019) to Revision A
Page
•
将“预告信息”更改为“生产数据” ............................................................................................................................................... 1
2
版权 © 2019, Texas Instruments Incorporated
TPS2596
www.ti.com.cn
ZHCSJQ2A –MAY 2019–REVISED AUGUST 2019
5 器件比较表
部件号
过压响应
OVC - 3.8V、5.7V、13.8V（引脚可选）
OVC - 3.8V、5.7V、13.8V（引脚可选）
可调 OVLO
热关断 (TSD) 响应
闭锁
TPS259620
TPS259621
TPS259630
TPS259631
自动重试
闭锁
可调 OVLO
自动重试
Copyright © 2019, Texas Instruments Incorporated
3
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ZHCSJQ2A –MAY 2019–REVISED AUGUST 2019
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6 Pin Configuration and Functions
DDA Package
8-Pin SOIC
Top View
OVLO/OVCSEL
GND
dVdt
GND
ILM
FLT
Thermal Pad
EN/UVLO
IN
OUT
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
GND
1
Ground
Ground
Analog
Output
A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for
the fastest turn on slew rate.
dVdt
2
3
Active High Enable for the Device. A resistor divider can be used to adjust the Undervoltage
Lockout threshold. Do not leave floating.
EN/UVLO
Analog Input
IN
4
5
Power
Power
Power Input
OUT
Power Output
Active Low indicator which will be pulled low when a fault is detected. It is an open-drain
output that requires an external pull-up resistance.
FLT
6
Digital Output
This is a dual function pin used to limit and monitor the output current. An external resistor
from this pin to GND sets the output current limit. The pin voltage can also be used to
monitor the output load current.
Analog
Output
ILM
7
TPS25963x: A resistor divider can be used to adjust the Overvoltage Lockout threshold. Do
not leave floating.
OVLO
8
Analog Input
Ground
TPS25962x: Overvoltage Clamp level select pin. Refer to Overvoltage Clamp for more
details.
OVCSEL
Thermal pad
The Exposed Pad is used primarily for heat dissipation and must be connected to system
ground plane for best thermal performance.
4
Copyright © 2019, Texas Instruments Incorporated
TPS2596
www.ti.com.cn
ZHCSJQ2A –MAY 2019–REVISED AUGUST 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
PIN
MIN
MAX UNITS
Maximum Input Voltage Range
Maximum Input Voltage Range (TA = 25 ℃)
Maximum Output Voltage Range
–0.3
21
V
V
VIN
IN
22
VOUT
OUT
EN/UVLO
OVCSEL/OVLO
DVDT
–0.3
–0.3
–0.3
min (21, VIN + 0.3)
V
VEN/UVLO Maximum Enable Pin Voltage Range
7
7
V
VOV
Maximum OVCSEL/OVLO Pin Voltage Range
Maximum dVdT Pin Voltage Range
Maximum FLTb Pin Voltage Range
Maximum FLTb Pin Sink Current
Maximum Continuous Switch Current
Junction temperature
V
VdVdT
VFLTB
IFLTB
IMAX
TJ
2.5
7
V
FLT
–0.3
V
FLT
10
mA
A
IN to OUT
Internally Limited
Internally Limited
°C
°C
°C
TLEAD
Tstg
Maximum Lead Temperature
300
150
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input Voltage Range
PIN
IN
MIN
MAX UNITS
VIN
2.7
19(1)
VIN + 0.3
6(2)
V
V
VOUT
VEN/UVLO
VOV
Output Voltage Range
OUT
Enable Pin Voltage Range
OVLO Pin Voltage Range (TPS25963x Only)
dVdT Pin Capacitor Voltage Rating
FLTB Pin Voltage Range
EN/UVLO
OVLO
DVDT
FLT
V
0.5
4
2
V
VdVdT
VFLTB
RILM
IMAX
V
6
7869
2
V
ILM Pin Resistance
ILM
453
–40
Ω
A
Continuous Switch Current
Junction temperature
IN to OUT
TJ
125
°C
(1) For TPS25962x, the input voltage should be limited to the selected Output Voltage Clamp Option as listed in the Electrical
Characteristics section
(2) For supply voltages below 6V, it is okay to pull up the EN pin to IN through a resistor of 100 KΩ or higher. For supply voltages greater
than 6V, it is recommended to use an appropriate resistor divider between IN, EN and GND to ensure the voltage at the EN pin is within
the specified limits.
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5
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ZHCSJQ2A –MAY 2019–REVISED AUGUST 2019
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7.4 Thermal Information
TPS2596X
DDA (SOIC-EP)
8 PINS
THERMAL METRIC(1)
UNIT
RθJA
RθJA
ΨJT
ΨJT
ΨJB
ΨJB
Junction-to-ambient thermal resistance
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-board characterization parameter
52.7(2)
119.8(3)
8.9(2)
17.5(3)
27.1(2)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
68.1(3)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) With exposed pad soldered to PCB
(3) Without exposed pad soldered to PCB
7.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V , RILM = 453 Ω , CdVdT = Open, OUT = Open. All
voltages referenced to GND.
PARAMETER
INPUT SUPPLY (IN)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TPS25963x
193
206
259
266
µA
µA
µA
µA
V
IQ
IN quiescent current
IN Shutdown Current
TPS25962x
VIN < 4 V, VEN/UVLO < VSD
VIN ≥ 4 V, VEN/UVLO < VSD
VIN Rising
0.1
ISD
0.4
2.53
2.42
1.132
2.58
2.46
VUVP(R)
VUVP(F)
2.46
2.36
IN Undervoltage Protection
threshold
VIN Falling
V
IN Undervoltage Protection
Hysteresis
110
mV
OUTPUT VOLTAGE CLAMP (OUT) - TPS25962X
ROVCSEL = Short to GND,
ROUT = 10 KΩ
3.75
5.54
3.83
5.69
3.92
5.83
14.52
3.7
V
V
V
V
V
V
Overvoltage Clamp
Threshold
ROVCSEL = 400 KΩ to GND,
ROUT = 10 KΩ
VOVC
ROVCSEL = OPEN, ROUT = 10
KΩ
12.97
3.47
13.77
3.59
ROVCSEL = Short to GND,
IOUT = 10 mA
Output Voltage During
Clamping
ROVCSEL = 400 KΩ to GND,
IOUT = 10 mA
VCLAMP
5.28
5.45
5.61
13.97
ROVCSEL = OPEN, IOUT = 10
mA
13.13
13.58
OUTPUT CURRENT LIMIT AND MONITOR (ILM)
Current monitor gain
as measured on ILM pin (IILM
IOUT = 0.13 A
531.22
635.77
653.21
657.15
800.00
684.05
µA/A
µA/A
GIMON
IOUT = 2 A
/ IOUT
)
RILM = 7.87 KΩ, VDS = 0.5
V, –40°C ≤ TA ≤ 80°C
0.113
0.125
0.139
A
RILM = 3.83 KΩ, VDS = 0.5 V
RILM = 909 Ω, VDS = 0.5 V
RILM = 453 Ω, VDS = 0.5 V
RILM = OPEN
0.224
0.949
1.83
0.247
1.005
2.004
0
0.269
1.051
2.147
A
A
A
A
ILIM
IOUT Current Limit
IOUT Circuit Breaker
Threshold
during RILM Short condition
RILM = Short to GND (Single
Point Failure Test IEC
62368-1)
ICB
1.5
A
6
Copyright © 2019, Texas Instruments Incorporated
TPS2596
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ZHCSJQ2A –MAY 2019–REVISED AUGUST 2019
Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V , RILM = 453 Ω , CdVdT = Open, OUT = Open. All
voltages referenced to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ON-RESISTANCE (IN TO OUT)
VIN < 4 V, IOUT = 0.2 A, TJ =
25 ℃
97
99.8
125.4
143.4
92.6
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
VIN < 4 V, IOUT = 0.2 A, TJ =
-40 to 85 ℃
VIN < 4 V, IOUT = 0.2 A, TJ =
-40 to 125 ℃
RON
ON State Resistance
VIN > 4 V, IOUT = 0.2 A, TJ =
25 ℃
89
VIN > 4 V, IOUT = 0.2 A, TJ =
-40 to 85 ℃
115.3
131
VIN > 4 V, IOUT = 0.2 A, TJ =
-40 to 125 ℃
ENABLE/UNDERVOLTAGE LOCK OUT (EN/UVLO)
VUVLO(R)
VUVLO(F)
VEN Rising
1.18
1.08
1.2
1.1
95
1.22
1.13
V
V
UVLO Threshold
UVLO Hysteresis
VEN Falling
mV
VEN threshold for lowest
shutdown current
VSD
VEN Falling
0.53
–0.1
1.05
0.1
V
IENLKG
EN leakage current
µA
OVERVOLTAGE LOCKOUT (OVLO) - TPS25963X
VOVLO(R)
VOVLO(F)
VOVLO Rising
1.17
1.08
1.2
1.1
95
1.22
1.13
V
V
OVLO Threshold
VOVLO Falling
OVLO Hysteresis
mV
uA
IOVLKG
OVLO pin leakage current
0.5 ≤ VOVLO ≤1.5V
–0.1
0.1
FAULT INDICATION (FLT)
FLT Internal Pull-down
resistance
RFLTB
FLT asserted
11.52
Ω
FLT de-asserted, pull-up
voltage 6 V
IFLTLKG
FLT pin leakage current
–1
1
µA
OVERTEMPERATURE PROTECTION (OTP)
Thermal Shutdown Rising
Threshold
TSD
TJ Rising
TJ Falling
157
°C
°C
Thermal Shutdown
Hysteresis
TSDHYS
11.5
DVDT
IDVDT
dVdt Pin Charging Current
DVDT gain
1.89
2.11
2.33
21.5
µA
V
GDVDT
20.31
20.93
Copyright © 2019, Texas Instruments Incorporated
7
TPS2596
ZHCSJQ2A –MAY 2019–REVISED AUGUST 2019
www.ti.com.cn
7.6 Timing Requirements
Typical Values are taken at TJ = 25°C unless specifically noted otherwise.
PARAMETER
TEST CONDITIONS
MIN
TYP
87
5
MAX
UNITS
µs
IOUT > 20% over ILIM to IOUT
≤ ILIM
tLIM
tSC
tOVLO
tOVC
Current limit response time
Short circuit response time
V
OUT ↓ to IOUT ≤ ILIM
µs
Overvoltage lockout
response
time
TPS25963x Only
1.3
5
µs
µs
Output clamp response time TPS25962x Only , IOUT = 2 A
Thermal Shutdown Auto-
Retry
tTSD,RST
TPS2596x1 Only
95
ms
Interval
7.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn-
on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin
to ground. As CdVdt is increased, it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt)
section for more details. The fall time, however, is dependent on the RC time constant of the load capacitance (COUT) and
Load Resistance (RL). The Switching Characteristics are only valid for the power-up sequence where the supply is available
in steady state condition and the load voltage is completely discharged before the device is enabled.Typical Values are taken
at TJ = 25 °C unless specifically noted otherwise. ROUT = 100 Ω, COUT = 1 µF .
PARAMETER
VIN
CdVdt = Open
CdVdt = 3300pF
UNIT
2.7 V
5 V
28.9
12.1
SRON
tD,ON
tR
Output Rising slew rate
42.7
75.1
77.5
78.9
82.9
74.7
94.1
128.4
152.2
173
13.1
V/ms
12 V
2.7 V
5 V
13.6
216.5
247.3
314.9
182.4
311.0
707.8
398.9
558.4
1022.7
12.3
Turn on delay
Rise time
µs
µs
µs
µs
12 V
2.7 V
5 V
12 V
2.7 V
5 V
tON
Turn on time
Turn off delay
12 V
2.7 V
5 V
211.3
12.2
11.6
10.3
tD,OFF
11.9
12 V
10.4
8
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TPS2596
www.ti.com.cn
ZHCSJQ2A –MAY 2019–REVISED AUGUST 2019
VEN
VUVLO(F)
VUVLO(R)
EN/UVLO
0
tON
tD,OFF
90%
VIN
SRON
OUT
10%
0V
tR
tD,ON
tF
Time
图 1. TPS2596xx Switching Times
版权 © 2019, Texas Instruments Incorporated
9
TPS2596
ZHCSJQ2A –MAY 2019–REVISED AUGUST 2019
www.ti.com.cn
7.8 Typical Characteristics
240
235
230
225
220
215
210
205
200
195
190
185
180
175
225
220
215
210
205
200
195
190
185
180
175
170
165
160
155
VIN (V)
2.7
3.3
12
19
VIN (V)
2.7
4.5
12
19
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D002
D021
OUT = OPEN
图 2. TPS25963x Quiescent Current
OUT = OPEN
图 3. TPS25962x Quiescent Current
270
70
65
60
55
50
45
40
35
30
VIN (V)
2.7
12
260
250
240
230
220
19
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D022
D005
OVCSEL = OPEN, VIN = 19 V
VEN/UVLO = 1 V
图 5. Disabled State Current
图 4. TPS25962x Quiescent Current During Overvoltage
Clamping
0.75
140
135
130
125
120
115
110
105
100
95
VIN (V)
2.7
VIN (V)
2.7
3.3
4
0.7
0.65
0.6
4.5
12
19
0.55
0.5
12
19
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
90
85
80
75
0.05
0
70
-0.05
65
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D004
D006
VEN/UVLO = 0 V
图 6. Shutdown Current
IOUT = 200 mA
图 7. ON Resistance
10
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Typical Characteristics (接下页)
2.54
1.21
1.2
2.52
2.5
1.19
1.18
1.17
1.16
1.15
1.14
1.13
1.12
1.11
1.1
2.48
2.46
2.44
2.42
2.4
Rising
Falling
Rising
Falling
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D007
D008
VIN = 12 V
图 9. EN/UVLO Disable Threshold
图 8. IN Supply Undervoltage Threshold
0.84
0.014
0.012
0.01
TJ (èC)
-40
0.82
0.8
25
85
0.78
0.76
0.74
0.72
0.7
125
0.008
0.006
0.004
0.002
0
VIN (V)
2.7
12
19
0.68
0.66
0.64
-0.002
-0.004
-0.006
-40
-20
0
20
40
TJ (èC)
60
80
100 120 140
0
0.5
1
1.5
2
2.5
3
VEN (V)
3.5
4
4.5
5
5.5
6
D014
D009
图 10. EN/UVLO Shutdown Threshold for Lowest Current
图 11. EN/UVLO Pin Leakage Current
Consumption
1.21
1.2
0.018
0.016
0.014
0.012
0.01
TJ (èC)
-40
25
1.19
1.18
1.17
85
125
1.16
Rising
Falling
1.15
0.008
0.006
0.004
0.002
0
1.14
1.13
1.12
1.11
1.1
-40
-20
0
20
40
TJ (èC)
60
80
100 120 140
0.5
1
1.5
2
2.5
3 3.5
VOVLO (V)
4
4.5
5
5.5
6
D001
D003
图 12. TPS25963x Overvoltage Lockout Threshold
图 13. TPS25963x OVLO Pin Leakage Current
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Typical Characteristics (接下页)
14
13
12
11
10
9
3.6
3.57
3.54
3.51
3.48
3.45
3.42
3.39
3.36
3.33
3.3
OVCSEL
Short to GND
400 KW
IOUT
10mA
150mA
1A
OPEN
8
7
6
5
4
3
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D017
D018
ROUT = 10 KΩ
OVCSEL = Short to GND, VIN = 4.2 V
图 14. TPS25962x Overvoltage Clamp Threshold
图 15. TPS25962x Overvoltage Clamping Voltage
5.5
13.6
13.55
13.5
5.45
5.4
13.45
13.4
5.35
5.3
13.35
13.3
IOUT
5.25
5.2
10mA
150mA
1A
IOUT
13.25
13.2
10mA
150mA
1A
5.15
13.15
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D024
D025
OVCSEL = 400 KΩ to GND, VIN = 6.1 V
OVCSEL = OPEN, VIN = 14.4 V
图 16. TPS25962x Overvoltage Clamping Voltage
图 17. TPS25962x Overvoltage Clamping Voltage
21.2
21
2.2
2.18
2.16
2.14
2.12
2.1
VIN (V)
2.7
12
19
20.8
20.6
20.4
20.2
20
VIN (V)
2.7
12
2.08
2.06
2.04
2.02
19
19.8
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D019
D020
图 18. DVDT Charging Current
图 19. DVDT Gain
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Typical Characteristics (接下页)
2.2
12
10
8
MIN
TYP
MAX
2
1.8
1.6
1.4
1.2
1
6
4
2
0
-2
-4
-6
-8
-10
-12
0.8
0.6
0.4
0.2
0
0
1000 2000 3000 4000 5000 6000 7000 8000
RILM (W)
0
0.2 0.4 0.6 0.8
1 1.2 1.4 1.6 1.8
ILIM (A)
2
2.2
D010
D011
Across Process, Voltage and Temperature Corners, VDS = 0.5 V
图 20. Current Limit vs RILM
图 21. Current Limit Accuracy
135
130
125
120
115
110
105
100
95
880
VIN (V)
2.7
VIN (V)
2.7
12
19
860
840
820
800
780
760
740
720
12
19
90
85
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D015
D016
VOUT = 0 V, RILM = 7.87 KΩ
图 22. Current Limit Foldback
VOUT = 0 V, RILM = 453 Ω
图 23. Current Limit Foldback
680
25
20
15
10
5
MIN
TYP
MAX
TJ (èC)
-40
25
677.5
675
85
125
672.5
670
667.5
665
0
662.5
660
-5
-10
-15
-20
657.5
655
652.5
0
0.2 0.4 0.6 0.8
1
IOUT (A)
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1 1.2 1.4 1.6 1.8
IOUT (A)
2
2.2
D013
D012
Across Process, Voltage and Temperature Corners, All values
normalized to mean GIMON value of 656 μA/A
图 25. Current Monitor Accuracy
图 24. Current Monitor Gain
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Typical Characteristics (接下页)
20000
10000
5000
20000
10000
5000
TA (èC)
-40
27
TA (èC)
-40
27
85
125
85
125
2000
1000
500
2000
1000
500
200
100
50
200
100
50
20
10
5
20
10
5
0
2
4
6
8
10
12
14
16
18
0
2
4
6
8
10
PD (W)
12
14
16
18
20
PD (W)
D023
D026
2- Layer PCB: 2 oz Cu with GND Plane area: 4.93 cm2 (Top) and
1.07 cm2 (Bottom)
1- Layer PCB: 2 oz Cu with GND Plane area: 4.43 cm2 (Top)
图 26. Thermal Shutdown Plot
图 27. Thermal Shutdown Plot
VIN = 12 V, COUT = 220 μF, RILM = 453 Ω
图 28. Input Hotplug Response
VIN = 12 V, COUT = 10 μF, RILM = 453 Ω, CDVDT = 2200 pF
图 29. Output Voltage Ramp and Inrush Current at Start Up,
CdVdT = 2200 pF
VIN = 12 V, COUT = 10 μF, RILM = 453 Ω, CDVDT = OPEN
VIN = 12 V, VEN = 3.3 V
图 30. Output Voltage Ramp and Inrush Current at Start Up,
图 31. Turn ON with EN
CdVdT = OPEN
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Typical Characteristics (接下页)
VIN = 12 V, VEN = 3.3 V
VIN = 12 V, RILM = 453 Ω, ROUT Varied From 8.33 Ω to 4.54 Ω
图 33. Overcurrent Response
图 32. Turn ON with VIN
VIN = 12 V, RILM = 453 Ω, ROUT = 5 Ω
VIN = 12 V, RILM = 453 Ω, ROUT = 5 Ω
图 34. Thermal Shutdown Latch-off Response - TPS2596x0
图 35. Thermal Shutdown Auto-Retry Response - TPS2596x1
VIN = 12 V, RILM = 453 Ω
VIN = 12 V, RILM = 453 Ω
图 36. Short-Circuit While ON Response
图 37. Short-Circuit While ON Response (Zoomed In)
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Typical Characteristics (接下页)
VIN = 12 V, RILM = 453 Ω
VIN = 12 V, RILM = 453 Ω
图 38. Power Up Into Short-Circuit
图 39. Power Up Into Short-Circuit (Zoomed In)
VIN increased from 12 V to 15 V
OVCSEL = Shorted to GND, VIN increased from 3 V to 5 V
图 40. TPS25963x Overvoltage Lockout Response
图 41. TPS25962x Overvoltage Clamp Response
OVCSEL = 400 KΩ to GND, VIN increased from 5 V to 7 V
图 42. TPS25962x Overvoltage Clamp Response
OVCSEL = OPEN, VIN increased from 12 V to 14 V
图 43. TPS25962x Overvoltage Clamp Response
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8 Detailed Description
8.1 Overview
The TPS2596xx is an integrated eFuse device that is used to manage load voltage and load current. The device
provides various factory programmed settings and user manageable settings, which allow device configuration
for handling different transient and steady state supply and load fault conditions, thereby protecting the input
supply and the downstream circuits connected to the device. The device also uses an in-built thermal shutdown
mechanism to protect itself during these fault events.
8.2 Functional Block Diagram
TPS25962x
FET Temperature Sense &
TSD
Overtemperature Protection
4
5
OUT
dVdt
IN
x 656 µA/A
Charge
Pump
OVC Threshold
Select
2.1 µA
8
OVCSEL
2
7
x21
UVPb
2.5 V
2.4 V
Gate control
Current Limit Amplifier
ILM
3
EN/UVLO
UVLOb
1.2 V
1.1 V
Short
detect
SWEN
SD
ILM pin fault
0.5 V
SD
UVPb
RETRY
/Q
Q
R
S
FLTb
FLT
6
1
FLTb
GND
TSD
11.5 O
ILM pin fault
Retry Timer*
RETRY
* Only for Auto-Retry Variant (TPS259621)
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Functional Block Diagram (接下页)
TPS25963x
FET Temperature Sense &
Overtemperature Protection
TSD
4
5
OUT
dVdt
IN
x 656 µA/A
UVPb
Charge
Pump
2.5 V
2.4 V
2.1 µA
2
7
x21
8
3
OVLO
OVPb
1.2 V
1.1 V
SWEN
Gate control
Current Limit Amplifier
EN/UVLO
UVLOb
ILM
1.2 V
1.1 V
Short
detect
SD
0.5 V
ILM pin fault
SD
UVPb
RETRY
/Q
Q
R
S
FLTb
FLT
6
1
FLTb
GND
OVPb
TSD
11.5 O
ILM pin fault
Retry Timer*
RETRY
* Only for Auto-Retry Variant (TPS259631)
8.3 Feature Description
8.3.1 Undervoltage Protection (UVP) and Undervoltage Lockout (UVLO)
TPS2596xx constantly monitors the input supply to ensure that the load is powered up only when the voltage is
at a sufficient level. During the start-up condition, the device waits for the input supply to rise above an internal
fixed threshold VUVP(R) before it proceeds to turn ON the FET. Similarly, during the ON condition, if the input
supply falls below the UVP threshold VUVP(F), the FET is turned OFF. The UVP rising and falling thresholds are
slightly different, thereby providing some hysteresis and ensuring stable operation around the threshold voltage.
The TPS2596xx devices also provide an user adjustable UVLO mechanism to ensure that the load is powered
up only when the voltage is at a sufficient level. This can be achieved by dividing the input supply and feeding it
to the EN/UVLO pin. Whenever the voltage at the EN/UVLO pin falls below a threshold VUVLO(F), the device turns
OFF the FET. The FET is turned ON again when the voltage rises above the threshold VUVLO(R). The rising and
falling thresholds on this pin are slightly different, thereby providing some hysteresis and ensuring stable
operation around the threshold voltage.
The user must choose the resistor divider values appropriately to map the desired input undervoltage level to the
UVLO threshold of the part.
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Feature Description (接下页)
VIN
R1
EN/UVLO
R2
图 44. Adjustable Undervoltage Lockout
(R1+ R2)
R2
VIN(UV) = VUVLO(F) x
(1)
8.3.2 Overvoltage Protection
The TPS2596xx devices provide 2 ways to handle an input overvoltage condition.
8.3.2.1 Overvoltage Lockout
The TPS25963x variants provide an user adjustable OVLO mechanism to ensure that the supply to the load is
cut off if the input supply voltage exceeds a certain level. This can be achieved by dividing the input supply and
feeding it to the OVLO pin. Whenever the voltage at the OVLO pin rises above a threshold VOVLO(R), the device
turns OFF the FET. When the voltage at the OVLO pin falls below the threshold VOVLO(F), the FET is turned ON
again. The rising and falling thresholds on this pin are slightly different, thereby providing some hysteresis and
ensuring stable operation around the threshold voltage.
Input Overvoltage
Event
Input Overvoltage
Removed
IN
0
VOVLO(R)
VOVLO(F)
OVLO
0
tOVLO
VIN
0
OUT
VFLT
FLT
0
Time
图 45. TPS25963x Overvoltage Lockout Response
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Feature Description (接下页)
The user should choose the resistor divider values appropriately to map the desired input overvoltage level to the
OVLO threshold of the part.
VIN
R1
OVLO
R2
图 46. TPS25963x Adjustable Overvoltage Lockout
(R1+ R2)
VIN(OV) = VOVLO(R) x
R2
(2)
8.3.2.2 Overvoltage Clamp
The TPS25962x variants provide a mechanism to clamp the output voltage to a user-selectable level quickly if
the input voltage crosses a certain threshold. This ensures the load is not exposed to high voltages during any
input overvoltage events and lowers the dependence on external protection devices (such as TVS/Zener diodes)
in this condition. Once the input supply voltage rises above the OVC threshold voltage VOVC, the device responds
by clamping the voltage to VCLAMP within a very short response time tOVC. As long as an overvoltage condition is
present on the input, the output voltage will be clamped to VCLAMP. When the input drops below the output clamp
threshold VOVC, the clamp releases the output voltage as shown in 图 47.
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Feature Description (接下页)
Input Overvoltage
Removed
Input Overvoltage
Event
Thermal
Shutdown
Auto-Retry
with Input
Overvoltage
IN
VOVC
0
tOVC
VCLAMP
OUT
0
VFLT
FLT
tTSD,RST
0
TSD
TSDHYS
TJ
Time
图 47. TPS25962x Overvoltage Clamp Response
The OVC threshold can be configured to one of 3 pre-defined levels by connecting the OVCSEL pin as shown in
表 1.
表 1. TPS25962x Overvoltage Clamp Threshold Selection
OVCSEL Pin Connection
Shorted to GND
OVC Threshold (typ)
3.8 V
5.7 V
Connected to GND through 400 KΩ resistor
Open
13.7 V
During the overvoltage clamp condition, there could be significant heat dissipation in the internal FET depending
on the VIN - VOUT voltage drop and the current (IOUT) through the FET leading to thermal shutdown if the condition
persists for an extended period of time. In this case, the device would either stay latched-off or start an auto-retry
cycle as explained in the Overtemperature Protection (OTP) section.
8.3.3 Inrush Current, Overcurrent and Short Circuit Protection
The TPS2596xx devices incorporate three levels of protection against overcurrent:
•
•
•
Adjustable slew rate for inrush current control (dVdt)
Active current limiting with adjustable limit (ILIM) for overcurrent protection
Fast short-circuit response to protect against hard short-circuits
8.3.3.1 Slew Rate and Inrush Current Control (dVdt)
The inrush current during turn on is directly proportional to the load capacitance and rising slew rate. 公式 3 can
be used to find the slew rate SRON required to limit the inrush current IINRUSH for a given load capacitance COUT
.
IINRUSH
(
mA
)
SR mV / ms =
(
)
CL
(
mF
)
(3)
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For loads requiring a slower rising slew rate, a capacitor can be connected to the dVdt pin to adjust the rising
slew rate and lower the inrush current during turn on. The required CdVdt capacitance value to produce a given
slew rate can be calculated using 公式 4.
42000
CdVdt pF =
(
)
SR mV / ms
(
)
(4)
8.3.3.2 Active Current Limiting
The load current is monitored during start-up and normal operation. When the load current exceeds the current
limit ILIM programmed by RILM resistor, the device regulates the current to the set limit ILIM within tLIM. The device
exits current limiting when the load current falls below ILIM. 公式 5 can be used to find the RILM value for a desired
current limit.
903
RILM W =
(
)
ILIM
( )
- 0.0112
A
(5)
In the current limiting state, the output voltage drops resulting in increased power dissipation in the internal FET
leading to thermal shutdown if the condition persists for an extended period of time. In this case, the device
either stays latched-off or starts an auto-retry cycle as explained in the Overtemperature Protection (OTP)
section.
Auto-Retry
into overload
Auto-Retry
(Overload removed)
Overload on OUT
Current Limit
Current Limit
ILIM
IOUT
0
VIN
OUT
FLT
dVdt limited
startup
0
tLIM
VFLTB
tTSD,RST
tTSD,RST
0
TSD
TSDHYS
TJ
Time
图 48. TPS2596x1 Overcurrent Response (Auto-retry)
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Manual Restart
(Device Re-enabled)
Thermal
Shutdown
Overload
Removed
Overload on OUT
VUVLO
EN
0
Current Limit
ILIM
IOUT
0
VIN
OUT
FLT
dVdt limited
startup
0
tLIM
VFLTB
0
TSD
TSDHYS
TJ
Time
图 49. TPS2596x0 Overcurrent Response (Latch-off)
8.3.3.3 Short-Circuit Protection
The current through the device increases very rapidly during a short-circuit event. If the current exceeds 1.5 x
ILIM, the device engages a fast current clamping circuit to regulate down the current faster than the nominal
overcurrent response time (tLIM). The device does not completely turn off the power FET to ensure uninterrupted
power in the event of transient overcurrents or supply transients. The device stops limiting the current once the
load current falls below the programmed ILIM threshold.
The output voltage drops in the current limiting state, resulting in increased power dissipation in the internal FET
and might lead to thermal shutdown if the condition persists for an extended period of time. In this case, the
device either stays latched-off or starts an auto retry cycle as explained in the Overtemperature Protection (OTP)
section.
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Hard Short on Thermal
Auto-retry into
Shutdown
output short
Thermal
Shutdown
output
Output short
removed
IOUT
ILIM
Current
limit with
foldback
Current
limit with
foldback
0
VIN
OUT
dVdt limited
startup
0
tSC
VFLT
FLT
0
tTSD,RST
tTSD,RST
TSD
TSDHYS
TJ
Time
图 50. TPS2596xx Short Circuit Response
8.3.4 Analog Load Current Monitor (IMON)
The device allows the system to monitor the output load current accurately by providing an analog current on the
ILM pin which is proportional to the current (IOUT) through the FET. The user can sense the voltage (VILM) across
the RILM to get a measure of the output load current.
VILM V
(
)
IOUT A =
)
(
GIMON mA / A x RILM W
(
)
( )
(6)
8.3.5 Overtemperature Protection (OTP)
Thermal Shutdown will occur when the junction temperature (TJ) exceeds the thermal shutdown threshold (TSD).
When the TPS2596x0 variant detects thermal overload, it will be shut down and remain latched off until the
device is power cycled or re-enabled by toggling the EN/UVLO pin. When the TPS2596x1 variant detects thermal
overload, it will remain off until it has cooled down sufficiently. Once the TPS2596x1 junction has cooled down
below TSD - TSDHYS, it will remain off for an additional delay of tTSD,RST after which it will automatically retry to
turn on if it is still enabled.
表 2. TPS2596x Thermal Shutdown
Device
Enter TSD
TJ ≥ TSD
TJ ≥ TSD
Exit TSD
TJ < TSD - TSDHYS and Power Cycle (VIN < VUVP(F)) / Enable Cycle (VEN
<
TPS2596x0 (Latch-Off)
TPS2596x1 (Auto-Retry)
VSD
)
TJ < TSD - TSDHYS and tTSD-RST timer expired
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8.3.6 Fault Indication
表 3 summarizes the protection response to various fault conditions.
表 3. Fault Response
Event / Fault
Overtemperature
Undervoltage
Protection Response
Shutdown
FLT Asserted
FLT Delay
Yes
No
Cut-off
Clamp (OVC - TPS25962x only)
Cut-off (OVLO - TPS25963x only)
Current Limit
No
Overvoltage
Yes
No
tOVLO
Overcurrent
Short-Circuit
Current Limit
No
ILM Pin Short to GND
ILM Pin Open
Shut down
Yes
No
Shut down
When the device turns off due to one of these fault conditions, the FLT pin is pulled low.
Power cycling the part or pulling the EN/UVLO pin voltage below VSD clears the fault and the FLT pin is de-
asserted. It also clears the tTSD,RST timer (Auto-retry variants only). Pulling the EN/UVLO just below the UVLO
threshold (VUVLO(F)) has no impact on the device in this condition. This is true for both Latch-off (TPS2596x0) and
Auto-retry (TPS2596x1) variants.
For Auto-retry (TPS2596x1) variants, at the end of the tTSD,RST timer after a fault, the device restarts
automatically and the FLT pin is de-asserted.
8.4 Device Functional Modes
The features of the device depend on the operating mode.
8.4.1 Enable and Fault Pin Functional Mode 1: Single Device, Self-Controlled
In this mode of operation, the device is enabled by the VIN voltage without the need of an external processor to
drive the ENABLE pin. The FLT pin is optionally monitored by an external host as shown in 图 51.
VFLT
TPS2596
VIN
IN
RFLT
R1
_
GPIO
FLT
EN
R2
图 51. Single Device, Self-Controlled
8.4.2 Enable and Fault Pin Functional Mode 2: Single Device, Host-Controlled
In this mode of operation, the device is enabled by the VIN voltage without the need of an external processor to
drive the ENABLE pin. The FLT pin is optionally monitored by an external host as shown in 图 53.
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TPS2596
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Device Functional Modes (接下页)
TPS2596
VFLT
VIN
IN
RFLT
_
GPIO
FLT
EN
GPIO
图 52. Single Device, Self-Controlled
8.4.3 Enable and Fault Pin Functional Mode 3: Multiple Devices, Self-Controlled
In this mode of operation, the devices are self-controlled (no host present). The EN and FLT pins of multiple
devices are shorted together as shown in 图 52. In this configuration, when any one of the TPS2596xx devices
detects a fault, it automatically disables the other TPS2596xx devices in the system.
TPS2596
VIN
_
EN
FLT
R1
TPS2596 EN
R2
_
FLT
_
EN
FLT
TPS2596
图 53. Multiple Devices, Self-Controlled
26
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS2596xx device is an integrated eFuse that is typically used for hot-swap and power rail protection
applications. The device operates from 2.7 V to 19 V with adjustable current limit and undervoltage protection.
The device aids in controlling the in-rush current and provides precise current limiting during overload conditions
for systems such as energy meters, white goods, building automation and adapter input protection. The device
also provides robust protection for multiple faults on the sub-system rail.
The following design procedure can be used to select the supporting component values based on the application
requirement.
9.2 Typical Application
9.2.1 Precision Current Limiting and Protection for White Goods
VIN
VOUT
COUT
2.7 V to 19 V
CIN
(Note 1)
IN
OUT
VFLT
R1
464 kO
100 µF
RFLT
EN/UVLO
D1
(Note 1)
D2
(Note 1)
R2
33.2 kO
FLT
OVLO
dVdt
GND
ILIM
CdVdt
2.2 nF
R3
47.5 kO
TPS25963x
RILM
909 O
(1) CIN is optional and 0.1 µF is recommended to suppress transients due to the inductance of PCB routing or from input
wiring. If system needs to pass IEC 61000-4-4 EFT test, minimum CIN of 1 µF should be used to prevent eFuse from
turning off during EFT bursts.
图 54. Typical Application Schematic: Simple eFuse for White Goods
9.2.2 Design Requirements
表 4. Design Parameters
DESIGN PARAMETER
Input voltage , VIN
EXAMPLE VALUE
12 V
8 V
Undervoltage lockout set point, VUV
Overvoltage protection set point , VOV
Overvoltage protection type
Load at start-up, RL(SU)
13.7 V
Lock-out
24 Ω
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Typical Application (接下页)
表 4. Design Parameters (接下页)
DESIGN PARAMETER
Current limit, ILIM
EXAMPLE VALUE
1 A
100 µF
85°C
Load capacitance, COUT
Maximum ambient temperatures, TA
9.2.3 Detailed Design Procedure
The designer must know the following:
•
•
•
•
•
Normal input operation voltage
Maximum output capacitance
Maximum current limit
Load during start-up
Maximum ambient temperature of operation
This design procedure seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria. A spreadsheet design tool TPS2596 Design
Calculator is also available for simplified calculations.
9.2.3.1 Programming the Current-Limit Threshold: RILM Selection
The RILM resistor at the ILM pin sets the over load current limit, this can be set using 公式 7.
903
903
R
ILM W =
=
= 913.2 ꢀ
(
)
I
LIM
( )
A
- 0.0112 1- 0.0112
(7)
Choose closest standard value resistor: 909 Ω with 1% tolerance.
9.2.3.2 Undervoltage and Overvoltage Lockout Set Point
The undervoltage lockout (UVLO) and overvoltage lockout (OVLO) trip point is adjusted using the external
voltage divider network of R1, R2 and R3as connected between IN, EN/UVLO, OVLO and GND pins of the
device. The values required for setting the undervoltage and overvoltage are calculated solving 公式 8 and 公式
9.
R 2 + R 3
VUVLO
=
ì VIN UV
(
)
R + R + R 3
1
2
(8)
R 3
VOVLO
=
ì VIN OV
(
)
R + R + R 3
1
2
(9)
Where VUVLO(R) is UVLO rising threshold (1.2 V). Because R1, R2 and R3 leak the current from input supply VIN,
these resistors must be selected based on the acceptable leakage current from input power supply VIN.
The current drawn by R1, R2 and R3 from the power supply is IR123 = VIN / (R1 + R2 + R3).
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the leakage
current expected.
From the device electrical specifications, VOVLO = 1.2 V and VUVLO = 1.2 V. For design requirements, VOV = 13.7
V and VUV = 8 V. To solve the equation, first choose the value of R3 = 47 kΩ and use 公式 9 to solve for (R1 +
R2) = 489.58 kΩ. Use Equation 8 and value of (R1 + R2) to solve for R2 = 33.48 kΩ and finally R1= 456.1 kΩ.
Using the closest standard 1% resistor values gives R1 = 464 kΩ, R2 = 33.2 kΩ, and R3 = 47.5 kΩ.
28
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9.2.3.3 Setting Output Voltage Ramp Time (TdVdT
)
For a successful design, the junction temperature of device must be kept below the absolute maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The required ramp-up capacitor CdVdT is calculated considering the two possible cases (see Case 1: Start-Up
Without Load. Only Output Capacitance COUT Draws Current and Case 2: Start-Up With Load. Output
Capacitance COUT and Load Draw Current ).
9.2.3.3.1 Case 1: Start-Up Without Load. Only Output Capacitance COUT Draws Current
During start-up, as the output capacitor charges, the voltage drop as well as the power dissipated across the
internal FET decreases. The average power dissipated in the device during start-up is calculated using 公式 11.
For TPS2596xx device, the inrush current is determined as shown in 公式 10.
VIN
IINRUSH = COUT
ì
TdVdT
(10)
(11)
Power dissipation during start-up is shown in 公式 11.
PD(INRUSH) = 0.5 ì V ì IINRUSH
IN
公式 11 assumes that load does not draw any current until the output voltage has reached its final value.
9.2.3.3.2 Case 2: Start-Up With Load. Output Capacitance COUT and Load Draw Current
When the load draws current during the turnon sequence, there is additional power dissipated. Considering a
resistive load during start-up RL(SU), load current ramps up proportionally with increase in output voltage during
TdVdT time. Equations 12 to 15 show the average power dissipation in the internal FET during charging time due
to resistive load.
V2
1
≈ ’
IN
PD(LOAD)
=
ì
∆ ÷
6
RL(SU)
« ◊
(12)
(13)
(14)
Total power dissipated in the device during start-up is 公式 13.
PD(STARTUP) = PD(INRUSH) + PD(LOAD)
Total current during start-up is given by 公式 14.
ISTARTUP = IINRUSH +IL (t)
If ISTARTUP > ILIMIT, the device limits the current to ILIMIT and the current-limited charging time is determined by 公
式 15.
»
…
…
…
…
ÿ
Ÿ
Ÿ
Ÿ
Ÿ
⁄
≈
∆
∆
∆
’
÷
÷
÷
ILIMIT
IINRUSH
TdvdT(Current-Limited) = COUT ìRL(SU)
ì
-1+LN
V
IINRUSH
IN
ILIMIT
-
∆
«
÷
◊
RL(SU)
(15)
The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as
shown in 图 55.
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20000
TA (èC)
-40
27
10000
5000
85
125
2000
1000
500
200
100
50
20
10
5
0
2
4
6
8
10
12
14
16
18
PD (W)
D023
图 55. Thermal Shutdown Limit Plot
For the design example under discussion, select ramp-up capacitor CdVdt = 22000 pF. The default slew rate for
CdVdt = 22000 pF is 1.9 mV/µs. With slew rate of 1.9 mV/µs, the ramp-up time TdVdt for 12 V input is 6.3 ms.
The inrush current drawn by the load capacitance COUT during ramp-up using 公式 16.
100 ꢀF ì 1.9 mV
IINRUSH
=
= 190 mA
ꢀs
(16)
(17)
The inrush power dissipation is calculated using 公式 17.
PD INRUSH = 0.5 ì 12 ì 190 m = 1.14 W
(
)
For 1.14 W of power loss, the thermal shutdown time of the device must not be less than the ramp-up time TdVdt
to avoid the false trip at the maximum operating temperature. 图 55 shows the thermal shutdown limit at TA = 85
°C, for 1.14 W of power, the shutdown time is infinite. Therefore, it is safe to use 6.3 ms as the start-up time
without any load on the output.
The additional power dissipation when a 10-Ω load is present during start-up is calculated using 公式 18.
1
12ì12
24
≈ ’
PD(LOAD)
=
ì
=1W
∆ ÷
6
« ◊
(18)
(19)
The total device power dissipation during start-up is given in 公式 19.
PD STARTUP = 1 + 1.14 = 2.24 W
图 55 shows TA = 85 °C and the thermal shutdown time for 2.24 W is approximately 2000 ms, which increases
the margins further for shutdown time and ensures successful operation during start up and steady state
conditions.
When COUT is large, there is a need to decrease the power dissipation during start-up. This can be done by
increasing the value of the CdVdt capacitor.
9.2.4 Support Component Selection: RFLT and CIN
Referring to application schematics, RFLT is required only if FLT is used; The resistor serves as pull-up for the
open-drain output driver. The current sunk by this pin should not exceed 10 mA. CIN is a bypass capacitor to help
control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range from
0.001 μF to 0.1 μF is recommended for CIN.
30
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9.2.5 Application Curves
图 57. Output Ramp With 24-Ω Load at Start-up
图 56. Output Ramp Without Any Load
图 59. Overcurrent Protection
图 58. Overvoltage Protection (OVLO)
9.3 System Examples
The TPS2596xx provides a simple solution for current limiting, inrush current control and supervision of power
rails for wide range of applications operating at 2.7 V to 19 V and delivering up to 2 A.
9.3.1 Current Limiting and Overvoltage Protection and for Energy Meter Power Rails
Energy meters generally use a single AC/DC power supply (for example: flyback converter) with multiple DC
outputs for powering blocks like Metrology (analog front-end, microcontroller, memory), Real Time Clock (RTC),
Relay (for remote load connect/disconnect) and Communications module. Metrology is the most critical sub-
system and is required to operate uninterrupted under all conditions, even if a fault occurs in any of the
supplementary blocks. One solution would be to oversize the power supply design so that it can handle the
excess current demands during a fault condition, which increases the cost of the meter. A more elegant and
cost-optimized solution would be to add an eFuse like TPS2596xx on the supplementary power rails, which
provides accurate current limiting and fast short-circuit protection, thereby ensuring reliable operation of the
metrology block without increasing the size or cost of the power supply. Apart from that, the TPS2596xx provides
additional benefits such as:
•
Overvoltage Protection (Lock-out and Clamp) to shield down-stream low voltage circuits from harmful
overvoltages arising from poor cross-regulation between windings or AC input voltage surges.
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System Examples (接下页)
•
Disconnect supply to rarely used loads to minimize power consumption
图 60 shows a typical energy meter power supply implementation using TPS2596xx.
VAC(IN)
Relay Driver
12 V
C01
Rectifier +
Noise FIlter
TPS25963x
OVLO ILM
R1
R2
CB
RILM
Communication
Module
3.6 V
C02
TPS25963x
OVLO ILM
Flyback Controller
ROVO
RILM
RS
Metrology
5 V
C03
TPS25963x
OVLO
ILM
RILM
R3
R4
Feedback
Opto-coupler
Circuit
图 60. Energy Meter Power Rail Protection Example
TIDA-010037 demonstrates energy meter design using eFuse for protecting auxiliary rails.
9.3.2 Precision Current Limiting and Protection in Appliances
Household and similar electrical appliances are subjected to various tests (for example: needle flame, glow wire)
as part of the certification for electrical and fire safety compliance as per the regulations. Special precautions
need to be taken in the design to pass these tests, which include the use of higher grade flame retardant plastic
material for the housing enclosures. There are certain provisions in the standard which can be leveraged to make
the certification easier, faster and also reduce the cost of plastic materials. For example, any node which has
less than 15 W of power available to it is classified as a LPC (Low Power Circuit as per the definition in IEC
60335-1) and deemed to be safe. All circuits or sub-systems further downstream from a LPC node are exempt
from the aforementioned tests.
eFuses like TPS2596xx are a simple and cost effective way to limit the power delivered to the downstream load.
The key parameter to be considered is the current imit tolerance and accuracy, which determines how high one
can set the nominal current limit without exceeding the 15-W power limit on the upper end. On the lower end, it
determines the maximum power the load can draw in normal conditions without hitting the current limit.
TPS2596xx provides a current limit accuracy of ±5 % (at room temperature), which allows the load to use nearly
90% out of the 15-W limit under normal operating conditions.
In contrast, an alternative current limiting solution with wider current limit tolerance, say ±25 % would leave only
50 % out of 15 W for the load circuit to operate under normal conditions. This places severe constraints on the
load circuit design and/or capabilities.
图 61 shows a sub-system example of a refrigerator and freezer system where TPS2596xx is used for precision
current limiting and protection of 15-W rails to ease the qualification as low-power circuit as per IEC 60335-1.
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System Examples (接下页)
12 V
+
TPS2596xx
TPS2596xx
LOAD1
OUT1
OUT1
OUT1
Brushed
DC Motor
Surge
Protection
Bipolar
Stepper
OUT2
OUT3
OUT2
OUT3
OUT2
LOAD2
LOAD3
Motor Driver
Motor Driver
Motor Driver
OUT3
OUT4
OUT4
OUT4
œ
12 V
I2C
3.3 V
ESD
Protection
I2C
DC-DC
Converter
Microcontroller
Temperature Sense
图 61. Appliances 15-W LPC Implementation Example
TIDA-010004 demonstrates a multi-load drive using single driver chip with eFuse for protection and 15-W LPC
implementation.
Refer to this Designing Low-Power Circuits (LPCs) using TPS2596 for Household and similar Appliances
application note for a detailed insight into implementing power limited circuits using eFuses.
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10 Power Supply Recommendations
The TPS2596xx devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 19 V. An input ceramic bypass
capacitor higher than 0.1 μF is recommended if the input supply is located more than a few inches from the
device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
10.1 Transient Protection
In the case of a short circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
•
•
•
•
Minimize lead length and inductance into and out of the device.
Use a large PCB GND plane.
Use a Schottky diode across the output to absorb negative spikes.
Use a low-value ceramic capacitor CIN = 0.001 μF to 0.1 μF to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with 公式 20:
LIN
VSPIKE(Absolute) = VIN + ILOAD x
CIN
(20)
where
•
•
•
•
VIN is the nominal supply voltage
ILOAD is the load current
LIN equals the effective inductance seen looking into the source
CIN is the capacitance present at the input
NOTE: Systems which need to pass IEC 61000-4-4 tests for immunity to Electrical Fast Transients (EFT) should
use a minimum CIN of 1 μF to ensure the TPS2596xx does not turn OFF during the EFT burst.
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the absolute maximum ratings of the device. The circuit implementation with optional protection
components (a ceramic capacitor, TVS and Schottky diode) is shown in 图 62.
TPS25963x
VIN = 2.7 to 19 V
VOUT
IN
OUT
3.3V
R4
R1
715 YQ
EN/UVLO
10 YQ
R2
102 YQ
COUT
1 µF
RLOAD
100 Q
CIN
0.1 µF
FLT
D2
D1
OVLO
dVdt
ILM
GND
R3
348 YQ
RILM
456 Q
CdVdt
3.3nF
图 62. Circuit Implementation with Optional Protection Components
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10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in
results:
•
•
•
•
•
•
•
Source bypassing
Input leads
Circuit layout
Component selection
Output shorting method
Relative location of the short
Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like
those in this data sheet because every setup is different.
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11 Layout
11.1 Layout Guidelines
•
For all applications, a ceramic decoupling capacitor of 0.01 μF or greater is recommended between the IN
terminal and GND terminal. For hot-plug applications, where input power-path inductance is negligible, this
capacitor can be eliminated or minimized.
•
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See 图 63 for a PCB layout example.
•
•
•
High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground must be a
copper plane or island on the board.
Locate the following support components close to their connection pins:
–
–
–
–
–
RILM
CdVdT
Resistor network for the EN/UVLO pin
Resistor network for the OVLO pin for TPS25693x variants
Pull-down resistor on the OVCSEL pin for TPS25692x variants
Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing from the RILM, CdVdT and ROVCSEL (for TPS25962x variants) components to the device pins must be as
short as possible to reduce parasitic effects on the current limit, soft-start timing and overvoltage clamp
response. These traces must not have any coupling to switching signals on the board.
•
•
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, a protection Schottky diode is recommended to address negative transients due to
switching of inductive loads, and it must be physically close to the OUT pins.
Obtaining acceptable performance with alternate layout schemes is possible. The Layout Example shown in
图 63 has been shown to produce good results and is intended as a guideline.
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11.2 Layout Example
Bottom/Inner Layer
Via
Top Layer
Power Ground
GND
1
8
7
6
*
*
*
2
3
GND
4
5
IN
OUT
VIN
VOUT
* Optional: Needed only to suppress the transients caused by inductive load switching
图 63. TPS2596xx Layout Example
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
《电子保险丝的基本知识》
《TPS2596EVM：TPS2596xx 评估模块》
《TPS2596 设计计算器》
《使用 TPS2596 为家用或类似用途电器设计低功耗电路 (LPC)》
《TIDA-010037 高精度分相 CT 电量计》
《TIDA-010004 基于单个驱动器且受全面保护的 12V 步进、刷式直流和执行器驱动器》
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2019 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS259620DDAR
TPS259620DDAT
TPS259621DDAR
TPS259621DDAT
TPS259630DDAR
TPS259630DDAT
TPS259631DDAR
TPS259631DDAT
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
8
8
8
8
8
8
8
8
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
259620
SN
SN
SN
SN
SN
SN
SN
259620
259621
259621
259630
259630
259631
259631
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
2500
250
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS259620DDAR
TPS259620DDAT
TPS259621DDAR
TPS259621DDAT
TPS259630DDAR
TPS259630DDAT
TPS259631DDAR
TPS259631DDAT
SO
Power
PAD
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
8
8
8
8
8
8
8
8
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.8
12.8
12.8
12.8
12.8
12.8
12.8
12.8
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
SO
Power
PAD
SO
Power
PAD
2500
250
SO
Power
PAD
SO
Power
PAD
2500
250
SO
Power
PAD
SO
Power
PAD
2500
250
SO
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
Power
PAD
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS259620DDAR
TPS259620DDAT
TPS259621DDAR
TPS259621DDAT
TPS259630DDAR
TPS259630DDAT
TPS259631DDAR
TPS259631DDAT
SO PowerPAD
SO PowerPAD
SO PowerPAD
SO PowerPAD
SO PowerPAD
SO PowerPAD
SO PowerPAD
SO PowerPAD
DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA
8
8
8
8
8
8
8
8
2500
250
366.0
366.0
366.0
366.0
366.0
366.0
366.0
366.0
364.0
364.0
364.0
364.0
364.0
364.0
364.0
364.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
2500
250
2500
250
2500
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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