TPS26400PWPR [TI]
TPS26400 42-V, 2-A eFuse With Integrated Reverse Input Polarity Protection;
| 型号： | TPS26400PWPR |
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TEXAS INSTRUMENTS |
| 描述： | TPS26400 42-V, 2-A eFuse With Integrated Reverse Input Polarity Protection |
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TPS2640
SLVSFQ6 – NOVEMBER 2020
TPS26400 42-V, 2-A eFuse With Integrated Reverse Input Polarity Protection
1 Features
3 Description
•
4.2-V to 42-V operating voltage, 45-V absolute
maximum
Integrated reverse input polarity protection down to
–42 V
– Zero additional components required
Integrated back to back MOSFETs with 150-mΩ
total RON
0.1-A to 2.23-A adjustable current limit (±5%
accuracy at 1 A)
Load protection during Surge (IEC 61000-4-5) with
suitable TVS
IMON current indicator output (±8.5% accuracy)
Low quiescent current, 300-μA in operating, 20-μA
in shutdown
The TPS26400 devices are compact, feature rich high
voltage eFuses with a full suite of protection features.
The wide supply input range of 4.2 to 42 V allows
control of many popular DC bus voltages. The device
can withstand and protect the loads from positive and
negative supply voltages up to ±42 V. Integrated back
to back FETs provide reverse current blocking feature
making the device suitable for systems with output
voltage holdup requirements during power fail and
brownout conditions. Load, source and device
protection are provided with many adjustable features
including overcurrent, output slew rate and
overvoltage, undervoltage thresholds. The internal
robust protection control blocks along with the high
voltage rating of the TPS26400 helps to simplify the
system designs for Surge protection.
•
•
•
•
•
•
•
Adjustable UVLO, OVP cut off, output slew rate
control
A shutdown pin provides external control for enabling
and disabling the internal FETs as well as placing the
device in a low current shutdown mode. For system
status monitoring and downstream load control, the
device provides fault and precise current monitor
output. The MODE pin allows flexibility to configure
the device between the three current-limiting fault
responses (circuit breaker, latch off, and Auto-retry
modes).
•
•
Reverse current blocking
Available in easy-to-use 16-pin HTSSOP and 24-
pin VQFN packages
Selectable current-limiting fault response options
(auto-retry, latch Off, circuit breaker modes)
•
2 Applications
•
•
•
•
•
HMI Power protection in Factory Automation
Fire Safety Systems
Electronic Thermostats and Video Doorbells
Industrial PCs
The device is available in a 5-mm × 4.4-mm 16-pin
HTSSOP as well as 5-mm x 4-mm 24-pin VQFN
package and are specified over a –40°C to +125°C
temperature range
Elevators
Device Information
PART NUMBER
TPS26400
PACKAGE(1)
HTSSOP (16)
VQFN (24)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
5.00 mm × 4.00 mm
TPS26400
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
IN: 4.5 V - 36 V
IN
OUT
OUT
CIN
COUT
Health Monitor
ON/OFF Control
R1
RFLTb
150 mꢀ
R4
>90 kΩ
UVLO
FLT
TPS26400
OVP
R2
SHDN
OUT_OVP(1)
dVdT
IMON
ILIM
Load
Monitor
MODE
RTN
GND
R5
R3
RIMON
CdVdT
RILIM
Simplified Schematic
Reverse Polarity Protection with –42-V Input
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2640
SLVSFQ6 – NOVEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements .................................................9
7.7 Typical Characteristics..............................................10
8 Parameter Measurement Information..........................15
9 Detailed Description......................................................16
9.1 Overview...................................................................16
9.2 Functional Block Diagram.........................................17
9.3 Feature Description...................................................17
9.4 Device Functional Modes..........................................27
10 Application and Implementation................................28
10.1 Application Information........................................... 28
10.2 Typical Application.................................................. 28
10.3 System Examples................................................... 34
10.4 Do's and Dont's.......................................................37
11 Power Supply Recommendations..............................38
11.1 Transient Protection................................................ 38
12 Layout...........................................................................39
12.1 Layout Guidelines................................................... 39
12.2 Layout Example...................................................... 40
13 Device and Documentation Support..........................42
13.1 Device Support....................................................... 42
13.2 Documentation Support.......................................... 42
13.3 Receiving Notification of Documentation Updates..42
13.4 Support Resources................................................. 42
13.5 Trademarks.............................................................42
13.6 Electrostatic Discharge Caution..............................42
13.7 Glossary..................................................................42
14 Mechanical, Packaging, and Orderable
Information.................................................................... 42
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
November 2020
*
Initial Release
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5 Device Comparison
Overvoltage
Part Number
Over Load Fault Response with MODE = Open
Protection
Overvoltage cut-
TPS26400
Circuit breaker with auto-retry
off, adjustable
6 Pin Configuration and Functions
OUT
OUT
FLT
16
IN
IN
1
2
3
4
15
14
13
UVLO
NC
1
2
3
4
5
6
7
19
N.C
N.C
N.C
N.C
N.C
ILIM
NC
PowerPAD™
Integrated Circuit
Package
18
17
IMON
GND
12
11
dVdT
ILIM
OVP
5
6
MODE
7
8
PowerPadTM
16
15
N.C
10
9
IMON
GND
SHDN
RTN
RTN
N.C
N.C
14
13
SHDN
MODE
Figure 6-1. PWP Package 16-Pin HTSSOP Top View
Figure 6-2. RHF Package 24-Pin VQFN Top View
Table 6-1. Pin Functions
PIN
TPS26400
HTSSOP VQFN
TYPE
DESCRIPTION
NAME
A capacitor from this pin to RTN sets output voltage slew rate See the Hot Plug-
In and In-Rush Current Control section.
dVdT
12
20
I/O
FLT
14
9
22
17
O
Fault event indicator. It is an open drain output. If unused, leave floating.
Connect GND to system ground.
GND
—
A resistor from this pin to RTN sets the overload and short-circuit current limit.
See the Overload and Short Circuit Protection section.
ILIM
11
10
19
18
I/O
O
Analog current monitor output. This pin sources a scaled down ratio of current
through the internal FET. A resistor from this pin to RTN converts current to
proportional voltage. If unused, leave it floating.
IMON
1
2
8
9
IN
Power Power input and supply voltage of the device.
Mode selection pin for over load fault response. See the Device Functional
Modes section.
MODE
N.C
6
4
13
I
1-7
11
—
No connect.
13
16
21
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Table 6-1. Pin Functions (continued)
PIN
TPS26400
HTSSOP VQFN
TYPE
DESCRIPTION
NAME
15
16
23
24
OUT
OVP
Power Power output of the device.
Input for setting the programmable overvoltage protection threshold. An
overvoltage event turns off the internal FET and asserts FLT to indicate the
overvoltage fault. Connect OVP pin to RTN pin externally to select the Factory
set V(IN) overvoltage trip level. See Overvoltage Protection (OVP) section.
5
12
—
I
PowerPad must be connected to RTN plane on PCB using multiple vias for
enhanced thermal performance. Do not use PowerPad as the only electrical
connection to RTN. For Programmable overvoltage clamp, connect the resistor
ladder from Vout to OVP to RTN.
PowerPadTM
—
—
RTN
8
7
15
14
—
I
Reference for device internal control circuits.
Shutdown pin. Pulling SHDN low makes the device to enter into low power
shutdown mode. Cycling SHDN pin voltage resets the device that has latched off
due to a fault condition.
SHDN
Input for setting the programmable undervoltage lockout threshold. An
undervoltage event turns off the internal FET and asserts FLT to indicate the
power-failure. Connect UVLO pin to RTN pin to select the internal default
threshold.
UVLO
3
10
I
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7 Specifications
over operating free-air temperature range (all voltages referred to GND (unless otherwise noted))(1)
7.1 Absolute Maximum Ratings
MIN
–45
–55
–0.3
–0.3
–45
MAX
UNIT
V
IN , IN-OUT
45
55
45
5
IN , IN-OUT (10 ms transient), TA = 25°C
[IN, OUT, FLT, UVLO, SHDN] to RTN
[OVP, dVdT, ILIM, IMON, MODE] to RTN
RTN
V
Input voltage
V
V
0.3
10
V
IFLT, IdVdT, ISHDN
Sink current
mA
IdVdT, IILIM, IIMON
Source current
Internally limited
Operating junction temperature
Transient junction temperature
Storage temperature
–40
–65
–65
150
T(TSD)
150
°C
°C
°C
TJ
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V (ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
over operating free-air temperature range (all voltages referred to GND (unless otherwise noted))
7.3 Recommended Operating Conditions
MIN
–42
0
NOM
MAX
42
UNIT
IN
UVLO, OUT, FLT
Input voltage
Resistance
42
V
OVP, dVdT, ILIM, IMON, SHDN
0
4
ILIM
5.36
1
120
kΩ
IMON
IN, OUT
dVdT
TJ
0.1
10
μF
nF
°C
External capacitance
Operating junction temperature
–40
25
125
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7.4 Thermal Information
TPS2640
PWP (HTSSOP)
THERMAL METRIC(1)
RHF (VQFN)
24 PINS
30.2
UNIT
16 PINS
38.6
22.7
18.2
0.5
R θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
R θJB
20.8
7.6
ψ JT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψ JB
18
7.6
R θJC(bot)
1.5
1.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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7.5 Electrical Characteristics
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
V(IN)
Operating input voltage
Internal POR threshold, rising
Internal POR hysteresis
4.2
42
V
V
V(PORR)
V(PORHys)
IQ(ON)
IQ(OFF)
I(VINR)
3.9
250
190
11
4
4.1
300
390
33
275
300
20
mV
µA
µA
µA
Enabled: V(SHDN) = 2 V
Supply current
V(SHDN) = 0 V
Reverse input supply current
V(IN) = –42 V, V(OUT) = 0 V
66
UNDERVOLTAGE LOCKOUT (UVLO) INPUT
V(IN) rising, V(UVLO) = 0 V
V(IN) falling, V(UVLO) = 0 V
14.25
13.25
180
14.9
13.8
200
1.19
1.1
15.75
14.75
240
Factory set V(IN) undervoltage trip
level
V(IN_UVLO)
V
V(SEL_UVLO)
V(UVLOR)
V(UVLOF)
I(UVLO)
Internal UVLO select threshold
UVLO threshold voltage, rising
UVLO threshold voltage, falling
UVLO input leakage current
mV
V
1.175
1.08
1.225
1.125
100
V
0 V ≤ V(UVLO) ≤ 42 V
I(SHDN) = 0.1 µA
–100
0
nA
LOW IQ SHUTDOWN (SHDN) INPUT
V(SHDN)
V(SHUTF)
I(SHDN)
Output voltage
2
0.55
–10
2.7
3.4
V
V
SHDN threshold voltage for low IQ
shutdown, falling
0.76
0.94
Leakage current
V(SHDN) = 0.4 V
µA
OVERVOLTAGE PROTECTION (OVP) INPUT
V(IN) rising, V(OVP) = 0 V
V(IN) falling, V(OVP) = 0 V
31
28.5
180
32.6
30.3
200
1.19
1.1
34
31.5
240
V(IN_OVP)
Factory set V(IN) overvoltage trip level
V
V(SEL_OVP)
V(OVPR)
V(OVPF)
I(OVP)
Internal OVP select threshold
Overvoltage threshold voltage, rising
Overvoltage threshold, falling
OVP input leakage current
mV
V
1.17
1.085
–100
1.225
1.125
100
V
0 V ≤ V(OVP) ≤ 4 V
0
nA
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)
dVdT charging current
dVdT discharging resistance
dVdT to OUT gain
V(dVdT) = 0 V
4
4.7
14
5.5
µA
Ω
R(dVdT)
V(SHDN) = 0 V, with I(dVdT) = 10 mA sinking
V(OUT)/V(dVdT)
GAIN(dVdT)
23.75
24.6
25.5
V/V
CURRENT LIMIT PROGRAMMING (ILIM)
V(ILIM)
ILIM bias voltage
1
0.1
1
V
A
R(ILIM) = 120 kΩ, V(IN) – V(OUT) = 1 V
R(ILIM) = 12 kΩ, V(IN) – V(OUT) = 1 V
R(ILIM) = 8 kΩ, V(IN) – V(OUT) = 1 V
R(ILIM) = 5.36 kΩ, V(IN) – V(OUT) = 1 V
0.085
0.95
0.115
1.05
I(OL)
1.425
2.11
1.5
2.23
1.575
2.35
Overload current limit
R(ILIM) = OPEN, open resistor current limit
(single point failure test: UL60950)
I(OL_R-OPEN)
I(OL_R-SHORT)
0.055
0.095
R(ILIM) = SHORT, shorted resistor current
limit (single point failure test: UL60950)
R(ILIM) = 120 kΩ, MODE = open
R(ILIM) = 5.36 kΩ, MODE = open
0.045
2
0.073
2.21
0.11
2.4
I(CB)
Circuit breaker detection threshold
A
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7.5 Electrical Characteristics
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R(ILIM) = 120 kΩ, V(IN) – V(OUT) = 5 V
R(ILIM) = 8 kΩ, V(IN) – V(OUT) = 5 V
R(ILIM) = 5.36 kΩ, V(IN) – V(OUT) = 5 V
0.08
0.1
0.12
I(SCL)
Short-circuit current limit
1.425
2.11
1.5
1.575
2.35
A
2.23
1.87 ×
I(OL)
0.015
I(FASTRIP)
Fast-trip comparator threshold
+
A
CURRENT MONITOR OUTPUT (IMON)
GAIN(IMON) Gain factor I(IMON): I(OUT)
PASS FET OUTPUT (OUT)
0.1 A ≤ I(OUT) ≤ 2 A
72
78.28
85
µA/A
0.1 A ≤ I(OUT) ≤ 2 A, TJ = 25°C
0.1 A ≤ I(OUT) ≤ 2 A, TJ = 85°C
140
150
150
160
210
RON
IN to OUT total ON resistance
mΩ
µA
0.1 A ≤ I(OUT) ≤ 2 A, –40°C ≤ TJ ≤
+125°C
80
250
12
V(IN) = 42 V, V(SHDN)= 0 V, V(OUT) = 0 V,
sourcing
V(IN) = 0 V, V(SHDN)= 0 V, V(OUT) = 24
V, sinking
Ilkg(OUT)
OUT leakage current in Off state
11
V(IN) = –42 V, V(SHDN)= 0 V, V(OUT) = 0
V, sinking
50
V(IN) – V(OUT) threshold for reverse
protection comparator, falling
V(REVTH)
–15
85
–10
96
–5
mV
mV
V(IN) – V(OUT) threshold for reverse
protection comparator, rising
V(FWDTH)
110
FAULT FLAG (FLT): ACTIVE LOW
R(FLT) FLT pull-down resistance
I(FLT) FLT input leakage current
THERMAL SHUT DOWN (TSD)
V(OVP) = 2 V, I(FLT) = 5 mA sinking
0 V ≤ V(FLT) ≤ 42 V
40
85
160
200
Ω
–200
nA
T(TSD)
TSD threshold, rising
157
10
ºC
ºC
T(TSDhyst)
MODE
TSD hysteresis
MODE = 402 kΩ to RTN
MODE = Open
Current limiting with latch
Circuit breaker mode with
auto-retry
MODE_SEL
Thermal fault mode selection
Current limiting with auto-
retry
MODE = Short to RTN
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7.6 Timing Requirements
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
MIN
NOM
MAX
UNIT
IN AND UVLO INPUT
UVLO_tON(dly)
UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100
mV, C(dvdt) = open
250
µs
UVLO turnon delay
UVLO turnoff delay
250 +
14.5 ×
C(dvdt)
UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100
mV, C(dvdt) ≥ 10 nF, [C(dvdt) in nF]
µs
µs
UVLO_toff(dly)
UVLO↓ (100 mV below V(UVLOF)) to FLT↓
10
SHUTDOWN CONTROL INPUT (SHDN)
250 +
14.5 ×
C(dvdt)
SHDN↑ to V(OUT) = 100 mV, C(dvdt) ≥ 10 nF,
[C(dvdt) in nF]
µs
SHUTDOWN exit
delay
tSD(dly)
SHDN↑ to V(OUT) = 100 mV, C(dvdt) = open
SHDN↓ (below V(SHUTF)) to FLT↓
250
10
µs
µs
SHUTDOWN entry
delay
OVER VOLTAGE PROTECTION INPUT (OVP)
OVP exit delay
tOVP(dly)
OVP↓ (20 mV below V(OVPF)) to V(OUT) = 100 mV
OVP↑ (20 mV above V(OVPR)) to FLT↓
200
6
µs
µs
OVP disable delay
CURRENT LIMIT
Fast-trip comparator
delay
ns
tFASTTRIP(dly)
I(OUT) > I(FASTRIP)
250
REVERSE PROTECTION COMPARATOR
(V(IN) – V(OUT))↓ (100-mV overdrive below
V(REVTH)) to internal FET turn OFF
1.5
45
70
tREV(dly)
Reverse protection
comparator delay
(V (IN) – V(OUT))↓ (10-mV overdrive below
V(REVTH)) to FLT↓
µs
(V(IN) – V(OUT))↑ (10-mV overdrive above
V(FWDTH)) to FLT↑
tFWD(dly)
THERMAL SHUTDOWN
tretry
Retry delay in TSD
512
ms
ms
OUTPUT RAMP CONTROL (dVdT)
SHDN↑ to V(OUT) = 23.9 V, with C(dVdT) = 47 nF
SHDN↑ to V(OUT) = 23.9 V, with C(dVdT) = open
10
tdVdT
Output ramp time
1.6
FAULT FLAG (FLT)
FLT assertion delay in
circuit breaker mode
tCB(dly)
MODE = OPEN, delay from I(OUT) > I(OL) to FLT↓
MODE = OPEN
4
ms
ms
Retry delay in circuit
breaker mode
tCBretry(dly)
tPGOODF
540
Falling edge
875
PGOOD delay (de-
glitch) time
Rising edge, C(dVdT) = open
1400
µs
tPGOODR
875 + 20
× C(dVdT)
Rising egde, C(dVdT) ≥ 10 nF, [C(dvdt) in nF]
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7.7 Typical Characteristics
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN
(unless stated otherwise).
300
250
200
150
100
50
1.24
1.22
1.2
V(UVLOR) (V)
V(UVLOF) (V)
ILOAD = 2 A
ILOAD = 1 A
ILOAD = 0.1 A
1.18
1.16
1.14
1.12
1.1
0
-50
-50
0
50
Temperature (èC)
100
150
0
50
Temperature (èC)
100
150
D002
D001
Figure 7-2. UVLO Threshold Voltage vs Temperature
Figure 7-1. On-Resistance vs Temperature Across Load Current
1.26
-8
V(OVPR) (V)
V(OVPF) (V)
1.23
V(REVTH) (mV)
-8.5
-9
-9.5
-10
1.2
1.17
1.14
1.11
1.08
-10.5
-11
-11.5
-12
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D006
D003
Figure 7-4. Reverse Voltage Threshold vs Temperature
Figure 7-3. OVP Threshold Voltage vs Temperature
100
34
V(FWDTH) (V)
V(IN_OVP) (V)
V(IN_OVP) (V)
99
98
97
96
95
94
93
92
91
90
33.5
33
32.5
32
31.5
31
30.5
30
-50
0
50
Temperature (èC
100
150
-50
0
50
Temperature (èC)
100
150
D008
D007
Figure 7-6. Internal OVP Threshold vs Temperature
Figure 7-5. V(FWDTH) vs Temperature
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7.7 Typical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN
(unless stated otherwise).
15.2
15
4
3.95
3.9
V(UVLOR) (V)
V(UVLOF) (V)
14.8
14.6
14.4
14.2
14
V(PORR) (V)
V(PORF) (V)
3.85
3.8
3.75
3.7
13.8
13.6
3.65
3.6
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D009
D012
Figure 7-7. Internal UVLO Threshold vs Temperature
Figure 7-8. Internal POR Threshold Voltage vs Temperature
Figure 7-9. Input Supply Current vs Supply Voltage in
Shutdown
Figure 7-10. Input Supply Current vs Supply Voltage During
Normal Operation
Figure 7-11. Input Supply Current vs Reverse Supply Voltage, –
V(IN)
Figure 7-12. Output Current vs Reverse Supply Voltage, – V(IN)
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7.7 Typical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN
(unless stated otherwise).
10
9
8
7
6
5
4
3
2
1
0
20
18
16
14
12
10
8
OVP Disable Delay (ms)
tSD(dly)
6
4
2
0
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D017
D018
Figure 7-13. OVP Disable Delay vs Temperature
Figure 7-14. Shutdown Entry Delay vs Temperature
200
0.82
0.8
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
V(SHUTF) (V)
100
70
0.78
0.76
0.74
0.72
0.7
50
30
20
10
7
5
0.68
0.66
0.64
3
2
1
0.01 0.02
-40
-20
0
20
40
60
80
100 120 140
0.05 0.1 0.2 0.3 0.5
Output Current (A)
1
2
3 4 567 10
Temperature (èC)
D019
D025
Figure 7-15. Shutdown Threshold Voltage Shutdown vs
Temperature
Figure 7-16. Current Monitor Output vs Output Current
1%
79.8
R(ILIM)= 24 kW
GAIN(IMON) (mA/A)
79.6
R(ILIM)= 12 kW
R(ILIM)= 8 kW
0.8%
0.6%
0.4%
0.2%
0
79.4
79.2
79
R(ILIM)= 5.36 kW
78.8
78.6
78.4
78.2
78
-0.2%
-0.4%
-0.6%
77.8
77.6
-50
0
50
Temperature (èC)
100
150
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D021
D020
Figure 7-18. Current Limit (% Normalized) vs Temperature
Figure 7-17. GAIN(IMON) vs Temperature
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7.7 Typical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN
(unless stated otherwise).
1%
0
3.2
2.8
2.4
2
R(ILIM) = 120 kW
R(ILIM) = 80 kW
R(ILIM) = 120 kW
R(ILIM) = 80 kW
R(ILIM) = 24 kW
R(ILIM) = 12 kW
R(ILIM) = 8 kW
R(ILIM) = 5.36 kW
-1%
-2%
-3%
-4%
-5%
-6%
1.6
1.2
0.8
0.4
0
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D024
D004
Figure 7-19. Current Limit (% Normalized) vs Temperature
Figure 7-20. Reverse Voltage Threshold vs Temperature
60
0.11
R(ILIM) = Open
R(ILIM) = Short
0.1
50
40
30
20
10
0
0.09
0.08
0.07
0.06
0.05
0.04
-50
0
50
Temperature (èC)
100
150
0
0.5
1
1.5
Circuit Breaker Threshold (A)
2
2.5
D005
D026
Figure 7-21. Current Limit for R(ILIM) = Open and Short vs
Temperature
Figure 7-22. Circuit Breaker Threshold Accuracy vs Circuit
Breaker Threshold I(CB)
16
14
12
10
8
10.4
UVLO_toff(dly)
10.2
10
9.8
9.6
9.4
9.2
9
6
4
-60 -40 -20
0
20
40
60
80 100 120 140
0
0.5
1 1.5
Current Limit (A)
2
2.5
Temperature (èC)
D022
D027
Figure 7-24. UVLO Turnoff Delay vs Temperature
Figure 7-23. Current Limit Accuracy vs Current Limit, I(OL)
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7.7 Typical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN
(unless stated otherwise).
100000
TA = -40èC
TA = 25èC
10000
TA = 85èC
TA = 105èC
TA = 125èC
1000
100
10
1
0.2
1
10
Power_Dissipation (W)
100
Figure 7-26. OVP Overvoltage Cut-Off Response
D023
Figure 7-25. Thermal Shutdown Time vs Power Dissipation
Figure 7-27. Hot-Short: Fast Trip Response and Current
Regulation
Figure 7-28. Hot-Short: Fast Trip Response (Zoomed)
Figure 7-29. Turnon Control With SHDN
Figure 7-30. Turnoff Control With SHDN
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8 Parameter Measurement Information
V(OUT)
VUVLO
V(UVLOF)-0.1 V
0.1 V
VUVLO
FLT
V(UVLOR)+0.1V
10%
time
0
time
0
UVLO_tON(dly)
UVLO_toff(dly)
-20 mV
110 mV
V(IN) -V(OUT)
V(IN) -V(OUT)
90%
FLT
FLT
10%
0
time
tREV(dly)
0
time
tFWD(dly)
I(FASTRIP)
V(OVPR)+0.1V
V(OVP)
I(SCL)
I(OUT)
FLT
10%
0
time
0
time
tOVP(dly)
tFASTRIP(dly)
Figure 8-1. Timing Waveforms
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9 Detailed Description
9.1 Overview
The TPS26400 is a high voltage industrial eFuse with integrated back-to-back MOSFETs and enhanced built-in
protection circuitry. It provides robust protection for all systems and applications powered from 4.2 V to 42 V. The
device can withstand ±42-V positive and negative supply voltages without damage. For hotpluggable boards, the
device provides hot-swap power management with in-rush current control and programmable output voltage
slew rate features. Load, source and device protections are provided with many programmable features
including overcurrent, overvoltage, undervoltage. The precision overcurrent limit (±5% at 1 A) helps to minimize
over design of the input power supply, while the fast response short circuit protection 250 ns (typical)
immediately isolates the faulty load from the input supply when a short circuit is detected.
The internal robust protection control blocks of the TPS26400 along with its ±42-V rating helps to simplify the
system designs for the surge compliance ensuring complete protection of the load and the device.
The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault
signal for the downstream system. The TPS26400 monitor functions threshold accuracy of ±3% ensures tight
supervision of the supply bus, eliminating the need for a separate supply voltage supervisor chip.
The device monitors V(IN) and V(OUT) to provide true reverse current blocking when a reverse condition or
input power failure condition is detected. The TPS26400 is also designed to control redundant power supply
systems. A pair of TPS26400 devices can be configured for Active ORing between the main power supply and
the auxiliary power supply (see the System Examples section).
Additional features of the TPS26400 include:
•
•
•
•
•
•
Current monitor output for health monitoring of the system
Electronic circuit breaker operation with overload timeout using MODE pin
A choice of latch off or automatic restart mode response during current limit fault using MODE pin
Over temperature protection to safely shutdown in the event of an overcurrent event
De-glitched fault reporting for brown-out and overvoltage faults
Look ahead overload current fault indication (see the Look Ahead Overload Current Fault Indicator section)
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9.2 Functional Block Diagram
OUT
IN
150 mΩ
-10 mV
+
PORb
Charge
Pump
+100 mV
4 V
3.72 V
Current
X78.2 µ
Sense
CP
+
UVLOb
1.19 V
1.1 V
REVERSE
VSEL_UVLO
SWEN
+
Gate Control Logic
IMON
UVLO
Current Limit Amp
Fast-Trip Comp
TSD
Thermal
Shutdown
+
OVP
(Threshold=1.8xIOL
)
1.19 V
1.1 V
1 V
+
OLR
SHDNb
œ
Over Voltage clamp detect
(TPS26602 Only)
VSEL_OVP
+
ILIM
OVP
Short detect
Ramp Control
24.6 x
SWEN
Avdd
FLT
I(LOAD) ≥ I(CB)
* Only for Latch Mode
OLR
85 Ω
Timeout
4 msec
timer
5 uA
SET
Q
Q
S
dVdT
RTN
UVLOb
1.4 msec
875 µs
CLR
R
14 Ω
PORb
TSD
PORb
Fault Latch
Avdd
SHDNb
Gate Enhanced (tPGOOD
)
OLR
Avdd
400 kΩ
Overload fault response
select detection
Reverse Input Polarity
Protection circuit
0.76 V
GND
SHDNb
+
RTN
TPS26400
MODE
SHDN
9.3 Feature Description
9.3.1 Undervoltage Lockout (UVLO)
Undervoltage comparator input. When the voltage at UVLO pin falls below V(UVLOF) during input power fail or
input undervoltage fault, the internal FET quickly turns off and FLT is asserted. The UVLO comparator has a
hysteresis of 90 mV. To set the input UVLO threshold, connect a resistor divider network from IN supply to UVLO
terminal to RTN as shown in Figure 9-1.
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V(IN)
IN
TPS26400
R1
UVLO
+
+
UVLOb
1.19 V
1.1 V
R2
OVP
RTN
OVP
1.19 V
1.1 V
R3
GND
Figure 9-1. UVLO and OVP Thresholds Set by R1, R2 and R3
The TPS26400 also features a factory set 15-V input supply undervoltage lockout V(IN_UVLO) threshold with 1-V
hysteresis. This feature can be enabled by connecting the UVLO terminal directly to the RTN terminal. If the
Under-Voltage Lock-Out function is not needed, the UVLO terminal must be connected to the IN terminal. UVLO
terminal must not be left floating.
The device also implements an internal power ON reset (POR) function on the IN terminal. The device disables
the internal circuitry when the IN terminal voltage falls below internal POR threshold V(PORF). The internal POR
threshold has a hysteresis of 275 mV.
9.3.2 Overvoltage Protection (OVP)
The TPS26400 incorporate circuitry to protect the system during overvoltage conditions. A voltage more than
V(OVPR) on OVP pin turns off the internal FET and protects the downstream load. To program the OVP threshold
externally, connect a resistor divider from IN supply to OVP terminal to RTN as shown in Figure 9-1. The
TPS26400 also feature a factory set 33-V Input overvoltage cut off V(IN_OVP) threshold with a 2-V hysteresis. This
feature can be enabled by connecting the OVP terminal directly to the RTN terminal. Figure 7-26 illustrates the
overvoltage cut-off functionality.
Programmable output overvoltage clamp can also be achieved using TPS26400 by connecting the resistor
ladder
from Vout to OVP to RTN as shown in Figure 9-2 . This results in clamping of output voltage close to OVP
setpoint
by resistors R4 and R5. as shown in Figure 9-3. This scheme will also help in achieving minimal system Iq
during off state. For this OVP configurataion, use R4 > 90 kΩ.
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V(IN)
IN
OUT
TPS26400
R1
UVLO
R4
+
+
UVLOb
1.19 V
1.1 V
OUT_OVP
R2
R5
OVP
RTN
OUT_OVP
OVP
1.19 V
1.1 V
RTN
Figure 9-2. Programmable Output OV Clamp
Figure 9-3. Programmable Output Overvoltage Clamp Response
9.3.3 Reverse Input Supply Protection
To protect the electronic systems from reverse input supply due to miswiring, often a power component like a
schottky diode is added in series with the supply line as shown in Figure 9-4. These additional discretes result in
a lossy and bulky protection solution. The TPS26400 devices feature fully integrated reverse input supply
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protection and does not need an additional diode. These devices can withstand –42 V reverse voltage without
damage. Figure 9-5 illustrates the reverse input polarity protection functionality.
INPUT
OUTPUT
INPUT
OUTPUT
TPS26400
eFuse
Hot-Swap Controller
GND
GND
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Figure 9-4. Reverse Input Supply Protection Circuits - Discrete vs TPS26400
Figure 9-5. Reverse Input Supply Protection at –42 V
9.3.4 Hot Plug-In and In-Rush Current Control
The device is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot"
power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets of
the system power. The controlled start-up also helps to eliminate conductive and radiative interferences. An
external capacitor connected from the dVdT pin to RTN defines the slew rate of the output voltage at power-on
as shown in Figure 9-6 and Figure 9-7.
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TPS26400
4 V
5 µA
dVdT
RTN
16 Ω
SWEN
C(dVdT)
Figure 9-6. Output Ramp Up Time tdVdT is Set by C(dVdT)
The dVdT pin can be left floating to obtain a predetermined slew rate (tdVdT) on the output. When the terminal is
left floating, the devices set an internal output voltage ramp rate of 23.9 V/1.6 ms. A capacitor can be connected
from dVdT pin to RTN to program the output voltage slew rate slower than 23.9 V/1.6 ms. Use Equation 1 and
Equation 2 to calculate the external C(dVdT) capacitance.
Equation 1 governs slew rate at start-up.
æ
ç
ö
÷
C dVdT
dV
OUT
æ
ö
÷
÷
ø
(
)
(
)
I(dVdT)
=
´ ç
ç
ç
è
÷
ø
Gain dVdT
dt
(
)
è
(1)
where
•
•
•
I(dVdT) = 4.7 μA (typical)
d
Gain(dVdT) = dVdT to VOUT gain = 24.6
The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using Equation 2.
tdVdT = 8 × 103 × V(IN) × C(dVdT)
(2)
VIN
Figure 9-7. Hot Plug-In and In-Rush Current Control at 24-V Input
9.3.5 Overload and Short Circuit Protection
The device monitors the load current by sensing the voltage across the internal sense resistor. The FET current
is monitored during start-up and normal operation.
9.3.5.1 Overload Protection
The device offers following choices for the overload protection fault response:
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•
•
Active current limiting (Auto-retry/Latch-off modes)
Electronic Circuit Breaker with overload timeout (Auto-retry)
See the configurations in Table 1 to select a specific overload fault response.
Table 9-1. Overload Fault Response Configuration Table
MODE Pin Configuration
Overload Protection Type
Electronic circuit breaker with auto-retry
Active current limiting with auto-retry
Device
Open
TPS26400
TPS26400
Shorted to RTN
A 402-kΩ resistor across MODE pin to RTN
pin
Active current limiting with latch-off
TPS26400
9.3.5.1.1 Active Current Limiting
When the active current limiting mode is selected, during overload events, the device continuously regulates the
load current to the overcurrent limit I(OL) programmed by the R(ILIM) resistor as shown in Equation 3.
12
IOL
=
R(ILIM
)
(3)
where
•
•
I(OL) is the overload current limit in Ampere
R(ILIM) is the current limit resistor in kΩ
During an overload condition, the internal current-limit amplifier regulates the output current to I(LIM). The FLT
signal assert after a delay of 875 μs. The output voltage droops during the current regulation, resulting in
increased power dissipation in the device. If the device junction temperature reaches the thermal shutdown
threshold (T(TSD)), the internal FET is turn off. The device configured in latch-off mode stays latched off until it is
reset by either of the following conditions:
•
•
Cycling V(IN) below V(PORF)
Toggling SHDN
Whereas the device configured in auto-retry mode, commences an auto-retry cycle 512 ms after TJ < [T(TSD) –
10°C]. The FLT signal remains asserted until the fault condition is removed and the device resumes normal
operation. Figure 9-8 and Figure 9-9 illustrates behavior of the system during current limiting with auto-retry
functionality.
IMON
V_OUT
FLTb
I_IN
Load transition from MODE pin connected RILIM = 8 kΩ
22 Ω to 12 Ω to RTN
RILIM = 5.36 kΩ
Figure 9-9. Response During Coming Out of
Overload Fault
Figure 9-8. Auto-Retry MODE Fault Behavior
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9.3.5.1.2 Electronic Circuit Breaker with Overload Timeout, MODE = OPEN
In this mode, during overload events, the device allows the overload current to flow through the device until
I(LOAD) < I(FASTRIP). The circuit breaker threshold I(CB) can be programmed using the R(ILIM) resistor as shown in
Equation 4.
12
I(CB) =
+ 0.03A
R(ILIM
)
(4)
where
•
•
I(CB) is circuit breaker current threshold in Ampere
R(ILIM) is the current limit resistor in kΩ
An internal timer starts when I(CB) < ILOAD
< IFASTRIP, and when the timer exceeds tCB(dly), the device turns OFF
the internal FET and FLT is asserted. After the internal FET is turned off,
the device commences an auto-retry cycle after 540 ms. The FLT signal remains asserted until the fault
condition is removed and the device resumes normal operation. Figure 9-10 and Figure 9-11 illustrate behavior
of the system during electronic circuit breaker with auto-retry functionality.
IMON
V_OUT
FLTb
I_IN
MODE left floating
Load Transition from RILIM = 8 kΩ
22 Ω to 12 Ω
Load Transition from 22 Ω to 12 Ω , RILIM = 8 kΩ
Figure 9-11. Zoomed at the Instance of Load Step
Figure 9-10. Circuit Breaker Functionality
9.3.5.2 Short Circuit Protection
During a transient output short circuit event, the current through the device increases very rapidly. As the
currentlimit amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a
fast-trip comparator, with a threshold I(FASTRIP). The fast-trip comparator turns off the internal FET within 250 ns
(typical), when the current through the FET exceeds I(FASTRIP) (I(OUT) > I(FASTRIP)), and terminates the rapid short-
circuit peak current. The fast-trip threshold is internally set to 87% higher than the programmed overload current
limit (I(FASTRIP) = 1.87 × I(OL) + 0.015). The fast-trip circuit holds the internal FET off for only a few microseconds,
after which the device turns back on slowly, allowing the current-limit loop to regulate the output current to I(OL)
.
Then, device behaves similar to overload condition. Figure 9-12 and Figure 9-13 illustrate the behavior of the
system when the current exceeds the fast-trip threshold.
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VIN = 24 V, RILIM = 5.36 kΩ
Figure 9-13. Zoomed at the Instance of Output
Short
Figure 9-12. Output Hot Short Functionality at 24-V
Input
9.3.5.2.1 Start-Up With Short-Circuit On Output
When the device is started with short-circuit on the output, it limits the load current to the current limit I(OL) and
behaves similar to the overload condition. Figure 9-14 illustrates the behavior of the device in this condition. This
feature helps in quick isolation of the fault and hence ensures stability of the DC bus
MODE pin connected to RTN
VIN = 24 V RILIM = 5.36 kΩ
Figure 9-14. Start-Up With Short on Output
9.3.5.3 FAULT Response
The FLT open-drain output asserts (active low) under following conditions:
•
•
•
Fault events such as undervoltage, overvoltage, over load, reverse current and thermal shutdown conditions
When the device enters low current shutdown mode when SHDN is pulled low
During start-up when the internal FET GATE is not fully enhanced
The device is designed to eliminate false reporting by using an internal "de-glitch" circuit for fault conditions
without the need for an external circuitry.
The FLT signal can also be used as Power Good indicator to the downstream loads like DC-DC converters. An
internal Power Good (PGOOD) signal is OR'd with the fault logic. During start-up, when the device is operating
in dVdT mode, PGOOD and FLT remains low and is de-asserted after the dVdT mode is completed and the
internal FET is fully enhanced. The PGOOD signal has deglitch time incorporated to ensure that internal FET is
fully enhanced before heavy load is applied by the downstream converters. Rising deglitch delay is determined
by tPGOOD(degl) = Maximum {(875 + 20 × C(dVdT)), tPGOODR}, where C(dVdT) is in nF and tPGOOD(degl) is in μs.
FLT can be left open or connected to RTN when not used. V(IN) falling below V(PORF) = 3.72 V resets FLT.
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9.3.5.3.1 Look Ahead Overload Current Fault Indicator
With the device configured in current limit operation and when the overload condition exists for more than
t PGOODF, 875 μs (typical), the FLT asserts to warn of impending turnoff of the internal FETs due to the
subsequent thermal shutdown event. Figure 9-15 and Figure 9-16 depict this behavior. The FLT signal remains
asserted until the fault condition is removed and the device resumes normal operation.
RILIM = 12 kΩ
RILIM = 12 kΩ
MODE pin connected
to RTN
Load transient event RILIM = 12 kΩ
from 37 Ω to 15 Ω
RILIM = 12 kΩ
MODE pin connected
to RTN
Load transient event
from 37 Ω to 15 Ω
Figure 9-15. Output Turnoff Due to Thermal
Shutdown With FLT Asserted in Advance
Figure 9-16. Look Ahead Overload Current Fault
Indication
9.3.5.4 Current Monitoring
The current source at IMON terminal is internally configured to be proportional to the current flowing from IN to
OUT. This current can be converted into a voltage using a resistor R(IMON) from IMON terminal to RTN terminal.
The IMON voltage can be used as a means of monitoring current flow through the system. The maximum
voltage range (V(IMONmax)) for monitoring the current is limited to minimum of ([V(IN) – 1.5 V, 4 V]) to ensure linear
output. This puts a limitation on maximum value of R(IMON) resistor and is determined by Equation 5.
Min [(V(IN) - 1.5), 4 V]
R
(
IMONmax
)
=
1.8 ì I
(
LIM
)
ì GAIN
(
IMON
)
(5)
(6)
The output voltage at IMON terminal is calculated using Equation 6 and Equation 7.
For IOUT > 50 mA,
V
(IMON) = [I(OUT) × GAIN(IMON)] × R(IMON)
where,
•
•
•
GAIN(IMON) is the gain factor I(IMON):I(OUT) = 78.4 μA/A (Typical)
I(OUT) is the load current
I(MON_OS) = 2 μA (Typical)
For IOUT < 50 mA (typical), use Equation 7.
V(IMON) = (I(IMON_ OS)) × R(IMON)
(7)
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This pin must not have a bypass capacitor to avoid delay in the current monitoring information. In case of
reverse input polarity fault, an external 100-kΩ resistor is recommended between IMON pin and ADC input to
limit the current through the ESD protection structures of the ADC.
9.3.5.5 IN, OUT, RTN, and GND Pins
The device has two pins for input (IN) and output (OUT). All IN pins must be connected together and to the
power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus
transients. The recommended input operating voltage range is 4.2 to 42 V. Similarly all OUT pins must be
connected together and to the load. V(OUT), in the ON condition, is calculated using Equation 8.
V(OUT) V(IN) – (RON) × I(OUT)
(8)
Where,
RON is the total ON resistance of the internal FETs.
•
GND pin must be connected to the system ground. RTN is the device ground reference for all the internal control
blocks. Connect the TPS26400 support components: R(ILIM), C(dVdT), R(IMON), R(MODE) and resistors for UVLO
and OVP with respect to the RTN pin. Internally, the device has reverse input polarity protection block between
RTN and the GND terminal. Connecting RTN pin to GND pin disables the reverse input polarity protection
feature and the TPS26400 gets permanently damaged when operated under this fault event.
9.3.5.6 Thermal Shutdown
The device has a built-in overtemperature shutdown circuitry designed to protect the internal FETs, if the junction
temperature exceeds T(TSD). After the thermal shutdown event, depending upon the mode of fault response, the
device either latches off or commences an auto-retry cycle 512 ms after TJ < [T(TSD) – 10°C]. During the thermal
shutdown, the fault pin FLT pulls low to indicate a fault condition.
9.3.5.7 Low Current Shutdown Control (SHDN)
The internal FETs and hence the load current can be switched off by pulling the SHDN pin below 0.76 V
threshold with a micro-controller GPIO pin or can be controlled remotely with an opto-isolator device as shown in
Figure 9-17 and Figure 9-18. The device quiescent current reduces to 20 μA (typical) in shutdown state. To
assert SHDN low, the pull down must sink at least 10 μA at 400 mV. To enable the device, SHDN must be pulled
up to atleast 1 V. Once the device is enabled, the internal FETs turnon with dVdT mode.
TPS26400
AVdd
Rpu
SHDN
from µC
GPIO
+
SHDNb
0.76V
GND
OFF
ON
Figure 9-17. Shutdown Control
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ON
OFF
AVdd
SHDN
+
SHDNb
a
k
C
E
0.84V
0.76V
œ
GND
TPS26400
Opto-Isolator
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Figure 9-18. Opto-Isolator Shutdown Control
9.4 Device Functional Modes
Different operational modes of the device are explained in Table 9-2.
Table 9-2. Device Operational Differences Under Different MODE Configurations
A 402-kΩ Resistor Connected
between MODE and RTN Pins
(Current Limit With Latchoff)
MODE Connected to RTN
(Current Limit With Auto-Retry)
MODE Pin = Open (Circuit
Breaker with Auto-Retry)
MODE Pin Configuration
Inrush current controlled by dVdT
Inrush limited to I(OL) level as set Inrush limited to I(OL) level as set Inrush limited to I(OL) level as set
by R(ILIM)
by R(ILIM)
by R(ILIM)
Fault timer runs when current is
limited to I(OL)
Start-up
Fault timer expires after tCB(dly)
causing the FETs to turnoff
If TJ > T(TSD), device turns off
Current is limited to I(OL) level as Current is limited to I(OL) level as Current is allowed through the
set by R(ILIM)
set by R(ILIM)
device if I(LOAD) < I(FASTTRIP)
Power dissipation increases as
V(IN) – V(OUT) increases
Power dissipation increases as
V(IN) – V(OUT) increases
Fault timer runs when the current
increases above I(OL)
Fault timer expires after tCB(dly)
causing the FETs to turnoff
Overcurrent response
Short-circuit response
Device turns off if TJ > T(TSD)
before timer expires
Device turns off when TJ > T(TSD) Device turns off when TJ > T(TSD)
TPS26400 device attempts to
restart 540 ms after TJ < [T(TSD)
10°C]
Device attempts restart 540 ms
Device remains off
–
after TJ < [T(TSD) – 10°C]
Fast turnoff when I(LOAD) > I(FASTRIP)
Quick restart and current limited to I(OL), follows standard start-up
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10 Application and Implementation
10.1 Application Information
The TPS26400 is an industrial eFuse, typically used for Hot-Swap and Power rail protection applications. It
operates from 4.2 V to 42 V with programmable current limit, overvoltage, undervoltage and reverse polarity
protection. The device aids in controlling in-rush current and provides robust protection against reverse current
and filed miss-wiring conditions for systems such as PLCs, Industrial PCs, Control and Automation and Sensors.
The device also provides robust protection for multiple faults on the system rail.
The Detailed Design Procedure section can be used to select component values for the device.
A spreadsheet design tool TPS26400 Design Calculator is available in the web product folder.
10.2 Typical Application
(1)
D2
VOUT
VIN: 4.2 V - 42 V
OUT
IN
(2)
CIN
COUT
150 mΩ
D3
R1
RFLTb
D1
UVLO
OVP
(1)
FLT
Health Monitor
TPS26400
ON/OFF Control
R2
R3
SHDN
IMON
ILIM
dVdT
Load Monitor
MODE
RTN
GND
RIMON
CdVdT
RILIM
Note
1. Optional TVS Diodes (D1 and D2) for Power Line Surge IEC61000-4-5 [±500 V, 2 Ω].
2. Optional Schotky Diode (D3) for output short circuit protection with inductlive loads and cables.
Figure 10-1. 24-V, 1-A eFuse Input Protection Circuit for Industrial PLC CPU
10.2.1 Design Requirements
Table 3 shows the Design Requirements for current input protection with TPS26610.
Table 10-1. Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
±20 mA
I(IN)
Input current
V(IN)
Input voltage
OutPut voltage
Current limit
–Vs to 50 V
±Vs
V(OUT)
I(LIM)
±30 mA
RBurden
Burden resistance
50 to 250 Ω
10.2.2 Detailed Design Procedure
10.2.2.1 Step by Step Design Procedure
To begin the design process, the designer needs to know the following parameters:
•
•
•
Input operating voltage range
Maximum output capacitance
Maximum current limit
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•
•
Load during start-up
Maximum ambient temperature
This design procedure below seeks to control junction temperature of the device in both steady state and
start-up conditions by proper selection of the output ramp-up time and associated support components. The
designer can adjust this procedure to fit the application and design criteria.
10.2.2.2 Selecting the ±Vs supplies for TPS26610
Select the supplies ±Vs higher than analog input voltage of the ADC used for current measurement. TPS2661x
devices have output over-volatage and under-voltage protection, the internal FETs are turned off if VOUT is more
than Vs or if VOUT is less than –Vs.
TPS2661x devices also have input under-voltage protection, the internal FETs are turned off if VIN is less than –
Vs.
10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using an external voltage divider
network of R1, R2 and R3 connected between IN, UVLO, OVP and RTN pins of the device. The values required
for setting the undervoltage and overvoltage are calculated by solving Equation 9 and Equation 10.
R3
V(OVPR) =
ì V(OV)
R1+ R2 + R3
(9)
R2 + R3
R1+ R2 + R3
V(UVLOR) =
ì V(UV)
(10)
For minimizing the input current drawn from the power supply {I(R123) = V(IN)/(R1+R2+R3)}, it is recommended to
use higher value resistance for R1, R2 and R3.
However, the leakage current due to external active components connected at resistor string can add error to
these calculations. So, the resistor string current, I(R123) must be chosen to be 20x greater than the leakage
current of UVLO and OVP pins.
The UVLO and the OVP pins can also be connected to the RTN pin to enable the internal default V(OV) = 33 V
and V(UV) = 15 V.
The power failure is detected on falling edge of the supply. This threshold voltage is 7.5% lower than the rising
threshold, V(UV). The voltage at which the device detects power fail can be calculated using Equation 12.
V(PFAIL) 0.925 × V(UV)
(11)
10.2.2.4 Programming Current Monitoring Resistor—RIMON
The voltage at IMON pin V(IMON) represents the voltage proportional to the load current. This can be connected
to an ADC of the downstream system for health monitoring of the system. The R(IMON) must be configured based
on the maximum input voltage range of the ADC used. R(IMON) is set using Equation 12.
V(IMONmax)
I(LIM) ì75 ì10-6
R(IMON) =
(12)
For I(LIM) = 1 A, and considering the operating voltage range of ADC from 0 V to 2.5 V, V(IMONmax) is 2.5 V and
R(IMON) is determined by Equation 13.
2.5
1ì75ì10-6
R(IMON) =
= 33.3kW
(13)
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Selecting the R(IMON) value less than determined ensures that ADC limits are not exceeded for maximum value
of the load current. Choose the closest standard 1% resistor value: R(IMON) = 33.2 kΩ.
If current monitoring up to I(FASTRIP) is desired, R(IMON) can be reduced by a factor of 1.8 as shown in Equation 5.
10.2.2.5 Setting Output Voltage Ramp Time—(tdVdT
)
For a successful design, the junction temperature of the device must be kept below the absolute-maximum rating
during dynamic (start-up) and steady state conditions. The dynamic power dissipation is often an order
magnitude greater than the steady state power dissipation. It is important to determine the right start-up time and
the in-rush current limit for the system to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor C(dVdT) is calculated considering the two possible cases:
10.2.2.5.1 Case 1: Start-Up Without Load—Only Output Capacitance C(OUT) Draws Current During Start-Up
During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and
the power dissipation decreases. Typical ramp-up of the output voltage, inrush current and instantaneous power
dissipated in the device during start-up are shown in Figure 10-2. The average power dissipated in the device
during start-up is equal to the area of triangular plot (red curve in Figure 10-3) averaged over tdVdT
.
2.5
30
24
18
12
6
Input Current (A)
Power DIssipation (W)
Output Voltage (V)
2
1.5
1
0.5
0
0
0
20
40
60
80
100
VIN = 24 V
CdVdT = 2.2 μF
COUT = 2.2 mF
Start-Up Time (%)
D050
Figure 10-2. Start-Up Without Load
VIN = 24 V
CdVdT = 2.2 μF
COUT = 2.2 mF
Figure 10-3. PD(INRUSH) Due to Inrush Current
The inrush current is determined as shown in Equation 14.
dV
dT
V(IN)
tdVdT
I = C ì
í I(INRUSH) = C(OUT) ì
(14)
Average power dissipated during start-up is given by Equation 15.
PD(INRUSH) 0.5 × V(IN) × I(INRUSH)
(15)
Equation 15 assumes that the load does not draw any current until the output voltage reaches its final value.
10.2.2.5.2 Case 2: Start-Up With Load—Output Capacitance C(OUT) and Load Draws Current During Start-Up
When the load draws current during the turnon sequence, additional power is dissipated in the device.
Considering a resistive load R L(SU) during start-up, typical ramp-up of output voltage, load current and the
instantaneous power dissipation in the device are shown in Figure 10-4. Instantaneous power dissipation with
respect to time is plotted in Figure 10-5. The additional power dissipation during start-up is calculated using
Equation 16.
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6
5.5
5
36
Input Current (A)
Power Dissipation (W)
Output Voltage (V)
33
30
27
24
21
18
15
12
9
4.5
4
3.5
3
2.5
2
1.5
1
6
0.5
0
3
0
0
20
40
60
80
100
Start-Up Time (%)
D051
VIN = 24 V
CdVdT = 2.2 μF
RL(SU) = 48 Ω
COUT = 2.2 mF
VIN = 24 V
CdVdT = 2.2 μF
RL(SU) = 48 Ω
COUT = 2.2 mF
Figure 10-5. PD(INRUSH) Due to Inrush and Load
Current
Figure 10-4. Start-Up With Load
1
6
V(IN)2
PD(LOAD) =
ì
RL(SU)
(16)
Total power dissipated in the device during start-up is given by Equation 17.
PD(STARTUP) PD(INRUSH) = PD(LOAD)
(17)
(18)
Total current during start-up is given by Equation 18.
I(STARTUP) = I(INRUSH) ÷ IL( t )
For the design example under discussion,
Select the inrush current I(INRUSH) = 0.1 A and calculate tdVdT using Equation 19.
24
t(dVdT) = 2.2mì
= 0.528s
0.1
(19)
(20)
For a given start-up time, CdVdT capacitance value is calculated using Equation 20.
t(dVdT)
C(dVdT) =
= 2.7mF
8 ì103 ì V(IN)
where
•
•
t(dVdT) = 0.528 s
V(IN) = 24 V
Choose the closest standard value: 2.2-μF/16-V capacitor.
The inrush power dissipation is calculated, using Equation 21.
PD(INRUSH) = 0.5 × V(IN) = I(INRUSH) 1.2W
(21)
where
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•
•
V(IN) = 24 V
I(INRUSH) = 0.1 A
Considering the start-up with 48-Ω load, the additional power dissipation, is calculated using Equation 22.
1
V(IN)2
PD(LOAD) = ( )ì
= 2 W
6
RL(SU)
(22)
where
•
•
V(IN) = 24 V
RL(SU) = 48 Ω
The total device power dissipation during start-up is given by Equation 23.
PD(STARTUP) = PD(INRUSH) + PD(LOAD) = 3.2W
(23)
where
•
•
PD(INRUSH) = 1.2 W
PD(LOAD) = 2 W
The power dissipation with or without load, for a selected start-up time must not exceed the thermal shutdown
limits as shown in Figure 10-6 .
From the thermal shutdown limit graph, at TA = 85°C, thermal shutdown time for 3.2 W is close to 28000 ms. It is
safe to have a minimum 30% margin to allow for variation of the system parameters such as load, component
tolerance, input voltage and layout. Selected 2.2-μF CdVdT capacitor and 528-ms start-up time (tdVdT) are within
limit for successful start-up with 48-Ω load.
Higher value C(dVdT) capacitor can be selected to further reduce the power dissipation during start-up.
10000
TA = -40èC
TA = 25èC
TA = 85èC
TA = 105èC
TA = 125èC
1000
100
10
1
0.1
1
10
Power Dissipation (W)
100
D052
Figure 10-6. Thermal Shutdown Time vs Power Dissipation
10.2.2.5.3 Support Component Selections—RFLTb and C(IN)
The RFLTb serves as pull-up for the open-drain fault output. The current sink by this pin must not exceed 10 mA
(see the Absolute Maximum Ratings table). Typical resistance value in the range of 10 kΩ to 100 kΩ is
recommended for RFLTb. The CIN is a local bypass capacitor to suppress noise at the input. Typical capacitance
value in the range of 0.1 μF to 1 μF is recommended for C(IN)
.
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10.2.3 Application Curves
V_IN
V_OUT
FLTb
I_IN
Figure 10-8. Start-Up With VIN—No Load
Figure 10-7. Start-Up With VIN—48-Ω Load
V_IN
SHDNb
V_OUT
I_IN
Figure 10-9. Power Fail With 24-Ω Load—Supports
1-A Load for 10-ms Power Fail
Figure 10-10. Start-Up With Shutdown Pin—48-Ω
Load
Figure 10-11. Power Down With Shutdown Pin—48-
Ω Load
Figure 10-12. Over Load Response—Load Stepped
from 100-Ω to 18-Ω Load
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VIN
VOUT
I_IN
Figure 10-13. Turnon With Short Circuit on Output
10.3 System Examples
Figure 10-14. Reverse Polarity Protection
10.3.1 Acive ORing Operation
IN
OUT
IN1: 4.2 V - 42 V
CIN
R1
150 mꢀ
UVLO
FLT
TPS26400
SHDN
OVP
R2
OUT
MODE
dVdT
IMON
ILIM
COUT
Common Bus
CdVdT
GND
RTN
R3
RILIM
SYSTEM LOAD
Hot-Swap
IN2: 4.2 V - 42 V
IN
OUT
CIN
R4
150 mꢀ
IN2
IN1
UVLO
FLT
TPS26400
OVP
SHDN
IMON
R5
R6
MODE
dVdT
ILIM
GND
RTN
RILIM
CdVdT
Figure 10-15. Active ORing Application Schematic
Figure 10-15 shows a typical redundant power supply configuration of the system. Schottky ORing diodes have
been popular for connecting parallel power supplies, such as parallel operation of wall adapter with a battery or a
hold-up storage capacitor. The disadvantage of using ORing diodes is high voltage drop and associated power
loss. The TPS26400 with integrated, N-channel back to back FETs provide a simple and efficient solution.
A fast reverse comparator controls the internal FET and it is turned ON or OFF with hysteresis as shown in
Figure 10-16. The internal FET is turned off within 1.5 μs (typical) as soon as V(IN) – V(OUT) falls below –110 mV.
It turns on within 40 μs (typical) once the differential forward voltage V(IN) – V(OUT) exceeds 100 mV. Figure 10-17
and Figure 10-18 show typical switch-over waveforms of Active ORing implementation using the TPS26400.
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Reverse Blocking
Forward Conduction
-10
100
VIN - V
mV
(
)
(
)
)
OUT
(
Figure 10-16. Active ORing Thresholds
VIN1 = 22 V
Cout = 47 μF
VIN2: Plugged In
at 24 V
Rload = 24 Ω
C(dVdT) = 22 nF
VIN1 = 22 V
Cout = 47 μF
VIN2: Plugged In
at 24 V
Rload = 24 Ω
C(dVdT) = 22 nF
Figure 10-17. Active ORing Between Two Supplies Figure 10-18. Active ORing Between Two Supplies
VOUT Change Over to VIN2 VOUT Change Over to VIN1
Note
All control pins of the un-powered TPS26400 device in the Active ORing configuration will measure
approximately 0.7 V drop with respect to GND. The system micro-controller should ignore IMON and
FLT pin voltage measurements of this device when these signals are being monitored.
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10.3.2 Field Supply Protection in PLC, DCS I/O Modules
TPS26400
24-V nominal (from field
SELV power supply)
To field loads (sensors &
Actuators
IN
OUT
Inrush Current
Control
Power FET isolation during over
voltage , Input Reverse Polarity and
short circuit faults
IMON
FLT
Load Current monitor & Fault
Diagnostics
SHDN
IMON
FLT
ON/OFF
Control
Fault
IMON
DC/DC
MCU
Field side
PLC side
Digital Isolator
Figure 10-19. Power Delivery Circuit Block Diagram in I/O Modules
The PLC or Distributed Control System (DCS) I/O modules are often connected to an external field power supply
to support higher power requirements of the field loads like sensors and actuators. Power-supply faults or
miswiring can damage the loads or cause the loads not to operate correctly. The TPS26400 can be used as a
front end protection circuit to protect and provide stable supply to the field loads. Under voltage, Over voltage
and reverse polarity protection features of the TPS26400 prevent the loads to experience voltages outside the
operating range, which can permanently damage the loads.
Field power supply is often connected to multiple I/O modules and is capable of delivering more current than a
single I/O module can handle. Overcurrent protection scheme of the TPS26400 limits the current from the power
supply to the module so that the maximum current does not rise above what the board is designed for. Fast short
circuit protection scheme isolates the faulty load from the field supply quickly and prevents the field supply to dip
and cause interrupts in the other I/O modules connected to the same field supply. High accurate (±5% at 1 A)
current limit facilitates more I/O modules to be connected to field supply. Load current monitor (IMON) and fault
indication (FLT) features facilitate continuous load monitoring.
The TPS26400 also acts as a smart diode with protection against reverse current during output side miswiring.
Reverse current can potentially damage the field power supply and cause the I/O modules to run hot or may
cause permanent damage.
If the field power supply is connected in reverse polarity (which is not unlikely as field power supplies are usually
connected with screw terminals), field loads can permanently get damaged due to the reverse voltage. The
reverse polarity protection feature of the TPS26400 prevents the reverse voltage to appear at the load side.
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10.3.3 Simple 24-V Power Supply Path Protection
With the TPS26400, a simple 24-V power supply path protection can be realized using a minimum of three
external components as shown in the schematic diagram in Figure 10-20. The external components required
are: a R(ILIM) resistor to program the current limit, C(IN) and C(OUT) capacitors.
System Load
IN
OUT
COUT
CIN
150 mꢀ
Input from a 24V
power supply
UVLO
OVP
FLT
TPS26400
SHDN
IMON
ILIM
MODE
RTN
dVdT
GND
RILIM
Figure 10-20. TPS2640 Configured for a Simple 24-V Supply Path Protection
Protection features with this configuration include:
•
•
•
•
•
•
Load and device protection from reverse input polarity fault down to –42V
15 V (typical) rising under voltage lock-out threshold
33 V (typical) rising overvoltage cut-off threshold
Inrush current control with 24-V/1.6-ms output voltage slew rate
Reverse Current Blocking
Accurate current limiting with Auto-Retry
10.4 Do's and Dont's
•
•
Do not connect RTN to GND. Connecting RTN to GND disables the Reverse Polarity protection feature
Connect the TPS26400 support components R(ILIM), C(dVdT), R(IMON), R(MODE) and UVLO, OVP resistors with
respect to RTN pin
•
Connect device PowerPAD to the RTN plane for an enhanced thermal performance
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11 Power Supply Recommendations
The TPS26400 eFuse is designed for the supply voltage range of 4.2 V ≤ VIN ≤ 42 V. If the input supply is
located more than a few inches from the device, an input ceramic bypass capacitor higher than 0.1 μF is
recommended. Power supply must be rated higher than the current limit set to avoid voltage droops during
overcurrent and short circuit conditions
11.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Abolsute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include
•
•
•
•
Minimizing lead length and inductance into and out of the device
Using large PCB GND plane
Schottky diode across the output to absorb negative spikes
A low value ceramic capacitor (C(IN) to approximately 0.1 μF) to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with Equation 24.
L IN
( )
Vspike Absolute = V IN + I Load
( ) )
´
(
)
(
C IN
( )
(24)
where
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
Some applications may require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Abolsute Maximum Ratings of the device. These transients can occur during positive and
negative surge tests on the supply lines. In such applications it is recommended to place atleast 1 μF of input
capacitor to limit the falling slew rate of the input voltage within a maximum of 15 V/μs.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 11-1.
IN
OUT
INPUT
OUTPUT
CIN
COUT
R4
R1
150 mꢀ
UVLO
FLT
*
*
TPS26400
OVP
SHDN
IMON
R2
MODE
dVdT
ILIM
GND
RTN
R3
RILIM
RIMON
CdVdT
A. Optional components needed for suppression of transients
Figure 11-1. Circuit Implementation With Optional Protection Components
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12 Layout
12.1 Layout Guidelines
•
For all the applications, a 0.1 μF or higher value ceramic decoupling capacitor is recommended between IN
terminal and GND.
•
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 12-1 and Figure 12-2 for PCB layout examples with HTSSOP and VQFN
packages respectively.
•
High current carrying power path connections must be as short as possible and must be sized to carry atleast
twice the full-load current.
•
•
RTN, which is the reference ground for the device must be a copper plane or island.
Locate all the TPS26400 support components R(ILIM), C(dVdT), R(IMON), and MODE, UVLO, OVP resistors
close to their connection pin. Connect the other end of the component to the RTN with shortest trace length.
The trace routing for the RILIM and R(IMON) components to the device must be as short as possible to reduce
parasitic effects on the current limit and current monitoring accuracy. These traces must not have any
coupling to switching signals on the board.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT and GND pins.
•
•
•
Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater
cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board RTN plane
directly under the device. Other planes, such as the bottom side of the circuit board can be used to increase
heat sinking in higher current applications. Designs that do not need reverse input polarity protection can
have RTN, GND and PowerPAD connected together. PowerPAD in these designs can be connected to the
PCB ground plane.
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12.2 Layout Example
Top Layer
Bottom layer GND plane
Top Layer RTN Plane
Bottom Layer RTN Plane
Via to Bottom Layer
Track in bottom layer
BOTTOM Layer GND Plane
Top Layer
Power GND Plane
High
Frequency
Bypass cap
OUT
IN
IN
OUT
FLT
VOUT PLANE
VIN PLANE
UVLO
N.C
N.C
PWP
OVP
dVdT
MODE
SHDN
RTN
ILIM
IMON
TOP Layer
RTN Plane
BOTTOM Layer RTN Plane
Figure 12-1. Typical PCB Layout Example With HTSSOP Package With a 2 Layer PCB
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Top Layer
Bottom layer GND plane
Top Layer RTN Plane
Bottom Layer RTN Plane
Via to Bottom Layer
Track in bottom layer
BOTTOM Layer GND Plane
Top Layer
Power GND Plane
High
Frequency
Bypass cap
IN
OUT
OUT
IN
VIN PLANE
VOUT PLANE
UVLO
N.C
FLT
N.C
dVdT
PWP
OVP
TOP Layer
RTN Plane
BOTTOM Layer RTN Plane
Figure 12-2. Typical PCB Layout Example With VQFN Package With a 2 Layer PCB
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13 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
13.1 Device Support
For TPS26400 PSpice Transient Mode, see SLVMDF4.
For TPS26400 Design Calculator, see SLVRBG7.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
•
•
TPS26400-02EVM: Evaluation Module for TPS26400 User's Guide
Power Multiplexing Using Load Switches and eFuses
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS26400PWPR
TPS26400RHFR
ACTIVE
ACTIVE
HTSSOP
VQFN
PWP
RHF
16
24
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
26400
NIPDAU
TPS
26400
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS26400PWPR
TPS26400RHFR
HTSSOP PWP
VQFN RHF
16
24
2000
3000
330.0
330.0
12.4
12.4
6.9
4.3
5.6
5.3
1.6
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS26400PWPR
TPS26400RHFR
HTSSOP
VQFN
PWP
RHF
16
24
2000
3000
350.0
367.0
350.0
367.0
43.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016H
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
6
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
PIN 1 INDEX
SEATING
PLANE
A
0.1 C
AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
0.30
16X
4.5
4.3
0.19
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
0.25
GAGE PLANE
1.2 MAX
2X 1.15 MAX
NOTE 5
0.15
0.05
0.75
0.50
8
9
0 -8
A
15
DETAIL A
TYPICAL
2X 0.3 MAX
NOTE 5
2.46
2.16
17
THERMAL
PAD
1
16
2.66
2.36
4223630/A 04/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016H
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.66)
METAL COVERED
BY SOLDER MASK
16X (1.5)
SYMM
1
16
(0.6) TYP
16X (0.45)
(R0.05) TYP
SYMM
(5)
NOTE 9
17
(1.2)
TYP
(2.46)
14X (0.65)
9
8
0.2) TYP
(
(1.2) TYP
VIA
SEE DETAILS
(5.8)
SOLDER MASK
DEFINED PAD
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
15.000
SOLDER MASK DETAILS
4223630/A 04/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016H
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.66)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
16X (1.5)
1
16
16X (0.45)
(R0.05) TYP
(2.46)
SYMM
17
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SEE TABLE FOR
SYMM
(5.8)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.97 X 2.75
2.66 X 2.46 (SHOWN)
2.43 X 2.25
0.125
0.15
0.175
2.25 X 2.08
4223630/A 04/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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