TPS26602PWPT [TI]
具有集成输入反极性保护功能的 4.2V 至 60V、150mΩ、0.1A 至 2.23A 电子保险丝
| PWP | 16 | -40 to 125;
| 型号： | TPS26602PWPT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成输入反极性保护功能的 4.2V 至 60V、150mΩ、0.1A 至 2.23A 电子保险丝 | PWP | 16 | -40 to 125 电子 PC 光电二极管 |
| 文件： | 总54页 (文件大小：4143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS2660
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
具有集成反向输入极性保护的 TPS2660x 60V 2A 工业电子保险丝
1 特性
3 说明
1
•
4.2V 至 60V 工作电压，绝对最大值为 62V
集成反向输入极性保护，低至 –60V
TPS2660x 器件是一系列功能丰富的紧凑型高电压电子
保险丝，具有一整套保护 功能）。4.2V 至 60V 的宽
电源输入范围可实现对众多常用直流总线电压的控制。
器件可以承受并保护由高达 ±60V 的正负电源供电的负
载。集成的背靠背 FET 提供反向电流阻断功能，因此
器件非常适合在电源故障和欠压条件下要求保持输出电
压的系统。该器件还具备许多可调功能，可提供负载、
电源和器件保护 功能 包括过流保护、输出转换率和过
压保护以及欠压保护。TPS2660x 内部可靠的保护控制
模块以及高耐压值有助于简化针对浪涌保护的系统设
计。
•
–
无需额外组件
•
•
总 RON 为 150mΩ 的集成背对背 MOSFET
0.1A 至 2.23A 可调节电流限制
（1A 时精确度为 ±5%）
•
•
提供功能安全
–
提供文档以帮助创建功能安全系统设计
使用最少的外部组件在浪涌期间提供负载保护 (IEC
61000-4-5)
•
•
•
•
•
•
IMON 电流指示器输出（精度为 ±8.5%）
低静态电流，工作时为 300µA，关断时为 20µA
可调节的 UVLO、OVP 切断、输出压摆率控制
反向电流阻断
借助关断引脚，可以从外部控制内部 FET 的启用/禁
用，还可以将器件置于低电流关断模式。为实现系统状
态监视和下游负载控制，器件提供故障和精密电流监视
输出。MODE 引脚有助于在三个限流故障响应（断路
器模式、闭锁模式和自动重试模式）之间灵活地对器件
进行配置。
38V 固定过压钳位（仅限 TPS26602）
采用易于使用的 16 引脚 HTSSOP 和 24 引脚
VQFN 封装
•
•
可选电流限制故障响应选项（自动重试、闭锁、断
路器模式）
器件采用 5mm × 4.4mm、16 引脚 HTSSOP 封装和
5mm x 4mm、24 引脚 VQFN 封装；额定温度范围为
–40°C 至 +125°C。
经 UL 2367 认证
–
–
文件编号169910
ILIM ≥ 5.36kΩ（最大电流为 2.35A）
R
器件信息(1)
•
UL60950 - 单点故障测试期间安全
开路/短路 ILIM 检测
器件型号
TPS26600
TPS26602
封装
封装尺寸（标称值）
–
HTSSOP (16)
5.00mm × 4.40mm
2 应用
TPS26600
TPS26601
TPS26602
VQFN (24)
5.00mm × 4.00mm
•
•
•
•
•
可编程逻辑控制器
分布式控制系统 (DCS)
控制和自动化
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
冗余电源 ORing
工业级浪涌保护
–60V 电源时的反向输入极性保护
简化电路原理图
VOUT
VIN: 4.2 V - 60 V
OUT
IN
CIN
COUT
150 mΩ
R1
RFLTb
UVLO
OVP
FLT
Health Monitor
TPS26600
R2
ON/OFF Control
SHDN
IMON
ILIM
dVdT
Load Monitor
MODE
RTN
R3
GND
RIMON
CdVdT
RILIM
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDG2
TPS2660
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
目录
9.4 Device Functional Modes........................................ 27
10 Application and Implementation........................ 28
10.1 Application Information.......................................... 28
10.2 Typical Application ............................................... 28
10.3 System Examples ................................................ 34
10.4 Do's and Don'ts..................................................... 37
11 Power Supply Recommendations ..................... 38
11.1 Transient Protection.............................................. 38
12 Layout................................................................... 39
12.1 Layout Guidelines ................................................. 39
12.2 Layout Example .................................................... 40
13 器件和文档支持 ..................................................... 42
13.1 器件支持................................................................ 42
13.2 文档支持................................................................ 42
13.3 接收文档更新通知 ................................................. 42
13.4 社区资源................................................................ 42
13.5 商标....................................................................... 42
13.6 静电放电警告......................................................... 42
13.7 Glossary................................................................ 42
14 机械、封装和可订购信息....................................... 42
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements................................................ 9
7.7 Typical Characteristics............................................ 10
Parameter Measurement Information ................ 16
Detailed Description ............................................ 17
9.1 Overview ................................................................. 17
9.2 Functional Block Diagram ....................................... 18
9.3 Feature Description................................................. 18
8
9
4 修订历史记录
Changes from Revision F (August 2019) to Revision G
Page
•
向特性 部分添加了提供功能安全的链接.................................................................................................................................. 1
Changes from Revision E (November 2017) to Revision F
Page
•
•
•
•
•
•
•
将工作电压从 55V 更改为 60V，将绝对最大值从 60V 更改为 62V（在特性 部分）.............................................................. 1
将说明 部分和简化原理图 中的输入范围从 55V 更改为 60V .................................................................................................. 1
Changed Input voltage MAX from 60 V to 62 V in the Absolute Maximum Ratings table .................................................... 6
Changed Input voltage MAX from 55 V to 60 V in the Recommended Operating Conditions table ..................................... 6
Changed Operating input voltage MAX from 55 V to 60 V in the Electrical Charateristics table........................................... 7
Added OVPMAX to the Overvoltage Protection section in the Electrical Characteristics table ............................................... 7
Changed voltage range from 55 V to 60 V in the Detailed Description, Application and Implementation and Power
Supply Recommendations sections ..................................................................................................................................... 17
Changes from Revision D (April 2017) to Revision E
Page
•
更新了故障响应 部分 .............................................................................................................................................................. 1
Changes from Revision C (March 2017) to Revision D
Page
•
Updated Pin Functions table ................................................................................................................................................. 4
Changes from Revision B (Feb 2017) to Revision C
Page
•
更新了特性 部分中的 UL 认证 ................................................................................................................................................ 1
2
版权 © 2016–2019, Texas Instruments Incorporated
TPS2660
www.ti.com.cn
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
Changes from Revision A (Aug 2016) to Revision B
Page
•
•
•
•
•
•
•
添加了 RHF 封装 .................................................................................................................................................................... 1
Changed "Reverse input supply current" from "52" to "66" in the Electrical Characteristics table......................................... 7
Changed "UVLO threshold voltage, falling" from "1.095" to "1.08" in the Electrical Characteristics table............................. 7
Changed "Over-voltage threshold voltage, rising" from "1.175" to "1.17" in the Electrical Characteristics table................... 7
Changed "Over-voltage threshold voltage, falling" from "1.095" to "1.085" in the Electrical Characteristics table................ 7
Changed "Ilkg(OUT)" from "35" to "50" in the Electrical Characteristics table............................................................................ 8
Changed FLT input leakage current from "–100" to "–200" (MIN) and "100" to "200" (MAX) in the Electrical
Characteristics table ............................................................................................................................................................... 8
Changes from Original (July 2016) to Revision A
Page
•
将器件状态从产品预发布 更改为生产数据.............................................................................................................................. 1
Copyright © 2016–2019, Texas Instruments Incorporated
3
TPS2660
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
5 Device Comparison Table
Part Number
TPS26600
TPS26601
TPS26602
Overvoltage Protection
Over Load Fault Response with MODE = Open
Overvoltage cut-off, adjustable
Overvoltage cut-off, adjustable
Overvoltage clamp, fixed (38 V)
Circuit breaker with auto-retry
Circuit breaker with latch
Circuit breaker with auto-retry
6 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
RHF Package
24-Pin VQFN
Top View
OUT
OUT
FLT
16
IN
IN
1
2
3
4
15
14
13
1
2
3
4
5
6
7
19
18
17
N.C
N.C
N.C
N.C
N.C
ILIM
UVLO
NC
IMON
NC
PowerPAD™
Integrated Circuit
Package
GND
12
11
dVdT
ILIM
OVP
5
6
PowerPadTM
16
15
N.C
MODE
RTN
7
8
10
9
IMON
GND
SHDN
RTN
N.C
N.C
14
13
SHDN
MODE
Pin Functions
PIN
TPS26600/1/2
TYPE
DESCRIPTION
NAME
HTSSOP
VQFN
A capacitor from this pin to RTN sets output voltage slew rate See the Hot Plug-
In and In-Rush Current Control section
dVdT
12
20
I/O
FLT
14
9
22
17
O
Fault event indicator. It is an open drain output. If unused, leave floating
Connect GND to system ground
GND
—
A resistor from this pin to RTN sets the overload and short-circuit current limit.
See the Overload and Short Circuit Protection section
ILIM
11
19
I/O
Analog current monitor output. This pin sources a scaled down ratio of current
through the internal FET. A resistor from this pin to RTN converts current to
proportional voltage. If unused, leave it floating
IMON
10
18
O
1
2
8
9
IN
Power
I
Power input and supply voltage of the device
Mode selection pin for over load fault response. See the Device Functional
Modes section
MODE
6
4
13
1-7
11
16
21
N.C
—
No connect
13
4
Copyright © 2016–2019, Texas Instruments Incorporated
TPS2660
www.ti.com.cn
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
Pin Functions (continued)
PIN
TPS26600/1/2
TYPE
DESCRIPTION
NAME
HTSSOP
VQFN
23
15
16
OUT
Power
I
Power output of the device
24
Input for setting the programmable overvoltage protection threshold (For
TPS26600/1 only). An overvoltage event turns off the internal FET and asserts
FLT to indicate the overvoltage fault. Connect OVP pin to RTN pin externally to
select the internal default threshold. For overvoltage clamp response
(TPS26602 Only) connect OVP to RTN externally
OVP
5
12
PowerPad must be connected to RTN plane on PCB using multiple vias for
enhanced thermal performance. Do not use PowerPad as the only electrical
connection to RTN
PowerPadTM
RTN
—
8
—
15
14
—
—
I
Reference for device internal control circuits
Shutdown pin. Pulling SHDN low makes the device to enter into low power
shutdown mode. Cycling SHDN pin voltage resets the device that has latched
off due to a fault condition
SHDN
7
Input for setting the programmable undervoltage lockout threshold. An
undervoltage event turns off the internal FET and asserts FLT to indicate the
power-failure. Connect UVLO pin to RTN pin to select the internal default
threshold
UVLO
3
10
I
Copyright © 2016–2019, Texas Instruments Incorporated
5
TPS2660
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (all voltages referred to GND (unless otherwise noted))(1)
MIN
MAX
62
UNIT
V
IN , IN-OUT
–60
–70
–0.3
–0.3
–60
IN , IN-OUT (10 ms transient), TA = 25°C
[IN, OUT, FLT, UVLO, SHDN] to RTN
[OVP, dVdT, ILIM, IMON, MODE] to RTN
RTN
70
V
Input voltage
62
V
5
V
0.3
10
V
IFLT, IdVdT, ISHDN
Sink current
mA
IdVdT, IILIM, IIMON
Source current
Internally limited
Operating junction temperature
Transient junction temperature
Storage temperature
–40
–65
–65
150
T(TSD)
150
°C
°C
°C
TJ
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (all voltages referred to GND (unless otherwise noted))
MIN
–55
0
NOM
MAX
60
UNIT
IN
UVLO, OUT, FLT
Input voltage
60
V
OVP, dVdT, ILIM, IMON, SHDN
0
4
ILIM
5.36
1
120
Resistance
kΩ
IMON
IN, OUT
dVdT
–dV(IN)/dt
TJ
0.1
10
µF
nF
External capacitance
V(IN) falling slew rate
20
V/µs
°C
Operating junction temperature
–40
25
125
7.4 Thermal Information
TPS2660
THERMAL METRIC(1)
PWP (HTSSOP)
RHF (VQFN)
UNIT
16 PINS
38.6
22.7
18.2
0.5
24 PINS
30.2
20.8
7.6
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
18
7.6
RθJC(bot)
1.5
1.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2016–2019, Texas Instruments Incorporated
TPS2660
www.ti.com.cn
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
7.5 Electrical Characteristics
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
V(IN)
Operating input voltage
4.2
3.9
250
190
11
60
4.1
300
390
33
V
V
V(PORR)
Internal POR threshold, rising
Internal POR hysteresis
4
275
300
20
V(PORHys)
IQ(ON)
mV
µA
µA
µA
V
Enabled: V(SHDN) = 2 V
Supply current
IQ(OFF)
V(SHDN) = 0 V
I(VINR)
Reverse input supply current
Overvoltage clamp
V(IN) = –60 V, V(OUT) = 0 V
V(IN) > 42 V, TPS26602 only
66
V(OVC)
36
37.5
40
UNDERVOLTAGE LOCKOUT (UVLO) INPUT
V(IN) rising, V(UVLO) = 0 V
V(IN) falling, V(UVLO) = 0 V
14.25
13.25
180
14.9 15.75
13.8 14.75
Factory set V(IN) undervoltage
trip level
V(IN_UVLO)
V
V(SEL_UVLO)
V(UVLOR)
V(UVLOF)
I(UVLO)
Internal UVLO select threshold
UVLO threshold voltage, rising
UVLO threshold voltage, falling
UVLO input leakage current
200
240
mV
V
1.175
1.08
1.19 1.225
1.1 1.125
V
0 V ≤ V(UVLO) ≤ 60 V
–100
0
100
nA
LOW IQ SHUTDOWN (SHDN) INPUT
V(SHDN)
V(SHUTF)
I(SHDN)
Output voltage
I(SHDN) = 0.1 µA
2
0.55
–10
2.7
3.4
V
V
SHDN threshold voltage for
low IQ shutdown, falling
0.76
0.94
Leakage current
V(SHDN) = 0.4 V
µA
OVERVOLTAGE PROTECTION (OVP) INPUT
V(IN) rising, V(OVP) = 0 V
V(IN) falling, V(OVP) = 0 V
31
28.5
180
32.6
30.3
200
34
31.5
240
Factory set V(IN) overvoltage
trip level
V(IN_OVP)
V
V(SEL_OVP)
V(OVPR)
Internal OVP select threshold
mV
V
Overvoltage threshold voltage,
rising
1.17
1.19 1.225
1.1 1.125
V(OVPF)
I(OVP)
Overvoltage threshold, falling
OVP input leakage current
1.085
–100
V
nA
V
0 V ≤ V(OVP) ≤ 4 V
0
100
55
OVPMAX
Maximum external OVP setting TPS26600, TPS26601 only
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)
dVdT charging current
V(dVdT) = 0 V
4
4.7
14
5.5
µA
Ω
V(SHDN) = 0 V, with I(dVdT) = 10 mA
sinking
R(dVdT)
dVdT discharging resistance
dVdT to OUT gain
GAIN(dVdT)
V(OUT)/V(dVdT)
23.75
24.6
25.5
V/V
CURRENT LIMIT PROGRAMMING (ILIM)
V(ILIM) ILIM bias voltage
1
V
R(ILIM) = 120 kΩ, V(IN) – V(OUT) = 1 V
R(ILIM) = 12 kΩ, V(IN) – V(OUT) = 1 V
R(ILIM) = 8 kΩ, V(IN) – V(OUT) = 1 V
R(ILIM) = 5.36 kΩ, V(IN) – V(OUT) = 1 V
0.085
0.95
0.1 0.115
1.05
1.5 1.575
1
I(OL)
1.425
2.11
2.23
2.35
Overload current limit
A
R(ILIM) = OPEN, open resistor current
limit (single point failure test:
UL60950)
I(OL_R-OPEN)
0.055
0.095
R(ILIM) = SHORT, shorted resistor
current limit (single point failure test:
UL60950)
I(OL_R-SHORT)
R(ILIM) = 120 kΩ, MODE = open
R(ILIM) = 5.36 kΩ, MODE = open
0.045 0.073
2.21
0.11
2.4
Circuit breaker detection
threshold
I(CB)
A
2
Copyright © 2016–2019, Texas Instruments Incorporated
7
TPS2660
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
0.08
TYP
MAX
UNIT
R(ILIM) = 120 kΩ, V(IN) – V(OUT) = 5 V
R(ILIM) = 8 kΩ, V(IN) – V(OUT) = 5 V
R(ILIM) = 5.36 kΩ, V(IN) – V(OUT) = 5 V
0.1
0.12
I(SCL)
Short-circuit current limit
1.425
2.11
1.5 1.575
A
2.23
1.87 ×
I(OL)
0.015
2.35
I(FASTRIP)
Fast-trip comparator threshold
+
A
CURRENT MONITOR OUTPUT (IMON)
GAIN(IMON)
Gain factor I(IMON):I(OUT)
0.1 A ≤ I(OUT) ≤ 2 A
72 78.28
85
µA/A
PASS FET OUTPUT (OUT)
0.1 A ≤ I(OUT) ≤ 2 A, TJ = 25°C
0.1 A ≤ I(OUT) ≤ 2 A, TJ = 85°C
140
150
150
160
210
RON
IN to OUT total ON resistance
mΩ
0.1 A ≤ I(OUT) ≤ 2 A, –40°C ≤ TJ ≤
+125°C
80
250
12
V(IN) = 60 V, V(SHDN)= 0 V, V(OUT) = 0
V, sourcing
OUT leakage current in Off
state
V(IN) = 0 V, V(SHDN)= 0 V, V(OUT) = 24
V, sinking
Ilkg(OUT)
11
µA
V(IN) = –60 V, V(SHDN)= 0 V, V(OUT)
0 V, sinking
=
50
V(IN) – V(OUT) threshold for
reverse protection comparator,
falling
V(REVTH)
–15
85
–10
96
–5
mV
mV
V(IN) – V(OUT) threshold for
reverse protection comparator,
rising
V(FWDTH)
110
FAULT FLAG (FLT): ACTIVE LOW
R(FLT)
FLT pull-down resistance
V(OVP) = 2 V, I(FLT) = 5 mA sinking
40
85
160
200
Ω
I(FLT)
FLT input leakage current
0 V ≤ V(FLT) ≤ 60 V
–200
nA
THERMAL SHUT DOWN (TSD)
T(TSD)
TSD threshold, rising
TSD hysteresis
157
10
ºC
ºC
T(TSDhyst)
MODE
Current limiting with
latch
MODE = 402 kΩ to RTN
MODE = Open
Circuit breaker mode
with auto-retry
MODE_SEL
Thermal fault mode selection
Circuit breaker mode
with latch
MODE = Open (TPS26601 only)
MODE = Short to RTN
Current limiting with
auto-retry
8
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7.6 Timing Requirements
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
MIN
NOM
MAX
UNIT
IN AND UVLO INPUT
UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV,
C(dvdt) = open
250
µs
UVLO_tON(dly) UVLO turnon delay
250 +
14.5 ×
C(dvdt)
UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV,
µs
µs
C(dvdt) ≥ 10 nF, [C(dvdt) in nF]
UVLO_toff(dly)
UVLO turnoff delay
UVLO↓ (100 mV below V(UVLOF)) to FLT↓
10
SHUTDOWN CONTROL INPUT (SHDN)
250 +
14.5 ×
C(dvdt)
SHDN↑ to V(OUT) = 100 mV, C(dvdt) ≥ 10 nF, [C(dvdt) in nF]
µs
SHUTDOWN exit delay
tSD(dly)
SHDN↑ to V(OUT) = 100 mV, C(dvdt) = open
SHDN↓ (below V(SHUTF)) to FLT↓
250
µs
µs
SHUTDOWN entry
delay
10
OVER VOLTAGE PROTECTION INPUT (OVP)
OVP↓ (20 mV below V(OVPF)) to V(OUT) = 100 mV,
TPS26600 & TPS26601 only
OVP exit delay
200
6
µs
µs
tOVP(dly)
OVP↑ (20 mV above V(OVPR)) to FLT↓, TPS26600 and
TPS26601 only
OVP disable delay
CURRENT LIMIT
Fast-trip comparator
delay
tFASTTRIP(dly)
I(OUT) > I(FASTRIP)
250
ns
µs
REVERSE PROTECTION COMPARATOR
(V(IN) – V(OUT))↓ (100 mV overdrive below V(REVTH)) to
internal FET turn OFF
1.5
45
70
tREV(dly)
Reverse protection
comparator delay
(V(IN) – V(OUT))↓ (10 mV overdrive below V(REVTH)) to
FLT↓
(V(IN) – V(OUT))↑ (10 mV overdrive above V(FWDTH)) to
FLT↑
tFWD(dly)
THERMAL SHUTDOWN
tretry
Retry delay in TSD
512
ms
ms
OUTPUT RAMP CONTROL (dVdT)
SHDN↑ to V(OUT) = 23.9 V, with C(dVdT) = 47 nF
SHDN↑ to V(OUT) = 23.9 V, with C(dVdT) = open
10
tdVdT
Output ramp time
1.6
FAULT FLAG (FLT)
FLT assertion delay in
circuit breaker mode
tCB(dly)
MODE = OPEN, delay from I(OUT) > I(OL) to FLT↓
4
ms
ms
Retry delay in circuit
breaker mode
tCBretry(dly
tPGOODF
)
MODE = OPEN
540
Falling edge
875
Rising edge, C(dVdT) = open
1400
PGOOD delay (de-
glitch) time
µs
875 +
20 ×
tPGOODR
Rising egde, C(dVdT) ≥ 10 nF, [C(dvdt) in nF]
C(dVdT)
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7.7 Typical Characteristics
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless stated otherwise)
300
250
200
150
100
50
1.24
1.22
1.2
ILOAD = 2 A
ILOAD = 1 A
ILOAD = 0.1 A
V(UVLOR) (V)
V(UVLOF) (V)
1.18
1.16
1.14
1.12
1.1
0
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D001
D002
Figure 2. UVLO Threshold Voltage vs Temperature
Figure 1. On-Resistance vs Temperature Across Load
Current
1.26
-8
V(OVPR) (V)
V(OVPF) (V)
1.23
V(REVTH) (mV)
-8.5
-9
-9.5
-10
1.2
1.17
1.14
1.11
1.08
-10.5
-11
-11.5
-12
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D003
D006
Figure 3. OVP Threshold Voltage vs Temperature
Figure 4. Reverse Voltage Threshold vs Temperature
100
34
V(FWDTH) (V)
V(IN_OVP) (V)
V(IN_OVP) (V)
99
98
97
96
95
94
93
92
91
90
33.5
33
32.5
32
31.5
31
30.5
30
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC
100
150
D007
D008
Figure 5. V(FWDTH) vs Temperature
Figure 6. Internal OVP Threshold vs Temperature
10
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Typical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless stated otherwise)
15.2
40
39
38
37
36
V(UVLOR) (V)
V(UVLOF) (V)
V(OVC) (V)
15
14.8
14.6
14.4
14.2
14
13.8
13.6
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D009
D010
Figure 7. Internal UVLO Threshold vs Temperature
Figure 8. Overvoltage Clamp Threshold vs Temperature
40
4
TA = 125èC
TA = 85èC
TA = 25èC
TA = -40èC
35
30
25
20
15
10
5
3.95
3.9
3.85
3.8
V(PORR) (V)
V(PORF) (V)
3.75
3.7
3.65
3.6
0
0
10
20
30
Supply Voltage (V)
40
50
60
-50
0
50
Temperature (èC)
100
150
D013
D012
Figure 10. Input Supply Current vs Supply Voltage in
Shutdown
Figure 9. Internal POR Threshold Voltage vs Temperature
450
400
350
300
250
200
0
-5
-10
-15
-20
-25
150
-30
TA = 125èC
TA = 125èC
100
-35
TA = 85èC
TA = 85èC
TA = 25èC
TA = -40èC
TA = 25èC
TA = -40èC
50
-40
0
-45
0
5
10 15 20 25 30 35 40 45 50 55 60
Supply Voltage (V)
-60
-50
-40
-30
Reverse Supply Voltage (V)
-20
-10
0
D014
D015
V(OUT) = 0 V
Figure 11. Input Supply Current vs Supply Voltage During
Normal Operation
Figure 12. Input Supply Current vs Reverse Supply
Voltage, – V(IN)
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Typical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless stated otherwise)
10
9
8
7
6
5
4
3
2
1
0
0
OVP Disable Delay (ms)
-5
-10
-15
-20
-25
TA = 125èC
TA = 85èC
TA = 25èC
TA = -40èC
-50
0
50
Temperature (èC)
100
150
-60
-50
-40
-30
-20
Reverse Supply Voltage (V)
-10
0
D017
D016
V(OUT) = 0 V
Figure 14. OVP Disable Delay vs Temperature
Figure 13. Output Current vs Reverse Supply Voltage, – V(IN)
20
0.82
0.8
tSD(dly)
V(SHUTF) (V)
18
16
14
12
10
8
0.78
0.76
0.74
0.72
0.7
6
0.68
0.66
0.64
4
2
0
-50
0
50
Temperature (èC)
100
150
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D018
D019
Figure 15. Shutdown Entry Delay vs Temperature
Figure 16. Shutdown Threshold Voltage Shutdown vs
Temperature
200
79.8
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
GAIN(IMON) (mA/A)
79.6
100
70
79.4
79.2
79
50
30
20
78.8
78.6
78.4
78.2
78
10
7
5
3
2
77.8
1
0.01 0.02
77.6
0.05 0.1 0.2 0.3 0.5
Output Current (A)
1
2
3 4 567 10
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D025
D020
Figure 17. Current Monitor Output vs Output Current
Figure 18. GAIN(IMON) vs Temperature
12
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Typical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless stated otherwise)
1%
0.8%
0.6%
0.4%
0.2%
0
1%
0
R(ILIM)= 24 kW
R(ILIM)= 12 kW
R(ILIM)= 8 kW
R(ILIM) = 120 kW
R(ILIM) = 80 kW
R(ILIM)= 5.36 kW
-1%
-2%
-3%
-4%
-5%
-6%
-0.2%
-0.4%
-0.6%
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D021
D024
Figure 19. Current Limit (% Normalized) vs Temperature
Figure 20. Current Limit (% Normalized) vs Temperature
3.2
0.11
R(ILIM) = 120 kW
R(ILIM) = 80 kW
R(ILIM) = 24 kW
R(ILIM) = 12 kW
R(ILIM) = 8 kW
R(ILIM) = 5.36 kW
R(ILIM) = Open
R(ILIM) = Short
2.8
2.4
2
0.1
0.09
0.08
0.07
0.06
0.05
0.04
1.6
1.2
0.8
0.4
0
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D004
D005
Figure 21. Over Load Current Limit vs Temperature
Figure 22. Current Limit for R(ILIM) = Open and Short vs
Temperature
60
16
14
12
10
8
50
40
30
20
10
0
6
4
0
0.5
1 1.5
Circuit Breaker Threshold (A)
2
2.5
0
0.5
1 1.5
Current Limit (A)
2
2.5
D026
D027
Figure 23. Circuit Breaker Threshold Accuracy vs Circuit
Breaker Threshold I(CB)
Figure 24. Current Limit Accuracy vs Current Limit, I(OL)
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Typical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless stated otherwise)
10.4
10.2
10
100000
10000
1000
100
UVLO_toff(dly)
TA = -40èC
TA = 25èC
TA = 85èC
TA = 105èC
TA = 125èC
9.8
9.6
9.4
9.2
9
10
1
0.2
-60 -40 -20
0
20
40
60
80 100 120 140
1
10
Power_Dissipation (W)
100
Temperature (èC)
D022
D023
Taken on 2-Layer board, 2 oz.(0.08-mm thick) with HTSSOP
device with RTN plane area: 1 cm2 (Top) and 4.6 cm2 (Bottom)
Figure 25. UVLO Turnoff Delay vs Temperature
Figure 26. Thermal Shutdown Time vs Power Dissipation
V_IN
V_OUT
FLTb
I_IN
RILIM = 5.36
OVP
RFLTb = 100 kΩ
RLOAD = 24 Ω
kΩ
Connected
to RTN
RILIM = 5.36 kΩ
RFLTb = 100 kΩ
RLOAD = 24 Ω
Figure 28. OV Clamp Response (TPS26602 Only)
Figure 27. OVP Overvoltage Cut-Off Response
RILIM = 5.36 kΩ
RFLTb = 100 kΩ
RILIM = 5.36 kΩ
Figure 29. Hot-Short: Fast Trip Response and Current
Regulation
Figure 30. Hot-Short: Fast Trip Response (Zoomed)
14
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Typical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless stated otherwise)
RILIM = 5.36 kΩ
RFLTb = 100 kΩ
RLOAD = 24 Ω
RILIM = 5.36 kΩ
RFLTb = 100 kΩ
RLOAD = 24 Ω
Figure 31. Turnon Control With SHDN
Figure 32. Turnoff Control With SHDN
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8 Parameter Measurement Information
V(OUT)
VUVLO
V(UVLOF)-0.1 V
0.1 V
VUVLO
FLT
V(UVLOR)+0.1V
10%
time
0
time
0
UVLO_tON(dly)
UVLO_toff(dly)
-20 mV
110 mV
V(IN) -V(OUT)
V(IN) -V(OUT)
90%
FLT
FLT
10%
0
time
tREV(dly)
0
time
tFWD(dly)
I(FASTRIP)
V(OVPR)+0.1V
V(OVP)
I(SCL)
I(OUT)
FLT
10%
0
time
0
time
tOVP(dly)
tFASTRIP(dly)
Figure 33. Timing Waveforms
16
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9 Detailed Description
9.1 Overview
The TPS2660x is a family of high voltage industrial eFuses with integrated back-to-back MOSFETs and
enhanced built-in protection circuitry. It provides robust protection for all systems and applications powered from
4.2 V to 60 V. The device can withstand ±60 V positive and negative supply voltages without damage. For hot-
pluggable boards, the device provides hot-swap power management with in-rush current control and
programmable output voltage slew rate features. Load, source and device protections are provided with many
programmable features including overcurrent, overvoltage, undervoltage. The precision overcurrent limit (±5% at
1 A) helps to minimize over design of the input power supply, while the fast response short circuit protection 250
ns (typical) immediately isolates the faulty load from the input supply when a short circuit is detected.
The internal robust protection control blocks of the TPS2660x along with its ±60 V rating helps to simplify the
system designs for the surge compliance ensuring complete protection of the load and the device.
The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault
signal for the downstream system. The TPS2660x monitor functions threshold accuracy of ±3% ensures tight
supervision of the supply bus, eliminating the need for a separate supply voltage supervisor chip.
The device monitors V(IN) and V(OUT) to provide true reverse current blocking when a reverse condition or input
power failure condition is detected. The TPS2660x is also designed to control redundant power supply systems.
A pair of TPS2660x devices can be configured for Active ORing between the main power supply and the
auxiliary power supply, (see the System Examples section).
Additional features of the TPS2660x include:
•
•
•
•
•
•
Current monitor output for health monitoring of the system
Electronic circuit breaker operation with overload timeout using MODE pin
A choice of latch off or automatic restart mode response during current limit fault using MODE pin
Over temperature protection to safely shutdown in the event of an overcurrent event
De-glitched fault reporting for brown-out and overvoltage faults
Look ahead overload current fault indication (see the Look Ahead Overload Current Fault Indicator section)
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9.2 Functional Block Diagram
OUT
IN
150mΩ
-10mV
+
PORb
Charge
Pump
+100mV
4V
3.72V
Current
Sense
X78.2µ
CP
+
UVLOb
1.19V
REVERSE
1.1V
VSEL_UVLO
SWEN
+
Gate Control Logic
IMON
UVLO
Current Limit Amp
Fast-Trip Comp
(Threshold=1.8xIOL
TSD
Thermal
Shutdown
+
OVP
1.19V
)
1.1V
1V
OLR
SHDNb
Over Voltage clamp detect
(TPS26602 Only)
VSEL_OVP
+
ILIM
OVP
Short detect
Ramp Control
24.6x
SWEN
FLT
Avdd
I(LOAD) ≥ I(CB)
* Only for Latch Mode
OLR
4msec
timer
SET
Timeout
85Ω
5uA
S
Q
dVdT
UVLOb
CLR
R
Q
1.4 msec
875 µs
14Ω
PORb
TSD
PORb
Fault Latch
Avdd
RTN
SHDNb
Gate Enhanced (tPGOOD
)
OLR
400kΩ
Avdd
Overload fault response
select detection
Reverse Input Polarity
Protection circuit
0.76V
GND
SHDNb
+
RTN
TPS2660x
MODE
SHDN
9.3 Feature Description
9.3.1 Undervoltage Lockout (UVLO)
Undervoltage comparator input. When the voltage at UVLO pin falls below V(UVLOF) during input power fail or
input undervoltage fault, the internal FET quickly turns off and FLT is asserted. The UVLO comparator has a
hysteresis of 90 mV. To set the input UVLO threshold, connect a resistor divider network from IN supply to UVLO
terminal to RTN as shown in Figure 34.
18
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Feature Description (continued)
V(IN)
IN
TPS26600/1
R1
UVLO
+
+
UVLOb
OVP
1.19 V
1.1 V
R2
OVP
RTN
1.19 V
1.1 V
R3
GND
Figure 34. UVLO and OVP Thresholds Set by R1, R2 and R3
The TPS2660x also features a factory set 15-V input supply undervoltage lockout V(IN_UVLO) threshold with 1 V
hysteresis. This feature can be enabled by connecting the UVLO terminal directly to the RTN terminal. If the
Under-Voltage Lock-Out function is not needed, the UVLO terminal must be connected to the IN terminal. UVLO
terminal must not be left floating.
The device also implements an internal power ON reset (POR) function on the IN terminal. The device disables
the internal circuitry when the IN terminal voltage falls below internal POR threshold V(PORF). The internal POR
threshold has a hysteresis of 275 mV.
9.3.2 Overvoltage Protection (OVP)
The TPS2660x incorporate circuitry to protect the system during overvoltage conditions. The TPS26600 and
TPS26601 feature overvoltage cut off functionality. A voltage more than V(OVPR) on OVP pin turns off the internal
FET and protects the downstream load. To program the OVP threshold externally, connect a resistor divider from
IN supply to OVP terminal to RTN as shown in Figure 34. The TPS26600 and TPS26601 also feature a factory
set 33-V Input overvoltage cut off V(IN_OVP) threshold with a 2-V hysteresis. This feature can be enabled by
connecting the OVP terminal directly to the RTN terminal. Figure 27 illustrates the overvoltage cut-off
functionality.
The TPS26602 features an internally fixed 38 V overvoltage clamp (VOVC) functionality. The OVP terminal of the
TPS26602 must be connected to the RTN terminal directly. The TPS26602 clamps the output voltage to VOVC
,
when the input voltage exceeds 38 V. During the output voltage clamp operation, the power dissipation in the
internal MOSFET is PD = (VIN – VOVC) × IOUT. Excess power dissipation for prolonged period can make the
device to enter into thermal shutdown. Figure 28 illustrates the overvoltage clamp functionality.
9.3.3 Reverse Input Supply Protection
To protect the electronic systems from reverse input supply due to miswiring, often a power component like a
schottky diode is added in series with the supply line as shown in Figure 35. These additional discretes result in
a lossy and bulky protection solution. The TPS2660x devices feature fully integrated reverse input supply
protection and does not need an additional diode. These devices can withstand –60 V reverse voltage without
damage. Figure 36 illustrates the reverse input polarity protection functionality.
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Feature Description (continued)
INPUT
OUTPUT
INPUT
OUTPUT
TPS2660x
eFuse
Hot-Swap Controller
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 35. Reverse Input Supply Protection Circuits - Discrete vs TPS2660x
Figure 36. Reverse Input Supply Protection at –60 V
9.3.4 Hot Plug-In and In-Rush Current Control
The devices are designed to control the in-rush current upon insertion of a card into a live backplane or other
"hot" power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets
of the system power. The controlled start-up also helps to eliminate conductive and radiative interferences. An
external capacitor connected from the dVdT pin to RTN defines the slew rate of the output voltage at power-on
as shown in Figure 37 and Figure 38.
TPS2660x
4 V
5 µA
dVdT
14 Ω
SWENb
C(dVdT)
RTN
GND
Figure 37. Output Ramp Up Time tdVdT is Set by C(dVdT)
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Feature Description (continued)
The dVdT pin can be left floating to obtain a predetermined slew rate (tdVdT) on the output. When the terminal is
left floating, the devices set an internal output voltage ramp rate of 23.9 V/1.6 ms. A capacitor can be connected
from dVdT pin to RTN to program the output voltage slew rate slower than 23.9 V/1.6 ms. Use Equation 1 and
Equation 2 to calculate the external C(dVdT) capacitance.
Equation 1 governs slew rate at start-up.
æ
ç
ö
÷
C dVdT
dV
OUT
æ
ö
÷
÷
ø
(
)
(
)
I(dVdT)
=
´ ç
ç
ç
è
÷
ø
Gain dVdT
dt
(
)
è
where
•
I(dVdT) = 4.7 µA (typical)
dV
(
dt
OUT
)
•
•
Gain(dVdT) = dVdT to VOUT gain = 24.6
(1)
(2)
The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using Equation 2.
tdVdT = 8 × 103 × V(IN) × C(dVdT)
VIN
CdVdT = 22 nF
Figure 38. Hot Plug-In and In-Rush Current Control at 24-V Input
9.3.5 Overload and Short Circuit Protection
COUT = 47 µF
RILIM = 5.36 kΩ
The device monitors the load current by sensing the voltage across the internal sense resistor. The FET current
is monitored during start-up and normal operation.
9.3.5.1 Overload Protection
The device offers following choices for the overload protection fault response:
•
•
Active current limiting (Auto-retry/Latch-off modes)
Electronic Circuit Breaker with overload timeout (Auto-retry/Latch-off modes)
See the configurations in Table 1 to select a specific overload fault response.
Table 1. Overload Fault Response Configuration Table
MODE Pin Configuration
Overload Protection Type
Device
TPS26600, TPS26602
TPS26601
Electronic circuit breaker with auto-retry
Electronic circuit breaker with latch-off
Open
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Feature Description (continued)
Table 1. Overload Fault Response Configuration Table (continued)
MODE Pin Configuration
Overload Protection Type
Device
TPS26600, TPS26601,
TPS26602
Shorted to RTN
Active current limiting with auto-retry
A 402-kΩ resistor across MODE
TPS26600, TPS26601,
TPS26602
Active current limiting with latch-off
pin to RTN pin
9.3.5.1.1 Active Current Limiting
When the active current limiting mode is selected, during overload events, the device continuously regulates the
load current to the overcurrent limit I(OL) programmed by the R(ILIM) resistor as shown in Equation 3.
12
IOL
=
R(ILIM
)
where
•
•
I(OL) is the overload current limit in Ampere
R(ILIM) is the current limit resistor in kΩ
(3)
During an overload condition, the internal current-limit amplifier regulates the output current to I(LIM). The FLT
signal assert after a delay of 875 µs.The output voltage droops during the current regulation, resulting in
increased power dissipation in the device. If the device junction temperature reaches the thermal shutdown
threshold (T(TSD)), the internal FET is turn off. The device configured in latch-off mode stays latched off until it is
reset by either of the following conditions:
•
•
Cycling V(IN) below V(PORF)
Toggling SHDN
Whereas the device configured in auto-retry mode, commences an auto-retry cycle 512 ms after TJ < [T(TSD)
–
10°C]. The FLT signal remains asserted until the fault condition is removed and the device resumes normal
operation. Figure 39 and Figure 40 illustrates behavior of the system during current limiting with auto-retry
functionality.
IMON
V_OUT
FLTb
I_IN
Load transition from 22 Ω to
12 Ω
MODE pin connected to RTN
RILIM = 5.36 kΩ
RILIM = 8 kΩ
Figure 40. Response During Coming Out of Overload Fault
Figure 39. Auto-Retry MODE Fault Behavior
9.3.5.1.2 Electronic Circuit Breaker with Overload Timeout, MODE = OPEN
In this mode, during overload events, the device allows the overload current to flow through the device until
I(LOAD) < I(FASTRIP). The circuit breaker threshold I(CB) can be programmed using the R(ILIM) resistor as shown in
Equation 4.
22
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12
I(CB) =
+ 0.03A
R(ILIM
)
where
•
•
I(CB) is circuit breaker current threshold in Ampere
R(ILIM) is the current limit resistor in kΩ
(4)
An internal timer starts when I(CB) < ILOAD < IFASTRIP, and when the timer exceeds tCB(dly), the device turns OFF the
internal FET and FLT is asserted. Once the internal FET is turned off, the device configured in latch-off mode
stays latched off, until it is reset by either of the following conditions:
•
•
Cycling V(IN) falling below V(PORF)
Toggling SHDN
whereas the device configured in auto-retry mode, commences an auto-retry cycle after 540 ms. The FLT signal
remains asserted until the fault condition is removed and the device resumes normal operation. Figure 41 and
Figure 42 illustrate behavior of the system during electronic circuit breaker with auto-retry functionality.
IMON
V_OUT
FLTb
I_IN
MODE left floating
Load Transition from 22 Ω to 12 Ω
Load Transition from 22 Ω to 12 Ω , RILIM = 8 kΩ
RILIM = 8 kΩ
Figure 41. Circuit Breaker Functionality
Figure 42. Zoomed at the Instance of Load Step
9.3.5.2 Short Circuit Protection
During a transient output short circuit event, the current through the device increases very rapidly. As the current-
limit amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator, with a threshold I(FASTRIP). The fast-trip comparator turns off the internal FET within 250 ns (typical),
when the current through the FET exceeds I(FASTRIP) (I(OUT) > I(FASTRIP)), and terminates the rapid short-circuit
peak current. The fast-trip threshold is internally set to 87% higher than the programmed overload current limit
(I(FASTRIP) = 1.87 × I(OL) + 0.015). The fast-trip circuit holds the internal FET off for only a few microseconds, after
which the device turns back on slowly, allowing the current-limit loop to regulate the output current to I(OL). Then,
device behaves similar to overload condition. Figure 43 and Figure 44 illustrate the behavior of the system when
the current exceeds the fast-trip threshold.
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VIN = 24 V, RILIM = 5.36 kΩ
Figure 43. Output Hot Short Functionality at 24-V Input
9.3.5.2.1 Start-Up With Short-Circuit On Output
Figure 44. Zoomed at the Instance of Output Short
When the device is started with short-circuit on the output, it limits the load current to the current limit I(OL) and
behaves similar to the overload condition. Figure 45 illustrates the behavior of the device in this condition. This
feature helps in quick isolation of the fault and hence ensures stability of the DC bus.
V_IN
V_OUT
FLTb
I_IN
MODE pin connected to RTN
VIN = 24 V RILIM = 5.36 kΩ
Figure 45. Start-Up With Short on Output
9.3.5.3 FAULT Response
The FLT open-drain output asserts (active low) under following conditions:
•
•
•
Fault events such as undervoltage, overvoltage, over load, reverse current and thermal shutdown conditions
When the device enters low current shutdown mode when SHDN is pulled low
During start-up when the internal FET GATE is not fully enhanced
The device is designed to eliminate false reporting by using an internal "de-glitch" circuit for fault conditions
without the need for an external circuitry.
The FLT signal can also be used as Power Good indicator to the downstream loads like DC-DC converters. An
internal Power Good (PGOOD) signal is OR'd with the fault logic. During start-up, when the device is operating in
dVdT mode, PGOOD and FLT remains low and is de-asserted after the dVdT mode is completed and the
internal FET is fully enhanced. The PGOOD signal has deglitch time incorporated to ensure that internal FET is
fully enhanced before heavy load is applied by the downstream converters. Rising deglitch delay is determined
by tPGOOD(degl) = Maximum {(875 + 20 × C(dVdT)), tPGOODR}, where C(dVdT) is in nF and tPGOOD(degl) is in µs. FLT can
be left open or connected to RTN when not used. V(IN) falling below V(PORF) = 3.72 V resets FLT.
24
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In case of reverse input polarity fault, care should be taken while interfacing FLT pin to the downstream I/O.
Refer to the application report, Fault Handling Using TPS2660 eFuse for further information.
9.3.5.3.1 Look Ahead Overload Current Fault Indicator
With the device configured in current limit operation and when the overload condition exists for more than
tPGOODF, 875 µs (typical), the FLT asserts to warn of impending turnoff of the internal FETs due to the
subsequent thermal shutdown event. Figure 46 and Figure 47 depict this behavior. The FLT signal remains
asserted until the fault condition is removed and the device resumes normal operation.
RILIM = 12 kΩ
MODE pin connected
to RTN
Load transient event
from 37 Ω to 15 Ω
RILIM = 12 kΩ
MODE pin connected
to RTN
Load transient event
from 37 Ω to 15 Ω
Figure 46. Look Ahead Overload Current Fault Indication
Figure 47. Output Turnoff Due to Thermal Shutdown With
FLT Asserted in Advance
9.3.5.4 Current Monitoring
The current source at IMON terminal is internally configured to be proportional to the current flowing from IN to
OUT. This current can be converted into a voltage using a resistor R(IMON) from IMON terminal to RTN terminal.
The IMON voltage can be used as a means of monitoring current flow through the system. The maximum voltage
range (V(IMONmax)) for monitoring the current is limited to minimum of ([V(IN) – 1.5 V, 4 V]) to ensure linear output.
This puts a limitation on maximum value of R(IMON) resistor and is determined by Equation 5.
Min [(V(IN) - 1.5), 4 V]
R
(
IMONmax
)
=
1.8 ì I
(
LIM
)
ì GAIN
(
IMON
)
(5)
The output voltage at IMON terminal is calculated using Equation 6 and Equation 7.
For IOUT > 50 mA,
V
(
IMON
)
= I
[
(
OUT
)
ìGAIN
(
IMON
)
ìR
(
IMON
)
]
Where,
•
•
•
GAIN(IMON) is the gain factor I(IMON):I(OUT) = 78.4 μA/A (Typical)
I(OUT) is the load current
I(MON_OS) = 2 µA (Typical)
(6)
(7)
For IOUT < 50 mA (typical), use Equation 7.
V
(
IMON
)
= (I(IMON _ OS))ìR(IMON)
This pin must not have a bypass capacitor to avoid delay in the current monitoring information.
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In case of reverse input polarity fault, an external 100-kΩ resistor is recommended between IMON pin and ADC
input to limit the current through the ESD protection structures of the ADC.
9.3.5.5 IN, OUT, RTN, and GND Pins
The device has two pins for input (IN) and output (OUT). All IN pins must be connected together and to the
power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus
transients. The recommended input operating voltage range is 4.2 to 60 V. Similarly all OUT pins must be
connected together and to the load. V(OUT), in the ON condition, is calculated using Equation 8.
V
(
OUT
)
= V
(
IN
)
- RON ì I
(
(
OUT
)
)
Where,
•
RON is the total ON resistance of the internal FETs.
(8)
GND pin must be connected to the system ground. RTN is the device ground reference for all the internal control
blocks. Connect the TPS2660x support components: R(ILIM), C(dVdT), R(IMON), R(MODE) and resistors for UVLO and
OVP with respect to the RTN pin. Internally, the device has reverse input polarity protection block between RTN
and the GND terminal. Connecting RTN pin to GND pin disables the reverse input polarity protection feature and
the TPS2660x gets permanently damaged when operated under this fault event.
9.3.5.6 Thermal Shutdown
The device has a built-in overtemperature shutdown circuitry designed to protect the internal FETs, if the junction
temperature exceeds T(TSD). After the thermal shutdown event, depending upon the mode of fault response, the
device either latches off or commences an auto-retry cycle 512 ms after TJ < [T(TSD) – 10°C]. During the thermal
shutdown, the fault pin FLT pulls low to indicate a fault condition.
9.3.5.7 Low Current Shutdown Control (SHDN)
The internal FETs and hence the load current can be switched off by pulling the SHDN pin below 0.76 V
threshold with a micro-controller GPIO pin or can be controlled remotely with an opto-isolator device as shown in
Figure 48 and Figure 49. The device quiescent current reduces to 20 μA (typical) in shutdown state. To assert
SHDN low, the pull down must sink at least 10 µA at 400 mV. To enable the device, SHDN must be pulled up to
atleast 1 V. Once the device is enabled, the internal FETs turnon with dVdT mode.
AVdd
Rpu
TPS2660x
SHDN
GND
from µC GPIO
+
SHDNb
0.76V
OFF
ON
Figure 48. Shutdown Control
26
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ON OFF
AVdd
Rpu
TPS2660x
SHDN
GND
+
SHDNb
a
k
C
E
0.76V
Opto Isolator
Figure 49. Opto-Isolator Shutdown Control
9.4 Device Functional Modes
The TPS26600, TPS26601 and TPS26602 respond differently to overload and short circuit conditions. The
operational differences are explained in Table 2.
Table 2. Device Operational Differences Under Different MODE Configurations
MODE Pin Configuration
MODE Connected to RTN
(Current Limit With Auto-Retry) between MODE and RTN Pins
(Current Limit With Latchoff)
A 402-kΩ Resistor Connected
MODE Pin = Open (Circuit
Breaker with Auto-Retry -
TPS26600 and TPS26602),
(Circuit Breaker With Latch -
TPS26601 Only)
Start-up
Inrush current controlled by dVdT
Inrush limited to I(OL) level as set Inrush limited to I(OL) level as set Inrush limited to I(OL) level as set
by R(ILIM)
by R(ILIM)
by R(ILIM)
Fault timer runs when current is
limited to I(OL)
Fault timer expires after tCB(dly)
causing the FETs to turnoff
If TJ > T(TSD), device turns off
If TJ > T(TSD), device turns off
Device turns off if TJ > T(TSD)
before timer expires
Overcurrent response
Current is limited to I(OL) level as Current is limited to I(OL) level as Current is allowed through the
set by R(ILIM)
set by R(ILIM)
device if I(LOAD) < I(FASTTRIP)
Power dissipation increases as
V(IN) – V(OUT) increases
Power dissipation increases as
V(IN) – V(OUT) increases
Fault timer runs when the current
increases above I(OL)
Fault timer expires after tCB(dly)
causing the FETs to turnoff
Device turns off when TJ > T(TSD) Device turns off when TJ > T(TSD) Device turns off if TJ > T(TSD)
before timer expires
Device attempts restart 540 ms
after TJ < [T(TSD) – 10°C]
Device remains off
TPS26600 and TPS26602
attempt restart 540 ms after TJ <
[T(TSD) – 10°C]. TPS26601
remains off
Short-circuit response
Fast turnoff when I(LOAD) > I(FASTRIP)
Quick restart and current limited to I(OL), follows standard start-up
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS2660x is an industrial eFuse, typically used for Hot-Swap and Power rail protection applications. It
operates from 4.2 V to 60 V with programmable current limit, overvoltage, undervoltage and reverse polarity
protections. The device aids in controlling in-rush current and provides robust protection against reverse current
and filed miss-wiring conditions for systems such as PLCs, Industrial PCs, Control and Automation and Sensors.
The device also provides robust protection for multiple faults on the system rail.
The Detailed Design Procedure section can be used to select component values for the device.
Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. Additionally, a spreadsheet design tool TPS2660x Design Calculator is available in the web product
folder.
10.2 Typical Application
IN: 18 V-30 V
OUT
OUT
FLT
IN
CIN
1 µF
COUT
2.2 mF
150 mΩ
R1
715 k
RFLTb
100 k
UVLO
OVP
Health Monitor
TPS26600
R2
20 k
ON/OFF Control
Load Monitor
SHDN
IMON
ILIM
dVdT
MODE
RTN
R3
30.1 k
CdVdT
2.2 µF
RIMON
33.2 k
GND
RILIM
11.8 k
Figure 50. 24-V, 1-A eFuse Input Protection Circuit for Industrial PLC CPU
10.2.1 Design Requirements
Table 3 shows the Design Requirements for TPS2660x.
Table 3. Design Requirements
DESIGN PARAMETER
Typical input voltage
EXAMPLE VALUE
V(IN)
24 V
18 V
V(UV)
V(OV)
RL(SU)
I(LIM)
C(OUT)
TA
Undervoltage lockout set point
Overvoltage cutoff set point
Load during start-up
30 V
48 Ω
Current limit
1 A
Load capacitance
2200 µF
85°C
Maximum ambient temperature
28
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10.2.2 Detailed Design Procedure
10.2.2.1 Step by Step Design Procedure
To begin the design process, the designer needs to know the following parameters:
•
•
•
•
•
Input operating voltage range
Maximum output capacitance
Maximum current limit
Load during start-up
Maximum ambient temperature
This design procedure below seeks to control junction temperature of the device in both steady state and
start-up conditions by proper selection of the output ramp-up time and associated support components. The
designer can adjust this procedure to fit the application and design criteria.
10.2.2.2 Programming the Current-Limit Threshold—R(ILIM) Selection
The R(ILIM) resistor at the ILIM pin sets the over load current limit, this can be set using Equation 9.
12
R(ILIM) =
= 12kW
ILIM
where
•
ILIM = 1A
(9)
Choose the closest standard 1% resistor value : R(ILIM) = 11.8 kΩ
10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using an external voltage divider
network of R1, R2 and R3 connected between IN, UVLO, OVP and RTN pins of the device. The values required
for setting the undervoltage and overvoltage are calculated by solving Equation 10 and Equation 11.
R3
V(OVPR) =
ì V(OV)
R1+ R2 + R3
(10)
R2 + R3
R1+ R2 + R3
V(UVLOR) =
ì V(UV)
(11)
For minimizing the input current drawn from the power supply {I(R123) = V(IN)/(R1+R2+R3)}, it is recommended to
use higher value resistance for R1, R2 and R3.
However, the leakage current due to external active components connected at resistor string can add error to
these calculations. So, the resistor string current, I(R123) must be chosen to be 20x greater than the leakage
current of UVLO and OVP pins.
From the device electrical specifications, V(OVPR) = 1.19 V and V(UVLOR) = 1.19 V. From the design requirements,
V(OV) is 30 V and V(UV) is 18 V. To solve the equation, first choose the value of R3 = 30.1 kΩ and use
Equation 10 to solve for (R1 + R2) = 728.7 kΩ. Use Equation 11 and value of (R1 + R2) to solve for R2 = 20.05 kΩ
and finally R1= 708.6 kΩ.
Choose the closest standard 1% resistor values: R1 = 715 kΩ, R2 = 20 kΩ, and R3 = 30.1 kΩ.
The UVLO and the OVP pins can also be connected to the RTN pin to enable the internal default V(OV) = 33 V
and V(UV) = 15 V.
The power failure is detected on falling edge of the supply. This threshold voltage is 7.5% lower than the rising
threshold, V(UV). The voltage at which the device detects power fail can be calculated using Equation 12.
V(PFAIL) = 0.925ì V(UV)
(12)
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10.2.2.4 Programming Current Monitoring Resistor—RIMON
The voltage at IMON pin V(IMON) represents the voltage proportional to the load current. This can be connected to
an ADC of the downstream system for health monitoring of the system. The R(IMON) must be configured based on
the maximum input voltage range of the ADC used. R(IMON) is set using Equation 13.
V(IMONmax)
I(LIM) ì75 ì10-6
R(IMON) =
(13)
For I(LIM) = 1 A, and considering the operating voltage range of ADC from 0 V to 2.5 V, V(IMONmax) is 2.5 V and
R(IMON) is determined by Equation 14.
2.5
1ì75ì10-6
R(IMON) =
= 33.3kW
(14)
Selecting the R(IMON) value less than determined ensures that ADC limits are not exceeded for maximum value of
the load current. Choose the closest standard 1% resistor value : R(IMON) = 33.2 kΩ.
If current monitoring up to I(FASTRIP) is desired, R(IMON) can be reduced by a factor of 1.8 as shown Equation 5.
10.2.2.5 Setting Output Voltage Ramp Time—(tdVdT
)
For a successful design, the junction temperature of the device must be kept below the absolute-maximum rating
during dynamic (start-up) and steady state conditions. The dynamic power dissipation is often an order
magnitude greater than the steady state power dissipation. It is important to determine the right start-up time and
the in-rush current limit for the system to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor C(dVdT) is calculated considering the two possible cases:
10.2.2.5.1 Case 1: Start-Up Without Load—Only Output Capacitance C(OUT) Draws Current During Start-Up
During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and
the power dissipation decreases. Typical ramp-up of the output voltage, inrush current and instantaneous power
dissipated in the device during start-up are shown in Figure 51. The average power dissipated in the device
during start-up is equal to the area of triangular plot (red curve in Figure 52) averaged over tdVdT
.
2.5
30
24
18
12
6
Input Current (A)
Power DIssipation (W)
Output Voltage (V)
2
1.5
1
0.5
0
0
0
20
40
60
80
100
Start-Up Time (%)
D050
VIN = 24 V
CdVdT = 2.2 µF
COUT = 2.2 mF
VIN = 24 V
CdVdT = 2.2 µF
COUT = 2.2 mF
Figure 51. Start-Up Without Load
Figure 52. PD(INRUSH) Due to Inrush Current
The inrush current is determined as shown in Equation 15.
dV
dT
V(IN)
tdVdT
I = C ì
í I(INRUSH) = C(OUT) ì
(15)
Average power dissipated during start-up is given by Equation 16.
30
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PD(INRUSH) = 0.5ì V(IN) ìI(INRUSH)
(16)
Equation 16 assumes that the load does not draw any current until the output voltage reaches its final value.
10.2.2.5.2 Case 2: Start-Up With Load—Output Capacitance C(OUT) and Load Draws Current During Start-Up
When the load draws current during the turnon sequence, additional power is dissipated in the device.
Considering a resistive load RL(SU) during start-up, typical ramp-up of output voltage, load current and the
instantaneous power dissipation in the device are shown in Figure 53. Instantaneous power dissipation with
respect to time is plotted in Figure 54. The additional power dissipation during start-up is calculated using
Equation 17.
6
5.5
5
36
33
30
27
24
21
18
15
12
9
Input Current (A)
Power Dissipation (W)
Output Voltage (V)
4.5
4
3.5
3
2.5
2
1.5
1
6
0.5
0
3
0
0
20
40
60
80
100
Start-Up Time (%)
D051
VIN = 24 V
RL(SU) = 48 Ω
VIN = 24 V
RL(SU) = 48 Ω
CdVdT = 2.2 µF
COUT = 2.2 mF
CdVdT = 2.2 µF
COUT = 2.2 mF
Figure 53. Start-Up With Load
Figure 54. PD(INRUSH) Due to Inrush and Load Current
1
V(IN)2
PD(LOAD) =
ì
6
RL(SU)
(17)
(18)
(19)
Total power dissipated in the device during start-up is given by Equation 18.
PD(STARTUP) = PD(INRUSH) + PD(LOAD)
Total current during start-up is given by Equation 19.
I(STARTUP) = I(INRUSH) + IL(t)
For the design example under discussion,
Select the inrush current I(INRUSH) = 0.1 A and calculate tdVdT using Equation 20.
24
t(dVdT) = 2.2mì
= 0.528s
0.1
(20)
For a given start-up time, CdVdT capacitance value is calculated using Equation 21.
t(dVdT)
8 ì103 ì V(IN)
C(dVdT) =
= 2.7mF
where
•
•
t(dVdT) = 0.528 s
V(IN) = 24 V
(21)
31
Choose the closest standard value: 2.2-µF/16-V capacitor.
The inrush power dissipation is calculated, using Equation 22.
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PD(INRUSH) = 0.5 ì V(IN) ìI(INRUSH) = 1.2W
where
•
•
V(IN) = 24 V
I(INRUSH) = 0.1 A
(22)
Considering the start-up with 48-Ω load, the additional power dissipation, is calculated using Equation 23.
1
V(IN)2
PD(LOAD) = ( )ì
= 2 W
6
RL(SU)
where
•
•
V(IN) = 24 V
RL(SU) = 48 Ω
(23)
(24)
The total device power dissipation during start-up is given by Equation 24.
PD(STARTUP) = PD(INRUSH) + PD(LOAD) = 3.2W
where
•
•
PD(INRUSH) = 1.2 W
PD(LOAD) = 2 W
The power dissipation with or without load, for a selected start-up time must not exceed the thermal shutdown
limits as shown in Figure 55.
From the thermal shutdown limit graph, at TA = 85°C, thermal shutdown time for 3.2 W is close to 28000 ms. It is
safe to have a minimum 30% margin to allow for variation of the system parameters such as load, component
tolerance, input voltage and layout. Selected 2.2-µF CdVdT capacitor and 528-ms start-up time (tdVdT) are within
limit for successful start-up with 48-Ω load.
Higher value C(dVdT) capacitor can be selected to further reduce the power dissipation during start-up.
10000
TA = -40èC
TA = 25èC
TA = 85èC
TA = 105èC
TA = 125èC
1000
100
10
1
0.1
1
10
Power Dissipation (W)
100
D052
Figure 55. Thermal Shutdown Time vs Power Dissipation
10.2.2.5.3 Support Component Selections—RFLTb and C(IN)
The RFLTb serves as pull-up for the open-drain fault output. The current sink by this pin must not exceed 10 mA
(see the Absolute Maximum Ratings table). Typical resistance value in the range of 10 kΩ to 100 kΩ is
recommended for RFLTb. The CIN is a local bypass capacitor to suppress noise at the input. Typical capacitance
value in the range of 0.1 µF to 1 µF is recommended for C(IN)
.
32
Copyright © 2016–2019, Texas Instruments Incorporated
TPS2660
www.ti.com.cn
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
10.2.3 Application Curves
V_IN
V_OUT
FLTb
I_IN
Figure 57. Start-Up With VIN—No Load
Figure 56. Start-Up With VIN—48-Ω Load
V_IN
SHDNb
V_OUT
I_IN
Figure 58. Power Fail With 24-Ω Load—Supports 1-A Load
Figure 59. Start-Up With Shutdown Pin—48-Ω Load
for 10-ms Power Fail
Figure 60. Power Down With Shutdown Pin—48-Ω Load
Figure 61. Over Load Response—Load Stepped from
100-Ω to 18-Ω Load
Copyright © 2016–2019, Texas Instruments Incorporated
33
TPS2660
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
VIN
VOUT
I_IN
Figure 62. Turnon With Short Circuit on Output
Figure 63. Reverse Polarity Protection
10.3 System Examples
10.3.1 Acive ORing Operation
IN1: 4.2 V - 60 V
IN
OUT
CIN
R1
150 mꢀ
UVLO
FLT
TPS26600
OVP
MODE
dVdT
SHDN
IMON
R2
R3
OUT
COUT
Concept
ILIM
Common Bus
GND
RTN
RILIM
CdVdT
SYSTEM
LOAD
Hot-Swap
IN2: 4.2 V - 60 V
IN
OUT
FLT
CIN
R4
150 mꢀ
IN2 IN1
UVLO
TPS26600
OVP
MODE
dVdT
SHDN
IMON
R5
R6
ILIM
GND
RTN
RILIM
CdVdT
Figure 64. Active ORing Application Schematic
Figure 64 shows a typical redundant power supply configuration of the system. Schottky ORing diodes have
been popular for connecting parallel power supplies, such as parallel operation of wall adapter with a battery or a
hold-up storage capacitor. The disadvantage of using ORing diodes is high voltage drop and associated power
loss. The TPS2660x with integrated, N-channel back to back FETs provide a simple and efficient solution.
A fast reverse comparator controls the internal FET and it is turned ON or OFF with hysteresis as shown in
Figure 65. The internal FET is turned off within 1.5 μs (typical) as soon as V(IN) – V(OUT) falls below –110 mV. It
turns on within 40 µs (typical) once the differential forward voltage V(IN) – V(OUT) exceeds 100 mV. Figure 66 and
Figure 67 show typical switch-over waveforms of Active ORing implementation using the TPS26600.
34
Copyright © 2016–2019, Texas Instruments Incorporated
TPS2660
www.ti.com.cn
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
System Examples (continued)
Reverse Blocking
Forward Conduction
-10
100
VIN - V
mV
(
)
(
)
OUT
Figure 65. Active ORing Thresholds
VIN1 = 22 V
Cout = 47 μF
Rload = 24 Ω
VIN1 = 22 V
Cout = 47 μF
Rload = 24 Ω
VIN2: Plugged In
at 24 V
C(dVdT) = 22 nF
VIN2: Plugged Out
C(dVdT) = 22 nF
Figure 67. Active ORing Between Two Supplies VOUT
Change Over to VIN1
Figure 66. Active ORing Between Two Supplies VOUT
Change Over to VIN2
NOTE
All control pins of the un-powered TPS2660x device in the Active ORing configuration will
measure approximately 0.7 V drop with respect to GND. The system micro-controller
should ignore IMON and FLT pin voltage measurements of this device when these signals
are being monitored.
Copyright © 2016–2019, Texas Instruments Incorporated
35
TPS2660
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
System Examples (continued)
10.3.2 Field Supply Protection in PLC, DCS I/O Modules
TPS2660
24-V nominal (from field
SELV power supply)
To field loads (sensors &
Actuators
IN
OUT
Power FET isolation during over
voltage , Input Reverse Polarity and
short circuit faults
Inrush Current
Control
IMON
FLT
Load Current monitor & Fault
Diagnostics
SHDN
IMON
FLT
ON/OFF
Control
Fault
IMON
DC/DC
MCU
Field side
PLC side
Digital Isolator
Figure 68. Power Delivery Circuit Block Diagram in I/O Modules
The PLC or Distributed Control System (DCS) I/O modules are often connected to an external field power supply
to support higher power requirements of the field loads like sensors and actuators. Power-supply faults or
miswiring can damage the loads or cause the loads not to operate correctly. The TPS2660x can be used as a
front end protection circuit to protect and provide stable supply to the field loads. Under voltage, Over voltage
and reverse polarity protection features of the TPS2660x prevent the loads to experience voltages outside the
operating range, which can permanently damage the loads.
Field power supply is often connected to multiple I/O modules and is capable of delivering more current than a
single I/O module can handle. Overcurrent protection scheme of the TPS2660x limits the current from the power
supply to the module so that the maximum current does not rise above what the board is designed for. Fast short
circuit protection scheme isolates the faulty load from the field supply quickly and prevents the field supply to dip
and cause interrupts in the other I/O modules connected to the same field supply. High accurate (±5% at 1 A)
current limit facilitates more I/O modules to be connected to field supply. Load current monitor (IMON) and fault
indication (FLT) features facilitate continuous load monitoring.
The TPS2660x also acts as a smart diode with protection against reverse current during output side miswiring.
Reverse current can potentially damage the field power supply and cause the I/O modules to run hot or may
cause permanent damage.
If the field power supply is connected in reverse polarity (which is not unlikely as field power supplies are usually
connected with screw terminals), field loads can permanently get damaged due to the reverse voltage. The
reverse polarity protection feature of the TPS2660x prevents the reverse voltage to appear at the load side.
36
Copyright © 2016–2019, Texas Instruments Incorporated
TPS2660
www.ti.com.cn
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
System Examples (continued)
10.3.3 Simple 24-V Power Supply Path Protection
With the TPS2660x, a simple 24-V power supply path protection can be realized using a minimum of three
external components as shown in the schematic diagram in Figure 69. The external components required are: a
R(ILIM) resistor to program the current limit, C(IN) and C(OUT) capacitors.
System Load
IN
OUT
COUT
CIN
150 mꢀ
Input from a 24V
power supply
UVLO
OVP
FLT
TPS26600
SHDN
IMON
ILIM
MODE
RTN
dVdT
GND
RILIM
Figure 69. TPS26600 Configured for a Simple 24-V Supply Path Protection
Protection features with this configuration include:
•
•
•
•
•
•
•
Load and device protection from reverse input polarity fault down to –60V
15 V (typical) rising under voltage lock-out threshold
33 V (typical) rising overvoltage cut-off threshold
Protection from 60 V from the external SELV supply
Inrush current control with 24V/1.6 ms output voltage slew rate
Reverse Current Blocking
Accurate current limiting with Auto-Retry
10.4 Do's and Don'ts
•
•
Do not connect RTN to GND. Connecting RTN to GND disables the Reverse Polarity protection feature
Do connect the TPS2660x support components R(ILIM), C(dVdT), R(IMON), R(MODE) and UVLO, OVP resistors with
respect to RTN pin
•
Do connect device PowerPAD to the RTN plane for an enhanced thermal performance
Copyright © 2016–2019, Texas Instruments Incorporated
37
TPS2660
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
11 Power Supply Recommendations
The TPS2660x eFuse is designed for the supply voltage range of 4.2 V ≤ VIN ≤ 60 V. If the input supply is
located more than a few inches from the device, an input ceramic bypass capacitor higher than 0.1 μF is
recommended. Power supply must be rated higher than the current limit set to avoid voltage droops during
overcurrent and short circuit conditions.
11.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include
•
•
•
•
Minimizing lead length and inductance into and out of the device
Using large PCB GND plane
Schottky diode across the output to absorb negative spikes
A low value ceramic capacitor (C(IN) to approximately 0.1 μF) to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with Equation 25.
L IN
( )
Vspike Absolute = V IN + I Load
´
(
)
( )
(
)
C IN
( )
where
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
(25)
Some applications may require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device. These transients can occur during positive and negative
surge tests on the supply lines. In such applications it is recommended to place atleast 1 µF of input capacitor to
limit the falling slew rate of the input voltage within a maximum of 20 V/µs.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 70.
INPUT
IN
OUT
OUTPUT
CIN
COUT
R4
R1
R2
150 mꢀ
UVLO
FLT
*
*
TPS26600
OVP
SHDN
IMON
MODE
dVdT
ILIM
GND
RTN
R3
RILIM
RIMON
CdVdT
* Optional components needed for suppression of transients
Figure 70. Circuit Implementation With Optional Protection Components
38
Copyright © 2016–2019, Texas Instruments Incorporated
TPS2660
www.ti.com.cn
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
12 Layout
12.1 Layout Guidelines
•
For all the applications, a 0.1 µF or higher value ceramic decoupling capacitor is recommended between IN
terminal and GND.
•
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 71 and Figure 72 for PCB layout examples with HTSSOP and VQFN
packages respectively.
•
High current carrying power path connections must be as short as possible and must be sized to carry atleast
twice the full-load current.
•
•
RTN, which is the reference ground for the device must be a copper plane or island.
Locate all the TPS2660x support components R(ILIM), C(dVdT), R(IMON), and MODE, UVLO, OVP resistors close
to their connection pin. Connect the other end of the component to the RTN with shortest trace length.
•
•
The trace routing for the RILIM and R(IMON) components to the device must be as short as possible to reduce
parasitic effects on the current limit and current monitoring accuracy. These traces must not have any
coupling to switching signals on the board.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT and GND pins.
•
Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater
cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board RTN plane
directly under the device. Other planes, such as the bottom side of the circuit board can be used to increase
heat sinking in higher current applications. Designs that do not need reverse input polarity protection can
have RTN, GND and PowerPAD connected together. PowerPAD in these designs can be connected to the
PCB ground plane.
Copyright © 2016–2019, Texas Instruments Incorporated
39
TPS2660
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
12.2 Layout Example
Top Layer
Bottom layer GND plane
Top Layer RTN Plane
Bottom Layer RTN Plane
Via to Bottom Layer
Track in bottom layer
BOTTOM Layer GND Plane
Top Layer
Power GND Plane
High
Frequency
Bypass cap
OUT
IN
IN
OUT
FLT
VOUT PLANE
VIN PLANE
UVLO
N.C
N.C
PWP
OVP
dVdT
MODE
SHDN
RTN
ILIM
IMON
TOP Layer
RTN Plane
BOTTOM Layer RTN Plane
Figure 71. Typical PCB Layout Example With HTSSOP Package With a 2 Layer PCB
40
Copyright © 2016–2019, Texas Instruments Incorporated
TPS2660
www.ti.com.cn
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
Layout Example (continued)
Top Layer
Bottom layer GND plane
Via to Bottom Layer
Track in bottom layer
Top Layer RTN Plane
Bottom Layer RTN Plane
BOTTOM Layer GND Plane
Top Layer
Power GND Plane
High
Frequency
Bypass cap
IN
OUT
IN
OUT
VIN PLANE
VOUT PLANE
UVLO
N.C
FLT
PWP
N.C
dVdT
OVP
TOP Layer
RTN Plane
BOTTOM Layer RTN Plane
Figure 72. Typical PCB Layout Example With VQFN Package With a 2 Layer PCB
版权 © 2016–2019, Texas Instruments Incorporated
41
TPS2660
ZHCSFF5G –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
13 器件和文档支持
13.1 器件支持
有关 TPS26600 PSpice 瞬态模式，请参阅 SLVMBR3B。
有关 TPS26602 PSpice 瞬态模式，请参阅 SLVMBR4C。
13.2 文档支持
13.2.1 相关文档
请参阅如下相关文档：
•
•
•
《TPS26600-02EVM：TPS2660x 评估模块用户指南》
《使用负载开关和电子保险丝的电源多路复用》
《TPS2660 简化 PLC 系统中的浪涌和电源故障保护电路》
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
42
版权 © 2016–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS26600PWPR
TPS26600PWPT
TPS26600RHFR
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
VQFN
PWP
PWP
RHF
16
16
24
2000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
26600
26600
NIPDAU
NIPDAU
TPS
26600
TPS26600RHFT
TPS26601RHFR
TPS26601RHFT
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
RHF
RHF
RHF
24
24
24
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
TPS
26600
TPS
26601
TPS
26601
TPS26602PWPR
TPS26602PWPT
TPS26602RHFR
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
VQFN
PWP
PWP
RHF
16
16
24
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
26602
26602
TPS
26602
TPS26602RHFT
ACTIVE
VQFN
RHF
24
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
26602
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS26600PWPR
TPS26600RHFR
TPS26600RHFT
TPS26601RHFR
TPS26601RHFT
TPS26602PWPR
TPS26602RHFR
TPS26602RHFT
HTSSOP PWP
16
24
24
24
24
16
24
24
2000
3000
250
330.0
330.0
180.0
330.0
180.0
330.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.9
4.3
4.3
4.3
4.3
6.9
4.3
4.3
5.6
5.3
5.3
5.3
5.3
5.6
5.3
5.3
1.6
1.3
1.3
1.3
1.3
1.6
1.3
1.3
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
VQFN
VQFN
VQFN
VQFN
RHF
RHF
RHF
RHF
3000
250
HTSSOP PWP
2000
3000
250
VQFN
VQFN
RHF
RHF
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS26600PWPR
TPS26600RHFR
TPS26600RHFT
TPS26601RHFR
TPS26601RHFT
TPS26602PWPR
TPS26602RHFR
TPS26602RHFT
HTSSOP
VQFN
PWP
RHF
RHF
RHF
RHF
PWP
RHF
RHF
16
24
24
24
24
16
24
24
2000
3000
250
350.0
367.0
210.0
367.0
210.0
350.0
367.0
210.0
350.0
367.0
185.0
367.0
185.0
350.0
367.0
185.0
43.0
35.0
35.0
35.0
35.0
43.0
35.0
35.0
VQFN
VQFN
3000
250
VQFN
HTSSOP
VQFN
2000
3000
250
VQFN
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016H
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
6
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
PIN 1 INDEX
SEATING
PLANE
A
0.1 C
AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
0.30
16X
4.5
4.3
0.19
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
0.25
GAGE PLANE
1.2 MAX
2X 1.15 MAX
NOTE 5
0.15
0.05
0.75
0.50
8
9
0 -8
A
15
DETAIL A
TYPICAL
2X 0.3 MAX
NOTE 5
2.46
2.16
17
THERMAL
PAD
1
16
2.66
2.36
4223630/A 04/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016H
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.66)
METAL COVERED
BY SOLDER MASK
16X (1.5)
SYMM
1
16
(0.6) TYP
16X (0.45)
(R0.05) TYP
SYMM
(5)
NOTE 9
17
(1.2)
TYP
(2.46)
14X (0.65)
9
8
0.2) TYP
(
(1.2) TYP
VIA
SEE DETAILS
(5.8)
SOLDER MASK
DEFINED PAD
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
15.000
SOLDER MASK DETAILS
4223630/A 04/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016H
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.66)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
16X (1.5)
1
16
16X (0.45)
(R0.05) TYP
(2.46)
SYMM
17
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SEE TABLE FOR
SYMM
(5.8)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.97 X 2.75
2.66 X 2.46 (SHOWN)
2.43 X 2.25
0.125
0.15
0.175
2.25 X 2.08
4223630/A 04/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RHF0024A
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
0.5
0.3
5.1
4.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.65 0.1
2X 2
(0.1) TYP
12
EXPOSED
8
THERMAL PAD
20X 0.5
7
13
3.65 0.1
2X
3
25
SYMM
SEE TERMINAL
DETAIL
19
1
0.30
0.18
24X
0.1
C B A
PIN 1 ID
(OPTIONAL)
24
20
SYMM
0.05
0.5
0.3
24X
4219064 /A 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHF0024A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.65)
SYMM
20
24
24X (0.6)
1
19
24X (0.24)
(3.65)
(1.575)
20X (0.5)
25
SYMM
(4.8)
(0.62)
TYP
(R0.05)
TYP
13
7
(
0.2) TYP
VIA
8
12
(1.025)
TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219064 /A 04/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHF0024A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6X (1.17)
(0.685) TYP
20
24
24X (0.6)
1
19
24X (0.24)
(1.24)
TYP
20X (0.5)
SYMM
(4.8)
25
6X (1.04)
13
(R0.05) TYP
7
METAL
TYP
12
8
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219064 /A 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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