TPS26613 [TI]
TPS2661x: 50-V, Universal 4â20 mA, ±20-mA Current Loop Protector With Input and Output Miswiring Protection;
| 型号： | TPS26613 |
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TEXAS INSTRUMENTS |
| 描述： | TPS2661x: 50-V, Universal 4â20 mA, ±20-mA Current Loop Protector With Input and Output Miswiring Protection |
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TPS2661
SLVSFE3C – NOVEMBER 2020 – REVISED DECEMBER 2021
TPS2661x: 50-V, Universal 4–20 mA, ±20-mA Current Loop Protector With
Input and Output Miswiring Protection
universal input protection for ±20 mA, 0 mA to 20 mA,
1 Features
and 4 mA–20 mA. Low RON values of 7.5 Ω minimizes
drop in the current loop, thereby extending operating
range and supporting operation even with lower
voltage power supplies. The device can withstand and
protect the loads from positive and negative supply
voltages up to ±50 V. The MODE pin allows flexibility
to enable 2x current limit through the device to enable
proper start-up of two wire transmitters. Device is
capable of operating from an external bipolar supply
as low as ± 2.25 V to ±20 V. The device can also
be powered from unipolar supplies as low as 3 V
to 30 V. The TPS26610 and TPS26613 feature loop
power mode to facilitate loop testing in un-powered
state without ±Vs supplies.
•
•
•
•
±50-V operating voltage, ±55-V absolute maximum
Integrated fixed bipolar 32-mA current limit
Allows 2x current limit at start-up
50% space savings compared to a typical discrete
protection circuit
•
•
Low R-on: 7.5-Ω typical
Low IQ (< 100 nA) – current drawn from loop when
powered from external supply
Protection against miswiring conditions on IN and
OUT
Protection during signal line surge IEC61000-4-5
(with external TVS)
Criteria-A EFT (IEC61000-4-4) immunity (with
external TVS)
Supports loop testing without supply (TPS26610
only)
•
•
•
•
The device also protects the system from output side
miswiring in analog outputs and sensor transmitters
by turning off the current path. The internal robust
protection control blocks along with the 50-V rating
of the TPS2661x help to protect against surge
(IEC61000-4-5) and EFT (IEC61000-4-4) transients
for signal lines. The device greatly reduces system
footprint by its 2.9-mm × 1.6-mm 8-pin SOT-23
package.
•
•
•
•
HART compliant
Enable control
SGOOD for system health monitoring
Thermal shutdown
2 Applications
•
Factory automation and control – PLCs - analog
input and output module
Motor drives control
HART inputs
HVAC controllers
Device Information(1)
•
•
•
•
•
PART NUMBER
TPS26610
PACKAGE
BODY SIZE (NOM)
TPS26611
UART IO protection
Thermal controller
TPS26612
SOT-23 (8)
2.9 mm × 1.6 mm
TPS26613
3 Description
TPS26614
The TPS2661x is a compact, feature-rich, fully
integrated current loop protector suitable for analog
inputs, analog outputs, sensor transmitters, HART
inputs, and UART IO protection. The device provides
ANALOG INPUT MODULE
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
+Vs
SGOOD
MODE
TPS26610
I+
IN
OUT
+Vs
GND
-Vs
4 to 20 mA
20 mA
ADC
ILOOP
Current Inputs
Precision
Burden
Resistor
-Vs
GND
I-
x
no. of channels
Typical Circuit Schematic
Miswiring Protection on Input From Field Supply
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2661
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SLVSFE3C – NOVEMBER 2020 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Timing Requirements..................................................7
7.7 Typical Characteristics................................................9
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................13
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................26
9.1 Application Information............................................. 26
9.2 Typical Application: Analog Input Protection for
Current Inputs with TPS26610.................................... 26
9.3 Typical Application: Analog Input Protection for
Multiplexed Current and Voltage Inputs with
TPS26611....................................................................29
9.4 System Examples..................................................... 31
10 Power Supply Recommendations..............................35
11 Layout...........................................................................36
11.1 Layout Guidelines................................................... 36
11.2 Layout Example...................................................... 36
12 Device and Documentation Support..........................37
12.1 Receiving Notification of Documentation Updates..37
12.2 Support Resources................................................. 37
12.3 Trademarks.............................................................37
12.4 Electrostatic Discharge Caution..............................37
12.5 Glossary..................................................................37
13 Mechanical, Packaging, and Orderable
Information.................................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2021) to Revision C (December 2021)
Page
•
Added TPS26613 and TPS26614 to the data sheet ..........................................................................................1
Changes from Revision A (March 2021) to Revision B (May 2021)
Page
•
Removed preview note from TPS26611 and TPS26612 in the Device Information table ................................. 1
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SLVSFE3C – NOVEMBER 2020 – REVISED DECEMBER 2021
5 Device Comparison Table
LOOP TESTING WITHOUT EXTENDED OVERLOAD
PART
NUMBER
LATCH-OFF or AUTO-
APPLICATION
EN PIN
±Vs SUPPLIES (LOOP
POWER MODE)
DURATION FOR FIRST
OVERLOAD EVENT
RETRY WITH INPUT < –Vs
Current Inputs. See Typical
TPS26610
TPS26611
No
Yes
No
No
Latch-off
Latch-off
Application: Analog Input Protection
for Current Inputs with TPS26610.
Multiplexed voltage and current
inputs. Analog outputs. See Typical
Application: Analog Input Protection
for Multiplexed Current and Voltage
Inputs with TPS26611.
Yes
Yes
No
Power supply protection for
transmitters and Analog outputs. See
Power Supply Protection of 2-Wire
Transmitter with TPS26612.
Yes. Overload expiry time is
increased up to 5 s (tAR_dis).
TPS26612
No
Latch-off
TPS26613
TPS26614
No
Yes
No
No
No
Auto-retry
Auto-retry
Current inputs
Multiplexed voltage and current inputs.
Analog outputs
Yes
6 Pin Configuration and Functions
SGOOD
SGOOD
8
1
8
1
GND
MODE
-Vs
GND
MODE
-Vs
VSNS
+Vs
2
3
7
2
3
7
6
EN
TPS26611
TPS26612
TPS26614
TPS26610
TPS26613
6
+Vs
4
5
4
5
IN
OUT
IN
OUT
Figure 6-1. TPS26610 and TPS26613 DDF Package
8-Pin SOT-23 (Top View)
Figure 6-2. TPS26611, TPS26612, and TPS26614
DDF Package 8-Pin SOT-23 (Top View)
Table 6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
GND
1
—
I
Reference ground for all internal voltages. Connect to GND of the ±Vs supply.
MODE selection pin for overload response. Sets current limit to IOL, 2 × IOL, or 2 × IOL with
extended IOL expiry time. See the Device Functional Modes for details.
MODE
–Vs
2
3
Negative supply for dual supply configurations. Connect to GND when used in a single
supply configuration.
P
IN
4
5
6
P
P
P
Signal/power input
OUT
+Vs
Signal/power output
Positive supply for powering the device
For the TPS26611, TPS26612, and TPS26614: Enable control. Pull EN low to turn off the
device. EN has internal an pullup and it can be left floating to enable the device.
EN
I
I
7
8
For the TPS26610 and TPS26613: Supply sensing input for transition to loop power mode.
If not used, this pin can be left open or floating.
VSNS
Signal good indicator pin. Whenever the device is within normal operating condition,
SGOOD shows low indicating signal is good to read.
This pin can also be used to drive an external LED to give a visual indication about the
state of system.
SGOOD
O
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
55
UNIT
IN, OUT, IN-OUT
–55
V
V
V
V
SGOOD, EN,MODE, VSNS
–0.3
5.5
32
+Vs
-Vs
-0.3
–22
0.3
IMODE, ISGOOD, IEN
Source Current
Sink Current
Internally Limited
Internally Limited
IEN
ISGOOD
200
150
µA
°C
Operating Junction temperature
Transient Junction temperature
Storage temperature
–40
TJ
–65
–65
T(TSD)
150
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–50
0
NOM
MAX
50
30
0
UNIT
IN,OUT
Voltage
V
+Vs,
Supply Voltage
Voltage
-Vs
–20
0
V
V
EN, SGOOD, VSNS
5
MODE
TJ
0
3
V
Operating Junction temperature
–40
125
°C
7.4 Thermal Information
TPS2661
THERMAL METRIC(1)
DDF (SOT-23-THN)
UNIT
8 PINS
117.8
57.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
40.2
ΨJT
2.2
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7.4 Thermal Information (continued)
TPS2661
THERMAL METRIC(1)
DDF (SOT-23-THN)
UNIT
8 PINS
ΨJB
Junction-to-board characterization parameter
40
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
–40° C ≤ TA = TJ ≤ +125° C, 2.25 V < +Vs < 30 V, -20 V < -Vs < 0 V, MODE = GND, SGOOD = Open, EN = 3.3 V (All
voltages referenced to GND, (unless otherwise noted))
PARAMETER
SIGNAL INPUT (IN)
V(IN)
TEST CONDITIONS
MIN
TYP
MAX UNIT
IN Signal Voltage
–50
50
V
Sum of Leakage Cureent (–Vs) < VIN , VOUT < (+Vs – 0.35 V)
from IN and OUT pins to
–0.1
0.1 µA
IQ
(+Vs – 0.35 V) < VIN, VOUT < +Vs
GND in normal operation
1
uA
%
Sum of leakage
current from IN and OUT
IQFLT
pins to -Vs pin during
fault as percentage of
loop current
VIN > +Vs, Current Limit Operation
20
V(IN)-V(OUT) = ±1 V, -Vs connected
to negative supply
Bipolar current limit
Unipolar Current limit
±25
25
±32
32
±40 mA
40 mA
–25 mA
V(IN)–V(OUT) = +1 V, -Vs connected
to GND
I(OL)
Unipolar current limit with V(IN) = –24-V V(OUT) = –19 V, –Vs
–40
–32
60
VIN <-VS
= –20 V. TPS26613/14 Only
Transient Pulse Over
Current Limit
V(IN)–V(OUT) = +1.5 V, MODE =
Floating
I(OL_Pulse)
50
±65
72 mA
±165 mA
±275 mA
MODE = GND
I(FASTRIP)
Fast-trip current limit
MODE = Floating or 180 kΩ to
GND
±140
-12.5 V < VIN <12.5 V; VOUT = 0 V;
EN = Low; +Vs = 15V; (-Vs) = -15
V ,TPS26611/12/14 Only
–9.75
–9.75
–6
–5.25 µA
–5.25 µA
–1 µA
Sum of leakage current
from IN and OUT pins in
Off state (Source)
IOff-Lkg-IN + IOff- Lkg-OUT
-12.5 V < VOUT < 12.5 V; VIN = 0 V;
EN = Low; +Vs = 15V; (-Vs) = -15
V, TPS26611/12/14 Only
-12.5 V< VIN <12.5 V; VOUT = 0 V;
EN = Low; +Vs = 15V; (-Vs) = -15
V ,TPS26611/12/14 Only
Leakage current from IN
pin in Off state (Source)
IOff-Lkg-IN
Leakage current from
OUT pin in Off state
(Source)
-12.5 V < VOUT < 12.5 V; VIN = 0 V;
EN = Low; +Vs = 15V; (-Vs) = -15
V ,TPS26611/12/14 Only
IOff-Lkg-OUT
–6
–1 µA
Overvoltage and Undervoltage Cutoff for OUT Pin
OUT Overvoltage
Protection Threshold,
Rising
TPS26610/11/13/14 Only
TPS26612 Only
(+Vs)+0.05
(+Vs)+1
(+Vs)+0.30
(+Vs)+1.50
V
V
VOUT_OVLO
VOUT_OVLO_hyst
VO/I_UVLO
OUT Overvoltage
Hysterises
30
75 mV
OUT/IN Undervoltage
Protection Threshold,
Falling
TPS26610/11/12 Only
(–Vs)-0.40
(–Vs)-0.20
V
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7.5 Electrical Characteristics (continued)
–40° C ≤ TA = TJ ≤ +125° C, 2.25 V < +Vs < 30 V, -20 V < -Vs < 0 V, MODE = GND, SGOOD = Open, EN = 3.3 V (All
voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OUT/IN undervoltage
Hysterises
VO/I_UVLO_hyst
TPS26610/11/12 Only
30
75 mV
OUT Undervoltage
Protection Threshold,
Falling
VO_UVLO
TPS26613/14 Only
TPS26613/14 Only
(–Vs)-0.40
30
(–Vs)-0.20
V
OUT undervoltage
Hysterises
VO_UVLO_hyst
75 mV
POWER SUPPLY PINS (+Vs/-Vs)
+Vs Supply Operating
Voltage
V(+Vs)
V(+Vs)
V(-Vs)
TPS26610/11/13/14
TPS26612 only
2.25
4
30
30
0
V
V
V
V
+Vs Supply Operating
Voltage
-Vs Supply Operating
Voltage
–20
3
Difference between +Vs
and -Vs
Vs_DIFF
50
Current sourced from
+Vs supply to GND in
normal operation
I(+Vs)
SGOOD = Floating
SGOOD = Floating
1.07
1.2
1.65 mA
1.75 mA
Current sourced from
+Vs supply to GND in
fault operation
I(+Vs)
Current sinked by -Vs
supply from GND
I(-Vs)
0.2 mA
OFF State Supply
Current
IVS_OFF
EN = Low (TPS26611/12/14 only)
0.27 mA
Loop Testing Vs/-Vs UNPOWERED (TPS26610/13 only)
Current Loop Testing : IN
to OUT Voltage drop
V(IN-OUT)no_Vs
IQno_Vs
+/-20mA current through IN pin
±5
±8.5
20
V
Percentage of forced IN
current going to -Vs pin
%
IOL_noVs
No supply current limit
±22
4.8
±45.5 mA
PASS FET
IN to OUT total ON
resistance
–40 ℃ < T < 125 ℃, I(IN)
Overload Current
<
RON
7.5
12.5
1.72
Ω
ENABLE (EN) TPS26611/12/14 Only
V(ENR) EN Rising Threshold
V(ENF)
V
V
EN Falling Threshold
1
EN Leakage Current
(Sink)
I(EN_LKG)
V(EN) = 5.5 V
V(EN) = 0 V
10 µA
µA
EN Leakage Current
(Source)
I(EN_LKG)
-10
V(EN)
EN Open Circuit Voltage I(EN) = –0.1 µA
2.1
2.5
V
VSNS (Supply Sensing) TPS26610/13 only
V(SNSR)
VSNS Rising threshold
VSNS Falling threshold
1.72
V
V
V(SNSF)
1
SIGNAL GOOD (SGOOD)
SGOOD Output Level,
HIGH
(+Vs) ≤ 2.5 V, 0 mA < ISGOOD < 1
mA
VOH_SGOOD
(+Vs)*(0.8)
(+Vs)
V
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7.5 Electrical Characteristics (continued)
–40° C ≤ TA = TJ ≤ +125° C, 2.25 V < +Vs < 30 V, -20 V < -Vs < 0 V, MODE = GND, SGOOD = Open, EN = 3.3 V (All
voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SGOOD Output Level,
HIGH
(+Vs) > 2.5 V, 0 mA < ISGOOD< 1
mA
VOH_SGOOD
RSGOOD
2
3
V
SGOOD pull down
impedance
0 µA < ISGOOD < 200 µA
6.3 kΩ
MODE
I(MODE)
MODE Source Current
Mode Selection Resistor
1.55
2
2.4 µA
kΩ
RMODE
180
THERMAL SHUTDOWN
Thermal Shutdown (TSD)
threshold, Rising
T(TSD)
160
11
°C
°C
Thermal Shutdown (TSD)
Hysterises
T(TSDHyst)
HART
BW
Input small signal
bandwidth
–25 mA < IIN < 25 mA, ΔIIN = 1
mApp at 1 kΩ
10
kHz
7.6 Timing Requirements
–40° C ≤ TA = TJ ≤ +125° C, 2.25 V < +Vs < 30 V, -20 V < -Vs < 0 V, MODE = GND, SGOOD = Open, EN = 3.3V (All voltages
referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Delay from +Vs/-Vs supply applied to
FET on, EN = Floating
tON_dly
Turn ON delay with Vs/-Vs supply
120
µs
Delay from +Vs/-Vs supply removed
to FET off, EN = Floating
tOFF_dly
Turn OFF delay with +Vs/-Vs supply
Turn ON delay with EN pin
10 µs
µs
+Vs/-Vs supply present, Delay from
EN HIGH to FET on,
tON_EN_dly
tOFF_EN_dly
120
+Vs/-Vs supply present, Delay from
EN LOW to FET off
Turn OFF delay with EN pin
10 µs
Load transient from 20 mA to 50 mA.
tOL
Overload Current Limit response time Time from Load Transient to Current
coming within 20%.of IOL
30
20
55 µs
50 µs
.
Load transient from 20 mA to 80 mA.
Time from Load Transient to Current
coming within 20% of IOL_Pulse
Pulse Overload Current Limit
response time
tOL_PULSE
MODE = GND, Current exceeding
120mA to FET off
5
5
µs
µs
µs
tFASTRIP
Fast-Trip Response Time
MODE = 180-kΩto GND or Open,
Current exceeding 240 mA to FET off
Deglitch delay during SGOOD
assertion
685
TSG_Deglitch
SGOOD Deglitch Delay
Deglitch delay during SGOOD de-
assertion
1.3 ms
V(OUT) ↑ 100 mV above VOUT_OVLO to
FET OFF
tOUT_OV_CUT
tO/I_UV_CUT
tO_UV_CUT
OUT OVLO Cutoff detection-time
1
1
1
5
5
5
µs
µs
µs
µs
OUT OR IN UVLO Cutoff
detectiontime
OUT/IN ↓100 mV below VO/I_UVLO to
FET OFF, TPS26610/11/12 Only
OUT ↓100 mV below VO_UVLO to FET
OFF, TPS26613/14 Only
OUT UVLO Cutoff detection-time
OUT Cutoff recovery time
V(OUT) ↓ 100 mV below
VOUT_OVLO_hyst to FET ON
tOUT_CUT_Rec
21
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7.6 Timing Requirements (continued)
–40° C ≤ TA = TJ ≤ +125° C, 2.25 V < +Vs < 30 V, -20 V < -Vs < 0 V, MODE = GND, SGOOD = Open, EN = 3.3V (All voltages
referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OUT/IN ↑100 mV above VO/
I_UVLO_hyst to FET ON,
TPS26610/11/12 Only
tO/I_CUT_Rec
IN OR OUT Cutoff recovery time
23.5
µs
OUT↑100 mV above VO_UVLO_hyst to
FET ON, TPS26613/14 Only
tO_CUT_Rec
OUT Cutoff recovery time
23.5
µs
tOL_Expiry
tOL_Pulse_Expiry
tOL_Extend
tRETRY1
Overload Current Limit expiry time
Pulse Overload Current expiry
IOL < I < IOL_PULSE expiry timer
Auto Retry Timer 1
Load transient from 20 mA to 50 mA
Load transient from 20 mA to 100 mA
100
50
ms
ms
s
5.00
0.80
1.60
s
tRETRY2
Auto Retry Timer 2
s
Auto Retry disabled time (TPS26612
only)
tAR_dis
5
s
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7.7 Typical Characteristics
+Vs = 15 V; –Vs = –15 V, MODE = OPEN, SGOOD = OPEN; EN/VSNS = OPEN; TA = 25º C (unless otherwise noted)
+Vs = 15 V; -Vs = GND; VIN = VOUT
VIN = VOUT = 0 V
Figure 7-1. IQ-ON (IN+OUT) vs VIN in Normal Operation
Figure 7-2. IQ (IN+OUT) vs Temperature in Normal Operation
+Vs = 30 V; –Vs = GND; VIN = VOUT + 1 V
VIN = VOUT - 1 V
Figure 7-3. IOL vs VIN for IOUT > 0
Figure 7-4. IOL vs VIN for IOUT < 0
Figure 7-6. IFast-trip vs Temperature for IOUT > 0
VIN = VOUT + 1.5 V; MODE = Open or 180 kΩ
Figure 7-5. IOL-Pulse vs VIN
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7.7 Typical Characteristics (continued)
+Vs = 15 V; –Vs = –15 V, MODE = OPEN, SGOOD = OPEN; EN/VSNS = OPEN; TA = 25º C (unless otherwise noted)
Figure 7-7. IFast-trip vs Temperature for IOUT < 0
VOUT = 0 V
Figure 7-8. (IOFF-Leakage-IN + IOFF-Leakage-OUT) vs VIN
VOUT = 0 V
VIN = 0 V
Figure 7-10. IOFF-Leakage-IN vs VIN
Figure 7-9. (IOFF-Leakage-IN + IOFF-Leakage-OUT) vs VOUT
Figure 7-12. OUT OVLO Thresholds (w.r.t Vs) vs Temperature
for TPS26611 and TPS26610
VIN = 0 V
Figure 7-11. IOFF-Leakage-OUT vs VOUT
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7.7 Typical Characteristics (continued)
+Vs = 15 V; –Vs = –15 V, MODE = OPEN, SGOOD = OPEN; EN/VSNS = OPEN; TA = 25º C (unless otherwise noted)
Figure 7-14. OUT and IN UVLO Thresholds (w.r.t -Vs) vs
Temperature
Figure 7-13. OUT OVLO Thresholds (w.r.t Vs) vs Temperature
for TPS26612
Figure 7-15. IVs vs Vs in ON State
Figure 7-16. IVs vs Vs in OFF State (EN = 0) for TPS26611 and
TPS26612
Figure 7-17. I-Vs vs -Vs in ON State
Figure 7-18. RON vs Temperature
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7.7 Typical Characteristics (continued)
+Vs = 15 V; –Vs = –15 V, MODE = OPEN, SGOOD = OPEN; EN/VSNS = OPEN; TA = 25º C (unless otherwise noted)
IOUT = 60 mA, MODE = 180 kΩ
Figure 7-20. Current Limit with MODE = GND
Figure 7-19. Thermal shutdown time vs Power Dissipation
Figure 7-21. Current Limit with MODE = OPEN
Figure 7-22. Auto Retry with MODE = 180 kΩ
Figure 7-23. Fast-Trip Protection
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8 Detailed Description
8.1 Overview
The TPS2661x is a family of devices providing complete protection for current inputs, voltage inputs/outputs, and
sensor supply in industrial and process automation systems. The device supports both unipolar 4-mA to 20-mA
current loops and bipolar ±20-mA current loops. The TPS26610 and TPS26613 are tailored for current inputs.
The device can be powered from an external supply and draws < 100-nA maximum current from the current
loop enabling design of high accuracy analog input systems. The devices feature an accurate 32-mA current
limit, which enables using low power components in the loop like the sense resistors, which reduces the overall
system size and cost. The TPS26611 and TPS26614 are specifically tailored for universal current inputs and
voltage/current multiplexed inputs while the TPS26612 is tailored for protection of two wire sensor transmitters.
The TPS2661x devices feature a configurable MODE pin to allow higher current for powering up of a variety
of two wire transmitters. The TPS26611 also has enable control for designing V/I multiplexed analog inputs or
universal analog input-output modules. The device also features a signal-good output to indicate if the there is
a valid current input. The signal good pin goes high in the event of any fault or during start-up of the system if
there is an inrush current. The device also protects the system from output miswiring in analog output modules
or sensor transmitters by cutting off the current path if the OUT pin goes outside the +/–Vs supply rails.
The robust protection of the TPS2661x along with its ±50-V rating helps to simplify the system designs for surge
compliance. The TPS2661x devices are immune to noise tests like electrical fast transients that are common
in industrial applications. These devices also simplify the system design for protection from surge transients
(IEC61000-4-5).
8.2 Functional Block Diagram
-ve IOUT
TPS26610
+ve IOUT
IOUT
Sense
IN
OUT
+
Ifast-trip
œ
Fast-
trip
Input
UV
+
Pass FET Drive
and Control
œ
IOL
Limiter
œ
VO/I_UVLO
+
Output
OV
œ
-Vs
Vs
+
VOUT_OVLO
∞
+
tOL_Expiry
tOL_Pulse_Expiry
tOL_Extend
IOL
IOL
Timer
Selection
œ
IOL
Threshold
Selection
VO/I_UVLO
Output
UV
2 x IOL
MODE
VSNS
TSG_Deglitch
D
SGOOD
Supply
Sensing
œ
V(SNSR)
V(SNSF)
RSGOOD
+
GND
Figure 8-1. Functional Block Diagram for TPS26610
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-ve IOUT
+ve IOUT
TPS26611 and TPS26612
IOUT
Sense
IN
OUT
+
Ifast-trip
œ
Fast-
trip
Input
UV
+
Pass FET Drive
and Control
œ
IOL
Limiter
+
œ
VO/I_UVLO
Output
OV
œ
-Vs
Vs
+
VOUT_OVLO
∞
+
tOL_Expiry
IOL
IOL
Timer
Selection
œ
IOL
Threshold
Selection
VO/I_UVLO
Output
UV
tOL_Pulse_Expiry
tOL_Extend
2 x IOL
MODE
TSG_Deglitch
D
SGOOD
Enable
Control
V(ENR)
V(ENF)
tON_EN_dly
RSGOOD
œ
EN
D
tOFF_EN_dly
+
IEN_LKG
V(EN)
GND
Figure 8-2. Functional Block Diagram for TPS26611 and TPS26612
-ve IOUT
TPS26613
+ve IOUT
IOUT
Sense
IN
OUT
+
–
Ifast-trip
Fast-
trip
Pass FET Drive
and Control
–
IOL
Limiter
VO_UVLO
+
Output
OV
–
+
-Vs
Vs
VOUT_OVLO
+
tOL_Expiry
tOL_Pulse_Expiry
tOL_Extend
IOL
IOL
Timer
Selection
–
IOL
Threshold
Selection
VO_UVLO
Output
UV
2 x IOL
MODE
VSNS
TSG_Deglitch
D
SGOOD
Supply
Sensing
–
V(SNSR)
V(SNSF)
RSGOOD
+
GND
Figure 8-3. Functional Block Diagram for TPS26613
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-ve IOUT
+ve IOUT
TPS26614
IOUT
Sense
OUT
IN
+
–
Ifast-trip
Fast-
trip
Pass FET Drive
and Control
–
IOL
Limiter
VO_UVLO
+
Output
OV
–
+
-Vs
Vs
VOUT_OVLO
+
tOL_Expiry
tOL_Pulse_Expiry
tOL_Extend
IOL
IOL
Timer
Selection
–
IOL
Threshold
Selection
VO_UVLO
Output
UV
2 x IOL
MODE
EN
TSG_Deglitch
D
SGOOD
Enable
Control
V(ENR)
V(ENF)
tON_EN_dly
RSGOOD
–
+
D
tOFF_EN_dly
IEN_LKG
V(EN)
GND
Figure 8-4. Functional Block Diagram for TPS26614
8.3 Feature Description
8.3.1 Overload Protection and Fast-Trip
The TPS2661x devices feature a fixed IOL value of 32-mA typical, bidirectional current limit. For use in unipolar
systems like 4–20-mA current loops where negative current is not desired, connect –Vs to GND to cut off when
there is a flow of reverse current (OUT to IN). If the current tries to exceed the IOL limit, the device regulates the
current, eventually reducing the output voltage. Overload current threshold and time for overload protection can
be selected by the MODE pin. See Device Functional Modes for details. The power dissipation across the device
during current regulation is (VIN – VOUT) × IOUT, which can heat up the device and lead to thermal shutdown.
After thermal shutdown, the device goes into auto retry. The mode pin selects the auto retry period. See Table
8-3 and Figure 8-24 for selection of the auto retry period.
The TPS2661x devices also feature a fast-trip comparator. During fast transient events like output short circuit,
miswiring, hotplug, and so forth, the current through the device increases rapidly. Due to limited bandwidth, the
current limit amplifier cannot respond quickly to these events . Hence, the fast-trip comparator architecture is
included for fast turn OFF of the internal FET during these events. The device turns off the internal FETs within
a time of t(FASTTRIP). See the Timing Requirements for t(FASTTRIP). The fast-trip circuit holds the internal FET
off for a short duration (50 μs), after which, the device turns back on slowly, allowing the current-limit loop to
regulate the output current to current limit as per MODE pin configuration. Figure 8-5 and Figure 8-7 illustrate the
current limit behavior of TPS2661x devices. Figure 8-8 illustrates the fast-trip protection of TPS2661x devices
and Figure 8-9 illustrates the auto-retry behavior in overload fault.
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-ve IOUT
+ve IOUT
IOUT
Sense
IN
OUT
+
IFASTRIP
Fasttrip
œ
Pass FET Drive
and Control
œ
IOL
Limiter
+
∞
IOL
tOL_Expiry
IOL
Threshold
Selection
IOL
Timer
Selection
tOL_Pulse_Expiry
tOL_Extend
2 x IOL
MODE
GND
Figure 8-5. Overload Protection and Fast-Trip
Figure 8-7. Current Limit Behavior for IOUT > 2 × IOL
with MODE = 180 kΩ
Figure 8-6. Current Limit Behavior for IOUT < 2 ×
IOLwith MODE = GND
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Figure 8-8. Fast-Trip Behavior
Figure 8-9. Auto-Retry Behavior
8.3.2 Reverse Current Blocking for Unipolar Current Inputs TPS26610, TPS26611 and TPS26612 (4–20
mA, 0–20 mA)
For reverse current blocking with TPS26610, TPS26611 and TPS26612 devices, connect burden resistor to
GND and use single supply (+Vs, GND) with the device as shown in Figure 8-10. In this configuration, the device
blocks the reverse current (OUT to IN) when IN pin voltage is negative.
+Vs
SGOOD
TPS26610
MODE
TPS26611
TPS26612
EN
VIN
VOUT
IN
OUT
I+
-Vs
GND
IOL > 0
ILOOP
Precision
Burden
Resistor
I-
GND
Figure 8-10. Reverse Current Blocking for Unipolar Current Inputs With TPS26610, TPS26611 and
TPS26612
8.3.3 OUTPUT and INPUT Cutoff During Overvoltage, Undervoltage Due to Miswiring
Table 8-1 summarizes the output and input cutoff present in TPS2661 devices
Table 8-1. Output and Input Miswiring Protection in TPS2661 Devices
Device
Output Overvoltage
Output Undervoltage
Input Undervoltage
TPS26610
TPS26611
TPS26612
TPS26613
TPS26614
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
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8.3.3.1 Output Overvoltage With TPS2661x Devices
The TPS2661x devices provide protection from overvoltage events on OUT pin by turning off the internal pass
FETs and cutting off the signal path whenever VOUT goes above VOUT_OVLO threshold. The signal path through
TPS2661x is restored again when VOUT goes below [VOUT_OVLO – VOUT_OVLO_Hyst] value. The device turns off
the internal FETs within a time of tOUT_OV_CUT after output voltage has gone above VOUT_OVLO threshold. See
Timing Requirements in Specifications for tOUT_OV_CUT.The device recovers from output overvoltage within a
time of tOUT_CUT_Rec after output voltage has gone below [VOUT_OVLO ‒ VOUT_OVLO_Hyst] value. See the Timing
Requirements in Specifications for tOUT_OV_CUT. Figure 8-11 illustrates the output overvoltage protection in
TPS2661x devices.
Figure 8-11. Output Overvoltage Protection
8.3.3.2 Output or Input Undervoltage With TPS26610, TPS26611 and TPS26612
TPS26610, TPS26611 and TPS26612 devices provide protection from undervoltage events on IN and OUT pins
by turning off the internal pass FETs and cutting off the signal path whenever VOUT or VIN goes below VO/I_UVLO
threshold. The signal path through the device is restored again when VOUT or VIN goes above [VO/I_UVLO
–
VO/I_UVLO_Hyst] value. The device turns off the internal FETs within a time of tO/I_UV_CUT after output or input
voltage has gone below VO/I_UVLO threshold. The device recovers from output or input undervoltage within a time
of tOUT_CUT_Rec after output or input voltage has gone above [VO/I_UVLO – VO/I_UVLO_Hyst] voltage. See the Timing
Requirements in Specifications for tO/I_UV_CUT and tOUT_CUT_Rec
IOUT
.
IN
OUT
Vs
Output
OV
œ
Pass FET Drive
and Control
+
VOUT_OVLO
+
+
-Vs
œ
Input
UV
Output
UV
œ
VO/I_UVLO
Figure 8-12. Output and Input Undervoltage Cutoff With TPS26610, TPS26611 and TPS26612
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In case of overvoltage, undervoltage and miswiring events on IN and OUT pins, voltages exceeding Absolute
Maximum Ratings (see Specifications) for IN and OUT Pins can damage the device. Figure 8-13 and Figure
8-14 illustrate the output and input undervoltage protection in these devices.
Figure 8-13. Output Undervoltage Protection
Figure 8-14. Input Undervoltage Protection
8.3.3.3 Output Undervoltage With TPS26613 and TPS26614
TPS26613 and TPS26614 devices provide protection from undervoltage events OUT pins by turning off the
internal pass FETs and cutting off the signal path whenever VOUT goes below VO_UVLO threshold. The signal
path through the device is restored again when VOUT goes above [VO_UVLO – VO_UVLO_Hyst] value. The device
turns off the internal FETs within a time of tO_UV_CUT after output voltage has gone below VO_UVLO threshold.
The device recovers from output undervoltage within a time of tOUT_CUT_Rec after output voltage has gone above
[VO_UVLO – VO_UVLO_Hyst] voltage. See the Timing Requirements in Specifications for tO_UV_CUT and tOUT_CUT_Rec
.
IOUT
IN
OUT
Vs
Output
OV
–
Pass FET Drive
and Control
+
VOUT_OVLO
+
–
-Vs
Output
UV
VO_UVLO
Figure 8-15. Output Undervoltage Cutoff in TPS26613 and TPS26614
8.3.4 External Power Supply (±Vs)
The TPS2661x devices are powered from an external +Vs/–Vs supply. This feature ensures that the TPS2661x
does not draw any current from the IN/OUT pins which carry current information. TPS26610 allows current
conduction from IN to OUT pins when +Vs/-Vs supplies are not present. TPS26611 and TPS26612 devices need
+Vs/–Vs or +Vs/GND for operation.
For systems requiring positive and negative voltage on IN and OUT pins of TPS2661x, use bipolar supplies (+Vs
and –Vs) with TPS2661x. Connect positive supply rail to +Vs and negative supply rail to –Vs pins. The device
supports dual supplies from as low as ±2.25 V up to ±20 V.
For systems requiring only positive voltage on IN and OUT pins of TPS2661x, use unipolar supply (+Vs and
GND) with TPS2661x .Connect positive supply rail to +Vs, and –Vs pin must be connected to GND of device.
When powered from single supplies, TPS26610, TPS26611, TPS26613 and TPS26614 devices can be powered
from +3 V up to +30 V and TPS26612 can be powered from +4 V up to +30 V.
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The device turns on the internal FETs with a delay time of tON_dly after powering up of +Vs supply and turns off
the internal FET with a delay time of tOFF_dly after powering down of +Vs supply. See the Timing Requirements in
Specifications for tON_dly and tOFF_dly
.
8.3.5 Loop Testing Without ±Vs Supply (Loop Power Mode in TPS26610, TPS26613 Only)
TPS26610 and TPS26613 devices allow a bipolar current limited conduction through the device even when the
external +Vs/–Vs supplies are not there. When the external supply is not there, the device switches to loop
power mode and derives its operating power from the 4–20-mA or ±20-mA current loop. This feature enables the
field installation engineer to check the wiring of the whole current loop system by passing a test current through
the current loop without actually powering on the system. This feature also helps in design of safety critical
redundant systems with two redundant measurements for the same current loop. In case power is not available
in one system, a second system connected in the loop is still be able to read the current information because the
loop is not broken. During loop testing without ±Vs supply, the device has a voltage drop of V(IN-OUT)no_Vs, the
current through device is limited to IOL_noVs. During loop testing, the device draws a current of IOL_noVs from IN
pin. See the Electrical Characteristics in Specifications for V(IN-OUT)no_Vs, Iqno_Vs and IOL_noVs
.
The device provides thermal protection during loop testing, if the power dissipation in device increases above
500 mW (typical), the devices turns off internal FET for short durations to limit the power dissipation. Figure 8-16
and Figure 8-17 illustrate the thermal protection during loop testing.
+Vs = 15 V, –Vs = –15 V, ROUT = 250 Ω, VIN = 21 V
+Vs = 15 V, –Vs = –15 V, ROUT = 250 Ω, VIN = –21 V
Figure 8-16. Thermal Protection During Loop
Testing for ILOOP > 0
Figure 8-17. Thermal Protection During Loop
Testing for ILOOP < 0
8.3.5.1 Supply Sensing With VSNS for Loop Power Mode With TPS26610 and TPS26613
For the TPS26610 and TPS26613 devices, the set-point for transition to loop power mode can be set by
connecting resistors (R1, R2) from +Vs pin to VSNS pin and GND pin as shown in Figure 8-18. The set-point
can be calculated as per Table 8-2. TI recommends to use resistors R1 and R2 for supply sensing when voltage
across burden resistor (ILOOP × RBurden) is more than 1.8 V. If VSNS is left open or floating, the device transitions
to loop power mode when +Vs is less than 1.8 V.
Table 8-2. Supply Sensing With VSNS for Loop Power Mode
Device Power Mode
+Vs Voltage
±Vs supplies
+Vs ≥ V(SNSR) × (R1 + R2) / R2(1)
(2)
Loop power
+Vs ≤ V(SNSF) × (R1 + R2) / R2(1)
(1) Use (R1 + R2) ≤ (+Vs) / (45 μA). For V(SNSR) and V(SNSF) values, see the Electrical Characteristics.
(2) Keep V(SNSF) × (R1 + R2) / R2 > (ILOOP × RBurden
)
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+Vs
R1
VSNS
MODE
I+
TPS26610
TPS26613
OUT
IN
-Vs
GND
ILOOP
RBurden
VOUT = ILOOP X RBurden
I-
GND
Figure 8-18. Supply Sensing With VSNS
+Vs = 15 V, –Vs = –15 V, ROUT = 250 Ω, MODE = GND
+Vs = 15 V, –Vs = –15 V, ROUT = 250 Ω, MODE = GND
Figure 8-19. Transition to Loop Power With R1 = 47 Figure 8-20. Transition to ± Vs Supplies Power with
kΩ and R2 = 6.8 kΩ for Supply Sensing R1 = 47 kΩ and R2 = 6.8 kΩ for supply Sensing
8.3.6 Enable Control With TPS26611, TPS26612, and TPS26614
TPS26611, TPS26612, and TPS26614 devices feature an EN pin for externally controlling the device through a
GPIO pin. To enable the device, EN pin can be left floating. The pin is internally pulled up with V(EN)
.
EN can also be made high with external voltage more than V(ENR) but less that or equal to 5 V. The internal FETs
are turned off when EN is pulled below V(ENF). EN pin can source and sink a current of I(EN_LKG). See Electrical
Characteristics for V(ENF), V(ENR) and I(EN_LKG). The EN feature helps the system designer to design universal
voltage and current analog inputs and outputs where a lot of pin multiplexing options are made available to the
end user. For turn-on and turn-off delay with EN pin, see tON_EN_dly and tOFF_EN_dly in Timing Requirements.
Figure 8-22 and Figure 8-23 illustrate the turn-on and turn-off control with enable pin.
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IOUT
IN
OUT
Pass FET Drive
and Control
Enable
Control
œ
V(ENR)
V(ENF)
tON_EN_dly
EN
D
tOFF_EN_dly
+
IEN_LKG
V(EN)
Figure 8-21. Enable Control
Figure 8-22. Turn-On With EN Pin
Figure 8-23. Turn-Off With EN Pin
8.3.7 Signal Good Indicator (SGOOD)
The TPS2661x provides an indication of the current signal flowing through pass FETs on the SGOOD pin.
Whenever the device is in normal operating condition, the SGOOD gives a signal LOW output. However in below
cases when the device is outside normal operating condition, the SGOOD pin goes HIGH:
•
•
•
•
Device current is > IOL (32-mA typical)
OUT goes outside +Vs/–Vs supply
IN goes below –Vs supply rail (for TPS26610, TPS26611, and TPS26612 only)
Device shuts down due to thermal limit or current limit
The SGOOD pin is also capable of driving an external LED to give a visual indication whenever the system is
outside normal operating conditions.
The SGOOD pin sourcing current is derived from +Vs supply rail. For de-glitch delays in assertion and de-
assertion of SGOOD, see TSG_Deglitch in Timing Requirements in Specifications.
8.4 Device Functional Modes
The device can provide higher current up to 2 × IOL for short durations. MODE pin of the device configures the
behavior of the device for higher current. Table 8-3 and Figure 8-24 describe the device behavior in different
modes for IOL > 0.
With MODE = GND, the device limits the current to IOL value for IOUT > IOL
.
With MODE = OPEN, the device limits the output current as:
•
For IOL < IOUT < 2 × IOL, the device allows current up to 2 × IOL for a duration of tOL_Pulse_Expiry and then limits
the current to IOL value for a duration tOL_Expiry
.
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•
For 2 × IOL < IOUT < I(FASTRIP), the device limits the current 2 × IOL value and for a duration of tOL_Pulse_Expiry
and then limits the current to IOL value for a duration tOL_Expiry
.
After the completion of tOL_Expiry period, the device goes into auto-retry.
With MODE = 180 kΩ, the device limits the output current as:
•
•
For IOL< IOUT < 2 × IOL, the device allows current up to 2 × IOL for a duration of tOL_Extend and then limits the
current to IOL value for a duration tOL_Expiry
For 2 × IOL < IOUT < I(FASTRIP), the device limits the current 2 × IOL value and for a duration of tOL_Pulse_Expiry
and then limits the current to IOL value for a duration tOL_Expiry
.
.
After the completion of tOL_Expiry period, the device goes into auto-retry. If the device heats up during overload
and the device temperature exceeds T(TSD) value, the device turns off the internal pass FETs. As the device
cools down and its temperature goes below [T(TSD) – T(TSDHyst)] value, the device goes into auto-retry.
Table 8-3. Device Operation Under Different MODE Configurations for IOL > 0
Auto-
Retry
Time
MODE Pin
Configuration
IOUT < IOL
(32 mA)
IOL (32 mA) < IOUT < 2 × IOL (60 mA)
2 × IOL (60 mA) < IOUT < I(FASTRIP)
Current limited to IOL for a duration of tOL_Expiry
Current flows (100 ms).
Current limited to IOL for a duration of
tOL_Expiry (100 ms).
tRETRY1
(800 ms)
Shorted to GND
normally
tOL_Expiry (100 ms) timer starts when IOUT exceeds tOL_Expiry (100 ms) timer starts when IOUT
IOL exceed IOL
.
.
Current limited to 2 × IOL for tOL_Pulse_Expiry
(50 ms) time after which it is limited to IOL
for tOL_Expiry (100 ms) time and then auto
retry.
Device allows current for tOL_Pulse_Expiry (50 ms)
time after which it is limited to IOL for tOL_Expiry
(100 ms) time and then auto retry.
Current flows
normally
tRETRY1
(800 ms)
Open
tOL_Pulse_Expiry (50 ms) timer starts when IOUT
tOL_Pulse_Expiry (50 ms) timer starts when
exceeds IOL
.
IOUT exceeds IOL
.
Current limited to 2 × IOL for tOL_Pulse_Expiry
(50 ms) time after which it is limited to IOL
for tOL_Expiry (100 ms) time and then auto
retry.
Device allows current for tOL_Extend (5 s) time after
which it is limited to IOL for tOL_Expiry (100 ms) time
and then auto retry.
180 kΩ from
MODE to GND
Current flows
normally
tRETRY2
(1.6 s)
tOL_Extend (5 s) timer starts when IOUT exceeds
tOL_Pulse_Expiry (50ms) timer starts when
IOL
.
IOUT exceeds IOL
.
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MODE = GND
2 × IOL
2 × IOL
2 × IOL
IOL
IOL
IOL
tRetry1
tRetry1
tOL_Expiry
tOL_Expiry
time
time
time
MODE = OPEN
2 × IOL
2 × IOL
2 × IOL
IOL
IOL
IOL
tOL_Pulse_Expiry
tOL_Pulse_Expiry
tOL_Expiry
tRetry1
tOL_Expiry
tRetry1
time
time
time
MODE = 180kΩ
2 × IOL
2 × IOL
2 × IOL
IOL
IOL
IOL
tOL_Extend
tOL_Pulse_Expiry
tRetry2
tOL_Expiry
tRetry2
tOL_Expiry
time
time
time
Case C:
2 × IOL< IOUT < IFASTRIP
Case A:
IOUT < IOL
Case B:
IOL< IOUT < 2 × IOL
Figure 8-24. Device Operation Under Different MODE Configurations for IOL > 0
Table 8-4 and Figure 8-25 describe the device behavior in different modes for IOL < 0.
Table 8-4. Device Operation Under Different MODE Configurations for IOL < 0
–2 × IOL(–60 mA) < IOUT
–IOL (–32 mA)
<
–I(FASTRIP) < IOUT < –2 ×
IOL (–60 mA)
MODE Pin Configuration
IOUT > –IOL (–32 mA)
Auto-Retry Time
Current limited to IOL for a Current limited to
duration of tOL_Expiry (100 IOL for a duration
Shorted to GND or Open
or 180 kΩ from MODE to Current flows normally
GND
ms).
of tOL_Expiry (100ms).
tRETRY1 (800 ms)
tOL_Expiry (100 ms) timer
tOL_Expiry (100ms) timer
starts when IOUT exceeds starts when IOUT exceed
IOL IOL.
.
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MODE = GND, MODE = OPEN OR MODE = 180kΩ
time
time
time
tOL_Expiry
tRetry1
tOL_Expiry
tRetry1
-IOL
-IOL
-IOL
-2 × IOL
-2 × IOL
-2 x IOL
Case C:
-IFASTRIP < IOUT < -2 x IOL
Case B:
-2 x IOL < IOUT < -IOL
Case A:
IOUT > -IOL
Figure 8-25. Device Operation Under Different MODE Configurations for IOL < 0
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS2661x is an industrial current loop protector, providing a robust signal line protection in a wide range of
industrial and automation systems. It is suitable for protection of all kinds of current loops like the 4–20-mA or
±20-mA current loops. TPS26610 is suitable for protection in current inputs whereas TPS26611 is suitable for
protection in multiplexed V/I inputs.
TPS26612 is suitable for protection in power supply of two wire current transmitters. With disabled auto-retry
time for first overload event, TPS26612 enables startup of power hungry transmitters requiring higher start up
current for longer durations.
TPS26611 and TPS26612 devices can be also used to protect voltage outputs or digital communication signals
like UART from miswiring of power supplies at these outputs. The device breaks the signal path by turning off
the FETs when there is a voltage higher than supply voltage and thus keeping the system protected.
TPS2661x provides complete protection from industrial surge transients (IEC61000-4-5) and provides immunity
from industrial fast transients (IEC610000-4-4) for signal lines.
9.2 Typical Application: Analog Input Protection for Current Inputs with TPS26610
Current Input in Analog Input Module
+Vs
TPS26610
Field Transmitter Output: 20mA
GND A
D1*
SGOOD
MODE
I+
IN
OUT
+Vs
-Vs
RFLT
GND
+
AINx
AINy
œ
CFLT
TVS3301
or Similar
ADC
RBurden
RFLT
ILOOP
I-
-Vs
GND A
D2*
GND B
SW1
Open: For Floating Burden Resistor
Closed: For Burden Resistor connected to GND
GND A
GND A
x no. of channels
Figure 9-1. Current Input Protection in AI Module
A. TVS Diodes D1*, D2* are required for protection from surge transients (IEC61000-4-5) when burden resistor is floating (SW1 = Open).
TPS26610 can be used for protection of current inputs in an Analog Input module as shown in Figure 9-1. The
current signal is measured by ADC across Rburden. Bipolar current limit of ±32 mA ensures that the precision
burden resistor as well as the ADC front end stays well protected against any unwanted voltages or currents
caused due to faulty transmitter or miswiring. High Voltage rating of IN pin of TPS26610 ensures that it also
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protects the system from surge and EFT events as well. For reverse current blocking (OUT to IN), connect
burden resistor to GND (SW1 = Closed) and used single supply (+Vs,GND) with TPS26610.
9.2.1 Design Requirements
Table 3 shows the design requirements for current input protection with TPS26610.
Table 9-1. Design Requirements
DESIGN PARAMETER
Input current
EXAMPLE VALUE
±20 mA
I(IN)
V(IN)
Input voltage
–Vs to 50 V
±Vs
V(OUT)
I(LIM)
Output voltage
Current limit
±30 mA
RBurden
Burden resistance
50 to 250 Ω
9.2.2 Detailed Design Procedure for Current Inputs with TPS26610
9.2.2.1 Selecting ±Vs Supplies for TPS26610
Select the ±Vs supplies for TPS2661x devices higher than absolute analog input voltage for ADC inputs.
TPS2661x devices have undervoltage and overvoltage protection on OUT pin and the internal FETs are turned
off if OUT pin has voltage higher than +Vs or lower than –Vs.
TPS2661x devices also have undervoltage protection on IN pin and the internal FETs are turned off if IN pin has
a voltage lower than –Vs. See External Power Supply for using unipolar or bipolar supply with TPS2661x.
9.2.2.2 Selecting RBurden
The value of Rburden must be selected to meet the analog the input range of the ADC for the loop current range.
In case of miswiring faults to field supplies, the maximum current and power dissipated in Rburden is decided by
MODE configuration of TPS26610 device.
Table 9-2. Selection of Rburden
Maximum Current in
Rburden(mA)
Maximum Power Dissipated in
Rburden (mW)
Rburden (Ω)
MODE Configuration
MODE = GND
50
100
250
50
40
40
40
70
70
70
80
160
MODE = GND
MODE = GND
400
MODE = OPEN or 180 kΩ
MODE = OPEN or 180 kΩ
MODE = OPEN or 180 kΩ
245(1)
490(1)
1225(1)
100
250
(1) Power dissipated only for a pulse duration of 50 ms
9.2.2.3 Selecting MODE Configuration for TPS26610
For minimum power dissipation in burden resistor, use MODE = GND. See Device Functional Modes for
selecting the mode configuration.
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9.2.3 Application Performance Plots for Current Inputs with TPS26610
Figure 9-2. Current Limiting with MODE = GND,
Rburden = 50 Ω
Figure 9-3. Current Limiting with MODE = OPEN,
Rburden = 50 Ω
Figure 9-4. Power Dissipation in Rburden = 250 Ω
with MODE = GND
Figure 9-5. IEC61000-4-5 (+1 kV, 42 Ω) Signal Line
Surge immunity with TVS3301 at IN
Figure 9-6. IEC61000-4-5 (–1 kV, 42 Ω) Signal Line
Surge immunity with TVS3301 at IN
Figure 9-7. Reverse Current blocking with VIN = –
12 V, –VS = GND and SW1 = Closed
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9.3 Typical Application: Analog Input Protection for Multiplexed Current and Voltage Inputs
with TPS26611
œ
+
Multiplexed V,I Input in Analog Input Module
GND
+Vs
D1*
RFLT
AIN0
AIN1
+Vs
CFLT
Vsignal
SGOOD
EN
AINP
AINM
TPS26611
ADC
MUX
MODE
VIN
RFLT
V+, I+
VOUT
AINx
IN
OUT
Isignal
Vsource
10V
+
AINCOM
-Vs
GND
œ
CFLT
TVS3301
or Similar
ILOOP
OR
RBurden
GND
Isource
20mA
4-20mA
RFLT
V-, I-
SW1
Open: For Floating Burden Resistor
D2*
Closed: For Burden Resistor connected to GND
œ
-V
+
s
GND
GND
x no. of channels
Figure 9-8. Protection for Multiplexed V/I Inputs in AI Module
A. Bias Resistors R1*, R2* are required for setting the common mode voltage for voltage input (EN = 0) when burden resistor is floating
(SW1 = Open).
B. Diodes D1*, D2* are required surge protection when burden resistor is floating (SW1 = Open).
TPS26611 can be used for protection of multiplexed inputs in an Analog Input module as shown in Figure 9-8.
For this configuration, connect the IN pin of TPS26611 to one channel of the ADC for voltage measurement and
connect OUT pin of TPS26611 to the other channel of ADC for current measurement. EN pin of TPS26611 can
be used to swtch between current and voltage measurements. With EN = 0, the internal FETs of TPS26611 are
turned off and voltage signal can be measured by ADC between AIN0 and AINCOM pins. Whereas with EN =
1, the internal FETs of TPS26611 are turned on and current signal can be measured by ADC between AINx and
AINCOM pins.
9.3.1 Design Requirements
Table 9-3. Design Parameters
PARAMETER
Input Current (IIN)
Input Voltage (VIN)
Current Limit for (IIN)
RBurden
VALUE
±20 mA
± 10 V
±32 mA
50 to 250 Ω
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9.3.2 Detailed Design Procedure for Analog Input Protection for Multiplexed Current and Voltage Inputs
with TPS26611
9.3.2.1 Selecting ±Vs Supplies for TPS26611
See Vs supply selection in Typical Application: Analog Input Protection for Current Inputs with TPS26610.
9.3.2.2 Selecting MODE Configuration for TPS26611
For minimum power dissipation in burden resistor, use MODE = GND. See Device Functional Modes for
selecting the mode configuration.
9.3.2.3 Selecting Bias Resistors R1, R2 for Setting Common Mode Voltage for Voltage Inputs
For setting the common mode voltage with floating burden resistor (SW1 = Open), bias resistor R1 and R2 are
required.
Resistors R1, R2 provide low impedance path for off state (EN = 0) leakage currents from IN and OUT pins
of TPS26611. R1, R2 are selected to keep bias current less than 4 μA through these resistors for current
measurements with Rburden (EN = 1).
Table 9-4. Selection of Bias Resistors R1, R2
Analog Input Voltage for
ADC
Bias Current Through
R1, R2
±Vs Supplies
R1
R2
±10 V
±12.5 V
±15 V
±15 V
±15 V
±18 V
< 4 μA
< 4 μA
< 4 μA
1.39 to 1.66 MΩ
1.35 to 1.71 MΩ
1.29 to 1.75 MΩ
6.67 to 6.94 MΩ
6.62 to 6.98 MΩ
6.58 to 7.04 MΩ
9.3.3 Application Performance Plots for V/I Inputs with TPS26611
In addition to current limiting, reduced power dissipation in burden resistor, reverse current blocking and surge
protection illustrated in Application Performance Plots for Current Inputs with TPS26610, TPS26611 provides
enable control for selecting between voltage and current inputs.
Figure 9-9. Enable Control with TPS26611 (EN =
Low)
Figure 9-10. Enable Control with TPS26611 (EN =
High)
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9.4 System Examples
9.4.1 Power Supply Protection of 2-Wire Transmitter with TPS26612
24V Power Supply Input
ANALOG INPUT MODULE
+Vs
D1*
OUT
IN
GND
SGOOD
EN
MODE
TPS26612
-Vs
GND
2 Wire
Transmitter
+Vs
SGOOD
EN
TPS26612
+Vs
MODE
4-20mA Current
IN
OUT
IIN
ADC
-Vs
GND
Precision
Burden
Resistor
GND
GND
x no. of channels
Figure 9-11. Power Supply Protection for 2-Wire Transmitter with TPS26612
TPS26612 can be used for protection of power supply powering a two wire field transmitter as shown in Figure
9-11. Connect an external signal diode (D1) from IN to +Vs pin of TPS26612 in case of external field supply to
protect the system from miswiring. In case the supply is internal to the module and miswiring is not a possibility,
the signal diode (D1) is not needed. TPS26612 device includes higher threshold for overvoltage protection on
OUT to accommodate the voltage drop of diode (D1) between IN and +Vs.
TPS26612 has over-load expiry time (tOL_expiry) disabled for the first overload fault after power-up up to a
duration of tAR_dis (5 sec). With overload expiry time disabled, TPS26612 is able to power up 2-wire transmitters
requiring higher start-up for longer durations (up to 5 sec.). The current limit threshold (IOL or 2 x IOL) for startup
can be selected by MODE pin.
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VIN = 24 V, COUT = 1 mF
VIN = 24 V, COUT = 1 mF
Figure 9-12. TPS26612: Startup of 2-Wire
transmitter with MODE = GND, IOUT = 30 mA
Figure 9-13. TPS26612: Startup of 2-Wire
transmitter with MODE = Open, IOUT = 60 mA
During the first overload fault, if the junction temperature reaches TSD, the device turns off the internal FETs and
turns on as the junction temperature goes below [TTSD – TTSDHyst].
9.4.2 Protection of 3-Wire Transmitters and Analog Output Modules With TPS26611, TPS26612
ANALOG OUTPUT MODULE or 3-Wire Transmitter
24VIN
+Vs
SGOOD
MODE
+Vs
DAC
Output
EN
TPS26611/12
OUT
-Vs
+
DAC
Amplifier
-
IN
OUT
Sense
GND
R1
-Vs
TVS3301
or Similar
D1*
GND
GND
Diode (D1) is required for Signal line Surge (IEC61000-4-5) protection.
Figure 9-14. Analog Output Protection with TPS26611 or TPS26612
TPS26611 or TPS26612 can be used for protection of the analog output a 3/4-wire transmitter and analog output
module against any high voltage field miswiring as shown in Figure 9-14. The OUT pin voltage is monitored
with respect to the +Vs/–Vs supply voltages. If the OUT voltage goes outside the +Vs/–Vs supply rails, the
FETs cutoff current conduction path and protects the whole system.The voltage at OUT pin of TPS2661x can be
sensed by DAC amplifier to compensate for RON of TPS2661x
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Figure 9-15. 1.2-kHz HART Signal Through
Figure 9-16. 2.2-kHz HART Signal Through
TPS2661x with ROUT = 250 Ω
TPS2661x with ROUT = 250 Ω
9.4.3 UART IO Protection With TPS26611, TPS26612
TPS26611 or TPS26612 can be used for protection of UART IO lines as shown in Figure 9-17. The OUT pin
voltage is monitored with respect to the +Vs/–Vs supply voltages. If the OUT voltage goes outside the +Vs/–Vs
supply rails, the FETs cutoff the current conduction path and protects the whole system.
+Vs
TPS26611/
TPS26612
RX
IN
OUT
-Vs
GND
+Vs
UART
TPS26611/
TPS26612
OUT
IN
TX
-Vs
GND
Figure 9-17. UART IO Protection
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Figure 9-18. 115.2-Kbps UART Signal Through TPS2661x with Vs of 5 V
Figure 9-18 shows a UART signal of 115.2 Kbps through TPS2661x with amplitude of 4 V.
9.4.4 Higher Loop Impedance With TPS26613 and TPS26614
TPS26613 and TPS26614 devices can support higher loop impedance by providing auto-retry feature when
input voltage is less than –Vs. TPS26613 and TPS26614 devices do not have UVLO protection on input and
provide auto-retry for transmitter output supporting higher loop impedance. Figure 9-19 provides the behavior of
TPS26613 device with input voltage less than –Vs.
Figure 9-19. Auto-Retry in TPS26613 and TPS26614 for Vin < –Vs
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10 Power Supply Recommendations
Table 10-1. Power Supplies for TPS2661x Devices
Device
TPS26610,
TPS26611,
TPS26613,
TPS26614
Dual Supply (±Vs)
+Vs: 2.25 V to 30 V, –Vs: –20 V to 0 V
+Vs: 2.25 V to 30 V, –Vs: –20 V to 0 V
Single Supply (+Vs, GND)
+Vs: 3 V to 30 V, –Vs: GND
TPS26612
+Vs: 4 V to 30 V, –Vs: GND
For operation with dual supplies, TPS2661x devices need a minimum difference of 3 V between +Vs and –Vs.
For reverse current blocking with single supply, see Reverse Current Blocking for Unipolar Current Inputs (4–20
mA, 0–20 mA).
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11 Layout
11.1 Layout Guidelines
•
•
•
Keep the loop current power-path as short as possible.
Place RMODE resistor close to MODE and GND pins of the device.
For protection from IEC61000-4-5 surge transients (signal lines) on input, place the TVS close to IN pin of the
device.
•
•
•
•
Place at least 100-nF ceramic capacitors close to the device if power supplies for ±Vs are far from the device.
Connect GND pin of the device to GND of ±Vs supplies.
Route both terminals of Rburden differentially to ADC inputs (AINP, AINM).
Keep EN and SGOOD signal lines away from loop current to avoid digital noise.
11.2 Layout Example
Top Layer
Bottom Layer
RMODE
GND
MODE
-Vs
SGOOD
EN/VSNS
100nF
0603
Optional
100nF
0603
Optional
-Vs
+Vs
TPS2661x
+Vs
OUT
IN
ILOOP+
10.4 mm
TVS3301
AINP
[For IEC61000-4-5 Signal
Line Surge]
125mW
RBurden
0805
ILOOP-
AINM
Area = 120 mm2
11.5 mm
Figure 11-1. Layout Example
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS26610DDFR
TPS26611DDFR
TPS26612DDFR
TPS26613DDFR
TPS26614DDFR
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDF
DDF
DDF
DDF
DDF
8
8
8
8
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2HSF
2HTF
2HUF
2L4F
2L5F
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS26610DDFR
TPS26611DDFR
TPS26612DDFR
TPS26613DDFR
TPS26614DDFR
SOT-
23-THIN
DDF
DDF
DDF
DDF
DDF
8
8
8
8
8
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
SOT-
23-THIN
SOT-
23-THIN
SOT-
23-THIN
SOT-
23-THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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20-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS26610DDFR
TPS26611DDFR
TPS26612DDFR
TPS26613DDFR
TPS26614DDFR
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
DDF
DDF
DDF
DDF
DDF
8
8
8
8
8
3000
3000
3000
3000
3000
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.4
0.2
8X
0.1
C A
B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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