TPS272C45_技术文档

TPS272C45

SLVSF24A – DECEMBER 2020 – REVISED DECEMBER 2021

TPS272C45 45-mΩ, Dual-Channel Smart High-Side Switch With Diagnostics

1 Features

3 Description

•

Low R_ON(45-mΩ typical) high-side switch for 24-V

industrial applications

Wide DC operating voltage range: 6 V to 36 V

Low quiescent current (Iq) of 0.5 mA per channel

(typical) from 24-V supply

Fixed (5.8 A) and adjustable (0.7 A to 4 A with

external resistor) current limiting

Drive inductive, capacitive, and resistive loads

– Integrated output clamp to support inductive

load discharge

– Capacitive load drive minimizing peak inrush

current through dual threshold current limiting

Robust output protection

– Thermal shutdown

– Protection against short to ground events

– Configurable fault handling

TPS272C45 is a dual-channel smart high-side switch

designed to meet the requirements of industrial

control systems. The low R_DSON(45 mΩ) minimizes

device power dissipation driving a wide range (100

mA to 3 A) of output load current. TPS272C45

provides an additional low voltage supply (3.3 V to

5 V) input pin to minimize no-load power dissipation.

The device integrates protection features such as

thermal shut down, output clamp, and overcurrent

limit. These features improve system robustness

during fault events such as short circuit.

•

TPS272C45 implements an adjustable threshold

current limiting circuit that improves the reliability

of the system by reducing inrush current when

driving large capacitive loads and minimizing overload

current. The device also implements a configurable

inrush current time period with a higher level of

allowed current to drive high inrush current loads like

lamps or for fast charging of capacitive loads. The

device also provides an accurate load current sense

that allows for improved load diagnostics enabling

better predictive maintenance.

•

Enhanced diagnostic feature

– Output load current measurement

– Open load (off-state) detection

Package: 24-pin QFN (5 mm × 4 mm)

Functional Safety-Capable

– Documentation available to aid functional safety

system design

•

TPS272C45 is available in a small 24-pin, 5 mm ×

4 mm QFN leadless package with 0.5 mm pin pitch

minimizing the PCB footprint.

2 Applications

•

Industrial PLC systems

– Digital output modules

– IO-Link master ports

Motor drives

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

TPS272C45

QFN (24)

5 mm × 4 mm

Building automation systems

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

24-V Power Supply

5-V/3.3-V Power

VS

Supply (Optional)

VS

TPS272C45

UV/OV

Detection

Internal Power

Supply

FET Vds Clamp

VDD

GND

VDD

GND

EN1

EN2

EN1

EN2

VOUT1

VOUT2

Gate Driver

Power FET

Channel 1/2

FLT

OUT1

MCU

DIA_EN

SEL

LATCH

ILIM1

ILIM2

ILIMD

Current Limit

To Inductive,

SNS

Thermal

Shutdown

Capacitive and

Resistive Load

R_SNS

FLT

DIA_EN

SEL

ILIM1

ILIM2

ILIMD

OUT2

Open-load

detection

Fault Indication

SNS

R_ILIM1

R_ILIM2

SNS Mux

Current Sense

R_ILIMD

GND

Typical Application Schematic

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

DATA.

TPS272C45

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SLVSF24A – DECEMBER 2020 – REVISED DECEMBER 2021

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

6.1 Recommended Connections for Unused Pins............6

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings........................................ 7

7.2 ESD Ratings............................................................... 7

7.3 Recommended Operating Conditions.........................7

7.4 Thermal Information....................................................8

7.5 Electrical Characteristics.............................................8

7.6 SNS Timing Characteristics...................................... 12

7.7 Switching Characteristics..........................................12

7.8 Typical Characteristics..............................................14

8 Parameter Measurement Information..........................16

9 Detailed Description......................................................18

9.1 Overview...................................................................18

9.2 Functional Block Diagram.........................................19

9.3 Feature Description...................................................19

9.4 Device Functional Modes..........................................39

10 Application and Implementation................................40

10.1 Application Information........................................... 40

10.2 Typical Application.................................................. 43

11 Power Supply Recommendations..............................48

12 Layout...........................................................................49

12.1 Layout Guidelines................................................... 49

12.2 Layout Example...................................................... 49

13 Device and Documentation Support..........................50

13.1 Documentation Support.......................................... 50

13.2 Receiving Notification of Documentation Updates..50

13.3 Support Resources................................................. 50

13.4 Trademarks.............................................................50

13.5 Electrostatic Discharge Caution..............................50

13.6 Glossary..................................................................50

14 Mechanical, Packaging, and Orderable

Information.................................................................... 51

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (December 2020) to Revision A (December 2021)

Page

•

Changed status from "Advance Information" to "Production Data".....................................................................1

2

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SLVSF24A – DECEMBER 2020 – REVISED DECEMBER 2021

5 Device Comparison Table

Integrated

Clamp for

Inductive Loads

Low

Device

Fault Diagnosis

Current Limit

Advantage

Voltage

Regulator

Lower device power dissipation with most of

the quiescent current drawn from the lower

voltage supply input – enables reduced total

heat dissipation and thus smaller module

sizes. Connect a 3.3V DC-DC regulator output

to VDD pin.

Single FLT pin,

SNS pin provides

per -ch fault

Dual level, inrush

period

TPS272C45A

No

Yes

Single fault pin reduces IO count.

Single FLT pin,

SNS pin provides

per -ch fault

Lower system costs with a single power

supply (cost of a low voltage regulator is

avoided).

TPS272C45B

Dual level, inrush

period

Yes

No

(1)

Enables usage of external TVS Clamp for high

inductive loading.

The device variant can be used with an

Single FLT pin,

SNS pin provides

per -ch fault

TPS272C45C

Dual level, inrush

period

(1)

external supply on VDD pin or using the

internal 3.3-V regulation by GNDing the VDD

pin.

Dual FLT pins provides easier fault diagnosis.

The device variant can be used with an

external supply on VDD pin or using the

internal 3.3-V regulation by GNDing the VDD

pin.

Dual fault FLT1/

FLT2 pins

TPS272C45D

Yes

Single level

(1) PRODUCT PREVIEW

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SLVSF24A – DECEMBER 2020 – REVISED DECEMBER 2021

6 Pin Configuration and Functions

1

19

18

17

VDD

ILIMD

GND

EN1

OUT1

2

OUT1

3

OUT1

4

NC

PowerPad^TM

16

15

5

EN2

OUT2

6

OUT2

14

13

LATCH

SEL

7

OUT2

Version C is PRODUCT PREVIEW

Figure 6-1. RHF Package 24-Pin QFN Top View Version A and C

1

2

3

4

5

6

7

19

18

17

GND

OUT1

ILIMD

GND

EN1

EN2

OUT1

NC

PowerPad^TM

16

15

OUT2

14

13

LATCH

SEL

OUT2

Version B is PRODUCT PREVIEW

Figure 6-2. RHF Package 24-Pin QFN Top View Version B

4

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1

2

3

4

5

6

7

19

18

17

VDD

OUT1

FLT2

GND

OUT1

NC

PowerPad^TM

16

15

EN1

EN2

OUT2

14

13

LATCH

SEL

OUT2

Figure 6-3. RHF Package 24-Pin QFN Top View Version D

Table 6-1. Pin Functions

I/O

DESCRIPTION

TPS272C45A,

TPS272C45C

NAME

DIA_EN

SEL

TPS272C45B

TPS272C45D

12

13

12

13

12

13

I

Enables diagnostic functionality

SEL = 0: SNS pin measures channel 1 load current or fault output SEL

= 1: SNS pin measures channel 2 load current or fault output.

Sets retry behavior. LATCH = 0: auto-retry after faults or LATCH = 1:

latch off after faults.

LATCH

14

I

EN2

EN1

15

16

17

18

15

16

15

16

17

—

I

Enables channel 2 output current

Enables channel 1 output current

GND

ILIMD

17, 19

18

GND Device ground

O

Connect R_ILIMDto GND to set higher inrush current limit time duration.

Open drain output with pulldown to signal fault on Ch2 (active low

signal).

FLT2

—

18

ILIM2

ILIM1

20

21

20

21

20

21

O

Connect R_ILIM2to GND to set channel 2 current limit.

Connect R_ILIM1to GND to set channel 1 current limit.

Heat dissipation pad – connect to device GND. Maximize PCB copper

area for the best heat dissipation.

PowerPad

VS

Pad

—

Primary input supply, connect through vias down to a power plane to

connect the two set of VS power pins.

23, 24, 8, 9

I

VOUT1

NC

1, 2, 3

4, 22

1, 2, 3

4, 22

1, 2, 3

4, 22

O

Channel 1 output

No connect pin, leave unconnected

Channel 2 output

VOUT2

5, 6, 7

O

Open drain output with pulldown to signal fault on either channel (active

low signal).

FLT

FLT1

SNS

10

—

11

10

—

11

—

10

11

Open drain output with pulldown to signal fault on Ch1 (active low

signal).

O

Analog current output corresponding to load current – connect a

resistor to GND to convert to voltage.

Version A: Connect low voltage supply input for lower

power dissipation

VDD

19

—

19

I

Version C, D: Optionally tie to gnd to use internal LDO or connect to

external low voltage supply.

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SLVSF24A – DECEMBER 2020 – REVISED DECEMBER 2021

6.1 Recommended Connections for Unused Pins

The TPS272C45 is designed to provide an enhanced set of diagnostic and protection features. However, if the

system design only allows for a limited number of I/O connections, some pins can be considered as optional.

Table 6-2. Connections for Optional Pins

PIN NAME

CONNECTION IF NOT USED

Ground through 1-kΩ resistor Analog current sense is not available.

With LATCH unused (pin grounded), the device auto-retries after a fault.

IMPACT IF NOT USED

SNS

If latched behavior is desired, but the system describes limited I/O, it is

possible to use one microcontroller output to control the latch function of

several high-side channels.

LATCH

ILIMD

GND pin of IC

If ILIMD pin is connected to IC_GND, the current limit threshold is at a

constant value determined by the ILIM1/ILIM2 resistor values (delay time of

zero).

GND pin of IC

If either ILIMx pin is left floating or connected to IC_GND, the device is set

to the default internal current-limit threshold.

ILIM1/ILIM2

FLT / FLTx

SEL

GND pin of IC

If the FLT pin is unused, the system cannot read faults from the output.

With SEL unused, only channel one current sensing or Fault reporting is

available from the SNS pin.

With DIA_EN unused, the analog current sense, open-load and short-to-

supply diagnostics are not available.

DIA_EN

VDD

GND pin of IC

Version A: Connect to a 3.3-V or 5-V supply

Version C, D: With VDD unused, all supply current is drawn from the

primary supply VS.

6

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7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.7

–1

MAX

48

UNIT

V

Maximum continuous supply voltage, Versions A, B, D: V_S

Maximum transient (< 100 us) voltage at the supply pin, Versions A, B, D : V_S

Maximum continuous supply voltage Version C, V_S

Maximum voltage across the VS and OUT pins (V_S- V_OUT) Version C,

Low voltage supply pin voltage, V_DD

60

V

60

V

71

V

5.5

VS

5.5

VS

–50

150

V

Enable pin voltage, V_EN1and V_EN2

–1

V

LATCH pin voltage, V_LATCH

–1

V

Diagnostic Enable pin voltage, V_{DIA_EN}

–1

V

Sense pin voltage, V_SNS

–1

V

FLT pin voltage, Version A, B, C V_FLT

–1

V

FLTx pin voltage, Version D, V_FLT1,V_FLT2

Select pin voltage, V_SEL

–1

V

–1

V

Reverse ground current, I_GND

Maximum junction temperature, T_J

Storage temperature, T_stg

V_S< 0 V

mA

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

UNIT

Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001⁽¹⁾

V_(ESD)

V_(surge)

All pins except VS and OUTx

±2000

V

Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC VS and OUTx with respect to

±4000

±750

JS-001⁽¹⁾

GND

Electrostatic

discharge

Charged device model (CDM), ANSI/ESDA/JEDEC

JS-002⁽²⁾

All pins

Electrostatic

discharge

Surge protection with 42 Ω, per IEC 61000-4-5;

1.2/50 μs ⁽³⁾

OUTx pins

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) Tested with application circuit and supply voltage (VS) of 24-V, ENx pins High (Output Enabled) and and EN pins Low (Outputs

Disabled)

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

4.5

MAX

36

UNIT

V_{S_OPMAX}

V_DD

Nominal supply voltage

V

Low Voltage Supply Voltage

3.0

5.5

V_EN1

V_EN2

,

Enable voltage

–1

36

V

V_LATCH

V_{DIA_EN}

V_FLT

LATCH voltage

–1

36

V

Diagnostic Enable voltage

FLT pin voltage (Versions A, B,C)

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7.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–1

MAX

5.5

36

UNIT

V

V_{FLT1, FLT2}

V_SEL

FLT1 , FLT2 pin voltage (Version D)

Select pin voltage

–1

V

V_SNS

Sense pin voltage

–1

7

V

T_A

Operating free-air temperature

–40

125

°C

(1) All operating voltage conditions are measured with respect to device GND

7.4 Thermal Information

TPS272C45

RHF (QFN)

24 PINS

32.2

THERMAL METRIC^{(1) (2)}

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

22.5

10.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

10.2

R_θJC(bot)

0.7

(1) For more information about traditional and new thermal metrics, see the SPRA953 application report.

(2) The thermal parameters are based on a 4-layer PCB according to the JESD51-5 and JESD51-7 standards.

7.5 Electrical Characteristics

V_S= 6 V to 36 V, V_DD= 3.0 V to 3.6 V, T_J= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT VOLTAGE AND CURRENT

V_DS,Clamp

V_S,OVPR

V_DSclamp voltage

FET current = 10 mA, V_S= 24 V

49

53

61

50

V

V_Sovervoltage protection Measured with respect to the GND pin of the device,

rising ENx = HI

41.5

45.5

V_Sovervoltage protection Measured with respect to the GND pin of the device,

V_S,OVPRF

V_S,OVPRD

V_S,UVLOR

V_S,UVLOF

V_DD,UVLOF

V_DD,UVLOR

40

30

43.5

72

48

85

V

µs

V

recovery falling

ENx = HI

V_Sovervoltage protection

deglitch time

Time from triggering the OVP fault to FET turn-off

V_Sundervoltage lockout

rising

Measured with respect to the GND pin of the device

3.5

4.0

2.6

2.8

2.90

4.5

2.9

3.0

V_Sundervoltage lockout

falling

2.4

V

V_DDundervoltage

lockout falling

2.63

2.74

V

V_DDundervoltage lockout

rising

V

One channel enabled, T_AMB= 85°C

Two channels enabled, T_AMB= 85°C

4.0

3.0

A

Continuous load current,

per channel

IL_NOM

Output leakage current

(per channel)

VS <= 36 V, T_J= 85°C

V_ENx= V_{DIA_EN}= 0 V, V_OUT= 0 V

I_OUT(OFF)

0.5

3.0

1.4

µA

VS quiescent current,

Dual Supply input,

both channels enabled,

diagnostics disabled.

V_S≤ 36 V, V_DD= 5 V

V_ENx= HI V_{DIA_EN}= 0 V, I_OUTx= 0

I_{Q_VS_DS}

1.05

mA

8

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7.5 Electrical Characteristics (continued)

V_S= 6 V to 36 V, V_DD= 3.0 V to 3.6 V, T_J= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD quiescent current,

I_{Q_VDD_DS}both channels enabled,

diagnostics disabled.

V_S≤ 36 V, V_DD= 3.3 V

V_ENx= 3.3 V V_{DIA_EN}= 0, I_OUTx= 0

2.0

mA

VDD quiescent current,

I_{Q_VDD_DS}both channels enabled,

diagnostics disabled.

V_S≤ 36 V, V_DD= 5 V

V_ENx= 5 V V_{DIA_EN}= 0, I_OUTx= 0 A

2.1

2.8

mA

VS quiescent

I_{Q_VS_DIA_D}current, Dual Supply

V_S≤ 36 V, V_DD= 5 V

V_ENx= V_{DIA_EN}= 5 V, I_OUTx= 0 A

input, both channels

S

diagnostics enabled

VS quiescent current,

single (VS only) supply

I_{Q_VS_SS}

V_ENx= HI V_{DIA_EN}= 0 V, I_OUTx= 0

V_ENx= V_{DIA_EN}= HI, I_OUTx= 0

T_J= 25°C

4.4

4.9

mA

input, both channels ON

diagnostics disabled

V_Squiescent current,

I_{Q_VS_DIA_S}single VS supply input,

both channels ON

S

diagnostics enabled

RON CHARACTERISTICS

45

23

mΩ

On-resistance

(Includes MOSFET and

package)

6 V ≤ V_S≤ 36 V,

I_OUTx< 4 A

T_J= 85°C

68

78

27

34

39

T_J= 125°C

R_ON

On-resistance when

6 V ≤ V_S≤ 36 V,

I_OUTx< 4 A

T_J= 25°C

T_J= 85°C

T_J= 125°C

channels are paralleled

(Includes MOSFET and V_EN1tied to V_EN2, V_OUT1

package) tied to V_OUT2

CURRENT SENSE CHARACTERISTICS

Current sense ratio

I_OUTx/ I_SNS

K_SNS

I_SNSI

I_OUTX= 1 A

1200

3.33

Current sense current

and accuracy

V_EN= V_{DIA_EN}= 5 V

I_OUT= 4 A

mA

%

Current sense current

and accuracy

I_OUT= 4 A

–4.4

–4

4.4

4

Current sense current

and accuracy

I_OUT= 2 A

1.67

0.83

mA

%

Current sense current

and accuracy

I_OUT= 2 A

Current sense current

and accuracy

I_OUT= 1 A

mA

%

Current sense current

and accuracy

I_OUT= 1 A

Current sense current

and accuracy

I_OUT= 500 mA

I_OUT= 200 mA

I_OUT= 100 mA

0.425

0.17

mA

%

Current sense current

and accuracy

–6

6

Current sense current

and accuracy

mA

%

Current sense current

and accuracy

–10

–18

10

18

Current sense current

and accuracy

0.083

mA

%

Current sense current

and accuracy

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7.5 Electrical Characteristics (continued)

V_S= 6 V to 36 V, V_DD= 3.0 V to 3.6 V, T_J= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Current sense current

and accuracy

I_SNSI

V_EN= V_{DIA_EN}= 5 V

I_OUT= 50 mA

0.0416

mA

Current sense current

and accuracy

–25

25

%

Paralleled channels

current sense accuracy

multiplier

V_EN1tied to V_EN2, V_OUT1Multiply percentage

tied to V_OUT2and I_Load accuracy specification by

I_SNSI

Paralleled

1.2

times

> 1 A

this factor

SNS CHARACTERISTICS

V_{DIA_EN}= HI device in

V_{DIA_EN}= HI, device in

I_SNSFH

I_SNSfault high-level

FLT state of CH selected, FLT state of CH selected,

Vs>10 V Vs>10 V

3.333

4.5

5.5

mA

V_S- V_SNSheadroom

I_{SNS_HR}

needed for current sense V_S= 6V, I_SNS= 3.4 mA

functionality

2.35

10

V

I_SNSleakage, with no

I_SNSleak

V_{DIA_EN}= HI, V_EN= HI, I_L= 0 mA

µA

load

CURRENT LIMIT CHARACTERISTICS

R_ILIMx= GND, open, or

out of range (< 4.3 kΩ,

and > 80 kΩ)

Heavy overload or short

circuit condition

I_CL

Current limitation Level

4.3

5.8

4.1

6.95

A

Heavy overload or short R_ILIMx= 5 kΩ, V_VS-V_OUT

I_CL

3.15

4.7

4.78

2.3

A

circuit condition

> 2 V

Overcurrent limit

threshold⁽¹⁾

R_ILIMx= 5 kΩ V_VS-V_VOUT

< 1V

I_{CL_LINPK}

I_CL

I_{CL_LINPK}

I_CL

I_{CL_LINPK}

K_CL

Overload condition⁽¹⁾

Heavy overload or short R_ILIMx= 10 kΩ, V_VS-V_OUT

Current limitation Level

1.58

0.52

2.05

circuit condition

> 2 V

Overcurrent limit

threshold⁽¹⁾

R_ILIMx= 10 kΩ V_VS-V_OUT

< 1V

Overload condition

2.42

0.82

0.9

I_CLCurrent Limitation

Level

Heavy overload or short R_ILIMx= 28.7 kΩ, V_VS

-

0.71

20.5

circuit condition

V_VOUT> 2 V

Overcurrent limit

threshold⁽¹⁾

R_ILIMx= 28.7 kΩ, V_VS

V_OUT< 1 V

-

Overload condition⁽¹⁾

A

Current Limit Ratio

A * kΩ

I_CLCurrent Limitation

I_{CL_match12}Level - Matching between

CH1 and CH2

Heavy overload or short R_ILIMx= 10 kΩ, V_VS-V_OUT

–10

10

%

A

circuit condition

= 24 V

Peak current before

regulation while enabling

switch into 100 mohm

load

2.7 times

I_CL

I_{CL_ENPS}

R_ILIMx= 5 kΩ to 20 kΩ, VS = 24V

Regulated current @

Short circuit when

Enabled

Current limitation level

during inrush delay

period

R_ILIMx= 5 kΩ, RILIMD >

40 kΩ V_VS-V_OUT> 20 V

I_CL

1.3

1.5

1.7

A

Nominal Higher Inrush

Current limit time delay

range

t_DELAY

Set by resistor on ILIMD pin in discrete steps

0

22

ms

µs

Variation in ILIMD pin set

delay time

t_{DELAY_VAR}

–250

250

Paralled Channels

Current Limitation Level V_EN1tied to V_EN2, V_OUT1

- Multiplier compared to tied to V_OUT2

one channel

I_CL,PRLL

R_ILIMx= 5 kΩ to 20 kΩ

1.1

FAULT CHARACTERISTICS

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7.5 Electrical Characteristics (continued)

V_S= 6 V to 36 V, V_DD= 3.0 V to 3.6 V, T_J= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Open-load (OL, wire

R_{pu_OL}

V_{OL_off}

t_OL1

break) detection internal V_ENx= 0 V, V_{DIA_EN}= 5 V

pull-up resistor

125

150

180

kΩ

Open-load (OL, wire

break) detection voltage V_ENx= 0 V, V_{DIA_EN}= 5 V

VS - VOUT

1.4

2.0

2.5

440

650

V

Open Load (wire-break)

indication-time from ENx

falling

V_ENxHI to LO, V_{DIA_EN}= 5 V, V_SEL= X⁽²⁾

I_OUT= 0 mA, Open load condition

170

300

µs

Open load (wire-break)

indication-time from

DIA_EN rising

V_ENx= 0 V, V_{DIA_EN}= LO to HI, V_SEL= X⁽²⁾

I_OUT= 0 mA, Open Load Condition

t_OL2

Open load (wire-break)

indication-time from V_OUTV_ENx= 0 V, V_{DIA_EN}= 5 V, V_SEL= X⁽²⁾

rising beyond open load I_OUT= 0 mA, V_S– V_OUTx= < 2 V

threshold

t_OL3

600

µs

T_ABS

T_REL

Thermal shutdown

160

93

185

118

210

143

°C

Relative thermal

shutdown threshold

Thermal shutdown

hysteresis

T_HYS

18

24

30

0.4

3

°C

V

Fault low-output voltage

I_FLT= 2 mA, sink current into the pin

(Versions A, B, C)

V_{ol_FLT}

V_{ol_FLTx}

t_RETRY

Fault low-output voltage

I_{FLT1 ,}I_FLT2= 2 mA, sink current into the pin

Version D

V

Time from fault shutdown until switch re-enable

(thermal shutdown or current limit).

Retry time

1

2

ms

EN1 AND EN2 PIN CHARACTERISTICS

V_{IL, ENx}

V_{IH, ENx}

Input voltage low-level

Input voltage high-level

0.8

2.5

V

2

V_{IHYS, ENx}Input voltage hysteresis

350

1.5

5

mV

MΩ

µA

R_ENx

Internal pulldown resistor

Input current high-level

0.8

I_{IH, EN}

V_EN= 5 V

DIA_EN PIN CHARACTERISTICS

V_{IL, DIA_EN}Input voltage low-level

V_{IH, DIA_EN}Input voltage high-level

0.8

V

2

V_IHYS,

Input voltage hysteresis

200

350

530

mV

DIA_EN

R_{DIA_EN}

Internal pulldown resistor

Input current high-level

0.8

2.5

1.5

5.0

2.5

MΩ

µA

I_{IH, DIA_EN}

V_{DIA_EN}= 5 V

10.0

SEL Characteristics

V_{IL, SEL}Input voltage low-level

V_{IH, SEL}Input voltage high-level

V_{IHYS, SEL}Input voltage hysteresis

0.8

V

2

200

0.8

2.5

350

1.5

5.0

530

2.5

mV

MΩ

µA

R_SEL

Internal pulldown resistor

Input current high-level

I_{IH, SEL}

V_{DIA_EN}= 5 V

10.0

LATCH PIN CHARACTERISTICS

V_{IL, LATCH}Input voltage low-level

V_{IH, LATCH}Input voltage high-level

0.8

V

2

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7.5 Electrical Characteristics (continued)

V_S= 6 V to 36 V, V_DD= 3.0 V to 3.6 V, T_J= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IHYS,

Input voltage hysteresis

200

350

530

mV

LATCH

R_LATCH

Internal pulldown resistor

Input current high-level

0.8

2.5

1.5

5.0

2.5

MΩ

µA

I_{IH, LATCH}

V_LATCH= 5 V

10.0

(1) The maximum current output under overload condition before current limiting occurs.

(2) SEL must be set to select the relevant channel. Diagnostics are performed on Channel 1 when SEL = 0 and diagnostics are performed

on channel 2 when SEL =1

7.6 SNS Timing Characteristics

V_S= 6 V to 36 V, T_J= -40°C to +125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SNS TIMING - CURRENT SENSE

Settling time from rising edge of DIA_EN

50% of V_{DIA_EN}to 95% of settled ISNS

V_ENx= 5 V, V_{DIA_EN}= 0 V to 5 V

R_SNS= 1 kΩ, I_L= 2 A

t_SNSION1

30

60

µs

Settling time from rising edge of DIA_EN

50% of V_{DIA_EN}to 95% of settled ISNS

V_ENx= 5 V, V_{DIA_EN}= 0 V to 5 V

R_SNS= 1 kΩ, I_L= 100 mA

Settling time from rising edge of EN and

DIA_EN

50% of V_{DIA_EN}V_ENto 95% of settled I_SNS

V_ENx= V_{DIA_EN}= 0 V to 5 V

V_S= 24 V, R_SNS= 1 kΩ, R_L= 12 Ω

t_SNSION2

85

µs

Settling time from rising edge of EN with

DIA_EN HI;

50% of V_{DIA_EN}V_ENto 95% of settled I_SNS

VS=24V V_ENx= 0 V to 5 V, V_{DIA_EN}

5 V R_SNS= 1 kΩ, I_L= 2A

=

t_SNSION3

V_ENx= 5 V, V_{DIA_EN}= 5 V to 0 V

R_SNS= 1 kΩ, I_L= 2 A

t_SNSIOFF1Settling time from falling edge of DIA_EN

20

µs

V_EN1= 5 V, V_{DIA_EN}= 5 V

R_SNS= 1 kΩ, I_OUT= 0.8 A to 2 A

t_SETTLEH

t_SETTLEL

Settling time from rising edge of load step

Settling time from falling edge of load step

V_ENx= 5 V, V_{DIA_EN}= 5 V

R_SNS= 1 kΩ, I_OUT= 2 A to 0.8 A

SNS TIMING - MULTIPLEXER

V_ENx= 5V, V_{DIA_EN}= 5 V

Settling time from current sense on CHx to V_SEL= 0 V to 5 V

t_MUX

20

µs

CHy

R_SNS= 1 kΩ, I_OUT1= 0.2 A, I_OUT2= 2

A

7.7 Switching Characteristics

V_S= 6 V to 36 V, T_J= -40°C to +125°C (unless otherwise noted)

Parameter

Test Conditions

Min

Typ

Max

Unit

V_S= 24 V, R_L= 48 Ω 50% of EN to

10% of VOUT

t_DR

CH1 and CH2 Turnon delay time

CH1 and CH2 Turnoff delay time

VOUTx rising slew rate

10

25

15

35

25

50

µs

V_S= 24 V, R_L= 48 Ω 50% of EN to

90% of VOUT

t_DF

V_S= 24 V, 25% to 75% of V_OUT

R_L= 48 Ω

,

SR2_R

0.45

0.5

0.65

0.9

1.05

V/µs

V_S= 24 V, 75% to 25% of V_OUT

R_L= 48 Ω

,

SR2_F

f_max

t_ON

VOUTx falling slew rate

Maximum PWM frequency

CH1 and CH2 Turnon time

1.4

1

V/µs

kHz

µs

V_S= 24 V, R_L= 48 Ω 50% of EN to

90% of VOUT

25

40

50

65

V_S= 24 V, R_L= 48 Ω 50% of EN to

10% of VOUT

t_OFF

CH1 and CH2 Turnoff time

80

µs

12

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7.7 Switching Characteristics (continued)

V_S= 6 V to 36 V, T_J= -40°C to +125°C (unless otherwise noted)

Parameter

Test Conditions

Min

Typ

Max

Unit

CH1 and CH2 Turnon and off

matching

1ms ON time switch enable

pulse V_BB= 24 V, R_L= 48 Ω

t_ON- t_OFF

–25

0

25

µs

%

200-µs enable pulse, V_S= 24 V, R_L=

48 Ω

F = f_max

CH1 and CH2 PWM accuracy -

average load current

Δ_PWM

–12.5

–20

12.5

10

100-µs enable pulse, V_S= 24 V, R_L=

48 Ω

F = f_max

CH1 and CH2 PWM accuracy -

average load current

Δ_PWM

t_ON- t_OFF

E_ON

%

100-µs enable pulse, V_S= 24 V, R_L=

CH1 Turnon and off timing matching 48 Ω

F = f_max

–40

10

µs

mJ

V_S= 24 V, R_L= 8 Ω, 1 ms pulse,

VOUT from 10% to 90% of VS

voltage

Switching energy losses during

turnon

0.3

0.4

0.35

V_S= 24 V, R_L= 8 Ω, 1 ms pulse,

VOUT from 10% to 90% of VS

voltage

Switching energy losses during

turnoff

E_OFF

0.25

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7.8 Typical Characteristics

I_{q_VS}vs. Temperature

I_{q_VDD}vs. Temperature

1.2

2.1

1.95

1.8

1.15

1.1

1.05

1.65

1.5

1

VS voltage

24 V

VDD voltage

5 V

30 V

3.3 V

0.95

1.35

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

V_DD= 3.3 V

R_OUT= open

V_EN= 3.3 V

V_{DIA_EN}= 0 V

V_S= 24 V

V_EN= 5 V

V_{DIA_EN}= 0 V

R_OUT= open

Figure 7-1. Quiescent Current (I_{Q_VS_DS}) From VS

Input Supply vs Temperature

Figure 7-2. Quiescent Current (I_{Q_VDD_DS}) From

VDD Input Supply vs Temperature

R_ONvs. Temperature

80

70

60

50

40

VS voltage

24 V

30 V

30

-50

-25

0

25

50

75

100

125

Temperature (^oC)

V_DD= 0 V

V_EN= 5 V

V_{DIA_EN}= 0 V

I_OUT= 200 mA

V_EN= 5 V

V_{DIA_EN}= 0 V

R_OUT= open

Figure 7-4. On Resistance (R_ON) vs Temperature

Figure 7-3. Quiescent Current (I_{Q_VS_SS}) From VS

Input Supply vs Temperature

66

64

62

60

58

56

54

52

50

48

46

72

70

68

66

64

62

60

58

56

54

52

50

48

46

44

VS Voltage

24 V

36 V

44

42

40

24 V

36 V

42

40

-40

-20

0

20

40

60

80

100

120

140

-40

-20

0

20

40

60

80

100

120

140

Temperature (^oC)

V_S= 24 V

V_EN= 0 V to 5 V

V_{DIA_EN}= 0 V

V_S= 24 V

V_EN= 0 V to 5 V

V_{DIA_EN}= 0 V

R_OUT= 48 Ω

Figure 7-5. Turn-on Time (t_ON) vs Temperature

Figure 7-6. Turn-off Time (t_OFF) vs Temperature

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5

1.8

1.75

1.7

VIH

VIL

3

2

1.65

1.6

VIH

1

0.7

0.5

1.55

1.5

0.3

0.2

1.45

1.4

0.1

0.07

0.05

1.35

1.3

VIL

Temperature

−40C

1.25

1.2

0.03

0.02

25C

85C

125C

1.15

-40

0.01

-20

0

20

40

60

80

100

120

140

Temperature (^oC)

0.02 0.03 0.05 0.07 0.1

0.2 0.3 0.40.5 0.7

1

2

3

4 5

Load Current

V_S= 24 V

V_{DIA_EN}= 0 V

R_OUT= 1 kΩ

V_S= 24 V, 30 V

R_SNS= 1 kΩ

V_EN= 5 V

V_{DIA_EN}= 5 V

Figure 7-8. VIH, V_ILvs Temperature

Figure 7-7. Current Sense Output Current (I_SNSI) vs

Load Current (I_OUT) Across Temperature

V_EN= 0 V to 5 V

V_S= 24 V

R_OUT= 10 Ω

V_EN= 5 V to 0 V

V_S= 24 V

R_OUT= 10 Ω

Figure 7-9. Turn-on Time (T_ON

)

Figure 7-10. Turn-off Time (T_OFF)

V_EN= V_{DIAG_EN}= 0

V to 5 V

V_S= 24 V

R_OUT= 10 Ω

V_EN= 5 V

V_{DIAG_EN}= 5 V

I_OUT1= 0.5 A to 2 A

Figure 7-12. I_SNSSettling Time on Rising Load Step

Figure 7-11. I_SNSSettling Time on DIA_EN

Transition

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8 Parameter Measurement Information

I_S

VOUT1

VOUT2

SEL

I_OUT2

VS

I_DD

I_OUT2

VDD

LATCH

I_LATCH

I_SEL

I_EN1

EN1

SNS

I_SNS

I_EN2

EN2

ILIM1

ILIM2

ILIMD

I_ILIM1

I_{DIA_EN}

DIA_EN

FLT

I_ILIM2

I_FLT

I_ILIMD

GND

Figure 8-1. Parameter Definitions

(1)

V_EN

50%

90%

t_DR

t_DF

V_OUT

10%

t_ON

t_OFF

A. Rise and fall time of V_ENis 100 ns.

Figure 8-2. Switching Characteristics Definitions

16

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V_EN1

V_{DIA_EN}

I_OUT1

I_SNS

t_SNSION1

t_SNSION2

t_SNSION3

t_SNSIOFF1

V_EN1

V_{DIA_EN}

I_OUT1

I_SNS

t_SETTLEH

t_SETTLEL

Rise and fall times of control signals are 100 ns. Control signals include: EN, DIA_EN, SEL

SEL pin must be set to the appropriate value.

Figure 8-3. SNS Timing Characteristics Definitions

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9 Detailed Description

9.1 Overview

The TPS272C45 device is a dual channel 45-mΩ smart high-side switch that is intended to provide protection

for output ports in 24-V Industrial systems. The device is designed to drive a variety of resistive, inductive and

capacitive loads. The device integrates various protection features including overload protection through current

limiting, thermal protection, and short-circuit protection. For more details on the protection features, refer to the

Feature Description and Application Information sections of the document.

In addition, the device diagnostics features include the analog SNS output that is capable of providing a signal

proportional to the load current flowing through the switch or constant high current as a fault indication. The

high-accuracy load current sense allows for integration of load diagnostic features that can enable predictive

maintenance for the system by watching for leading indicators of load failures. The device also integrates open

load detection to enable protection against wire breaks. In addition, the device includes a single open drain FLT

pin output (version A, B, C) and dual FLT pin outputs (version D) that indicate device fault states such as short to

GND, short to supply, or overtemperature.

The TPS272C45 is one device in TI's industrial high side switch family. For each device, the part number

indicates elements of the device behavior. Figure 9-1 explains the device nomenclature.

TPS

27

2

C

45

X

RHFR

Package Designator

Prefix

40 V Industrial

High Side Switch

Device Version

R_ON(mΩ)

27

28

S

Single Channel

60 V Industrial

High Side Switch

2

4

Dual Channel

Quad Channel

Generation

Figure 9-1. Naming Convention

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9.2 Functional Block Diagram

VS

UV/OV

Detection

Internal Power

Supply

FET Vds Clamp

GND

VDD

EN1

EN2

VOUT1

Gate Driver

Power FET

Channel 1/2

LATCH

ILIM1

ILIM2

ILIMD

VOUT2

Current Limit

Thermal

Shutdown

FLT

DIA_EN

SEL

Open-load

detection

Fault Indication

SNS

SNS Mux

Current Sense

9.3 Feature Description

9.3.1 Programmable Current Limit

The TPS272C45 integrates a dual stage adjustable current limit. For the most efficient and reliable output

protection, the current limit can be set as close to the DC current level as possible. Sometimes, systems require

high inrush current handling as well (example incandescent lamp and capacitive loads). By integrating a dual

stage current limit, the TPS272C45 enables robust DC current limiting while still allowing flexible inrush handling.

With the adjustable current limit feature, a lower current limit setting can reduce the fault energy and the output

current during a load failure event such as a short-circuit or a partial load short (soft-short). By lowering fault

energy and current, the overall system improves through:

•

Reduced size and cost in current carrying components such as PCB traces and module connectors

Less disturbance at the power supply (VS pin) during a short circuit event

Less additional budget for the power supply to account for overload currents in one channel or more

Improved protection of the downstream load

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9.3.1.1 Inrush Current Handling

The TPS272C45 uses a resistor from the following pins to the IC GND to configure the current limit behavior:

ILIM1, ILIM2, and ILIMD. The ILIM1 and ILIM2 pin resistors set the current limit thresholds for CH1 and CH2

respectively while ILIMD pin resistor sets a delay time for the device to operate in a higher or lower current limit

during device start-up or output turn-on by retry after a fault (thermal) shutdown).

24-V Power Supply

5-V/3.3-V Power

Supply (Optional)

VS

VOUT1

VOUT2

VDD

ILIM1

ILIM2

ILIMD

R_ILIM1

R_ILIM2

GND

R_ILIMD

Load 1

Load 2

Figure 9-2. Current Limit Set Functionality

The ILIM1/ILIM2 thresholds and the ILIMD pin resistor controlled timing enable flexible inrush current control

behavior. The following table shows the various options available.

Table 9-1. Inrush Current Limit Options

Case

Number

ILIMD Resistor Inrush Delay Time Current Limit During

Notes

Settings

(ms)

Inrush Duration

At the level set by

ILIM1/2 resistor

The device shows constant current limit threshold in each

channel at all times set by the ILIM1/2 resistors.

1

2

Short to GND

0

The current is set higher during the duration of the inrush

delay to support high inrush current loads like incandescent

Discrete resistor

values

Programmable in

discrete steps

2- 18

Current limit at 2

times the level set by lamps. See figure (case 1) showing current limit behavior

ILIM1/2 resistor

(See table

enabling into a short circuit with ILIM1/2 threshold set at 2.2

A.

below)

Additional feature to limit the current and power dissipation

during initial phase of charging large power supply capacitor

loads. The Vds dependence of current limit exists only

during the duration set by the ILIMD resistor.

If the ILIMD resistor is not connected (floating) or > 40.2 kΩ,

the inrush current limit behavior defaults to Case 3.

Current limit fixed at

1.5-A threshold for

Vds > 16 V, or at the

level set by ILIM1/2

resistor if Vds < 16 V

3

40.2 kΩ +/–2%

Fixed 30

Table 9-2. Delay Resistor Values

ILIMD Resistor Value

Delay

2 ms

3.48 kΩ

7.15 kΩ

12.1 kΩ

17.8 kΩ

24.9 kΩ

4 ms

6 ms

10 ms

18 ms

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IOUT (A)

2 x I_CL

I_CL

Time (S)

EN (V)

V_EN

Note: t_DELAYset by ILIMD

Time (S)

t_DELAY

Figure 9-3. Inrush Current Control (Case 2) With a Shorted Load

IOUT

1xILIM

(e.g. 2.2A)

1.5A

EN

Note : t_DELAY= 30ms

t_DELAY

Figure 9-4. Inrush Current Control (Case 3) With a Shorted Load

For the Case 2, when the ENx pin goes high to turn on one of the channels (or the channel is turned on

automatically to retry after a fault shutdwon), the device defaults to twice current limit threshold as determined

by R_ILIM1/R_ILIM2or the maximum internal current limit level (whichever is lower). The internal current limit level

is defined in the Specifications section of this document. After a T_DELAYperiod that is determined by R_ILIMD, the

current limit changes to the threshold determined by R_ILIM1/R_ILIM2. The delay can be set in the range from 0 (the

current limit threshold at all times set to that determined by R_ILIM1/R_ILIM2) to a maximum of 22 ms in dscrete

steps.

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Each channel operates independently with current limit thresholds controlled by R_ILIM1and R_ILIM2(so both

channels can have separate current limit thresholds). If channel 2 is enabled after channel one, channel 2 has its

own separate timing.

The initial inrush current period when the current limit is higher enables two different system advantages when

driving loads

•

Enables higher load current to be supported for a period of time of the order of milliseconds to drive high

inrush current loads like incandescent bulb loads.

•

Enables fast capacitive load charging. In some situations, it is ideal to charge capacitive loads at a higher

current than the DC current to ensure quick supply bring up. This architecture allows a module to quickly

charge a capacitive load using the initial higher inrush current limit and then use a lower current limit to

reliably protect the module under overload or short circuit conditions.

While in current limiting mode, at any level, the device has a high power dissipation. If the FET temperature

exceeds the over-temperature shutdown threshold, the device turns off just the channel that is overloaded. After

cooling down, the device either latches off or re-tries, depending on the state of the LATCH pin. If the device is

turning off prematurely on start-up, TI recommends to improve the PCB thermal layout, lower the current limit to

lower power dissipation, or decrease the inrush current (capacitive loading).

9.3.1.2 Calculating R_ILIMx

To set the current limit thresholds, connect resistors from both ILIM1 and ILIM2 pins to GND. The current limit

threshold for each channel is determined by Equation 1 (R_ILIMxin kΩ):

I_CL= K_CL/ R_ILIMx

(1)

The nominal K_CLvalue to be used in the calculation is 20.5 A.kΩ. The allowed R_ILIMxrange is between 5 kΩ

and 28.2 kΩ. If either pin is floating, grounded, or outside of the range specified, the current limit defaults to an

internal level that is defined in the Specifications section of this document.

9.3.1.3 Configuring ILIMx From an MCU

In many situations, modules like to allow the current limit to be set programmatically from an MCU. This action

enables a module to set current limits to fit the load after determining what load is plugged in. As described, the

TPS272C45 current limits are set by R_ILIMx. However, the R_ILIMxthat is seen by the device can be configured

through small external FETs as shown in Figure 9-5.

24-V Power Supply

5-V/3.3-V Power

Supply (Optional)

VS

VOUT1

VOUT2

VDD

ILIM1

ILIM2

ILIMD

R_{ILIM1_1}

R_{ILIM1_2}

GND

R_ILIMD

MCU_IO

Load 1

Load 2

Figure 9-5. Dynamic ILIMx Control

For example, R_{ILIM1_1}can set the device to 500-mA ILIM while R_{ILIM1_2}can set the device at 2-A ILIM. After

the MCU realizes how much current draw is required by the load, the MCU can drive one of the series FET's

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to set the ILIM to be ideal for the specific load. The current limit (ILIM1 and ILIM2) thresholds can be changed

dynamically, but the inrush current limit delay set with the ILIMD resistor cannot be changed after powerup.

The external FET switches used to dynamically adjust the current limit must be chosen with a minimum

capacitance (Coss) from the drain the ground. The total capacitance to PCB ground at the ILMx pins including

from traces must be limited to less than 100 pF.

9.3.2 Low Power Dissipation

There are two primary sources of power dissipation in the TPS272C45:

1. Resistive losses in the primary FET, which are calculated as (I_LOAD)²× R_ON

2. Controller losses due to quiescent operating current, which are calculated as I_Q× V_SUPPLY

If I_LOADis significantly more than 1 A, the resistive losses dominates the controller losses and they can be

ignored. However, if I_LOADis less than 1 A, the controller losses comprise a significant portion of the total device

power dissipation. To lower the controller losses, version A of the TPS272C45 introduces a secondary low

voltage supply on pin VDD that can power much of the device functionality. By lowering the controller supply

voltage from 24 V to 3.3 V, the total controller losses decrease significantly. Table 9-3 shows the impact this

second supply can make on the total device power dissipation calculated at a worst case supply voltage of 30

V, without diagnostics enabled. There is an additional contribution to power dissipation from the current sense

circuitry as well as the sensed current out of the SNS pin when diagnostics are enabled. Savings of over 80 mW

per channel in the IC is achieved by powering the device with a separate 3.3-V supply.

Table 9-3. Power Dissipation Calculations

Resistive Losses

(Maximum, 125°C)

Controller Losses

(Maximum, 125°C)

Total P_DISS(Maximum,

125°C)

I_LOAD

Version

B

A

B

A

39 mW

211 mW

50 mW

211 mW

50 mW

250 mW

89 mW

500 mA (both channels)

624 mW

735 mW

674 mW

2 A (both channels)

By using version TPS272C45A and providing a 3.3-V supply to the VDD pin, for a 500-mA output module the

worst case device total heating is cut from 250 mW to 89 mW, about a 30% decrease in per channel power

dissipation. This lower power dissipation, in addition to the small size of the TPS272C45, enables modules

that have many low current outputs to shrink the size of their casings without limiting output power distribution

capability. To minimize power dissipation, the VDD supply must be powered by a small DC/DC providing the less

than 5 mA per device. Multiple devices can use one DC/DC converter to limit system costs, as shown in Figure

9-6.

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24-V Power Supply

5-V/3.3-V

DC/DC

VS

VOUT1

VOUT2

VDD

GND

VS

VOUT1

VOUT2

VDD

GND

To Addi onal

TPS272C45

Figure 9-6. Secondary Low Voltage Supply Schematic

For higher current modules, the resistive losses dominate the total power dissipation and the impact of the

secondary supply is less valuable. For example, Table 9-3 shows that for a 2-A output, providing the secondary

supply lowers the total device dissipation by only 12%. In this case, to lower total system costs, versions with

an internal regulator that need only single supply input can be used. If using versions C or D and the secondary

supply is not useful or available, the VDD pin can be grounded and all current is drawn from the primary supply

with no loss of functionality, but higher power dissipation.

9.3.3 Protection Mechanisms

The TPS272C45 protects the system against load fault events like short circuits, inductive load kickback,

overload events, overvoltage and over-temperature events. This section describes the details for protecting

against each of these fault cases.

There are a number of protection features which, if triggered, causes the switch to automatically disable:

•

Current limit

Thermal shutdown

DC overvoltage on VS supply above the overvoltage protection threshold, V_OVPR

When one of these protections are triggered for either channel, the device enters the FAULT state. In the FAULT

state, the fault indication is available on the FLT pin for an MCU to monitor and react to.

The fault indication is reset and the switch turns back on when all of the below conditions are met:

•

LATCH pin is low

t_RETRYhas expired

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•

All faults are cleared (thermal shutdown, current limit, overvoltage)

9.3.3.1 Short-Circuit Protection

TPS272C45 provides output short-circuit protection to ensure that the device prevents current flow in the event

of a low impedance path to GND, removing the risk of damage or significant supply droop. The device is

specified to protect against short-circuit events regardless of the state of the ILIM pins and or supply voltages up

to 36V and across the entire opeprating temperature range -40 °C 125°C.

Figure 9-7 shows the behavior of the TPS272C45 when the device is enabled into an overload condition and

then recovers to a normal load.

Voltage (V)

V_S

V_S- V_DS

Time (s)

Current (A)

I_{CL_ENPS}

I_CL

I_NOM

dt

Time (s)

Figure 9-7. Enable into Short-Circuit Behavior

Due to the low impedance path, the output current rapidly increases until it hits the current limit threshold. Due to

the response time of the current limiting circuit, the measured maximum current can temporarily exceed the I_CL

value defined as I_{CL_ENPS}, before it settles to the current limit regulation value (I_CL).

In this state high power is dissipated in the FET, so eventually the internal thermal protection temperature for the

FET is reached and the device safely shuts down. Then if LATCH pin is low the part waits t_RETRYamount of time

and turns back on.

Figure 9-8 shows the behavior of the TPS272C45 when a short-circuit occurs when the device is in the on-state

and already outputting current. When the internal pass FET is fully enabled, the current clamping settling time

is slower so to ensure overshoot is limit, the device implements a fast trip turn-off at a high current threshold

(approximately 40% higher than I_CL). When this fast trip threshold is hit, the device shuts off after a delay for a

short period of time before quickly re-enabling and clamping the current to the regulation current limit level (I_CL)

after a brief transient overshoot to the higher peak current level. The device then keeps the current clamped at

the regulation current limit until the thermal shutdown temperature is hit and the device safely shuts off.

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Current (A)

I_{CL_ENPS}

I_CL

Thermal Shutdown

t_RETRY

I_NOM

Time (s)

Figure 9-8. On-State Short-Circuit Behavior

Overload Behavior shows the behavior of the TPS272C45 when there is a small change in impedance that

sends the load current above the I_CLthreshold. The current rises to I_{CL_LIN}above the regulation level. Then the

current limit regulation loop kicks in and the current drops to the I_CLvalue.

Current (A)

I_{CL_ENPS}

I_{CL_LINPK}

I_CL

I_NOM

t_RETRY

Thermal Shutdown

Time (s)

Figure 9-9. Overload Behavior

In all of these cases, the internal thermal shutdown is safe to hit repetitively. There is no device risk or lifetime

reliability concerns from repeatedly hitting this thermal shutdown level.

9.3.3.1.1 V_SDuring Short-to-Ground

When V_OUTis shorted to ground, the module power supply (V_S) can see a transient decrease. This decrease is

caused by the sudden increase in current flowing through the cable inductance. For ideal system behavior, TI

recommends that the module maintain V_S> 3 V (above the maximum V_UVLOF) during V_OUTshort-to-ground. This

event is typically accomplished by placing bulk capacitance on the power supply node. If V_Sgoes below V_UVLOF

the device can sustain unexpected latch and timing behavior.

,

9.3.3.2 Inductive Load Demagnetization

When switching off an inductive load, the inductor can impose a negative voltage on the output of the switch.

The TPS272C45 includes voltage clamps between V_Sand V_OUTto limit the voltage across the FETs and

demagnetize load inductance if there is any. The negative voltage applied at the OUT pin drives the discharge of

inductor current. Figure 9-10 shows the device discharging a 40-mH load.

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Figure 9-10. TPS272C45 Inductive Discharge (40 mH)

The maximum acceptable load inductance is a function of the energy dissipated in the device and therefore the

load current and the inductive load. The maximum energy and the load inductance the device can withstand for

one pulse inductive dissipation at 125°C is shown in Figure 9-11.The device can withstand 50% of this energy

for one million inductive repetitive pulses with a >4-Hz repetitive pulse. If the application parameters exceed this

device limit, use a protection device like a freewheeling diode to dissipate the energy stored in the inductor.

700

650

600

550

500

450

400

350

300

250

200

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

Current (A)

Figure 9-11. TPS272C45 Inductive Load Discharge Energy Capability at 125°C

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For more information on driving inductive loads, refer to TI's How to Drive Inductive, Capacitive, and Lighting

Loads With Smart High-Side Switches application report.

9.3.3.3 Thermal Shutdown

The TPS272C45 includes a temperature sensor on the power FET and also within the controller portion of the

device. The device registers a thermal shutdown fault:

•

T_J,FET> T_ABS

T_J,FET- T_J,control> T_REL

After the fault is detected, the switch turns off. If T_J,FETpasses T_ABS, the fault is cleared when the switch

temperature decreases by the hysteresis value, T_HYS. If instead the T_RELthreshold is exceeded, the fault is

cleared after T_RETRYpasses.

Each channel shuts down independently in case of a thermal event, as each has its own temperature sensor and

fault reporting.

9.3.3.4 Undervoltage Lockout on VS (UVLO)

The device monitors the supply voltage at the VS pin to prevent unpredicted behaviors in the event that the

supply voltage is too low. When the supply voltage falls down to V_UVLOF, the device enters the shut down state

automatically. When the supply rises up to V_UVLOR, the device turns back on.

Fault is not indicated on the FLT pin during an UVLO event. During an initial ramp of V_VSfrom 0 V at a ramp

rate slower than 1 V/ms, V_ENxpins must be held low until V_Sis above the UVLO threshold. For best operation,

ensure that V_Shas risen above UVLO before setting the V_ENxpins to high.

9.3.3.5 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)

The device monitors the input supply voltage V_VDD(in versions A/C/D with external supply input) to prevent

unpredictable behavior in the event that the supply voltage is too low. When the supply voltage falls down to

V_{VDD_UVLOF}, the device switches operation to the VS (24 V) power supply, but results in increased current draw

from the VS supply input.

9.3.3.6 Power-Up and Power-Down Behavior

All versions of the device power up from the OFF state only when the VS supply input exceeds the V_VSUVLOR

threshold (independent of the VDD supply input level). When VS supply is above the threshold, the internal

regulators are enabled, the device version is recognized. The device then enters the standby state. With

versions A, C, and D and using using an external supply on VDD pin - the device will use the internal regulators

until the VDD voltage exceeds V_{VDD_UVLOR}

.

In case the VDD power supply is enabled first and the VDD voltage exceeds V_{VDD_UVLOR}before the VS supply is

up and the VS voltage exceeds VS_UVLOR, the device remains in the off-state.

The behavior of all versions of the device in case of brown-out or power loss in VS supply is as described in

Undervoltage Lockout on VS (UVLO). For versions A, C, and D if the VDD power supply is lost (VDD supply

voltage falls below V_{VDD_UVLOR}threshold), the device switches over to the internal power supply, the switch

outputs are disabled.

9.3.3.7 Overvoltage Protection (OVPR)

The device monitors the supply voltage V_VSto prevent higher voltages from appearing at the output than can

be supported by the load, when the supply voltage is too high. When the supply voltage goes above V_{VS_OVPR}

,

the FET is shut down automatically after a deglitch time to prevent short transients or noise from triggering the

protection. When the supply falls below V_{VS_OVPF}, the FET is allowed to turn back on.

9.3.4 Diagnostic Mechanisms

As systems demand more intelligence, it is becoming increasingly important to have robust diagnostics

measuring the conditions of output power. The TPS272C45 integrates many diagnostic features that enable

modules to provide predictive maintenance and intelligence power monitoring to the system.

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9.3.4.1 Current Sense

The SNS output can be used to sense the load current through either channel. The SNS pin outputs a current

that is proportional to the load current through either channel, depending on the state of the SEL pin. This

current is sourced into an external resistor to create a voltage that is proportional to the load current. This

voltage can be measured by an ADC or comparator and used to implement intelligent current monitoring for a

system. To ensure accurate sensing measurement, R_SNSmust be connected to the same ground potential as the

μC ADC.

The SNS pin output is controlled by the SEL pin. If SEL pin is low, SNS outputs load current proportional to

channel 1, whereas if SEL is high SNS outputs load current proportional to channel 2.

Equation 3 shows the transfer function for calculating the load current from the SNS pin current.

I_SNSI= I_OUT/ K_SNS

(2)

K_SNSis defined in the Specifications section.

9.3.4.1.1 R_SNSValue

The following factors must be considered when selecting the R_SNSvalue:

•

Current sense ratio (K_SNS)

Largest and smallest diagnosable load current required for application operation

Full-scale voltage of the ADC

Resolution of the ADC

For an example of selecting R_SNSvalue, reference R_ISNSCalculation in the applications section of this data

sheet.

9.3.4.1.1.1 Current Sense Output Filter

To achieve the most accurate current sense value, TI recommends to filter the SNS output. There are two

methods of filtering:

•

Low-Pass RC filter between the SNS pin and the ADC input. This filter is illustrated in Figure 10-1 with

typical values for the resistor and capacitor. The designer must select a C_SNScapacitor value based on

system requirements. A larger value provides improved filtering but a smaller value allows for faster transient

response.

•

The ADC and microcontroller can also be used for filtering. TI recommends that the ADC collects several

measurements of the SNS output. The median value of this data set must be considered as the most

accurate result. By performing this median calculation, the microcontroller can filter out any noise or outlier

data.

9.3.4.2 Fault Indication

The following faults are registered on the FLTx pin:

•

FET thermal shutdown

Active current regulation

Thermal Shutdown caused by current limitation

Open-load (FET OFF state only)

Open-load or short-to-supply are not indicated while the switch is enabled, although in on-state these conditions

can still be detected through the sensed current (ISNS current). Hence, if there is a fault indication while the

channel is enabled, then it must be either due to an overcurrent or overtemperature event. On the other hand, a

fault indication while the output (FET) is disabled must be either due to an open load or output short-to-supply.

In versions A, B, C of the device, the open drain FLT pin output is a global fault output. FLT pin indicates a fault

when one occurs in either channel. The FLT signal can be deactivated by toggling the EN input of the faulted

channel and sequential toggling of ENx inputs can be used to determine the faulted channel. In versions A, B, C

of the device the SNS pin also indicates the fault status of the channel, provided the faulted channel is selected

with the SEL pin.

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In version D of the device, there are two (FLT1 and FLT2) pin outputs corresponding the presence of a fault in

each channel. The independent FLTx signals can be used to easily determine the faulted channel. The FLTx

signal is deactivated by toggling the EN input of the faulted channel. In version D of the device the SNS pin does

not indicate the fault status of the channel, just the load current sense.

Table 9-4 shows the states for both the SNS pin and the FLT pins based on the fault states and ENx/SEL pin

state (applies to versions A, B, C). By looking at these pins, it is possible to detect where the fault has occurred.

The method to identify the channel that caused the FLT signal is as follows when an MCU is monitoring the SNS

pin output. If the SNS is signaling a fault (with I_SNSFHcurrent output) while SEL=LO, then the fault is in channel

1, whereas with SEL=HI, the fault is in channel 2. If SNS pin signals fault with SEL at either LO or HI, then

both channels are faulted. As discussed earlier, the type of faults (whether it is overcurrent, overtemperature or

open-load) can be determined by the state of EN input in each channel. If the SNS pin output is not monitored, it

is still possible to identify the channel that is faulted. To do this, the EN pin in each channel must be toggled (LO

to HI or HI to LO as the case can be). If the fault indication on the FLT pin is removed by toggling the EN input

in a channel, then the fault is in that channel. If the fault indication does not go away with toggling EN input of

both channels, then the fault is in both. The time duration for toggling the EN input must be kept below 10 us to

ensure that there is no impact on the actual output of the channels.

Table 9-4. Device Fault Mux (Versions A, B, C)

INPUTS

OUTPUTS

SEL

0

CH1 FAULT

CH2 FAULT

SNS

FLT

High

Low

0

1

CH1 load current

0

Corresponds to fault

case⁽¹⁾

0

1

0

Low

Corresponds to fault

case⁽¹⁾

0

1

0

1

0

1

0

1

Low

High

Low

CH2 load current

Corresponds to fault

case⁽¹⁾

CH2 load current

Corresponds to fault

case⁽¹⁾

(1) Table 9-5 describes this behavior

While typically the SNS pin output corresponds to I_LOAD, in a fault case the switch turns off and I_LOADgoes to

zero so the SNS behavior is modified in a fault case. In the event of a fault cases where SEL is monitoring the

proper channel, the SNS pin outputs a voltage level corresponding to the fault type to enable improved diagnosis

as shown in Table 9-5.

By looking at the combination of the ENx condition, FLT , and SNS pins, it is possible to distinguish between fault

states. Each channel has independent fault states, so the table below applies to CH1 when SEL = LO and CH2

when SEL = HI.

Table 9-5. Distinguishing Different Fault Cases (Versions A, B, C)

Channel State

Fault Case

SNS

FLT

Regulating current past the initial inrush delay

set by ILIMD resistor

I_SNSFH

Low

Enabled

Short-to-supply/open-load

T_Jovertemperature

0

High

Low

High

I_SNSFH

0

Short-to-supply/open-load

T_Jovertemperature

Disabled

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In version D of the device the fault table is shown in Table 9-6. By looking at these pins, it is possible to

detect which channel the fault has occurred. As discussed earlier, the type of faults (whether it is overcurrent,

overtemperature or open_load) can be determined by the state of EN input in each channel.

Table 9-6. Device Fault Mux (Version D)

INPUTS

OUTPUTS

CH1 FAULT

CH2 FAULT

FLT1

High

FLT2

High

Low

0

1

0

1

Low

High

Low

9.3.4.2.1 Fault Event Diagrams

Note

All timing diagrams assume that the SEL pin is low to measure channel one behavior on the SNS pin.

DIA_EN and SEL pins have no effect on the FLT (versions A, B, C) or FLT1, FLT2 (version D) pin

output.

The LATCH, SEL, DIA_EN, and ENx pins are controlled by the user. The timing diagrams represent

possible use-cases.

Figure 9-12 shows the device fault reporting behavior in the event of a fault in channel 2 (only) with LATCH and

SEL pin set to LO. As shown, the fault signaling is deactivated when EN is toggled (in this case from HI to LO to

HI). The faulted channel can be determined by toggling the EN pin with a short pulse (less than 10-us wide) that

does not affect the output of the channel.

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CH2_FAULT

FAULT

t

EN2

t

FLT

t

Figure 9-12. FLT Pin Behavior (Versions A, B, C)

Figure 9-13 shows the device fault reporting behavior in the event of an overcurrent fault when EN goes high. As

shown, the fault signaling is active only after the initial inrush current limit phase is complete.

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I_OUTx

2xI_CL

1xI_CL

t

T_delay

FLT

t

ENx

t

Figure 9-13. FLT Pin Behavior With an Overcurrent Event On Channel Enable (Versions A, B,C)

Figure 9-14 shows the device fault and retry behavior when there is a slow creep into an overcurrent event. As

shown, the switch clamps the current until it hits thermal shutdown, and then the device remains latched off until

the LATCH pin is low.

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FLT

µC

resets

the latch

LATCH

DIA_EN

SNS signals

over-current

FLT

Current

SNS

Current

SNS

High-z

SNS

VOUTx

EN high throughout

ENx

T_ABS

T_HYS

T_J

t_RETRY

I_CL

I_OUTx

t

Switch is disabled. Temp

decreases by T_HYS, but

waits for LATCH

Load reaches limit. Current is

limited. Temp reaches limit.

Switch follows ENx.

Normal operation.

Figure 9-14. Current Limit – Latched Behavior

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Figure 9-15 shows the behavior with LATCH tied to GND; hence, the switch retries after the fault is cleared and

t_RETRYhas expired.

Signaling

FLT

DIA_EN

Current

Sense

SNS signals

over-current

Current

Sense

SNS

High-z

VOUTx

EN stays high throughout

ENx

T_ABS

T_HYS

T_J

t_RETRY

I_CL

I_OUTx

t

Load reaches limit.

Current is limited. Temp

reaches limit.

Switch is disabled. T_J

decreases by T_HYS

Switch follows ENx.

Normal operation.

Figure 9-15. Current Limit – LATCH = 0

When the switch retries after a shutdown event, the fault indication remains until V_OUTxhas risen to V_VS– 1.8 V.

After V_OUTxhas risen, the FLT output is reset and current sensing is available. If there is a short-to-ground and

V_OUTis not able to rise, the SNS fault indication remains indefinitely. Figure 9-16 illustrates auto-retry behavior

and provides a zoomed-in view of the fault indication during retry.

Note

Figure 9-16 assumes that t_RETRYhas expired by the time that T_Jreaches the hysteresis threshold.

LATCH = LO and DIA_EN = HI

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FLT

SNS signals

over-current

SNS signals

over-current

SNS signals

over-current

SNS signals

over-current

SNS

VOUT

EN

T^ABS

T^HYS

T^J

t

FLT

SNS signals over-current

Current Sense

SNS

VS – 1.8 V

VOUT

EN

T^ABS

T^HYS

T^J

t

Figure 9-16. Fault Indication During Retry

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9.3.4.3 Short-to-Supply or Open-Load Detection

The TPS272C45 is capable of detecting short-to-supply and open-load events regardless of whether the switch

is turned on or off, however the two conditions use different methods to signify fault. This feature enables

systems to recognize mis-wiring or wire-break events.

9.3.4.3.1 Detection With Switch Enabled

When the switch is enabled, the short-to-supply and open-load conditions are detected through the current

sense feature. In both cases, the load current drops from the nominal value and instead be measured as close to

zero. By measuring load current through the SNS pin, this state can be recognized.

9.3.4.3.2 Detection With Switch Disabled

While the switch is disabled and DIA_EN high, an internal comparator watches the condition of V_OUT. The

TPS272C45 includes a nominally 150-kΩ pull-up resistor from OUT pin to VS pin in series with a switch

controlled by the DIA_EN signal. So, if the load is disconnected (open load condition) or there is a short to

supply the V_OUTvoltage is pulled towards V_VS. In either of these events, the internal comparator measures V_OUT

as higher than the open load threshold (V_OL,off) and a fault is indicated on the FLT pin (Version A) or FLTx pins

(Version D) and on the SNS pin (only for versions A, B, C). No external component is required in most cases,

however if there is a pull-down resistor to GND on V_OUT, an additional external pull-up resistor can be necessary

to bias V_OUTappropriately.

Open load fault signaling on the SNS and the internal pull-up on OUT is enabled only if DIA_EN is set HI. To

detect open-load threshold at higher pull-down load current, an external pull-up resistor (and potentially a switch)

can be needed.

While the switch is disabled, the fault indication mechanisms continuously represent the present status.

For example, if V_OUTdecreases from greater than V_{OL_off}to less than V_{OL_off}, the fault indication is reset.

Additionally, the fault indication is reset upon the falling edge of DIA_EN (for SNS pin) or the rising edge of EN.

VS

V_(OL,off)

An_ol_fault

Digital

OUT

FLT

TPS272C45

GND

Figure 9-17. Open-Load Detection Circuit

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FLT

DIA_EN

SNS goes to ISNSFH

to indicate Open-

Load FLT

High-z

SNS

t_OL2

Enabled

V_OL

VOUT

EN

t

SNS output is

disabled

Open-Load occurs

and the condition is

determined by the

internal comparator.

Switch is disabled

The open-load fault is

indicated.

Figure 9-18. Open-Load Detection Timing

9.3.4.4 Current Sense Resistor Sharing

Multiple high-side devices can use the same R_SNSas shown in Figure 9-19. This action reduces the total number

of passive components in the system and the number of ADC terminals that are required of the microcontroller.

38

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Microcontroller

GPIO

DIA_EN

Switch 1

Switch 2

Switch 3

Switch 4

SNS

GPIO

ADC

RPROT

CSNS

RSNS

Figure 9-19. Sharing R_SNSAmong Multiple Devices

9.4 Device Functional Modes

During typical operation, the TPS272C45 can operate in a number of states that are described below.

9.4.1 Off

OFF state occurs when the device is not powered.

9.4.2 Diagnostic

DIAGNOSTIC state occurs with DIA_EN is high but ENx are both low. The switch can be used to perform

diagnostics like off-state open-load detection in this state.

9.4.3 Active

In ACTIVE state, the switch is enabled with ENx high. The diagnostic functions like current sense can be either

on or off during ACTIVE state.

9.4.4 Fault

The FAULT state is entered if a fault shutdown occurs (thermal shutdown or current limit). After all faults are

cleared, the LATCH pin is low, and the retry timer has expired, the device transitions out of FAULT state. If the

EN pin is high, the switch re-enables. If the EN pin is low, the switch remains off.

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

Figure 10-1 shows the schematic of a typical application of the TPS272C45. The schematic includes all standard

external components. This section of the data sheet discusses the considerations in implementing commonly

required application functionality.

If reverse polarity can be applied to the VS supply voltage input, the ground network protection circuit must be

added. The diode prevents the reverse current flow from the GND pin to supply. An additional resistor of 10

ohms or less is added to reduce the current flow if the VS to GND voltage rating is exceeded during any surge

conditions. TI recommends the 1-K resistor in parallel to keep the GND potential close to the board GND under

conditions where the ground network diode can be reverse biased.

VDD

C_VDD

VS

C_VIN1

C_VIN2

VS

GND

VDD DIA_EN

SEL

R_FLT

Optional

Reverse

Polarity

FLT

EN1

Protection

EN2

I/O Source

R_ILIMD

R_ILIM1

R_ILIM2

ILIMD

ILIM1

Load

VOUT1

VOUT2

C_OUT

ILIM2

Load

SNS

ADC

C_OUT

R_PROT

R_SNS

C_SNS

Figure 10-1. System Diagram

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Table 10-1. Recommended External Components

COMPONENT

TYPICAL VALUE

PURPOSE

R_SNS

1 kΩ

Translate the sense current into sense voltage.

R_PROT

10 kΩ

Low-pass RC filter resitance and protection for the ADC input.

C_SNS

100 pF

Low-pass filter capacitance for the ADC input.

R_ILIMx

5 kΩ to 40 kΩ

Set current limit threshold, connect from pin to IC GND.

Filtering of voltage transients (for example, ESD, IEC 61000-4-5) and improved

emissions.

C_Vin1

4.7 nF to Device GND

C_Vin2

C_VDD

C_OUT

Z_TVS

100 nF to Module GND Stabilize the input supply and filter out low frequency noise.

2.2 uF to Module GND

22 nF

Stabilize the input supply and limit supply excursions.

Filtering of voltage transients (for example, ESD, RF transients)

Clamp surge voltages at the supply input.

36-V TVS

Diode + < 10 ohm from

D_GND, Z_GND

Device GND to Module Optional for reverse polarity protection if needed.

GND

10.1.1 IEC 61000-4-5 Surge

The TPS272C45 is designed to survive against IEC 61000-4-5 surge using external TVS clamps. The device

is rated to 48 V ensuring that external TVS diodes can clamp below the rated maximum voltage of the

TPS272C45. Above 48 V, the device includes V_DSclamps to help shunt current and ensure that the device

survives the transient pulses. Depending on the class of the output, TI recommends that the system has a

SMBJ36A or SMCJ36A between VS and module GND.

10.1.2 Inverse Current

Inverse current occurs when 0 V < V_VS< V_OUT. In this case, current can flow from VOUT to VS. Inverse current

cannot be caused by a purely resistive load. However, a capacitive or inductive load can cause inverse current.

For example, if there is a significant amount of load capacitance and the V_Snode has a transient droop, V_OUT

can be greater than V_S.

The TPS272C45 does not detect inverse current. When the switch is enabled, inverse current passes through

the switch. When the switch is disabled, inverse current can pass through the MOSFET body diode. The device

continues operating in the normal manner during an inverse current event.

10.1.3 Loss of GND

The ground connection can be lost either on the device level or on the module level. If the ground connection is

lost, both the channel outputs are disabled irrespective of the EN input level. If the switch was already disabled

when the ground connection was lost, the outputs remain disabled even when the channels are enabled. The

steady state current from the output to the load that remains connected to the system ground is below the

level specified in the Specifications section of this document. When the ground is reconnected, normal operation

resumes.

10.1.4 Paralleling Channels

If an application requires lower power dissipation than is possible with a 45-mΩ switch, the TPS272C45 can

have both channel outputs and ENx pins tied together to function as a single 22.5-mΩ high side switch. In this

case, there is some decrease in I_SNSand I_LIMaccuracy, however the device functions properly.

10.1.5 Thermal Information

When outputting current, the TPS272C45 heats up due to the power dissipation. The transient thermal

impedance curve can be used to determine the device temperature during a pulse current of a given duration

(time). This Z_θJAvalue here corresponds to a JEDEC standard 2s2p thermal test PCB with no thermal vias.

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60

50

40

30

20

10

0

1E-5

0.0001

0.001

0.01

0.1

0.5

2 3 5 10 20

100

1000

time (s)

Figure 10-2. TPS272C45 Transient Thermal Impedance

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10.2 Typical Application

This application example demonstrates how the TPS272C45 device can be used as output switches in a digital

output module. In this example, consider an 8-channel module with a maximum output current capability of 2 A

per channel.

Backplane

Power

24-V Field

Power

V+

TPS272C45

VS

VDD

Charge

Pump

Output

Clamp

Gate

drive

V_OUT

MON

V_OUT

1

2

A0

A1

V_OUT

Fault and Protection

EN

FLT

SEL

DIA_EN

Current

Sense/

FAULT

SNS

V_SNS

GND

VS

V_OUT

2

A6

TPS272C45

4

GND

A7

To Additional

Channels

Figure 10-3. Block Diagram for PLC Digital Output Module

10.2.1 Design Requirements

For this design example, use the input parameters shown in Table 10-2.

Table 10-2. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_S

24 V +/–20%

Load

2-A maximum DC

Load type

Resistive, Inductive, Capacitive

Maximum of 2.4 A

Load current sense

Regulation current limit (I_LIM

Ambient temperature

Device version

)

2.6-A typical

70°C

A

10.2.2 Detailed Design Procedure

10.2.2.1 R_ILIMCalculation

In this application, the TPS272C45 must allow for the maximum DC current with margin but minimize the energy

in the switch and the load on the input supply during a fault condition by minimizing the current limit.

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The nominal current limit must be set such that the worst case (lowest) current limit is higher than the maximum

load current (2 A). Because the lower limit is 23% below the typical value, for this application, the best I_LIMset

point is approximately 2.6 A for both channels. The below equation allows you to calculate the R_ILIMvalue that is

placed from the I_LIMxpins to GND pin of the device. R_ILIMis calculated in kΩ.

R_ILIM= K_CL/ I_CL

(3)

The K_CLvalue in the Specifications section is 20.5 A × kΩ. So the calculated value of R_ILIMclosest 2% resistor is

7.87 kΩ.

10.2.2.2 Diagnostics

If the load is disconnected due a break in the connecting wire, an alert is desired. Open-load detection can be

performed in the switch-enabled state with the current sense feature of the TPS272C45 device. Similarly in the

off-state, a check for wire break can be performed. Under open load condition, with the DIA_EN set high, the

current in the SNS pin is the fault current and the can be detected from the sense voltage measurement.

10.2.2.2.1 Selecting the R_ISNSValue

Table 10-3 shows the requirements for the load current sense in this application. The K_SNSvalue is specified for

the device and can be found in the Specifications section.

Table 10-3. R_SNSCalculation Parameters

PARAMETER

EXAMPLE VALUE

Current sense ratio (K_SNS

)

1200

Largest diagnosable load current

Smallest diagnosable load current

2.4 A

50 mA

Full-scale ADC voltage

ADC resolution

5 V

10 bit

The load current measurement up to 2.4 A ensures that even in the event of a overcurrent but below the

set current limit, the MCU can register and react by turning off the FET while the low level of 50 mA allows

for accurate measurement of low load currents and enable the distinction open load faults from nominal load

currents.

The R_SNSresistor value can be selected such that the largest diagnosable load current puts the SNS pin

voltage (V_SNS) less than the ADC full-scale. With this design, any ADC value that shows full scale (FS) can be

considered a fault. Additionally, the R_SNSresistor value must ensure that the smallest diagnosable load current

does not cause V_SNSto fall below at a least a few LSB of the ADC. With the given example values, a 2.4-kΩ

sense resistor satisfies both requirements shown in Table 10-4.

Table 10-4. V_SNSCalculation

LOAD (A)

SENSE RATIO

1200

I_SNS(mA)

R_SNS(Ω)

V_SNS(V)

% of 5-V ADC

2.4

2.0

2400

4.8

96%

0.024

1200

0.02

2400

0.048

0.96% (9 LSB)

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10.2.3 Application Curves

Upon enabling our device into a capacitive load, TPS272C45 defaults its current limit to 2x ICL for a period of

time programmed set by ILIMD. In the figure below, you can see TPS272C45 charging a 1-mF capacitor using

the inrush current handling feature. During the first 4 mS after enabling the device, IOUT1 is 2 times the icl

programmed (4 A). After, the 4-mS period, the current folds back to the programmed icl (2 A).

Figure 10-4. TPS272C45 Capacitor Charging

If the device has a no-load case due to an open load or wire-break, the device registers the fault even in an

off-state if the DIA_EN pin is high. Figure 10-5 shows the device behavior when an open load event is registered

with EN low and DIAG_EN is raised. Systems can PWM DIA_EN to lower system power losses while still

watching for open load events and the same timing applies.

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Figure 10-5. Open-Load (t_OL) Detection Time

If the output of the TPS272C45 is short-circuited, the device protects the system from failure. Depending on

R_ILIM, the current limit set-point varies. The waveforms below show examples of the current limit behavior when

the device is enabled into a short circuit.

In the Figure 10-6, the output is permanently shorted. Upon enabling the device, the current reaches the 2 times

current limit is enabled for 6 mS set by ILIMD resistor. After the inrush current period, the current is reduced to

the programmed current limit set by R_ILIM.In this case, because the power dissipation is low enough, the device

is able to constantly act as a current source.

Figure 10-6. Enabling into Short (R_ILIM= 10 k , V_S= 6 V, Delay = 6 mS)

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In Figure 10-7, the output is also permanently shorted. Upon enabling the device, the current reaches the 2

times current limit, however because the power dissipation is greater due to the higher input voltage at Vs the

device reaches its thermal shutdown threshold and disables itself before reaching the programmed delay time.

Figure 10-7. Enabling into Short (R_ILIM= 10 k , V_S= 24 V, Delay = 6 mS)

The Figure 10-8 shows that after the device has been enabled into a short and due to the high power dissipation,

the device reaches its thermal shutdown threshold. The device then shuts down the FET for a period of tRETRY

and re-enables the FET into the short. The capture shows the continuous retry cycle and protection because the

short is permanently applied.

Figure 10-8. Permanent Short Behavior (R_ILIM= 10 k , V_S= 24 V, Delay = 6 mS)

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In the event a short is applied to the output while a load is being driven, the device activates its fast trip

comparator and shutdown the output to limit the inrush current. The device then immediately re-enables into

the short and limit the current to the programmed current limit value. The figure below describes the described

behavior.

Figure 10-9. On-State Short circuit (R_ILIM= 10 k , V_S= 24 V )

11 Power Supply Recommendations

The TPS272C45 device is designed to operate in a 24-V industrial system. The allowed supply voltage range

(VS pin) is 6 V to 36 V as measured at the VSpin with respect to the GND pin of the device. In this range

the device meets full parametric specifications as listed in the Electrical Characteristics table. The maximum

continuous operating voltage is 36 V. The device is also designed to withstand voltage transients beyond this

range. The device version A requires an external power supply input in the range 3.0 V to 5.5 V. The C and

D versions of the device have an secondary internal regulator (nominally 3.3 V) but an external supply can be

optionally provided at the VDD pin to lower the power dissipation in the IC. Version B always use an internal

3.3V regulator, so a single 24V supply (VS pin) is sufficient.

Table 11-1. Operating Voltage Range

Input Supply Voltage Range

Note

Supply voltage pin

Nominal supply voltage, all parametric

specifications apply. The device is completely

short-circuit protected up to 125°C.

VS

6 V to 36 V

Required for version A, and optional for

versions C and D. A DC/DC converter supply

reduces the overall power dissipation.

VDD

3.0 to 5.5 V

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12 Layout

12.1 Layout Guidelines

To achieve optimal thermal performance, connect the exposed pad to a large copper pour. On the top PCB layer,

the pour can extend beyond the package dimensions as shown in the example below. In addition to this, TI

recommends to also have a GND plane either on one of the internal PCB layers or on the bottom layer.

Vias must connect this plane to the top GND pour.

Ensure that all external components are placed close to the pins. Device current limiting performance can be

harmed if the R_ILIMis far from the pins and extra parasitics are introduced.

12.2 Layout Example

OUT2

13

14

15

16

7

6

5

4

3

2

1

SEL

LATCH

EN2

EN1

OUT2

NC

PowerPad^TM

OUT1

GND

ILIMD

17

18

OUT1

VDD 19

Figure 12-1. Layout Example

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13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

•

Texas Instruments, Adjustable Current Limit of Smart Power Switches application report

Texas Instruments, How to Drive Inductive, Capacitive, and Lighting Loads With Smart High-Side Switches

application report

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

13.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

23-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS272C45ARHFR

TPS272C45DRHFR

VQFN

RHF

24

3000

330.0

12.4

4.3

5.3

1.3

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS272C45ARHFR

TPS272C45DRHFR

VQFN

RHF

24

3000

367.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RHF0024A

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

0.5

0.3

5.1

4.9

0.30

0.18

DETAIL

OPTIONAL TERMINAL

TYPICAL

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2.65 0.1

2X 2

(0.1) TYP

12

EXPOSED

8

THERMAL PAD

20X 0.5

7

13

3.65 0.1

2X

3

25

SYMM

SEE TERMINAL

DETAIL

19

1

0.30

0.18

24X

0.1

C B A

PIN 1 ID

(OPTIONAL)

24

20

SYMM

0.05

0.5

0.3

24X

4219064 /A 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RHF0024A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.65)

SYMM

20

24

24X (0.6)

1

19

24X (0.24)

(3.65)

(1.575)

20X (0.5)

25

SYMM

(4.8)

(0.62)

TYP

(R0.05)

TYP

13

7

(

0.2) TYP

VIA

8

12

(1.025)

TYP

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

EXPOSED

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219064 /A 04/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RHF0024A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

6X (1.17)

(0.685) TYP

20

24

24X (0.6)

1

19

24X (0.24)

(1.24)

TYP

20X (0.5)

SYMM

(4.8)

25

6X (1.04)

13

(R0.05) TYP

7

METAL

TYP

12

8

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219064 /A 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS272C45
厂家：	TEXAS INSTRUMENTS
描述：	TPS272C45 45-mÎ©, Dual-Channel Smart High-Side Switch With Diagnostics
文件：	总59页 (文件大小：2545K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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