TPS274160BRLHR [TI]
具有可调节电流限制的 36V、160mΩ、1.35A、4 通道工业高侧开关 | RLH | 28 | -40 to 125;
| 型号： | TPS274160BRLHR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调节电流限制的 36V、160mΩ、1.35A、4 通道工业高侧开关 | RLH | 28 | -40 to 125 开关 |
| 文件： | 总38页 (文件大小：1532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS274160
ZHCSLS1A – MAY 2020 – REVISED NOVEMBER 2020
TPS274160x 160mΩ 四通道智能高侧开关
1 特性
3 说明
•
•
四通道 160mΩ 智能高侧开关
宽直流工作电压范围：5V 至 36V
– 50V 绝对最大电压
精确可调节电流限制范围（250mA 至 4A）
智能诊断功能
TPS274160 器件是一款智能高侧开关，通过四个集成
式 160mΩ NMOS 功率 FET 和一个电荷泵来驱动栅
极。该器件提供强大的保护和诊断功能，可以驱动各种
电感、容性和电阻性负载，例如低瓦数灯泡、LED、继
电器、电磁阀、加热器和子模块。该器件可通过并行通
道实现灵活的多通道输出配置，并采用超小型 WQFN
封装，可在空间受限的应用中使用。
•
•
– TPS274160A：开漏故障输出
– TPS274160B：模拟电流感应
– 关闭状态下开路负载或对电源短路检测
强大的保护特性
该器件具有短路和过热保护功能，可在故障期间安全地
关闭输出。该器件还支持从外部调节电流限值。这一特
性通过减小驱动大容性负载时的浪涌电流并尽可能降低
过载电流，可提高系统的可靠性，从而消除系统欠压的
情况。
•
– 短路保护
– 电感负载反激式钳位
– 欠压锁定 (UVLO) 保护
– 接地失效保护
该器件还集成了诊断功能，例如输出电流监控（B 版
本）和开路负载检测，从而使模块更加智能并实现预测
性维护功能。
• VS 和 OUT 引脚提供出色 ESD 保护
– ±8/±15kV IEC 61000-4-2 ESD 接触/空气放电
•
•
采用小型 28 引脚无引线 QFN 封装
提供功能安全
器件信息
封装(1)
器件型号
TPS274160A
TPS274160B
封装尺寸
– 可帮助进行功能安全系统设计的文档
2 应用
WQFN (28)
4mm x 5mm
•
•
•
•
数字输出模块
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
独立远程 I/O
电机驱动器
电磁阀或阀驱动器
5-V/24-V Field
Power
LDO or
DC/DC
3.3/5V
Optional
Input
Protection
(e-Fuse/
RPP)
Input
Protection
(e-Fuse)
ISO
DC/DC
Power
5-V/24-V
Backplane
Power
V+
TPS274160
VIN
Charge
Pump
Overcurrent Is Clamped
at the Set Value of 1 A.
Vds
Clamp
Gate
drive
VOUT
MON
VOUT
VOUT
VOUT
VOUT
1
2
A0
A1
Current Limit &
Thermal
Protection
Enable
and
Fault
De-
Serializer
4 EN
3
4
4
Digital
Isolation
A2
A3
Bus
ASIC
MCU
Current
Sense/
FAULT
4
ST
4
Serializer
GND
VIN
VOUT
4
A12
TPS274160
GND
To Additional
Channels
A15
GND
应用示例
驱动具有可调节电流限制的电容性负载
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSF05
TPS274160
ZHCSLS1A – MAY 2020 – REVISED NOVEMBER 2020
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................27
9 Application and Implementation..................................28
9.1 Application Information............................................. 28
9.2 Typical Application.................................................... 29
9.3 Capacitive Load Drive and Application Curves.........29
10 Power Supply Recommendations..............................30
11 Layout...........................................................................31
11.1 Layout Guidelines................................................... 31
11.2 Layout Examples.....................................................31
12 Device and Documentation Support..........................32
12.1 接收文档更新通知................................................... 32
12.2 支持资源..................................................................32
12.3 Trademarks.............................................................32
12.4 静电放电警告.......................................................... 32
12.5 术语表..................................................................... 32
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................6
7.6 Switching Characteristics ...........................................8
7.7 Typical Characteristics.............................................. 11
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................15
Information.................................................................... 32
4 Revision History
Changes from Revision * (May 2020) to Revision A (November 2020)
Page
更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
将数据表状态从“预告信息”更改为“量产数据”.............................................................................................1
•
•
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5 Device Comparison Table
PART NO.
TPS274160A
TPS274160B
FAULT REPORTING MODE
Open-drain digital output
Current-sense analog output
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6 Pin Configuration and Functions
1
2
3
4
5
6
7
22
21
20
OUT2
NC
1
2
3
4
5
6
7
22
21
20
OUT2
NC
EN3
EN4
ST1
EN3
EN4
SEH
SEL
FAULT
CS
VS
VS
VS
VS
PowerPadTM
PowerPadTM
ST2
19
18
19
18
ST3
ST4
VS
VS
VS
VS
17
16
15
17
16
15
CL
CL
NC
NC
OUT3
OUT3
8
8
NC
NC
NC – No internal connection
NC – No internal connection
图 6-1. RLH Package 28-Pin WQFN With Exposed
图 6-2. RLH Package 28-Pin WQFN With Exposed
Thermal Pad TPS274160A Top View
Thermal Pad TPS274160B Top View
表 6-1. Pin Functions
PIN
TPS274160
I/O
DESCRIPTION
NAME
Version A
Version B
Adjustable current limit. Connect to device GND if external current limit is not
used.
CL
7
7
O
CS
6
O
I
Current-sense output.
—
DIAG_EN
11
11
Enable-disable pin for diagnostics; internal pulldown.
Global fault report with open-drain structure, ORed logic for quad-channel fault
conditions.
FAULT
5
O
—
GND
EN1
EN2
EN3
EN4
NC
9,26
9, 26
Ground pin.
—
27
27
I
I
I
I
Input control for channel 1 activation; internal pulldown.
Input control for channel 2 activation; internal pulldown.
Input control for channel 3 activation; internal pulldown.
Input control for channel 4 activation; internal pulldown.
No internal connection.
28
28
1
1
2
2
8, 21, 16
8, 21, 16
—
O
O
O
O
I
ST1
3
4
5
6
Open-drain diagnostic status output for channel 1.
Open-drain diagnostic status output for channel 2.
Open-drain diagnostic status output for channel 3.
Open-drain diagnostic status output for channel 4.
CS channel-selection high bit; internal pulldown.
CS channel-selection low bit; internal pulldown.
Thermal shutdown behavior control, latch off or auto-retry; internal pulldown.
Output of the channel 1 high side-switch, connect to the load.
Output of the channel 2 high side-switch, connect to the load.
—
—
ST2
ST3
—
ST4
—
SEH
SEL
THER
OUT1
OUT2
3
—
—
4
I
10
10
I
24, 25
22, 23
24, 25
22, 23
O
O
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NAME
表 6-1. Pin Functions (continued)
PIN
TPS274160
I/O
DESCRIPTION
Version A
14, 15
Version B
14, 15
OUT3
OUT4
VS
O
O
I
Output of the channel 3 high side-switch, connect to the load.
12, 13
12, 13
Output of the channel 4 high side-switch, connect to the load.
Power supply.
17, 18, 19, 20 17, 18, 19, 20
Thermal
pad
Connect to device GND or leave floating
—
—
—
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
Input Voltage on Supply pin
50
V
(3)
Reverse polarity voltage (4)
V
mA
V
–36
–100
–0.3
–10
–0.3
–30
–2.7
—
Current on GND pin
t < 2 minutes
250
7
Voltage on ENx, DIAG_EN, SEL, SEH, and THER pins
Current on ENx, DIAG_EN, SEL, SEH, and THER pins
Voltage on STx or FAULT pins
Current on STx or FAULT pins
Voltage on CS pin
mA
V
—
7
10
7
mA
V
Current on CS pin
30
7
mA
V
Voltage on CL pin
–0.3
—
Current on CL pin
6
mA
°C
°C
Operating junction temperature
Storage temperature, Tstg
150
150
–40
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to GND.
(3) Maximum voltage including long transients < 400 ms.
(4) Reverse polarity condition:time t < 180s, reverse current < IR(2), ENx = 0 V, GND pin 1-kΩ resistor in parallel with diode.
7.2 ESD Ratings
VALUE
UNIT
Electrostatic
discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
All pins except VS and
VOUTx
V(ESD1)
V(ESD2)
V(ESD3)
V(ESD4)
±2000
V
Electrostatic
discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
VS and VOUTx with respect
to GND
±5000
±750
V
V
Electrostatic
discharge
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
All pins
Electrostatic
discharge
Contact/Air discharge, per IEC 61000-4-2 (3)
VS, OUTx
VS, OUTx
±8/±15
±1000
kV
V
Surge protection with 42 Ω, per IEC 61000-4-5;
1.2/50 μs (3)
V(surge) Transient surge
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Tested with the application circuit and supply voltage of 24 V DC and always ON, EN Inputs High → Output High (ON)
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
VVS
Continuous DC Supply operating voltage (1)
Voltage on ENx, DIAG EN, SEL, SEH, and THER pins
Voltage on ST and FAULT pins
5
0
36
5
V
0
5
V
Inom
TA
Nominal DC load current per channel (all channels on)
Operating ambient temperature range
0
1.35
125
A
°C
–40
(1) Transients up to the absolute maximum is allowed
7.4 Thermal Information
TPS274160
RLH(QFN)
28 PINS
31.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
17.3
9.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJT
9.6
ψJB
RθJC(bot)
0.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
(5 V ≤ Vs ≤ 36 V; −40°C ≤ TJ ≤ 125°C, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
3.5
3
TYP MAX UNIT
VVS(uvr)
VVS(uvf)
Undervoltage turnon
Undervoltage shutdown
VS voltage rising,VVS > VVS(uvr), device turns on.
VS voltage falling, VVS < VVS(uvf) device shuts off.
3.7
3.2
4
V
V
3.4
Undervoltage shutdown,
hysteresis
VVS(uv,hys)
Iqd
0.5
V
Device quiescent current,
diagnostics enabled
VVS < 30 V, ENx = 5 V, DIAG_EN = H/L, Ioutx = 0 A,
current limit = 2 A, all channels on
6.2
1.4
5
mA
VVS < 30 V, ENx = DIAG_EN = OUTx = THER = 0 V,
TJ = 25°C
Ioff
Standby current
µA
VVS < 30 V, ENx = DIAG_EN = OUTx = THER = 0 V,
TJ = 125°C
Standby current with diagnostic
enabled
VVS < 30 V, ENx = 0 V, DIAG_EN = 5 V, VVS – VOUTx
Vol(off), not in open-load mode
>
Ioff(diag)
toff(deg)
5
mA
ms
EN from high to low, if elapsed time > toff(deg), the
device enters into standby mode.
Standby mode deglitch time(1)
10
12.5
160
15
VVS < 30 V, ENx = DIAG_EN = OUTx = 0, TJ = 25°C
0.5
8
µA
µA
Iout(leak)
Output leakage current in off-state
VVS < 30 V, ENx = DIAG_EN = OUTx = 0, TJ < 125°C
V
VS ≥ 5V, TJ = 25°C
VS ≥ 5 V, TJ = 125°C
rDS(on)
On-state resistance
mΩ
260
6
V
Percentage Difference in On-state
resistance between channels
%
A
ΔrDS(on)
V
VS ≥ 5V, TJ = 25°C
(1)
(rDS(on)CHx - rDS(on)CHy
)
Icl(int)
Internal current limit
Internal current limit value, CL pin connected to GND
8
14
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7.5 Electrical Characteristics (continued)
(5 V ≤ Vs ≤ 36 V; −40°C ≤ TJ ≤ 125°C, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Internal current limit value under thermal shutdown
6.5
A
Current limit during thermal
shutdown
External current limit value under thermal shutdown.
The percentage of the external current limit setting
value
Icl(TSD)
70%
Source-to-drain body diode
voltage
Vds(clamp )
VF
50
70
V
V
A
0.3
0.7
2.5
0.9
Drain−source diode voltage
EN = 0, Iout = −0.15 A.
Continuous reverse current from t < 60 s, VVS = 24 V, ENx = 0 V, TJ = 25°C, single
source to drain
IR(1)
channel reversed current to supply
t < 60 s, VVS = 24 V, ENx = 0 V, GND pin 1-kΩ resistor
in parallel with diode. TJ = 25°C. Reverse-current
condition, All channels reversed
Continuous reverse current from
source to drain
IR(2)
2.0
A
VIH
Logic high-level voltage
Logic low-level voltage
Logic-pin pulldown resistor
2
V
V
VIL
0.8
R(logic,pd)
DIAG_EN VVS = VDIAG_EN=5V
200
100
275
175
350
kΩ
ENx, SEL, SEH, THER pins, VVS = VENx
VSEL=VSEH=VTHER=5V
=
R(logic,pd)
Ignd(loss)
Vol(off)
Logic-pin pulldown resistor
250
20
kΩ
µA
V
Output leakage current under
GND loss condition
VVS = 24 V
ENx = 0 V, when VVS – VOUTx> Vol(off), duration longer
than tol(off), then open load is detected, off state
Open load detection threshold
1.6
2.6
800
100
Open-load detection threshold
deglitch time
ENx =0V, when VVS – VOUTx> Vol(off) , duration longer
than tol(off), then open load is detected, off state
tol(off)
300
560
µs
ENx = 0 V, DIAG_EN= 5 V, VVS – VOUTx = 24 V, TJ =
125°C, open load
Iol(off)
Off-state output sink current
Status low-output voltage
µA
VOL(STx)
ISTx = 2 mA, version A only
IFAULT = 2 mA, version B only
0.2
0.2
V
V
VOL(FAULT) Fault low-output voltage
Deglitch time when current limit
occurs(1)
ENx = DIAG_EN = 5 V, the deglitch time from current
limit toggling to FAULT, STx, CS report.
tcl(deg)
80
180
µs
°C
°C
TSD
Thermal shutdown threshold
160
175
155
Thermal shutdown status reset
threshold
TSD(rst)
Thermal swing shutdown
threshold
Tsw
60
10
°C
°C
Hysteresis for resetting the
thermal shutdown or thermal
swing
Thys
KCS
KCL
Current sense ratio (Ver. B only)
Current limit ratio
300
2500
Current limit internal threshold
voltage(1) (2)
VCL(th
)
0.8
V
Current sense accuracy, (ICS
×
×
×
×
dKCS / KCS
dKCS / KCS
dKCS / KCS
dKCS / KCS
-50
-10
-5
50
10
5
%
%
%
%
VVS = 24 V, Ioutx ≥ 5 mA (Version B)
VVS = 24 V, Ioutx ≥ 25 mA (Version B)
VVS = 24 V, Ioutx ≥ 50 mA (Version B)
VVS = 24 V, Ioutx ≥ 100 mA (Version B)
K
CS – IOUT) /IOUT × 100
Current sense accuracy, (ICS
CS – IOUT) /IOUT × 100
Current sense accuracy, (ICS
CS – IOUT) /IOUT × 100
Current sense accuracy, (ICS
CS – IOUT) /IOUT × 100
K
K
-3
3
K
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7.5 Electrical Characteristics (continued)
(5 V ≤ Vs ≤ 36 V; −40°C ≤ TJ ≤ 125°C, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Current sense accuracy, (ICS
×
dKCS / KCS
dKCL / KCL
-2
2
%
%
VVS = 24 V, Ioutx ≥ 0.5 A (Version B)
K
CS – IOUT) /IOUT × 100
External current limit accuracy,
( IOUT – ICL × KCL –) × 100 / ICL VVS = 24 V, Ilimit ≥ 0.25 A
× KCL
-20
-15
20
External current limit accuracy,
( IOUT – ICL × KCL –) × 100 / ICL VVS = 24 V, 2 A ≤ Ilimit ≤ 7 A
× KCL
dKCL / KCL
15
4
%
V
0
0
V
VS ≥ 6.5 V
Current-sense voltage linear
range(1)
VCS(lin)
Vs –
2.5
5 V ≤ VVS < 6.5 V
0
0
2.2
2.2
6.5
V
VS ≥ 6.5 V, Vcs,lin ≤ 4 V
5 V ≤ VVS < 6.5 V, Vcs,lin ≤ VVS – 2.5 V
VS ≥ 7 V, fault mode
IOUTx(lin)
Output-current linear range(1)
A
V
4.5
V
Min(Vs
- 2,
VCS(H)
Current sense pin output voltage
6.5
V
5 V ≤ VVS < 7 V, fault mode
4.5)
Current-sense pin output current
available in fault mode
ICS(H)
Vcs = 4.5 V, VVS > 7 V
15
mA
µA
Current-sense leakage current in
disabled mode
ICS(leak)
DIAG_EN = 0 V, TJ =125ºC
0.5
(1) Value specified by design, not subject to production test.
(2) Vcl,th tolerance is included in the dKCL / KCL tolerance.
7.6 Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A, IN rising
edge to 10% of Voutx
td,on
Turnon delay time
Turnoff delay time
Channel turnon time
Channel Turnoff time
Turnon slew rate
20
50
50
90
90
µs
µs
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A, IN falling
edge to 90% of Voutx
td,off
20
90
VS = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A 50% of
EN to 90% of VOUT
td,rise
120
120
0.3
0.3
150
150
0.55
0.55
µs
VS = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A 50% of
EN to 10% of VOUT
td,fall
90
µs
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A, Voutx
from 10% to 90%
dV/dton
dV/dtoff
0.1
0.1
V/µs
V/µs
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A, Voutx
from 90% to 10%
Turnoff slew rate
Vs = 24 V, Iload= 0.5A. td, rise is the IN rising edge
to Vout = 90%.
td,match
50
µs
t
d,rise – td,fall
–50
td, fall is the IN falling edge to Vout = 10%.
CS settling time from DIAG_EN
disabled
Vs = 24 V, ENx = 5 V, Ioutx = 0.5 A. current limit =
2 A. DIAG_EN falling edge to 10% of Vcs.
tcs,off1
tcs,on1
tcs,off2
tcs,on2
20
20
µs
µs
µs
µs
CS settling time from DIAG_EN
enabled
Vs = 24 V, ENx = 5 V, Ioutx = 0.5 A. current limit is
2A. DIAG_EN rising edge to 90% of Vcs.
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A. current
limit = 2 A. EN falling edge to 10% of Vcs
CS settling time from IN falling edge
CS settling time from IN rising edge
100
150
Vs = 24 V, DIAG_EN = 5 V, Ioutx = 0.5 A. current
limit = 2 A. EN rising edge to 90% of Vcs
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PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
50 µs
DIAG_EN = 5 V, current sense output delay when
multi-sense pins SEL and SEH transition from
channel to channel
Multi-sense transition delay from
channel to channel
tSEx
td,rise
td,fall
V_ENx
90%
90%
V_OUTx
10%
10%
td,on
td,on dV/dton
dV/dtoff
图 7-1. Output Delay Characteristics
V_ENx
Iout
V_DIAG_EN
V_CS
tcs,off2
tcs,off1
tcs,on1
tcs,on2
图 7-2. CS Delay Characteristics
Open Load
V_ENx
Vcs,H
V_CS
V_STx, V_FLT
tol,off
图 7-3. Open-Load Blanking-Time Characteristics
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SEH
SEL
VCS
tSEx
VCS(CH2)
VCS(CH1)
图 7-4. Multi-Sense Transition Delay
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7.7 Typical Characteristics
1.6
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
DIAG_EN High
DIAG_EN Low
1.5
1.4
1.3
1.2
1.1
1
EN1 High
EN1 Low
EN2 High
EN2 Low
EN3 High
EN3 Low
EN4 High
EN4 Low
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
Ambient Temperature (èC)
D002
D001
图 7-6. DIAG_EN Voltage Threshold
图 7-5. ENx Voltage Threshold
1.5
0.8
OUT`1
OUT2
OUT3
OUT4
0.75
0.7
1.4
1.3
1.2
1.1
1
0.65
0.6
SEx High
SEx Low
0.55
0.5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
Ambient Temperature (èC)
D004
D003
图 7-8. Body-Diode Forward Voltage
图 7-7. SEx Voltage Threshold
64
0.3
0.25
0.2
63.5
63
62.5
62
61.5
61
0.15
0.1
60.5
60
59.5
59
Ch 1
Ch 2
Ch 3
Ch 4
5 V
13 V
24 V
0.05
58.5
58
0
57.5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
Ambient Temperature (èC)
D006
D005
图 7-10. Channel-1 FET On-Resistance
图 7-9. Drain-to-Source Clamp Voltage
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7.7 Typical Characteristics (continued)
0.3
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.05
0
0.15
0.1
5 V
13 V
24 V
5 V
13 V
24 V
0.05
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
Ambient Temperature (èC)
D0076
D0068
图 7-11. Channel-2 FET On-Resistance
图 7-12. Channel-3 FET On-Resistanc
0.3
18
16
14
12
10
8
Ch 1
Ch 2
Ch 3
Ch 4
0.25
0.2
0.15
0.1
6
4
5 V
13 V
24 V
0.05
2
0
-40
0
-40
-20
0
20
40
60
80
100 120 140
-20
0
20
40
60
Ambient Temperature (ºC)
80
100 120 140
Ambient Temperature (èC)
D0096
D010
图 7-13. Channel-4 FET On-Resistanc
图 7-14. Current-Sense Ratio at 5 mA
2.5
2.25
2
1
0.8
0.6
0.4
0.2
0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 1
Ch 2
Ch 3
Ch 4
1.75
1.5
1.25
1
0.75
0.5
0.25
0
-0.2
-0.4
-0.6
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
Ambient Temperature (èC)
D011
D012
图 7-15. Current-Sense Ratio at 25 mA
图 7-16. Current-Sense Ratio at 50 mA
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7.7 Typical Characteristics (continued)
1
1
0.5
0
Ch 1
Ch 2
Ch 3
Ch 1
0.8
Ch 2
Ch 3
Ch 4
0.6
Ch 4
0.4
0.2
0
-0.5
-1
-0.2
-0.4
-0.6
-0.8
-1
-1.5
-2
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
Ambient Temperature (èC)
D013
D014
图 7-17. Current-Sense Ratio at 100 mA
图 7-18. Current-Sense Ratio at 500 mA
1.5
Ch 1
Ch 2
Ch 3
Ch 4
0.5
1
0
-0.5
-1
-1.5
-2
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
D015
图 7-19. Current-Sense Ratio at 1 A
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8 Detailed Description
8.1 Overview
The TPS274160 device is a quad-channel smart high-side switch, with an internal charge pump and NMOS
power FETs. The TPS274160 device integrates fault diagnostics and a high-accuracy current-sense feature that
enable intelligent control of the load. The adjustable current-limit function greatly improves the reliability of whole
system. There are two versions of the device. The TPA274160A contains open drain digital output for diagnostic
reporting. The TPS274160B device implements a high accuracy current sense analog output.
TPS274160A device implements the digital fault report with an open-drain structure. When a fault occurs, the
device pulls STx down to GND. A 3.3- or 5-V external pullup is required to match the microcontroller supply
level. The digital status of each channel can report individually, or globally by connecting the STx pins together.
The TPS274160B device integrates a high-accuracy current sense circuit that enables precise load current
sensing without the need for on-board calibration. The integrated current mirror (selectable one-channel at a
time) can source a fraction (1 / K(CS) ) of the load current. The mirrored current flows into the CS-pin resistor to
become a voltage signal. K(CS) is a near-constant value across temperature and supply voltage. A wide linear
region from 0 V to 4 V allows a better real-time load-current monitoring. The CS pin can also report a fault with
pullup voltage of VCS(H)
.
The external high-accuracy current limit allows setting the current-limit value by applications. When overcurrent
occurs, the device improves system reliability by clamping the inrush current effectively. The device can also
save system cost by reducing the size of PCB traces and connectors, and the capacity of the preceding power
stage. Besides, the device also implements an internal current limit with a fixed value.
The TPS274160 device integrates active clamp between the drain and the source of the FETs. This clamp
ensures that the device is protected during switch off cycle of inductive loads like relays, solenoids and valves.
During the inductive load turn-off, the energy of the power supply and the load are dissipated on the high-side
switch. The device also optimizes the switching-off slew rate when the clamp is active, which helps the system
design by keeping the effects of transient power dissipation and EMI to a minimum.
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8.2 Functional Block Diagram
VS
Internal LDO
Internal Reference
Auxiliary Charge Pump
Temperature Sensor
Output
Clamp
Gate Driver
and
Charge Pump
ENx
OUT1
OUT2
Protection
and
Diagnostics
Oscillator
THER
CS
OUT3
OUT4
Current-Sense
Mux
Current Sense
SEH
SEL
ESD
Protection
Current Limit
CL
FAULT
Current Limit
Reference
2
DIAG_EN
GND
Diagnosis
STx
Temperature
Sensor
4
OTP
8.3 Feature Description
8.3.1 Pin Current and Voltage Conventions
Note that throughout the data sheet, the current directions on the respective pins are as shown by the arrows in
图 8-1. All voltages are measured relative to the ground plane.
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Ivs
VS
Vvs
IENx
VENx
ENx
VSTx
VFAULT
,
ISTx
IFAULT
,
STX,
FAULT
IDIAG_EN
VDIAG_EN
IOUTx
DIAG_EN
CL
VOUTx
OUTx
ICL
VCL
ICS
VCS
CS
ITHER
VTHER
THER
ISEx
VSEx
SEx
GND
IGND
VGND
Ground Plane
图 8-1. Voltage and Current Conventions
8.3.2 Accurate Current Sense
High-accuracy current sense is implemented in the TPS274160B device. This feature enables continuous
current monitoring and accurate load diagnostic without extensive calibration.
The integrated current mirror sources 1 / K(CS) of the load current, and the mirrored current flows into the
external current sense resistor to become a voltage signal. The current mirror is shared by the four channels.
K(CS) is the ratio of the output current and the sense current. It is a constant value across the temperature and
supply voltage. Each device is calibrated accurately during production, so post-calibration is not required. See 图
8-2 for more details.
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VSUP
VS
IOUT/K(CS)
IOUT
VCS(H)
FAULT
4x
OUTx
CS
R(CS)
图 8-2. Current-Sense Block Diagram
When a fault occurs, the CS pin also works as a fault report with a pullup voltage, VCS(H). See 图 8-3 for more
details.
VCS
VCS(H)
VCS(lin)
Fault Report
Current Monitor
IOUTx
Normal Operating
On-State: Current Limit, Thermal Fault
Off-State: Open Load or Short to Battery
or Reverse Polarity
图 8-3. Current-Sense Output-Voltage Curve
Use 方程式 1 to calculate R(CS)
.
V
CS ´ K(CS)
VCS
ICS
R(CS)
=
=
IOUTx
(1)
Take the following points into consideration when calculating R(CS)
.
• Ensure VCS is within the current-sense linear region (VCS, IOUTx(lin)) across the full range of the load current.
Check R(CS) with 方程式 2.
VCS(lin)
VCS
ICS
R(CS)
=
£
ICS
(2)
• In fault mode, ensure ICS is within the source capacity of the CS pin (ICS(H)). Check R(CS) with 方程式 3.
VCS(H,min)
VCS
ICS
R(CS)
=
³
ICS(H,min)
(3)
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8.3.3 Adjustable Current Limit
A high-accuracy current limit allows high reliability of the design. It protects the load and the power supply from
overstressing during short-circuit-to-GND or power-up conditions. The current limit can also save system cost by
reducing the size of PCB traces and connectors, and the capacity of the preceding power stage.
When a current-limit threshold is hit, a closed loop activates immediately. The output current is clamped at the
set value, and a fault is reported out. The device heats up due to the high power dissipation on the power FET. If
thermal shutdown occurs, the current limit is set to ICL(TSD) to reduce the power dissipation on the power FET.
See 图 8-4 for more details.
The device has two current-limit thresholds.
• Internal current limit – The internal current limit is fixed at ICL(int). Tie the CL pin directly to the device GND
for large-transient-current applications.
• External adjustable current limit – An external resistor is used to set the current-limit threshold. Use the 方程
式 4 to calculate the R(CL). VCL(th) is the internal band-gap voltage. K(CL) is the ratio of the output current and
the current-limit set value. It is constant across the temperature and supply voltage. The external adjustable
current limit allows the flexibility to set the current limit value by applications.
VCL(th)
IOUT
ICL
=
=
R(CL)
K(CL)
V
CL(th) ´ K(CL)
R(CL)
=
IOUT
(4)
VSUP
VS
IOUT/K(CL)
–
+
+
Internal Current Limit
–
IOUT
+
VCL(th)
4x
OUT
External Current Limit
–
+
VCL(th)
CL
图 8-4. Current-Limit Block Diargam
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Note that if using a GND network which causes a level shift between the device GND and board GND, the CL
pin must be connected with device GND.
For better protection from a hard short-to-GND condition (when the ENx pins are enabled, a short to GND occurs
suddenly), the device implements a fast-trip protection to turn off the related channel before the current-limit
closed loop is set up. The fast-trip response time is less than 1 μs, typically. With this fast response, the device
can achieve better inrush current-suppression performance.
8.3.4 Inductive-Load Turn-Off Clamp
When switching an inductive load off, the inductive reactance tends to pull the output voltage negative.
Excessive negative voltage could cause the power FET to break down. To protect the power FET, an internal
clamp between drain and source is implemented, namely VDS(clamp)
.
VDS(clamp) = VVS - VOUT
(5)
During the period of demagnetization (tdecay), the power FET is turned on for inductance-energy dissipation. The
inductive load energy is dissipated in the high-side switch. Total energy includes the energy of the power supply
(E(VS)) and the energy of the load (E(load)). If resistance is in series with inductance, some of the load energy is
dissipated on the resistance.
E
(HSS) = E(VS) + E(load) = E(VS) + E(L) - E(R)
(6)
When an inductive load switches off, E(HSS) causes a high thermal stress on the device.. The upper limit of the
power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation
condition.
VSUP
VDS(clamp)
EN
L
–
OUT
R
GND
+
图 8-5. Drain-to-Source Clamping Structure
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IN
VVS
VOUT
VDS(clamp)
E(HSS)
IOUT
t(decay)
图 8-6. Inductive Load Switching-Off Diagram, note EN pin waveform referred to as IN
From the perspective of the high-side switch, E(HSS) equals the integration value during the demagnetization
period.
t(decay)
E(HSS)
=
VDS(clamp) ´IOUT (t)dt
ò
0
æ
ö
÷
÷
ø
R´IOUT(max) + VOUT
L
t(decay)
=
´lnç
ç
è
R
VOUT
é
ù
ú
æ
ö
÷
÷
ø
R´IOUT(max) + VOUT
VVS + VOUT
ê
E(HSS) = L ´
´ R´IOUT(max) - VOUT lnç
R2
ç
VOUT
ê
ú
è
ë
û
(7)
(8)
When R approximately equals 0, E(HSD) can be given simply as:
VVS + VOUT
1
2
E(HSS)
=
´L ´IO2 UT(max
)
VOUT
图 8-7 is a waveform of the device driving an inductive load. Channel 1 is the EN signal (blue), channel 2 is the
supply voltage VVS (cyan), channel 3 is the output voltage VOUT (magenta), channel 4 is the output current
IOUT(green), and channel M is the measured power dissipation E(HSS)
.
On the waveform, the duration of VOUT from VVS to (VVS – VDS(clamp)) is around 120 µs. The device optimizes
the switch-off slew rate when the clamp is active. As shown in 图 8-7, the controlled slew rate is around 0.5 V/µs.
The 图 8-8 plots the maximum inductive energy (EAS) that can be discharged safely by the device a function of
the inductor load current in a single pulse in a single channel at one time. If the stored energy in the inductor at
the particular load current is higher, then an external clamp will be required.
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500
400
300
200
100
0
0
1
2
3
4
Load Current (A)
5
6
7
D020
图 8-8. Maximum Energy Dissipation (EAS) Allowed
图 8-7. Inductive Load Switching-Off Waveform
TJ_start = 125°C - Single Pulse, One Channel
Note that for PWM-controlled inductive loads, it is recommended to add the external freewheeling circuitry
shown in 图 8-9 to protect the device from repetitive power stressing. The TVS clamp is used to achieve the fast
decay. See 图 8-9 for more details.
VS
Output
Clamp
OUTx
GND
D
L
TVS
图 8-9. Protection With External Circuitry
8.3.5 Fault Detection and Reporting
8.3.5.1 Diagnostic Enable Function
The DIAG_EN pin enables or disables the diagnostic functions. If multiple devices are used, but the ADC
resource is limited in the microcontroller, the MCU can use GPIOs to set DIAG_EN high to enable the
diagnostics of one device while disabling the diagnostics of the other devices by setting DIAG_EN low. In
addition, the device can keep the power consumption to a minimum by setting DIAG_EN and ENx low.
8.3.5.2 Multiplexing of Current Sense
For version B, SEL and SEH are two pins to multiplex the shared current-sense function among the four
channels. See 表 8-1 for more details.
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表 8-1. Diagnosis Configuration Table
CS ACTIVATED
CHANNEL
DIAG_EN
ENx
SEH
SEL
CS, FAULT, STx
PROTECTIONS AND DIAGNOSTICS
H
L
Diagnostics disabled, full protection
Diagnostics disabled, no protection
L
High impedance
—
—
—
0
0
1
1
0
1
0
1
Channel 1
Channel 2
Channel 3
Channel 4
H
See Table 8-2
See 表 8-2
—
8.3.5.3 Fault Table
表 8-2 applies when the DIAG_EN pin is enabled.
表 8-2. Fault Table
STx
CS
FAULT
CONDITIONS
ENx OUTx THER CRITERION
FAULT RECOVERY
(VER. A) (VER. B) (VER. B)
L
L
H
H
0
H
H
—
—
—
—
—
—
Normal
In linear
region
H
H
Current limit
triggered
Overlaod, short to ground
H
L
L
L
L
VCS(H)
VCS(H)
L
L
Auto
Auto
—
—
Open load(1), short to supply,
reverse polarity
V
VS – VOUTx <
H
V(ol,off)
Output auto-retry. Fault
recovers when TJ < T(SD,rst) or
when ENx toggles.
L
Thermal shutdown
Thermal swing
H
H
TSD triggered
L
L
VCS(H)
L
L
—
—
Output latch off. Fault recovers
when ENx toggles.
H
TSW triggered
VCS(H)
Auto
—
(1) An external pullup is required for open-load detection.
8.3.5.4 STx and FAULT Reporting
For version A, four individual STx pins report the fault conditions, each pin for its respective channel. When a
fault condition occurs, it pulls STx down to GND. A 3.3- or 5-V external pullup is required to match the supply
level of the microcontroller. The digital status of each channel can be reported individually, or globally by
connecting all the STx pins together.
For version B, a global FAULT pin is used to monitor the global fault condition among all the channels. When a
fault condition occurs on any channel, the FAULT pin is pulled down to GND. A 3.3-V or 5-V external pullup is
required to match the supply level of the microcontroller.
After the FAULT report, the microcontroller can check and identify the channel in fault status by multiplexed
current sensing. The CS pin also works as a fault report with an internal pullup voltage, VCS(H)
.
8.3.6 Full Diagnostics
8.3.6.1 Short-to-GND and Overload Detection
When a channel is on, a short to GND or overload condition causes overcurrent. If the overcurrent triggers either
the internal or external current-limit threshold, the fault condition is reported out. The microcontroller can handle
the overcurrent by turning off the switch. The device heats up if no actions are taken. If a thermal shutdown
occurs, the current limit is ICL(TSD) to keep the power stressing on the power FET to a minimum. The device
automatically recovers when the fault condition is removed.
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8.3.6.2 Open-Load Detection
8.3.6.2.1 Channel On
When a channel is on and an open-load event occurs, it can be detected as an ultra-low VCS voltage at the CS
pin and handled by the micro-controller. The high-accuracy current sense in the low current range, enables the
open-load detection at very low current thresholds. Note that the detection is not reported on the STx or FAULT
pins. The microcontroller must proactively multiplex the SEL and SEH pins to detect the channel-on open-load
fault.
8.3.6.2.2 Channel Off
When a channel is off, if a load is connected, the output is pulled down to GND. But if an open load occurs, the
output voltage is close to the supply voltage (VVS – VOUTx< V(ol,off)), and the fault is reported out.
There is always a leakage current I(ol,off) present on the output due to internal logic control path or external
humidity, corrosion, and so forth. Thus, TI recommends an external pullup resistor to offset the leakage current
when an open load is detected. The recommended pullup resistance is 20 kΩ.
VSUP
Open-Load Detection in Off State
V(ol,off)
R(PU)
VDS
Load
图 8-10. Open-Load Detection in Off-State
8.3.6.3 Short-to-Supply Detection
Short-to-supply has the same detection mechanism and behavior as open-load detection, in both the on-state
and off-state. See 表 8-2 for more details.
In the on-state, reverse current flows through the FET instead of the body diode, leading to less power
dissipation. Thus, the worst case occurs in the off-state.
• If VOUTx – VVS < V(F) (body diode forward voltage), no reverse current occurs.
• If VOUTx – VVS > V(F), reverse current occurs. The current must be limited to less than IR(1). Setting an ENx
pin high can minimize the power stress on its channel. Also, for external reverse protection, see Reverse-
Current Protection for more details.
8.3.6.4 Input Reverse Polarity Detection
Reverse polarity detection has the same detection mechanism and behavior as open-load detection both in the
on-state and off-state. See 表 8-2 for more details.
In the on-state, the reverse current flows through the FET instead of the body diode, leading to less power
dissipation. Thus, the worst case occurs in the off-state. The reverse current must be limited to less than IR(2)
.
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Set the related ENx pin high to keep the power dissipation to a minimum. For external reverse-blocking circuitry,
see Reverse-Current Protection for more details.
8.3.6.5 Thermal Fault Detection
To protect the device in severe power stressing cases, the device implements two types of thermal fault
detection, absolute temperature protection (thermal shutdown) and dynamic temperature protection (thermal
swing). Respective temperature sensors are integrated close to each power FET, so the thermal fault is reported
by each channel. This arrangement can help the device keep the cross-channel effect to a minimum when some
channels are in a thermal fault condition.
8.3.6.5.1 Thermal Shutdown
Thermal shutdown is active when the absolute temperature TJ > T(SD). When thefrmal shutdown occurs, the
respective output turns off. The THER pin is used to configure the behavior after the thermal shutdown occurs.
• When the THER pin is low, thermal shutdown operates in the auto-retry mode. The output automatically
recovers when TJ < T(SD) – T(hys), but the current is limited to ICL(TSD) to avoid repetitive thermal shutdown.
The thermal shutdown fault signal is cleared when TJ < T(SD,rst) or after toggling the related ENx pin.
• When the THER pin is high, thermal shutdown operates in the latch mode. The output latches off when
thermal shutdown occurs. When the THER pin goes from high to low, thermal shutdown changes to auto-
retry mode. The thermal shutdown fault signal is cleared after toggling the related ENx pin.
Thermal swing activates when the power FET temperature is increasing sharply, that is, when ΔT = T(FET)
–
T(Logic) > T(sw), then the output turns off. The output automatically recovers and the fault signal clears when ΔT =
T(FET) – T(Logic) < T(sw) – T(hys). Thermal swing function improves the device reliability when subjected to
repetitive fast thermal variation. As shown in 图 8-11, multiple thermal swings are triggered before thermal
shutdown occurs.
Thermal Behavior After Short to GND
VTHER
VINx
T(SD)
T(SD,rst)
T(hys)
TJ
T(hys)
T(SW)
ICL
IOUTx
ICL(TSD)
VCS(H)
VCS
VFAULT
or VST
图 8-11. Thermal Behavior Diagram
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8.3.7 Full Protections
8.3.7.1 UVLO Protection
The device monitors the supply voltage VVS, to prevent unpredicted behaviors when VVS is too low. When VVS
falls down to VVS(uvf), the device shuts down. When VVS rises up to VVS(uvr), the device turns on.
8.3.7.2 Loss-of-GND Protection
When loss of GND occurs, output is shut down regardless of whether the ENx pin is high or low. The device can
protect against two ground-loss conditions, loss of device GND and loss of module GND.
8.3.7.3 Protection for Loss of Power Supply
When loss of supply occurs, the output is shut down regardless of whether the ENx pin is high or low. For a
resistive or a capacitive load, loss of supply has no risk. But for a charged inductive load, the current is driven
from all the I/O pins to maintain the inductance current. To protect the system in this condition, TI recommends
two types of external protections: the GND network or the external free-wheeling diode. In addition, the
recommended components per the application diagram needs to be implemented for protection.
VBAT
VS
I/Os
MCU
High-Side Switch
OUT
L
图 8-12. Protection for Loss of Power Supply, Method 1
VBAT
VS
I/Os
MCU
High-Side Switch
OUT
L
图 8-13. Protection for Loss of Power Supply, Method 2
8.3.7.4 Reverse-Current Protection
Reverse current occurs in two conditions: short to supply and reverse polarity.
• When a short to the supply occurs, there is only reverse current through the body diode. IR(1) specifies the
limit of the reverse current.
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• In a reverse-polarity condition, there are reverse currents through the body diode and the device GND pin.
IR(2) specifies the limit of the reverse current.
To protect the device, TI recommends two types of external circuitry.
• Adding a blocking diode. Both the IC and load are protected when in reverse polarity.
VBAT
VS
´
OUT
Load
Copyright © 2016, Texas Instruments Incorporated
图 8-14. Reverse-Current External Protection, Method 1
• Adding a GND network. The reverse current through the device GND is blocked. The reverse current through
the FET is limited by the load itself. TI recommends a resistor in parallel with the diode as a GND network.
The recommended selection are 1-kΩ resistor in parallel with an > 100-mA diode. If multiple high-side
switches are used, the resistor and diode can be shared among devices. The reverse current protection
diode in the GND network forward voltage should be less than 0.6 V in any circumstances. In addition a
minimum resistance of 4.7 K is recommended on the I/O pins.
VSUP
VS
OUT
Load
图 8-15. Reverse-Current External Protection, Method 2
8.3.7.5 MCU I/O Protection
In some severe conditions, such as the high voltage transients or the loss of supply with inductive loads, a
negative pulse occurs on the GND pin This pulse can cause damage on the connected microcontroller. TI
recommends serial resistors to protect the microcontroller, for example, 4.7-kΩ when using a 3.3-V
microcontroller and 10-kΩ for a 5-V microcontroller.
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VSUP
I/Os
VS
MCU
High-Side Switch
OUT
Load
图 8-16. MCU I/O External Protection
8.4 Device Functional Modes
8.4.1 Working Modes
The device has three working modes, the normal mode, the standby mode, and the standby mode with
diagnostics.
Note that IN must be low for t > t(off,deg) to enter the standby mode, where t(off,deg) is the standby mode deglitch
time used to avoid false triggering. 图 8-17 shows a working-mode diagram.
Standby Mode
(ENx low, DIAG low)
DIAG_EN low and
ENx high to low and
t > toff,deg
DIAG_EN
high to low
ENx low to high
DIAG_EN
low to high
ENx high to low and
DIAG_EN high and
t > toff,deg
Standby mode
with diagnostic
(ENx low, DIAG high)
Normal Mode
(ENx high)
ENx low to high
图 8-17. Working Modes
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9 Application and Implementation
Note
以下应用部分的信息不属于 TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
图 9-1 shows the schematic of a typical application of the . It includes all standard external components. This
section of the datasheet discusses the considerations in implementing commonly required application
functionality.
Supply
Input
CVS
VS
R(ser)
Load
OUT1
OUT2
EN1, 2, 3, 4
DIAG_EN
COUT
R(ser)
R(ser)
Load
Load
Load
Legend
SEH
SEL
COUT
COUT
COUT
R(ser)
MCU
Module GND
Device GND
OUT3
OUT4
5 V
R(pu)
R(ser)
FAULT
CS
CL
OPTIONAL for
reverse polarity
protection
R(CS)
THER
GND
RGND
DGND
R(CL)
With the ground protection network, the device ground will be offset relative to the microcontroller ground.
图 9-1. System Diagram
表 9-1. Recommended External Components
COMPONENT
R(ser)
TYPICAL VALUE
PURPOSE
Protect microcontroller and device I/O pins
Translate the sense current into sense voltage
Low-pass filter for the ADC input
10 kΩ
R(CS)
CSNS
RGND
DGND
1 kΩ
100 pF - 10 nF
1 kΩ
Stabilize GND potential during turn-off of inductive load
Protects device during reverse supply condition
BAS21 Diode
Set current limiting value, short to IC GND to set the current limit to the internal
setting.
R(CL)
1-kΩ typical
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表 9-1. Recommended External Components (continued)
COMPONENT
TYPICAL VALUE
PURPOSE
10 nF to Device GND and
100 nF to module GND
CVS
Filtering of voltage transients (for example, surge)
ZVS
TVS to module GND
22 nF
Clamp voltage spikes at the input.
COUT
Filtering of voltage transients (for example, ESD)
9.2 Typical Application
The following figure shows example of a typical application based on the TPS274160B device. The loads can be
varied and be different on each channel.
Supply
Input
VS
R(ser)
LED Strings,
Small Power Bulbs
OUT1
EN1, 2, 3, 4
DIAG_EN
R(ser)
Solenoids, Valves, Relays
R(ser)
OUT2
OUT3
SEH
SEL
R(ser)
MCU
Power-Module:
Cameras, Sensors, Displays
5 V
R(pu)
General Resistive, Capacitive,
Inductive Loads
R(ser)
OUT4
FAULT
CS
CL
R(CS)
GND
THER
R(CL)
图 9-2. Typical Application Diagram.
9.2.1 Design Requirements
• VVS = 24-V nominal
• Load range is from 0.1 A to 1 A for each channel
• Current sense for fault monitoring
• Expected current-limit value of 2.5 A
• Automatic recovery mode when thermal shutdown occurs
• Full diagnostics with 5-V MCU
9.2.2 Detailed Design Procedure
To keep the 1-A nominal current in the 0 to 4-V current-sense range, calculate the R(CS) resistor using 方程式 9.
To achieve better current-sense accuracy, a 1% tolerance or better resistor is preferred.
V
CS´ K(CS)
VCS
ICS
4´ 300
R(CS)
=
=
=
= 1200 W
IOUT
1
(9)
To set the adjustable current limit value at 2.5-A, calculate R(CL) using 方程式 10.
V
CL(th) ´ K(CL)
0.8´ 2500
R(CL)
=
=
= 800 W
IOUT
2.5
(10)
TI recommends R(ser) = 10 kΩ for 5-V MCU, and R(pu) = 10 kΩ as the pullup resistor.
9.3 Capacitive Load Drive and Application Curves
In this application example we show the case of driving a large capacitive load at the input of a sensor hub
supply node. The input capacitance is a 2.3-mF capacitor and is charged to a 12-V supply voltage . The nominal
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total load current at the node is 0.4 A and the current limit is set to 1 A and chosen to be well in excess of the
peak load current. 图 9-3 shows a test example of soft-start when driving the large capacitive load. 图 9-4 shows
an expanded waveform of the output current.
Overcurrent Is Clamped
at the Set Value of 1 A.
VS = 12 V
Load current = 0.4
A
Current limit = 1 A
CH1 = ENx
VVS = 12 V
Load current = 0.4
A
Current limit = 1 A
CH1 = ENx
ENx = ↑
ENx = ↑
CL = 2.3 mF
CL = 2.3 mF
CH2 = FAULT
CH3 = output
voltage
CH4 = output
current
CH2 = FAULT
CH3 = output
voltage
CH4 = output
current
图 9-3. Driving a Capacitive Load With Adjustable
图 9-4. Driving a Capacitive Load, Expanded
Current Limit
Waveform
10 Power Supply Recommendations
The TPS274160 device is designed to operate with a 12-V or 24-V nominal DC supply input. The DC supply
voltage range should be within the range specified in the Recommended Operating Conditions. The device is
also designed to withstand voltage transients beyond this range at the supply input pin up to the absolute
maximum voltage specifications.
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11 Layout
11.1 Layout Guidelines
To prevent thermal shutdown, TJ must be less than 150°C. The WQFN package has good thermal impedance.
However, the PCB layout is very important. Good PCB design can optimize heat transfer, which is absolutely
essential for the long-term reliability of the device.
• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat
flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when there are not any heat sinks attached to the PCB on the other side of the package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
11.2 Layout Examples
11.2.1 Without a GND Network
Without a GND network, tie the thermal pad directly to the board GND copper for better thermal performance.
1
2
3
4
5
6
7
22
21
20
OUT2
NC
EN3
EN4
ST1
VS
VS
ST2
19
18
Thermal
Pad
ST3
ST4
VS
VS
17
16
15
CL
NC
OUT3
8
NC
图 11-1. Layout Example Without a GND Network
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS274160ARLHR
TPS274160BRLHR
ACTIVE
ACTIVE
WQFN
WQFN
RLH
RLH
28
28
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
274160A
274160B
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RLH0028A
4.1
3.9
A
B
PIN 1 INDEX AREA
5.1
4.9
0.8
MAX
A
SEATING PLANE
0.08 C
0.05
0.00
2.55±0.1
2X 2.5
(0.1) TYP
9
14
24X 0.5
8
15
SYMM
29
2X
3.55±0.1
3.5
1
22
0.30
28X
PIN 1 ID
(OPTIONAL)
0.18
28
23
0.1
C A B
C
SYMM
0.5
0.3
0.05
28X
4224734/A 12/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RLH0028A
PLASTIC QUAD FLATPACK- NO LEAD
(3.8)
(2.55)
2X (2.5)
23
28
28X (0.6)
28X (0.24)
1
22
24X (0.5)
4X (0.61)
SYMM
2X
29
(3.55) (4.8)
(3.5)
2X
(1.525)
8
15
(R0.05) TYP
9
14
(Ø 0.2) VIA
TYP
4X (1.025)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
0.07 MAX
ALL AROUND
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224734/A 12/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RLH0028A
PLASTIC QUAD FLATPACK- NO LEAD
(3.8)
2X (2.5)
6X (1.13)
23
28
28X (0.6)
28X (0.24)
1
22
24X (0.5)
6X
(1.02)
29
SYMM
2X
(4.8)
(3.5)
2X
(1.22)
8
15
(R0.05) TYP
METAL
9
14
TYP
4X (0.665)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
76% PRINTED COVERAGE BY AREA
SCALE: 15X
4224734/A 12/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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