TPS274C65_技术文档

TPS274C65

SLVSFZ2 – APRIL 2023

TPS274C65xS 65-mΩ, Quad-Channel Smart High-Side Switch With SPI Interface and

Diagnostics

1 Features

3 Description

•

Quad-channel 65-mΩ R_ONSPI-controlled smart

high-side switch

– Low R_ONensures low power dissipation for

500-mA to 2-A DC loads

– SPI control allows for simple isolation of control

from output

Adjustable current limiting enables improved

system level reliability

– Current limit set-point from 300 mA to 2.6 A

Capable of driving inductive, capacitive, and

resistive loads

– Dual current limit threshold for inrush current

management

The TPS274C65xS device is a quad-channel smart

high-side switch with a serial interface (SPI) control

and is designed to meet the requirements of industrial

control systems. The low 65-mΩ R_DSONminimizes

device power dissipation even when providing large

output load current. The device integrates protection

and diagnostic features to ensure system protection

even during harmful events like short circuits or load

failures. The device protects against faults through a

reliable current limit which is adjustable from 300 mA

to 2.6 A to provide protection regardless of output

load current. The TPS274C65xS has a configurable

inrush current period which sets a higher current limit

during turn-on for high inrush current loads, charging

capacitive loads faster, or driving incandescent bulbs.

•

– Integrated output clamp to demagnetize

inductive loads

•

Robust output protection

The TPS274C65xS also provides accurate current

sense and an integrated analog to digital converter

(AS) that allows for improved load diagnostics. By

reporting load current digitally, the device allows

for communication over any isolation barrier while

enabling predictive maintenance and load diagnostics

to improve system lifetime. Additional diagnostic

features are integrated, such as on-state or off-state

open load detection and short-to-supply detection.

– Integrated thermal shutdown

– Protection against short to ground events

– Configurable fault handling

Diagnostic features enable improved module

intelligence

– Output load current measurements

– Wire-break and short to supply detection

Small 6 mm x 6 mm leadless package

The TPS274C65xS is available in a small 6 mm ×

6 mm QFN package with 0.5-mm pin pitch which

minimizes solution PCB footprint.

2 Applications

•

Industrial PLC system

– Digital output module

– IOLink master port

– Sensor supply

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

TPS274C65xS

QFN (40)

6.00 mm × 6.00 mm

24V

Optional

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

DC/DC

Converter

5V/3.3V

REG_EN

VDD

VS

TPS274C65xS

INT_REG

Status

LEDs

Charge

Pump

LEDx

LED

Module

Output

Clamp

Gate

drive

V^IN/V^OUT

MON

OUTx

4

Config,

Open Load

Flags &

Protection

Detection

Reverse

Current

Blocking

4

FLT

Current

Sense

RCBx

Temp

Sense

MUX

MCU

ADC

VOUT

Sense

SPI

4

Interface

SPI

Typical Application Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change

without notice.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

6.1 Pinout - Version AS & BS............................................5

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings........................................ 7

7.2 ESD Ratings............................................................... 7

7.3 Recommended Operating Conditions.........................7

7.4 Thermal Information....................................................8

7.5 Electrical Characteristics.............................................8

7.6 Switching Characteristics..........................................11

7.7 SPI Timing Requirements......................................... 12

8 Parameter Measurement Information..........................13

9 Detailed Description......................................................14

9.1 Overview...................................................................14

9.2 Functional Block Diagram.........................................15

9.3 Feature Description...................................................15

9.4 Device Functional Modes..........................................44

10 TPS274C65BS Available Registers List.....................45

11 TPS274C65 Registers..................................................47

12 Application and Implementation................................69

12.1 Application Information........................................... 69

12.2 Power Supply Recommendations...........................72

12.3 Layout..................................................................... 72

13 Device and Documentation Support..........................74

13.1 Receiving Notification of Documentation Updates..74

13.2 Support Resources................................................. 74

13.3 Trademarks.............................................................74

13.4 Electrostatic Discharge Caution..............................74

13.5 Glossary..................................................................74

14 Mechanical, Packaging, and Orderable

Information.................................................................... 75

14.1 Tape and Reel Information......................................75

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

April 2023

*

Initial Release

2

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5 Device Comparison Table

Table 5-1. Functionality Comparison

Reverse

Current

Blocking

(RCB)

Integrated Integrated

Part Number

Interface

Current Sense

Available Registers

LED Driver

ADC

Digital via SPI or analog

output

See TPS274C65

Registers

TPS274C65AS

TPS274C65BS

SPI

Yes

No

Yes

No

Yes

No

See TPS274C65BS

Available Registers List

No current sense

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6 Pin Configuration and Functions

40

39

38

37

36

35

34

33

32

31

1

2

READY

FLT

30

29

28

27

26

25

24

23

22

21

ADDCFG

REG_EN

3

DSPI

DNC

DO_EN

VDD

4

5

DNC

GND

ISNS

PowerPad™

6

LEDOUT4

7

SDO

LEDOUT3

LEDOUT2

LEDOUT1

8

SDI

SCLK

9

10

CS

GND

12

13

14

15

16

17

18

19

20

11

Figure 6-1. RHA Package, 40-Pin QFN, AS Version (Top View)

4

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40

39

38

37

36

35

34

33

32

31

DNC

FLT

1

2

30

29

28

27

26

25

24

23

22

21

ADDCFG

REG_EN

3

DSPI

DNC

DO_EN

VDD

4

5

DNC

GND

DNC

PowerPad

6

7

SDO

DNC

8

SDI

SCLK

9

10

CS

GND

12

13

14

15

16

17

18

19

20

11

Figure 6-2. RHA Package, 40-Pin QFN, BS Version (Top View)

6.1 Pinout - Version AS & BS

Do Not Connect for pins labeled DNC

TPS274C65AS

TPS274C65BS

Type

Description

Number

Logic low output indicating the IC is ready for SPI data transmission

(connect to GND pin of the IC with resistor)

1

READY

DNC⁽⁽²⁾⁾

FLT

O

I

Fault output – on any (one or more) channel - open drain, needs to

be pulled up to VDD pin

2

3

FLT

Setting this pin low would disable all of the outputs. Set high to

enable SPI based output Internal pull-down

DO_EN

4

VDD⁽¹⁾

GND

VDD⁽¹⁾

GND

P

--

Logic Supply Input⁽¹⁾

5,21

Device ground

SNS current output – use a parallel RC network to the GND pin of

the IC.

6

ISNS

DNC⁽²⁾

O

7

SDO

SDI

SDO

SDI

I

SPI Data Output from the device

SPI device (secondary) data input

SPI Clock Input

8

I

9

SCLK

CS

SCLK

O

I

10

CS

SPI Chip select

11

RCB3

OUT3

VS

DNC⁽²⁾

OUT3

VS

O

P

Gate connection for reverse current blocking FET Ch3

Output voltage for channel 3

24V Switch Supply input to the IC

12,13

14-17

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Do Not Connect for pins labeled DNC

TPS274C65AS

OUT4

TPS274C65BS

Type

Description

Output voltage for channel 4

Number

18,19

20

OUT4

O

--

RCB4

DNC⁽²⁾

Gate connection for reverse current blocking FET Ch4

LED matrix select driver

Do not connect

22

LEDOUT1

LEDOUT2

LEDOUT3

LEDOUT4

DNC⁽²⁾

23

24

25

26

27

DNC⁽²⁾

--

Do not connect

Configure the device in daisy chain SPI mode when the pin is pulled

HI

28

29

DSPI

I

Internal Regulator Enable pin, float to enable. Tie to GND to disable

and use an external supply input to VDD

REG_EN

SPI IC Address Configuration pin – set the 3-bit address of each IC

(up to 8 on one board) with a resistor to GND pin of the IC. Leave

floating if using Daisy Chain mode.

30

ADDCFG

I

31

RCB2

OUT2

VS

DNC⁽²⁾

OUT2

VS

O

P

Gate connection for reverse current blocking FET Ch2

Output voltage for channel 2

32,33

34-37

38,39

40

24V Switch Supply input to the IC

OUT1

RCB1

OUT1

DNC⁽²⁾

O

Output voltage for channel 1

Gate connection for reverse current blocking FET Ch1

Exposed

Pad

GND

I

Connected to GND pin of the IC

(1) When the device is configured to support an external regulator connected to VDD, it is required that the

supply input for the external regulator is derived from the same VS supply of TPS274C65 as shown in the Typical Application

Schematic.

(2) Do Not Connect for pins labeled DNC

6

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7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

-0.3

MAX

39

UNIT

V

Continuous supply voltage, V_VSto IC_GND

Maximum transient (< 1 ms) voltage at the supply pin (with respect to IC GND), V_VS, during ON state

VOUT voltage to IC_GND

60

V

-30 V_VS+0.3

V

V_DSvoltage

-0.7

–0.3

-0.3

–0.3

39

7.0

V

Low voltage supply pin voltage, V_DD

Digital Input pin voltages, V_DIG

LED drive pin voltage, V_{LED_OUT}

Analog pin voltage REG_EN

Low voltage supply pin voltage, V_DD

V

VOUT

-0.7

RCBx pin voltage, V_RCBx

VOUT + 6

V

Sense pin voltage, V_SNS

FLT pin voltage, V_FLT

–0.3

7.0

V

FLT pin voltage, V_FLT

ST pin voltage, V_ST

V_S< 0 V

ST pin voltage, V_ST

7.0

V

Reverse ground current, I_GND

Maximum junction temperature, T_J

Storage temperature, T_stg

–50

150

mA

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

UNIT

Electrostatic

discharge

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001⁽¹⁾

All pins except VS and

VOUTx

V_ESD1

V_ESD2

V_ESD3

±2000

V

Electrostatic

discharge

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001⁽¹⁾

VS and VOUTx with respect

to GND

±4000

±500

Electrostatic

discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

All pins

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

12

MAX

UNIT

V_{S_OPMAX}

V_DD

Nominal supply voltage

36

5.5

5.0

125

V

Low Voltage Supply Voltages

All Digital Input pin voltage

ST, FLT pin voltage

Low Voltage Supply Voltages

3.0

V_DIG

–0.3

–40

V

V_ST,V_FLT

V_{LED_OUTx}

V_ANA

ST, FLT pin voltage

V

LED_OUTx pin voltage

V

SNS, ADDCFG, REG_EN pin voltage

Operating free-air temperature

V

T_A

°C

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UNIT

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7.4 Thermal Information

TPS274C65X

RHA (QFN)

40 PINS

25.4

THERMAL METRIC^{(1) (2)}

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

15.8

7.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

7.6

R_θJC(bot)

0.6

(1) For more information about traditional and new thermal metrics, see the SPRA953 application report.

(2) The thermal parameters are based on a 4-layer PCB according to the JESD51-5 and JESD51-7 standards.

7.5 Electrical Characteristics

V_VS= 11 V to 36 V, V_VDD= 3.0 V to 5.5 V, T_J= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT VOLTAGE AND CURRENT

V_{DS_Clamp}

V_DSclamp voltage

CHx

FET current = 10 mA, V_S= 24 V

39

33

44

37

50

41

V

V_{DS_Clamp}

FET current = 10 mA, V_SFET current = 10 mA, V_S

V_DSclamp voltage

CHx

= 19 V

V_{DS_Clamp}

FET current = 10 mA, V_SFET current = 10 mA, V_S

V_DSclamp voltage

CHx

= 10 V

Measured with respect

to the GND pin of the

device, All channels ON threshold.

Output FETs turned off

at VS less than this

V_Sundervoltage

V_{S_UVPF}

8

9

10

V

protection falling

Measured with respect

to the GND pin of the

device, All channels ON threshold.

Output FETs turned ON

at VS more than this

V_Sundervoltage

V_{S_UVPR}

9

10

20

11

25

V

protection recovery rising

V_Sundervoltage

V_{S_UVPRH}

Time from triggering the UVP fault to FET turn-off

15

µs

protection deglitch time

Reported in

Measured with respect

VS_UV_WRN register

to the GND pin of the

bit when below this

device,

V_Sundervoltage warning

V_{S_UVWF}

falling

11.5

12.5

13.5

14.5

V

threshold

VS_UV_WRN register bit

Measured with respect

cleared when below this

to the GND pin of the

threshold and register

device,

V_Sundervoltage warning

V_{S_UVWR}

recovery rising

read

V_DDundervoltage

V_DD,UVLOF

Measured with respect to the GND pin of the device

2.7

2.8

2.9

V

lockout falling

V_DDundervoltage lockout

V_DD,UVLOR

rising

2.88

2.98

All channels enabled, T_AMB= 85°C

Two channels enabled, T_AMB= 85°C

1.6

2.5

A

Continuous load current,

per channel

IL_NOM

Vs = VOUT <36

V, Switch and All

Diagnostics disabled,

measured into the OUTx

Leakage current from

Iout,leakx

40

µA

OUT to GND in off-state

8

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7.5 Electrical Characteristics (continued)

V_VS= 11 V to 36 V, V_VDD= 3.0 V to 5.5 V, T_J= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VS <= 36 V, V_OUT= 0

Channel disabled, diagnostics disabled. Tj <= 85C

0

0.5

3.0

µA

Output leakage current

(per channel)

I_OUT(OFF)

VS <= 36 V, V_OUT= 0

Channel disabled, diagnostics disabled Tj <= 125C

0

1

10

µA

V_DDquiescent current,

SCLK ON, all

diagnostics disabled,

(WB_OFF, WB_ON,

SHRT_VS, ADC)

external VDD

V_S≤ 36 V, V_DD= 5.5 V

All channels

enabled, I_OUTx= 0 A

V_S≤ 36 V, V_DD= 5.5 V

All channels

enabled, I_OUTx= 0 A

VDD I_Q

2.8

3.5

mA

VDD quiescent current,

SCLK off, all diagnostics

disabled ((WB_OFF,

WB_ON, SHRT_VS),

ADC enabled and

V_S≤ 36 V, V_DD= 5.5 V

All channels

enabled, I_OUTx= 0 A

V_S≤ 36 V, V_DD= 5.5 V

All channels

enabled, I_OUTx= 0 A

VDD I_Q

1.85

2.1

mA

converting, external VDD

V_Squiescent current,

SCLK off, all

diagnostics disabled,

(WB_OFF, WB_ON,

SHRT_VS, ADC) internal

VDD

V_S≤ 36 V,

All channels

enabled, I_OUTx= 0 A

V_S≤ 36 V,

All channels

enabled, I_OUTx= 0 A

VS I_Q

I_{leak_LG}

4.9

2.0

5.6

2.45

24

mA

V_Squiescent current,

SCLK off, all diagnostics V_S≤ 36 V, V_DD= 3.0 V

(WB_OFF, WB_ON,

SHRT_VS, ADC)

enabled, external VDD

V_S≤ 36 V, V_DD= 3.0 V

All channels

enabled, I_OUTx= 0 A

All channels

enabled, I_OUTx= 0 A

V_Squiescent current,

SCLK off, all diagnostics

(WB_OFF, WB_ON,

SHRT_VS, ADC)

disabled, RCB enabled,

external VDD

V_S≤ 36 V, V_DD= 3.0 V

All channels

enabled, I_OUTx= 0 A

V_S≤ 36 V, V_DD= 3.0 V

All channels

enabled, I_OUTx= 0 A

2.0

Leakage current out of

the output pins with the

GND of IC disconnected, RL = 24 Ω

Load ground connected All channels enabled

to supply ground

V_S≤ 30 V, V_DD= 5.5 V,

RL = 24 Ω

All channels enabled

0.65

RON CHARACTERISTICS

T_J= 25°C

T_J= 85°C

T_J= 125°C

T_J= 25°C

T_J= 85°C

T_J= 125°C

65

33

mΩ

On-resistance

(Includes MOSFET and

package)

10 V ≤ V_S≤ 36 V, I_OUT1

I_OUT2= 200 mA

=

96

110

R_ON

On-resistance when 2

channels are paralleled

(Includes MOSFET and

package)

10 V ≤ V_S≤ 36 V, I_OUT1

I_OUT2> 200 mA.

V_OUT1tied to V_OUT2

48

55

VDD_REG CHARACTERISTICS

VDD Output voltage

(Internal regulator

enabled)

Includes load and line

regulation across the

range.

6 V ≤ V_S≤ 36 V, I_VDD

20 mA

<

V_VDD

3.1

3.3

3.5

10

V

Load regulation of

internal VDD regulator

when enabled

6 V ≤ V_S≤ 36 V, I_VDD

20 mA

LR_VDD

uV/mA

mV

Load transient regulation 6 V ≤ V_S≤ 36 V, I_VDD

LR_{tran_VDD}of internal VDD regulator <step from 5 mA to 15

when enabled mA in 10 μs

1 uF

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7.5 Electrical Characteristics (continued)

V_VS= 11 V to 36 V, V_VDD= 3.0 V to 5.5 V, T_J= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Current Limit of internal

regulator

I_{CL_VDD}

6 V ≤ V_S≤ 36 V

25

50

mA

CURRENT SENSE CHARACTERISTICS

Current sense ratio

I_OUTx/ I_SNS

I_OUTX= 1 A, Range =

2.4A

I_SNSICHx

I_OUTX= 1 A

1200

Paralleled channels

current sense accuracy

multiplier

I_SNSI

Paralleled

Current Sense Diagnostic

Enabled

1.0

2.76

8.5

1.2

ADC Performance Characteristics

V_ADCEFfHI

Tconv1

ADC refernce voltage

2.8

2.84

128

V

ADC sample update time

in each measurement

µs

ENOB

INL

Effective resolution

ADC INL

Current measurement

bits

2.0

0.5

LSB

ADC current

consumption

I_ADC

mA

SNS CHARACTERISTICS

CURRENT LIMIT CHARACTERISTICS

I_CLCurrent Limitation

Current limitation level or

fault indication threshold

I_{CL_reg}

Level

Settting = 2.6 A

2.30

0.88

2.6

1.0

2.86

2.95

1.1

A

Threshold before current

limiting - Overload

condition

Overcurrent limit

I_{CL_LINPK}

Setting = 2.6 A V_VS

V_VOUT< 1V

-

threshold

I_CLCurrent Limitation

Current limitation level or

fault indication threshold

I_{CL_reg}

Level

Settting = 1.0 A

Threshold before current

limiting - Overload

Conditions

Overcurrent limit

I_{CL_LINPK}

Setting = 1.0 A V_VS

V_VOUT< 1V

1.12

threshold

Peak current before

regulation while enabling

switch into 100 mohm

load

T_J= -40°C to 125°C

VS = 24V, Minimum

inductance = 2.2 µH

I_{CL_PK1}

Settting = 2.6 A

A

10

Peak current threshold

when short is applied

while switch enabled

T_J= -40°C to 125°C

VS = 24V, Minimum

inductance = 2.2 µH

I_{CL_PK2}

Settting = 2.6 A

A

9.4

Regulated current @

Short circuit RL < 200

mohms when Enabled

Parallel I_CLCurrent

Limitation Level

I_{CL_P}

5.2

Paralled Peak current

T_J= -40°C to 125°C

enabling into permanent VS = 24V, Minimum

I_{CL_PK1_P}

6.4

short

inductance = 2.2 µH

Paralled Channels

Current Limit Accuracy

Multiplier

V_OUT1tied to V_OUT2

parallel channel mode

enabled

,

I_CL,PARALLE

0.9

1.1

L

FAULT CHARACTERISTICS

Wire-break (WB) or

I_{WB_ON_TH}Open-load (OL) detection WB_ON_CHx = enabled

Switch enabled,

WB_ON_CHx = enabled

0.19

0.32

48

0.45

mA

µA

on-state threshold

WB_ON_TH_= 000

Off State Wirebreak or

Open-load (OL) detection

internal pull-up current

Switch disabled, WB_OFF_CHx = enabled

WB_PU=00

I_{WB_OFF}

10

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7.5 Electrical Characteristics (continued)

V_VS= 11 V to 36 V, V_VDD= 3.0 V to 5.5 V, T_J= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Off state WireBreak

(WB) or Open-load (OL)

detection voltage

V_{WB_OFF_T}

Channel Disabled, off-state wire-break diagnostics

enabled

5.5

V

H

CHx RCB Fault Deglitch Channel Enabled, RCB

Channel Enabled, RCB

enabled

t_{RCB_DGL}

T_ABS

1.2

185

130

ms

°C

time

enabled

Thermal shutdown

160

110

210

150

Thermal shutdown

warning

T_OTW

Thermal shutdown

hysteresis

T_HYS

20

27

35

°C

V

I_FLT= 2 mA, sink current

into the pin

V_{ol_FLT}

Fault low-output voltage

0.4

Reverse current

protection comparator

delay

Time from VS-VOUT <

50mV overdrive to FET

gate off

Time from VS-VOUT <

50mV overdrive to FET

gate off

t_{RCB_F}

1.6

2

2.4

5.7

µs

V

V_{RCB_pu}

RCBx FET gate voltage

4.2

DIGITAL INPUT PIN CHARACTERISTIC

DIG pin Input voltage

high-level

0.7 x

V_VDD

V_{IH, DIG}

V_{IL, DIG}

3.0V ≤ VDD ≤ 5.5V

V

DIG pin Input voltage

low-level

0.3 x

V_VDD

3.0V ≤ VDD ≤ 5.5V

V_DIG= 5 V

R_DIGx

Internal pulldown resistor

Input current high-level

0.7

1.2

5

2.0

MΩ

µA

I_{IH, DIG}

DIGITAL OUTPUT PIN CHARACTERISTICS

Output Logic High

Voltage Drop

V_OH

READY Pin current = -4mA

-0.4

V

V_{OL_SDO}

V_{OL_FLT}

LED DRIVER CHARACTERISTICS

Output Logic Low Voltage SDO Pin current = 4mA Pin current = -4mA

0.2

0.4

V

Output Logic Low Voltage FLT Pin current = 4mA

Pin current = -4mA

I_LED (average current

LED High Side / Low side over 4 phases) = 4 mA,

drop Channels 1 and 4

I_LED (average current

over 4 phases) = 4 mA,

LED switch current = 16 LED switch current = 16

V_{drop_HL14}

0.2

V

mA

I_LED (average current

LED High Side / Low side over 4 phases) = 4 mA,

I_LED (average current

over 4 phases) = 4 mA,

V_{drop_HL23}

V

drop Channels 2 and 3

LED switch current = 32 LED switch current = 32

mA mA

LED driver PWM

frequency

1000

Hz

PWM_LED

7.6 Switching Characteristics

V_S= 6 V to 36 V, T_J= -40°C to +125°C (unless otherwise noted)

Parameter

Test Conditions

Min

Typ

Max

Unit

V_S= 24 V, R_L= 48 Ω 50% of EN to

10% of VOUT

t_DR

CH1 and CH2 Turnon delay time

CH1 and CH2 Turnoff delay time

VOUTx rising slew rate

5

8

12

µs

V_S= 24 V, R_L= 48 Ω 50% of EN to

90% of VOUT

t_DF

9

12

1.4

17

V_S= 24 V, 25% to 75% of V_OUT

R_L= 48 Ω,

,

SR2_R

0.9

1.7

V/µs

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7.6 Switching Characteristics (continued)

V_S= 6 V to 36 V, T_J= -40°C to +125°C (unless otherwise noted)

Parameter

Test Conditions

Min

Typ

Max

Unit

V/µs

kHz

V_S= 24 V, 75% to 25% of V_OUT

R_L= 48 Ω,

,

SR2_F

f_max

t_ON

VOUTx falling slew rate

Maximum PWM frequency

CHx Turnon time

0.9

1.3

1.7

1

V_S= 24 V, R_L= 48 Ω 50% of EN to

90% of VOUT

25

30

-4

40

µs

V_S= 24 V, R_L= 48 Ω 50% of EN to

10% of VOUT

t_OFF

CHx Turnoff time

40

5

µs

1ms ON time switch enable

pulse V_BB= 24 V, R_L= 48 Ω

t_ON- t_OFF

CHx Turnon and off matching

CHxTurnon and off matching

-15

100-µs OFF time switch enable

pulse, V_S= 24 V, R_L= 48 Ω, F = f_max

-4

5

100-µs ON time switch enable

pulse, V_S= 24 V, R_L= 48 Ω, F = f_max

-4

5

100-µs enable pulse, V_S= 24 V, R_L=

48 Ω

F = f_max

CHx PWM accuracy - average load

current

Δ_PWM

-12

8

12

4

%

100-µs enable pulse, V_S= 24 V, R_L=

48 Ω

F = f_max

CH1x Turnon and off timing

matching

t_ON- t_OFF

-4

µs

7.7 SPI Timing Requirements

Over operating junction temperature T_J= –40°C to 125°C and operating V_VS= 2.3 to 36 V (unless otherwise noted).

MIN

NOM

MAX

UNIT

C_SDO= 30 pF;

t_SPI

SPI clock (SCLK) period

100

ns

t_high

t_low

High time: SCLK logic high-time duration

Low time: SCLK logic low-time duration

45

ns

t_sucs

NCS setup time: Time delay between falling edge of NCS and rising edge of SCLK

SDI setup time: Setup time of

SDI before the falling edge of

SCLK

SDI setup time: Setup time of SDI before the falling

edge of SCLK

t_{su_SDI}

15

30

ns

t_{h_SDI}

t_{d_SDO}

t_hcs

SDI hold time: Hold time of SDI before the falling edge of SCLK

Delay time: Time delay from rising edge of SCLK to data valid at SDO

Hold time: Time between the falling edge of SCLK and rising edge of NCS

nCS disable time, nCS high to SDO high impedance

ns

30

45

t_{dis_cs}

10

SPI transfer inactive time (time between two

transfers) during which NCS must remain high

t_hics

500

ns

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8 Parameter Measurement Information

(1)

V_{DO_EN}

50%

90%

t_DR

t_DF

V_OUT

10%

t_ON

t_OFF

(1) Rise and fall time of V_{DO_EN}is 100 ns.

Figure 8-1. Switching Characteristics Definitions

t_hics

t_hcs

t_sucs

CS

t_SPI

SCLK

t_high

t_low

X

LSB

X

MSB

SDI

t_{su_SDI}

t_{h_SDI}

Z

LSB

Z

MSB

SDO

t_{d_SDO}

t_{dis_cs}

Figure 8-2. SPI Timing

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9 Detailed Description

9.1 Overview

The TPS274C65 device is a quad channel 65-mΩ smart high-side switch intended for use for output ports

with protection for 24-V industrial systems. The device is designed to drive a variety of resistive, inductive

and capacitive loads. The device integrates various protection features including overload protection through

current limiting, thermal protection, short-circuit protection, and reverse current protection. For more details on

the protection features, refer to the Feature Description and Application Information sections of the document.

In addition, the device diagnostics features include a digital per-channel readout of output current, output voltage

and FET temperature. The high-accuracy load current sense allows for integration of load measurement features

that can enable predictive maintenance for the system by watching for leading indicators of load failures. The

device also integrates open load detection in on and off states to enable protection against wire breaks. In

addition, the device includes an open drain FLT pin output that indicates device fault states such as short to

GND, short to supply, overtemperature, and the other fault states discussed.

The TPS274C65 is one device in TI's industrial high side switch family. For each device, the part number

indicates elements of the device behavior. Figure 9-1 explains the device nomenclature.

TPS

27

4

C

65

AS

RHA

Package Designator

Prefix

40 V Industrial

High Side Switch

Device Version

27

28

S

Single Channel

60 V Industrial

High Side Switch

R_ON(m

)

2

4

Dual Channel

Quad Channel

Generation

Figure 9-1. Naming Convention

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9.2 Functional Block Diagram

REG_EN

VDD

VS

3.3V

Reg

Charge

Pump

LEDx

LED

Module

Output

Clamp

Gate

drive

V_IN/V_OUT

MON

OUTx

4

Config,

FLT

Flags &

Protection

RCB

4

Current

RCBx

Sense

Temp

Sense

VOUT

Sense

MUX

ADC

SPI

4

SPI

Interface

GND

9.3 Feature Description

9.3.1 Pin Diagrams

This section presents the I/O structure of all digital input and output pins.

VDD

STATE

V_IH

CONNECTION

Tied to VDD

Tied to GND

INPUT

Logic High

Logic Low

V_IL

R_PD

ESD

Figure 9-2. Logic Level Input Pin

Figure 9-3 shows the input structure for the logic levels pin, CS. The input can be with a voltage or external

resistor.

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VDD

STATE

V_IH

CONNECTION

Tied to VDD

Tied to GND

INPUT

R_PU

Logic High

Logic Low

V_IL

ESD

Figure 9-3. Logic Level Input Pin (CS)

Figure 9-4 shows the structure of the open-drain output pin, FAULT. The open-drain output requires an external

pullup resistor to function properly.

VDD

STATE

No Fault

Fault

STATUS

Pulled-Up

R_PU

OUTPUT

Inactive

Active

Pulled-Down

ESD

Figure 9-4. Open Drain Output Pin (FAULT)

9.3.2 SPI Mode Operation

The TPS274C65xS communicates with the host controller through a high-speed SPI serial interface. The

interface has three logic inputs: clock (CLK), chip select (CS), serial data in (SDI), and one data out (SDO).

The SDO is three-stated when CS is high. The maximum SPI clock rate is 10 MHz. The capacitance at

SPI communication pins (CLK, CS, SDI, SDO) needs to be minimized to achieve high SPI communication

frequencies.

The device supports both simple daisy chain⁽¹⁾and addressable SPI; the selection of mode is from the DSPI

pin. The main advantage of the addressable SPI mode is that diagnostics and configuration is easier. The two

different modes of SPI that is fixed for a given system implementation and cannot be changed dynamically or on

the fly. The two modes can be used with or without CRC.

The two modes are described in detail:

1. Addressable SPI mode - non-daisy-chained SPI bus with one single/shared CS through chip addressing.

Each chip on the shared SPI is assigned an individual chip address with the address set through a resistor

(three-bit address for the chip). Addressed SPI (DSPI pin pulled low) allows direct communication with up

to eight TPS274C65xS on a shared SPI using a single shared CS signal. The three-bit address of each IC

(up to eight on one board) is set with a resistor to GND on this pin Addressed SPI offers the advantage

of direct chip access. CRC check is enabled when CRCEN=1. The SPI main device addresses a specific

chip by sending the appropriate A2, A1, A0 logic in the first three bits of the SPI read/write command. The

TPS274C65xS monitors the SPI address in each SPI read or write cycle and responds appropriately when

the address matches the programmed address for that IC. The added advantage is that it is possible to

update the SW state register and read the data in the various read only fault and data registers in every read

as well as write command frame. The transmission speed will be faster for addressable SPI compared to the

daisy chain SPI as the direct data transmission will happen immediately once the address is transmitted.

2. Daisy chain SPI mode is enabled by setting DSPI pin high. In this mode, multiple TPS274C65xS devices

are configured in a serial fashion. In the 16-bit daisy-chain mode, only a minimum read capability and Switch

state ON/OFF write is possible- the FAULT status can be read out on each write to the switch ON-OFF

register. It is not possible to write to the LED registers or re-configure the device and at the same time

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update the switch state. However, it is possible to update the SW state register and read the data in the

various read only fault and data registers. The 24-bit SPI format allows the write to the SW_STATE register

in every read as well as write command frame as well enable CRC. The speed of the transmission for daisy

chain will be depending on the CLK frequency as well as the number of devices connected in series.

The communication between the TPS274C65 IC and the controller or MCU is through a SPI bus in a master-

slave configuration. The external MCU is always an SPI master that sends command requests on the SDI pin of

the TPS274C65 IC and receives device responses on the SDO pin of the IC. The TPS274C65 device is always

an SPI slave device that receives command requests and sends responses (such as status and measured

values) to the external MCU over the SDO line. The following lists the characteristics of the SPI:

The TPS274C65 device can be connected to the master MCU in the following formats.

•

One slave device

TPS274C65

SCLK

SDI

Controller

SPI

SDO

Communication

nSCS

CS1

MCLK

MO

SPI

Communication

MI

TPS274C65

CS2

SCLK

SDI

SPI

SDO

Communication

nSCS

Figure 9-5. Independent Slave Configuration

Multiple slave devices in parallel connection (addressable SPI mode)

•

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TPS274C65

SCLK

SDI

Controller

SPI

ADDCFG

SDO

Communication

nSCS

MCLK

MO

MI

SPI

Communication

TPS274C65

CS

SCLK

SDI

ADDCFG

SPI

SDO

Communication

nSCS

Figure 9-6. Addressable SPI Configuration

Multiple slave devices in series (daisy chain) connection limited only by the SPI write frame speed

•

requirements.

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TPS274C65

nSCS

SCLK

Controller

SPI

SDI

Communication

SDO

CS

MCLK

MO

SPI

Communication

MI

TPS274C65

SDI

SDO

SPI

SCLK

nSCS

Communication

Figure 9-7. Daisy Chain Configuration

SPI mode controls the following functions.

•

ON/OFF control of the switches.

Disable the diagnostics to reduce the quiescent current consumption.

Select the channel(s) and measurements for VOUT, IOUT and TEMP.

Fault management (clearing faults and action/response on fault).

Watchdog timer - the device will generate an error if the SW_STATE register has not been successfully

written into within the watchdog timeout period. The customer can disable the watchdog feature using the

WD_EN bit (default is off).

•

The current limit protection threshold

Table 9-1. SPI IC Address Configuration

Resistor Value(kΩ)

ADDCFG Code

13.3

000

17.8

23.7

31.6

44.2

59

001

010

011

100

101

110

111

78.7

110

Note: Please use resistor with <1% tolerance.

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Table 9-2. SPI Configuration

Pin Configuration

SPI Register Configuration

SCLK Cycle per Frame

DSPI

D24BIT

CRC_EN

x

0

24 bits, no CRC

32 bits, with CRC

16 bits, no CRC

24 bits, with CRC

24 bits, no CRC

0

x

0

1

0

1

0

1

SPI Sequence Frame Format

CS

1

3

5

7

9

11

13

15

17

19

21

23

CLK

SDI

2

4

6

8

10

12

14

16

18

20

22

24

A2

A1

A0

R(0)

CH4

CH3

CH2

CH1

RSVD

RA6

RA5

F5

RA4

RA3

RA2

RA1

RA0

0

X

0

Chip Address

Rd

SPIErr

Err

SW STATE

Register Address

Don’t Care

Hi-Z

A2

A1

A0

X

F7

F6

F4

F3

F2

F1

F0

D7

D6

D5

D4

D3

D2

D1

D0

SDO

Hi-Z

Chip Address

X

FAULT STATUS TYPE

DATA OUT

Figure 9-8. 24-bit Read, DSPI=0, D24BIT=x, CRC_EN=0

CS

1

3

5

7

9

11

13

15

17

19

21

23

CLK

2

4

6

8

10

12

14

16

18

20

22

24

A2

A1

A0

W(1)

CH4

CH3

CH2

CH1

RSVD

RA6

RA5

F5

RA4

RA3

RA2

RA1

RA0

D7 X

D6

D5

D4

D3

D2

D1

D0

SDI

Chip Address

Wr

SW STATE

Register Address

DATA IN

Hi-Z

SpiErr

A2

A1

A0

X

F7

F6

F4

F3

F2

F1

F0

RSVD

CH4

CH3

CH2

CH1

SDO

Hi-Z

Err

Chip Address

X

FAULT STATUS TYPE

Per Channel FAULT

Figure 9-9. 24-bit Write, DSPI=0, D24BIT=x, CRC_EN=0

CS

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

CLK

2

4

6

8

10

12

14

16

18

20

22

24

26

0

28

0

30

32

A1

A2

A0

R(0)

CH4

CH3

CH2

CH1

RSVD

RA6

RA5

F5

RA4

RA3

RA2

RA1

RA0

X

0

CRC3

CRC2

CRC1

CRC0

SDI

Chip Address

Rd

SW STATE

Register Address

Don’t Care

CRC BYTE

Hi-Z

SpiErr

Err

A2

A1

A0

X

F7

F6

F4

F3

F2

F1

F0

D7

D6

D5

D4

D3

D2

D1

D0

0

CRC3

CRC2

CRC0

SDO

HI-Z

Chip Address

x

FAULT STAUS TYPE

DATA OUT

CRC BYTE

Figure 9-10. 32-bit Read, DSPI=0, D24BIT=x, CRC_EN=1

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CS

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

CLK

SDI

2

4

6

8

10

12

14

16

18

20

22

24

26

0

28

0

30

32

A2

A1

A0

W(1)

CH4

CH3

CH2

CH1

RSVD

RA6

RA5

F5

RA4

RA3

RA2

RA1

RA0

D7 X

D6

D5

D4

D3

D2

D1

D0

0

CRC3

CRC2

CRC1

CRC0

Chip Address

Wr

SpiErr

Err

SW STATE

Register Address

DATA IN

CRC BYTE

Hi-Z

A2

A1

A0

X

F7

F6

F4

F3

F2

F1

F0

RSVD

CH4

CH3

CH2

CH1

0

CRC3

CRC2

CRC1

CRC0

SDO

HI-Z

Chip Address

x

FAULT STAUS TYPE

Per Channel Fault Status

CRC BYTE

Figure 9-11. 32-bit Write, DSPI=0, D24BIT=x, CRC_EN=1

CS

1

3

5

7

9

11

13

15

CLK

SDI

2

4

6

8

10

12

14

16

R(0)

RA6

RA5

RA4

RA3

RA2

RA1

RA0

RSVD

CH4

CH3

CH2

D1

CH1

Read

Register Address

SW STATE

F7

F6

F5

F4

F3

F2

F1

F0

D7

D6

D5

D4

D3

D2

D0

SDO

FAULT_STATUS_TYPE

DATA OUT

Figure 9-12. 16-bit Read, DSPI=1, D24BIT=0, CRC_EN=0

CS

1

3

5

7

9

11

13

15

CLK

2

4

6

8

10

12

14

16

W(1)

RA6

F6

RA5

RA4

RA3

RA2

RA1

RA0

D7

D6

D5

D4

D3

D2

D1

D0

SDI

Write

Register Address

WRITE DATA

F7

F5

F4

F3

F2

F1

F0

D7

D6

D5

D4

D3

D2

SDO

DATA_OUT

FAULT_STATUS_TYPE

Figure 9-13. 16-bit Write, DSPI=1, D24BIT=0, CRC_EN=0

CS

1

3

5

7

9

11

13

15

17

19

21

23

CLK

2

4

6

8

10

12

14

16

18

20

22

24

R(0)

RA6

RA5

RA4

RA3

RA2

RA1

RA0

RSVD

CH4

CH3

CH2

CH1

X

SDI

Rd

Register Address

SW STATE

Don’t Care

F7

F6

F5

F4

F3

F2

F1

F0

D7

D6

D5

D4

D3

D2

D1

D0

X

SDO

FAULT STAUS TYPE

DATA OUT

Don’t Care

Figure 9-14. 24-bit Read, DSPI=1, D24BIT=1, CRC_EN=0

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CS

1

3

5

7

9

11

13

15

17

19

21

23

CLK

SDI

2

4

6

8

10

12

14

16

18

20

22

24

W(1)

RA6

RA5

RA4

RA3

RA2

RA1

RA0

D7

D6

D5

D4

D3

D2

D1

D0

CH4X

CH3

CH2

CH1

X

Wr

Register Address

WRITE DATA

SW STATE

Don’t Care

F7

F6

F5

F4

F3

F2

F1

F0

D7

D6

D5

D4

D3

D2

D1

D0

X

SDO

FAULT STAUS TYPE

DATA OUT

Don’t Care

Figure 9-15. 24-bit Read, DSPI=1, D24BIT=1, CRC_EN=0

CS

1

3

5

7

9

11

13

15

17

19

21

23

CLK

2

4

6

8

10

12

14

16

18

20

22

24

R(0)

RA6

F6

RA5

F5

RA4

RA3

RA2

RA1

RA0

RSVD

CH4

CH3

CH2

CH1

0

X

0

CRC3

CRC2

CRC1

CRC0

SDI

Rd

Register Address

SW STATE

CRC BYTE

F7

F4

F3

F2

F1

F0

D7

D6

D5

D4

D3

D2

D1

D0

0

CRC3

CRC2

CRC1

CRC0

SDO

CRC BYTE

DATA OUT

FAULT STAUS TYPE

Figure 9-16. 24-bit Read, DSPI=1, D24BIT=1, CRC_EN=1

CS

1

3

5

7

9

11

13

15

17

19

21

23

CLK

2

4

6

8

10

12

14

16

18

20

22

24

W(1)

RA6

F6

RA5

F5

RA4

RA3

RA2

RA1

RA0

D7

D6

D5

D4

D3

D2

D1

D0

CH4X

CH3

CH2

CH1

CRC3

CRC2

CRC1

CRC0

SDI

Wr

Register Address

WRITE DATA

SW STATE

CRC BYTE

F7

F4

F3

F2

F1

F0

D7

D6

D5

D4

D3

D2

D0

0

CRC3

CRC2

CRC1

CRC0

SDO

FAULT STAUS TYPE

DATA OUT

CRC BYTE

Figure 9-17. 24-bit Write, DSPI=1, D24BIT=1, CRC_EN=1

9.3.2.1 Diagnostic Bit Behavior

Mask

Register

Read Clear Faults

THERMAL_SD_CH_STAT

ILIM_STAT

WB_ON_STAT

0

1

5

WB_OFF_STAT

0

SHRT_VS_STAT

FAULT_TYPE_STAT[1...6]

MUX

Real Time Faults

THERMAL_SD_CH_STAT_RT

ILIMIT_STAT_RT

WB_ON_STAT_RT

WB_OFF_STAT_RT

SHRT_VS_STAT_RT

FLT_LTCH_DIS

Figure 9-18. Fault Signaling Scheme

9.3.3 Programmable Current Limit

The TPS274C65xS integrates a dual stage adjustable current limit. For the most efficient and reliable output

protection, the current limit can be set as close to the DC current level as possible. However often systems

require high inrush current handling as well (example incandescent lamp and capacitive loads). By integrating a

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dual stage current limit, the TPS274C65xS enables robust DC current limiting while still allowing flexible inrush

handling.

A lower current limit lowers fault energy and current during a load failure event such as a short-circuit or a partial

load failure. By lowering fault energy and current, the overall system improves through:

•

Reduced size and cost in current carrying components such as PCB traces and module connectors

Less disturbance at the power supply (V_Spin) during a short circuit event

Less additional budget for the power supply to account for overload currents in one channel or more

Improved protection of the downstream load

Table 9-3. Current Limit Setting Table

ILIM_REG_xx[3]

ILIM_REG_xx[2]

ILIM_REG_xx[1]

ILIM_REG_xx[0]

ILIM Threshold(A)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

Table 9-4. Inrush Current Period Setting Table

ILIM_REG_xx[7]

ILIM_REG_xx[6]

ILIM_REG_xx[5]

ILIM_REG_xx[4]

Inrush Period (ms)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

4

6

8

10

12

16

20

24

28

32

40

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Table 9-4. Inrush Current Period Setting Table (continued)

ILIM_REG_xx[7]

ILIM_REG_xx[6]

ILIM_REG_xx[5]

ILIM_REG_xx[4]

Inrush Period (ms)

1

0

1

0

1

48

56

64

Table 9-5. ILIM Configuration Table

ILIM_CONFIG

ILIM level during ILIMDELAY

FLT reporting during ILIMDELAY

0

As programmed with INRUSH_LIMIT[1:0]

and ILIM_REG_xx[3:0]

Fault not reported

1

As programmed with ILIM_REG_xx[3:0]

Fault is reported

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9.3.3.1 Inrush Current Handling

The current limit thresholds and the inrush current time duration can be set by SPI register writes to enable

flexible inrush current control behavior. The following table shows the various options available.

Table 9-6. Inrush Current Limit Options

Current Limit During Inrush

Duration

Notes

INRUSH_LIMI INRUSH_LIMI

T[1] T[0]

Current limit at the level set by

register

The device will show constant current limit threshold in each channel

at all times set by the register values

0

The current is set higher during the duration of the inrush delay

to support high inrush current loads like incandescent lamps - See

figure (Case B) showing ex current limit behavior enabling into a

short circuit

Current limit at 2x the level set by

register

0

1

Current limit at 0.5x the level set

Feature to limit the current and power dissipation during the charging

large power supply capacitor loads.

by

register

1

0

1

Current limit fixed at 2.6 A

threshold

An example current limit timing behavior is shown Figure 9-19.

IOUT

2xILIM

1xILIM

t_DELAY

Figure 9-19. Inrush current limit set to 2x ILIM with a delay set by the ILIMDELAY register setting.

Initially current load is higher than the twice the limit and then decreases to the 1x limit

The above waveform shows the current limiting behavior on enabling the outputs during the initial inrush period.

The initial inrush current period when the current limit is higher enables two different system advantages when

driving loads

•

Enables higher load current to be supported for a period of time in the order of milliseconds to drive high

inrush current loads like incandescent bulb loads.

•

Enables fast capacitive load charging. In some situations, it is ideal to charge capacitive loads at a higher

current than the DC current to ensure quick supply bring up. This architecture allows a module to quickly

charge a capacitive load using the initial higher inrush current limit and then use a lower current limit to

reliably protect the module under overload or short circuit conditions.

While in current limiting mode, at any level, the device will have a high power dissipation. If the FET temperature

exceeds the over-temperature shutdown threshold, the device will turn off just the channel that is overloaded.

After cooling down, the device will either latch off or re-try, depending on the latch configuration. If the device is

turning off prematurely on start-up, it is recommended to improve the PCB thermal layout, lower the current limit

to lower power dissipation, or decrease the inrush current (capacitive loading).

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9.3.4 DO_EN Feature

DO_EN pin allows user to turn OFF all the channels regardless of the SW_STATE register status. If the DO_EN

is kept low, all the output channels cannot be turned ON even if the SW_STATE register shows channels are

enabled.

When the SW_STATE commands are sent during DO_EN low period, the register values will be stored in

the register. Once the DO_EN goes high, then the output states will follow the register values stored in the

SW_STATE.

9.3.5 Protection Mechanisms

The TPS274C65xS protects the system against load fault events like short circuits, inductive load kickback,

overload events and over-temperature events. This section describes the details for protecting against each of

these fault cases.

There are protection features which, if triggered, will cause the switch to automatically disable:

•

Thermal Shutdown

The fault indication is reset and the switch will turn back on when all of the below conditions are met:

•

t_RETRYhas expired

All faults are cleared (thermal shutdown and current limit)

Please note that if device hits thermal shutdown during the inrush period, the device will retry with the higher

inrush current.

9.3.5.1 Overcurrent Protection

When I_OUTreaches the current limit threshold, I_CL, the device will register an overcurrent fault and begin

regulating the current at the set limit. When any switch is in the FAULT state it will be indicated on the FLT

pin. This protects the system against overload cases where the load attempts to draw more than it's max rated

current, so the TPS274C65 can recognize and limit current or shut off during these cases. In the case of a slow

overload with the device channel enabled for a while, the current limit levels are as shown in Figure 9-20.

I_OUTx

Slow overload

I_{CL_th= CL_S}

I

I_{CL_Reg}

t

t2

t1

Switch

Turns Off

Figure 9-20. Overload Response

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STx

VOUTx

ENx

T_ABS

T_J

I_CL

I_OUTx

t

Load current increases to threshold.

Normal opera on Current is limited. Temp increases

Normal opera on

but does not reach T_ABS/REL

.

Figure 9-21. Overcurrent Behavior

For more details on the current limiting functionality, please see Programmable Current Limit.

9.3.5.2 Short Circuit Protection

The TPS274C65xS provides output short-circuit protection to ensure that the device will prevent current flow

in the event of a low impedance path to GND, removing the risk of damage or significant supply droop. The

TPS274C65xS is guaranteed to protect against short-circuit events regardless of the state of the ILIM pins and

with up to 36 V supply at 125°C.

Figure 9-22 shows the behavior of the TPS274C65xS when the device is enabled into a short-circuit.

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Current (A)

I_{CL_ENPS}

I_CL

Thermal Shutdown

t_RETRY

Time (s)

Figure 9-22. Enable into Short-Circuit Behavior

Due to the low impedance path, the output current will rapidly increase until it hits the current limit threshold. Due

to series inductance and deglitch, the measured maximum current may temporarily exceed the I_CLvalue defined

as I_{CL_ENPS}, however it will settle to the current limit.

In this state high power is dissipated in the FET, so eventually the internal thermal protection temperature for the

FET is reached and the device safely shuts down. If the device is not configured in latch mode, the device will

wait t_RETRYamount of time and turn the channel back on.

Figure 9-23 shows the behavior of the TPS274C65xS when a short-circuit occurs when the device is in the

on-state and already outputting current. When the internal pass FET is fully enabled, the current clamping

settling time is slower so to ensure overshoot is limited, the device implements a fast trip level at a level I_OVCR

.

When this fast trip threshold is hit, the device immediately shuts off for a short period of time before quickly

re-enabling and clamping the current to I_{CL_Reg}level after a brief transient overshoot to the I_{CL_ENPS}level. The

device will then keep the current clamped at the regulation current limit until the thermal shutdown temperature is

hit and the device will safely shut-off.

Current (A)

I_OVCR

I_{CL_ENPS}

I_CL

Thermal Shutdown

t_RETRY

I_NOM

Time (s)

Figure 9-23. On-State Short-Circuit Behavior

Soft Short- Circuit Behavior illustrated in Soft Short-Circuit Behavior shows the behavior of the TPS274C65xS

when there is a small change in impedance that sends the load current above the I_CLthreshold. The current

rises to I_{CL_LINPK}since the FET is still in the linear mode. Then the current limit kicks in and the current drops to

the I_CLvalue.

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Current (A)

I_{CL_ENPS}

I_{CL_LINPK}

I_CL

I_NOM

t_RETRY

Thermal Shutdown

Time (s)

Figure 9-24. Soft Short-Circuit Behavior

In all of these cases, the internal thermal shutdown is safe to hit repetitively. There is no device risk or lifetime

reliability concerns from repeatedly hitting this thermal shutdown level.

9.3.5.2.1 V_SDuring Short-to-Ground

When V_OUTis shorted to ground, the module power supply (V_S) can see a transient decrease. This is caused

by the sudden increase in current flowing through the cable inductance. For ideal system behavior, it is

recommended that the module supply capacitance be increased by adding bulk capacitance on the power

supply node.

9.3.5.3 Inductive Load Demagnetization

When switching off an inductive load, the inductor may impose a negative voltage on the output of the

switch. The TPS274C65 includes voltage clamps between V_Sand V_OUTto limit the voltage across the FETs

and demagnetize any load inductance. The maximum acceptable load inductance is a function of the device

robustness. The maximum single pulse and repetitive pulse energy is defined in Electrical Characteristics. If the

application parameters exceed this device limit, it is necessary to use a protection device like an external TVS

diode to dissipate the energy stored in the inductor. Please make sure the maximum clamping voltage of the

external TVS is smaller than the internal clamping voltage, so the external clamp engages before the internal

clamp to safely dissipate the inductive energy.

For more information on driving inductive loads, refer to TI's How to drive inductive, capacitive, and lighting loads

with smart high side switches application report.

9.3.5.4 Thermal Shutdown

The TPS274C65 includes a temperature sensor on the power FET and also within the controller portion of the

device. There are two cases that the device will register a thermal shutdown fault:

•

T_J,FET> T_ABS

(T_J,FET– T_J,controller) > T_REL

The first condition enables the device to register a long-term overtemperature event (caused by ambient

temperature or too high DC current flow), while the second condition allows the device to quickly register

transient heating that is causes in events like short-circuits.

After the fault is detected, the switch will turn off. If T_J,FETpasses T_ABS, the fault is cleared when the switch

temperature decreases by the hysteresis value, T_HYS. If instead the T_RELthreshold is exceeded, the fault is

cleared after T_RETRYpasses.

Each channel will shut down independently in case of a thermal event, as each has it's own temperature sensor

and fault reporting.

9.3.5.5 Undervoltage protection on VS

The device monitors the supply voltage V_Sto prevent unpredicted behaviors in the event that the supply voltage

is too low. When the supply voltage falls down to V_{S_UVPF}, the swtiches will shut off When the supply rises up to

V_{S_UVPR}, the device turns back on.

The VS undervoltage fault will be indicated through the register and FLTpin unless masked.

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VDD

VOUTx

ENx

V_{VS_UVR}

V_HYS

V_{VS_UVF}

t_{DLY_VSUV}

VS

t

VS rises.

Normal SW opera on

a er delay.

Switch is Disabled. But the device is

in enabled state.

VS decreases below V_UVF

.

Figure 9-25. VS UVP

9.3.5.6 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)

The device monitors the input supply voltage V_VDDto prevent unpredictable behavior in the event that the supply

voltage is too low. When the supply voltage falls down to V_{VDD_UVLOF}, the device channel outputs are disabled

and READY pin is pulled high. The device will resume normal operation when VDD rises above the VDD_UVLOR

threashold. The device will indicate through the POR bit if a reset of the digital has occured.

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VS

VOUTx

V_{VDD_UVLOR}

V_HYS

V_{VDD_UVLOF}

t_{DLY_RST}

VDD

t

VDD rises.

Normal powerup

opera on

VDD decreases below

V_UVLOF

The device is disabled and the

digital registers are reset.

.

Figure 9-26. VDD UVLO

9.3.5.7 Power-Up and Power-Down Behavior

Device is in OFF or POR state when the device is not powered. FAULT, READY and VOUTx will be in high-Z

state.

Once the V_S> V_{S_UVPR}and V_DD> V_DD,UVLOR, the device starts to read in the configurations and READY will be

pulled low when the device is ready for the SPI communication.

In case the VDD power supply is enabled the first and the VDD voltage exceeds V_DD,UVLORbefore the VS supply

is up and VS voltage exceeds V_{S_UVPR}, the outputs remain disabled.

9.3.5.8 Reverse Current Blocking

Inverse (reverse) current occurs when V_VS<V_OUT. In this case, current will flow from V_OUTxto VS. Inverse current

can be caused by miswiring at the output, or a capacitive or inductive load can cause inverse current. For

example, if there is a significant amount of load capacitance and the V_Snode has a transient droop, V_OUTxmay

be greater than V_S. The V_Sdroop may be caused by inrush current from a different load. Similarly load/supply

faults and inductive loads can cause supply to be pushed up as well. Another application is to provide protection

when output connection to supply (miswiring) occurs when the input power supply is not available or connected.

The device monitors V_Sand V_OUTto provide true reverse current blocking when a reverse condition or input

power failure condition is detected.

To prevent reverse current flow, TPS274C65AS integrates a NMOS gate driver that drives an external blocking

FET. The blocking FET is enabled as soon as the device is enabled and V_VS>V_{S_UVP}. When a reverse current

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condition is detected such as V_OUT>V_VS, the blocking FET gets disabled to prevent unwanted reverse currents

and signaled through RVRS_BLK_FLT and FLT. Once off, TPS274C65xS continously monitor internal current

flow until forward current is detected in the internal FET or V_S>V_OUT, and TPS274C65AS subsequently re-enable

external FET. During reverse current event, current sensing is not available, and I_SNSand ADC register go to 0

mA.

When the RCB function is enabled and RCB FET is connected, the RCB faults are not reported during the

reverse current event because the reverse current flow is blocked before the faults can be reported out.

RCB_DIS bit needs to be turned high if there's no external RCB FET connected, and the RCB pins need to be

left floating. Each channel has RCB_CHx bit to configure the RCB FET to be always OFF or with normal RCB

function as described above. Table 9-7 shows some example use cases for the RCB feature.

Table 9-7. Common Applications for RCB

Example Application

RCB_DIS

Per Channel RCB

Comment

Digital Output Module but reverse 1

current blocking function is not

desired

RCB_CHx = X

RCB pin left floating and not

connected to the RCB FET.

Digital Output Module and

reverse current blocking function

is needed

0

RCB_CHx = 1

RCB_CHx = 0

RCB_CHx = 1

RCB pin connected to the RCB

FET gate with normal RCB

function.

Digital Input Ouput module with

RCB FET used to conduct current

in DI configuration

RCB pin connected to the RCB

FET gate with RCB FET always

OFF. No RCB detection.

Digital Input Ouput module with

the channel in Digital Output

configuration

RCB pin connected to the FET

gate with normal RCB function.

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RCB_EN

RCB_VGS

STx

VOUTx

ENx

I_VOUTx

VS

t

VS dips below

VOUTx

Normal

opera on

VOUTx spikes

above VS

Normal opera on

Figure 9-27. Reverse Current Blocking

9.3.6 Diagnostic Mechanisms

As systems demand more intelligence, it is becoming increasingly important to have robust diagnostics

measuring the conditions of output power. The TPS274C65 integrates many diagnostic features that enable

modules to provide predictive maintenance and intelligence power monitoring to the system.

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9.3.6.1 Current Sense

The SNS output may be used to sense the load current through any channel. The SNS pin will output a current

that is proportional to the load current through either channel. This current will be sourced into an external

resistor to create a voltage that is proportional to the load current. This voltage may be measured by an ADC

or comparator and used to implement intelligent current monitoring for a system. To ensure accurate sensing

measurement, R_SNSshould be connected to the same ground potential as the μC ADC.

Equation 3 shows the transfer function for calculating the load current from the SNS pin current.

I_SNSI= I_OUT/ K_SNS

(1)

dI_SNST/dT and K_SNSare defined in the Specifications section.

9.3.6.1.1 R_SNSValue

The following factors should be considered when selecting the R_SNSvalue:

•

Current sense ratio (K_SNS)

Largest and smallest diagnosable load current required for application operation

Full-scale voltage of the ADC

Resolution of the ADC

9.3.6.1.1.1 SNS Output Filter

To achieve the most accurate current sense value, it is recommended to filter the SNS output. There are two

methods of filtering:

•

Low-Pass RC filter between the SNS pin and the ADC input. This filter is illustrated in Figure 12-1 with typical

values for the resistor and capacitor. The designer should select a C_SNScapacitor value based on system

requirements. A larger value will provide improved filtering but a smaller value will allow for faster transient

response.

•

The ADC and microcontroller can also be used for filtering. It is recommended that the ADC collects several

measurements of the SNS output. The median value of this data set should be considered as the most

accurate result. By performing this median calculation, the microcontroller can filter out any noise or outlier

data.

9.3.6.2 Fault Indication

The following faults will be register a fault that will show on the FLT pin (unless masked):.

•

FET Thermal Shutdown

Active Current Regulation

Thermal Shutdown caused by Current Limitation

Open load detection in on-state or off-state

V_OUTShort to Battery

LATCH(AUTO_

RETRY_DIS)

FAULT

Condition

VS

VDD

ENx

OUTx

FLT

Recovery

VS

<V_{S_UVP}

>V_DD,UVLO

X

H

-

Undervoltage

>V_{S_UVP}

>V_DD,UVLO

L

X

H

-

Normal

H

Short to Supply,

Off-state open

load

>V_{S_UVP}

>V_DD,UVLO

L

H

X

L

-

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LATCH(AUTO_

RETRY_DIS)

FAULT

VS

VDD

ENx

OUTx

FLT

Recovery

>V_{S_UVP}

>V_DD,UVLO

H

L

Auto-retry

Short to GND,

Overload, TSD

Latch-off. Fault

recovers when

ENx toggles.

>V_{S_UVP}

>V_DD,UVLO

H

L

H

L

9.3.6.2.1 Current Limit Behavior

I_OUTx

2xI_{CL_Reg}

1xI_{CL_Reg}

t

T_delay

FLT

t

ENx

t

Figure 9-28. FLT Pin Behavior With an Overcurrent Event on Channel Enable

Figure 9-29 shows the device fault and retry behavior when there is a slow creep into an over-current event. As

shown, the switch clamps the current until it hits thermal shutdown, and then the device will remain latched off

until the AUTO_RETRY_DIS bit is low.

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FLT

AUTO_RETRY

_DIS

DIA_EN

SNS signals

over-current

FLT

Current

SNS

Current

SNS

High-z

SNS

VOUTx

EN high throughout

ENx

T_ABS

T_HYS

T_J

t_RETRY

I_CL

I_OUTx

t

Switch is disabled. Temp

decreases by T_HYS, but

waits for LATCH

Load reaches limit. Current is

limited. Temp reaches limit.

Switch follows ENx.

Normal operation.

Figure 9-29. Current Limit – Latched Behavior

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Figure 9-30 shows the behavior with AUTO_RETRY_DIS = 1 (Latched behavior); hence, the switch will retry

after the fault is cleared and t_RETRYhas expired.

Signaling

FLT

AUTO_RETRY

_DIS

Current

Sense

SNS signals

over-current

Current

Sense

SNS

High-z

VOUTx

EN stays high throughout

ENx

T_ABS

T_HYS

T_J

t_RETRY

I_CL

I_OUTx

t

Load reaches limit.

Current is limited. Temp

reaches limit.

Switch is disabled. T_J

decreases by T_HYS

Switch follows ENx.

Normal operation.

Figure 9-30. Current Limit – AUTO_RETRY_DIS = 0

When the switch retries after a shutdown event, the fault indication will remain until V_OUTxhas risen to V_BB– 1.8

V. Once V_OUTxhas risen, the FLT output is reset and current sensing is available. If there is a short-to-ground

and V_OUTis not able to rise, the SNS fault indication will remain indefinitely. Figure 9-31 illustrates auto-retry

behavior and provides a zoomed-in view of the fault indication during retry.

Note

Figure 9-31 assumes that t_RETRYhas expired by the time that T_Jreaches the hysteresis threshold.

AUTO_RETRY_DIS = 0

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FLT

SNS signals

over-current

SNS signals

over-current

SNS signals

over-current

SNS signals

over-current

SNS

VOUT

EN

T_ABS

T_HYS

T_J

t

FLT

SNS signals over-current

Current Sense

SNS

VS – 1.8 V

VOUT

EN

T_ABS

T_HYS

T_J

t

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9.3.6.3 Short-to-Battery and Open-Load Detection

The TPS274C65 is capable of detecting short-to-battery and open-load events regardless of whether the switch

is turned on or off, however the two conditions use different methods to signify fault. This feature enables

systems to recognize mis-wiring or wire-break events.

9.3.6.4 On-State Wire-Break Detection

When the switch is enabled, TPS274C65 supports on-state open load detecttion as low as 0.32mA. In order

to achieve this accuracy, TPS274C65 uses a higher resistance path that is enabled for a short period of

time(T_{WB_ON1}). If the WB_ON is kept high, the higher resistance path will be turned on again after 100ms retry

time. The wire-break will also be retried whenever the WB_ON signal is toggled. Please refer to Figure 9-32

for the wire-break detection timing diagram. This functionality is enabled when EN_WB_ON and diagnostics

are enabled, during this time open-load threshold will be detected and signaled through WB_ON_FLT bit if wire

break is detected.

Table 9-8. Open-Load ON-State Detection Threshold

WB_ON_THD[2]

WB_ON_THD[1]

WB_ON_THD[0]

Typical Current Threshold (mA)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.32

0.64

0.96

1.28

1.6

1.92

2.24

2.56

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Requesting Diagnostic

before auto-retry

WB_ON

Diagnostic EN

100ms auto-retry

2 A

IL

No WB_ON fault

FLT STx

t_{WB_ON1}= 20us

VOUTx

ENx

t

IL

Switches back

to the main

FET

IL

Switches back to the main FET

and out of diagnostic as current

is greater than WB_diag

switched

to higher

R FET for

20us

switched

to higher

R FET for

20us

switched

to higher

R FET for

20us

Switch is in the ON

state

threshold for 100ms

Figure 9-32. ON-State Wire-Break Detection

9.3.6.5 Off State Wire-Break Detection

While the switch disabled and WB_OFF_CHx_EN high, an internal comparator watches the condition of V_OUT

.

The TPS274C65 includes a current source connected to V_OUTcontrolled by the DIA_EN signal. So, if the load

is disconnected (open load condition) or there is a short to battery the V_OUTvoltage will be pulled towards V_S. In

either of these events, the internal comparator will measure V_OUTas higher than the open load threshold (V_OL,off

)

and a fault is indicated on the FLT pin and on the SNS pin. No external component are required in most cases,

however if there is external pull-down resistor to GND on V_OUT, an additional external pull-up resistor might be

necessary to bias V_OUTappropriately.

The comparator and detection circuitry is only enabled when EN = LOW. Open load will be indicated on the FLT

pin even if WB_OFF_CHx_EN is set low, but will need an external pull-up resistor (and potentially a switch).

Open load fault signaling on the SNS is enabled only if WB_OFF_CHx_EN is set HI.

While the switch is disabled, the fault indication mechanisms will continuously represent the present status. For

example, if V_OUTdecreases from greater than V_OLto less than V_OL, the fault indication is reset. Additionally, the

fault indication is reset upon WB_OFF_CHx_EN = 0 or the rising edge of EN.

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VS

6.7V

V_{WB_OFF_TH}

Fault

Register

VOUT

V_{SHRT_VS_TH}

OUT

VOUT

FLT

TPS274C65

Load

Figure 9-33. Open Load Detection Circuit

WB Diagnos c

EN

FLT STx

t_{WB_OFF2}

Enabled

VOUT depends on

external condi ons

V_OL

VOUTx

ENx

t

The condi on is

determined by the internal

comparator.

Switch is disabled and

DIA_EN goes high.

The open-load

fault is indicated.

Diagnos c

Disabled

Figure 9-34. Off-State Open Load Detection Timing

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WB Diagnos c

EN

FLT STx

t_{WB_OFF1}

Enabled

VOUT depends on external condi ons

V_OL

VOUTx

ENx

t

Switch is disabled by

the enable pin.

The condi on is determined by

the internal comparator.

The fault is

indicated.

Diagnos c

Disabled

Figure 9-35. Off-State Open Load Detection Timing

9.3.6.6 ADC

The device includes an internal ADC that can convert the current sense, temperature sense, input and output

voltages. The ADC reference voltage is fixed internally as shown in the electrical characteristics table.

The TPS274C65AS device has a successive approximation 10-bit ADC which can convert multiple channels

serially. The ADC can be used to convert the following (but each or all of these can be disabled using SPI

register configuration.

1. Sensed load current. The sense resistor converting the sense current to voltage should be sized such that

the max load current (including the 20% over the nominal load value) produces a voltage value at the SNS

pin (V_ISNS) that falls roughly at 80% of the ADC range. In this case, if ISNS is at the upper end of the ADC

range, the device ADC output indicates that there is an over-load condition, and if ISNS is in the lower end of

the ADC range, they know that there is an under-load condition. However, given the very low current values

that need to be diagnosed, additional scaling of the V_ISNS voltage or the sensed current may be needed

at the very low current limit. Note that the current output occurs only when the switch is enabled ON. The

V_ISNS voltage would be sampled by the MUX switch only when the switch is fully ON (switch enable digital

signal gated with the ISNS_DELAY signal from) allowing the SNS current to settle. The four-sample average

would be done only after the MUX switch is ON. The ADC ISNS reports FF as the output value.

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ADC_currentin decimal = round[(2^{number of ADC bits}-1)*I_load*R_SNS/(K_SNS*V_ADCREF)]

(2)

2. VS/VOUT voltage signals applied to the general purpose ADC pins. Note that the VOUT voltage need only

be sensed as a fraction of the VS voltage.

ADC_voltagein decimal = round[(2^{number of ADC bits}-1)*V_S/OUT/30]

(3)

(4)

where V_S/OUTcan be either V_Sor V_OUT

3. Temperature sensed in each FET.

ADC_tempin decimal = round[(2^{number of ADC bits}-1)*(0.83-T_IC/450)]

where T_ICis in ℃

The ADC’s reference voltage pin is ADREFHI which is generated internally thus making the max voltage

convertible to the ADCREFHI. Internally the ADC’s ground reference is connected to the IC GND pin, so

externally should be connected to the same pin to minimize the PCB ground shift errors.

The ADC scheduling is round robin with the following order:

1. ISNS

2. TSNS

3. VOUT_SNS

4. VSNS.

Raw

Analog

ADC_REFHI

Signal

VS_SNS

8 bit

register

Averaging

Decimation

VOUT_SNS

TSNS

4

MUX

10 bit ADC

GND

Figure 9-36. ADC Block Diagram

9.3.7 LED Driver

TPS274C65 integrates an LED driver designed to drive 8 Status LEDs using only 4 outputs(LEDOUT1-

LEDOUT4). This design provides the flexibility to ensure any combination of LEDs can be turned on at any

given time and the user can configure the outputs through SPI using the TPS274C65 Registers. This LED driver

is designed to control each output with independent clock signals with ON phases offset from each other. This

ensures maximum flexibility for the user assigning use cases when configuring LED driver.

An example application is to provide ON/OFF channel status and fault indication per channel. In this example,

the user could assign channel specific functionality for D1-D4 such as channel on or off and tie D5-D8 as fault

indication LEDs. However, the user has full discretion on how they want to leverage these outputs.

RS and RF resistors determine the LED current through each LED and should be chosen according to the LED's

current/light density specifications. Current will flow from VDD pins to the LEDs, and the average current through

each LED will be VDD/RS(or RF)/4.

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3.3V/5V

VDD

LEDOUT1

LEDOUT2

RS

D1

D2

D3

D4

SPI

Interface

4

LEDOUT3

LEDOUT4

D8

D7 D6

D5

RF

GND

Figure 9-37. LED Driver

9.4 Device Functional Modes

During typical operation, the TPS274C65 can operate in a number of states that are described below.

9.4.1 OFF/POR

Off state occurs when the device is not powered. FAULT, READY and VOUTx will be in high-Z state.

9.4.2 INIT

Once the V_S> V_{S_UVPR}and V_DD> V_DD,UVLOR, the device starts to read in the configurations and READY will be

high in this state.

9.4.3 Active

Once READY is low from the INIT state, the device enters active state, where the switch states are constantly

written in through SPI.

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10 TPS274C65BS Available Registers List

The registers listed in TPS274C65 Registers section show all available registers in the AS version. Some

registers are not available in the BS version. Available Registers in TPS274C65BS Version shows the registers'

availability in the BS version.

Table 10-1. Available Registers in TPS274C65BS Version

ADDRESS

0x00

REG_NAME

FUNCTIONAL IN BS ADDRESS

VERSION

REG_NAME

FUNCTIONAL IN BS

VERSION

FAULT_TYPE_STAT

FAULT_CH_STAT

Y

0x18

0x19

0x1A

ADC_RESULT_CH2_ N

V

0x01

ADC_RESULT_CH3_ N

V

0x02

FAULT_GOBAL_TYP

E

ADC_RESULT_CH4_ N

V

0x03

0x04

SHRT_VS_CH_STAT

WB_OFF_CH_STAT

Y

0x1B

0x1C

ADC_RESULT_VS

N

ADC_RESULT_VS_L

SB

0x05

0x06

0x07

WB_ON_CH_STAT

ILIMIT_CH_STAT

Y

0x1D

0x1E

0x1F

SW_STATE

Y

N

LED_OUT_ON

LED_ERR_ON

THERMAL_SD_CH_

STAT

0x08

0x09

THERMAL_WRN_CH Y

_STAT

0x20

0x21

SW_FS_STATE

DEV_CONFIG1

Y

RVRS_BLK_CH_STA N

T

0x0A

0x0B

RESERVED

N

0x22

0x23

DEV_CONFIG2

DEV_CONFIG3

ADC_RESULT_CH1_ N

I

See Registers with

Partial BIts Available

in BS

0x0C

0x0D

ADC_RESULT_CH1_ N

I_LSB

0x24

0x25

DEV_CONFIG4

DEV_CONFIG5

Y

ADC_RESULT_CH2_ N

I

See Registers with

Partial BIts Available

in BS

0x0E

0x0F

ADC_RESULT_CH2_ N

I_LSB

0x26

0x27

DEV_CONFIG6

FAULT_MASK

N

ADC_RESULT_CH3_ N

I

See Registers with

Partial BIts Available

in BS

0x10

0x11

0x12

0x13

0x14

0x15

0x16

ADC_RESULT_CH3_ N

I_LSB

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

EN_WB_OFF_CH

EN_WB_ON_CH

EN_SHRT_VS_CH

ADC_ISNS_DIS

ADC_TSNS_DIS

ADC_VSNS_DIS

ADC_CONFIG1

Y

N

ADC_RESULT_CH4_ N

I

ADC_RESULT_CH4_ N

I_LSB

ADC_RESULT_CH1_ N

T

ADC_RESULT_CH2_ N

T

ADC_RESULT_CH3_ N

T

ADC_RESULT_CH4_ N

T

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Table 10-1. Available Registers in TPS274C65BS Version (continued)

ADDRESS

0x17

REG_NAME

FUNCTIONAL IN BS ADDRESS

VERSION

REG_NAME

FUNCTIONAL IN BS

VERSION

ADC_RESULT_CH1_ N

V

0x2F

CFG_CRC

Y

There are some registers contains bits that are not available in the BS version. The bits marked RSVD in Table

10-2 are not functional in the BS version.

Table 10-2. Registers with Partial Bits Available in BS

ADDRESS REG_NAME b7

b6

b5

b4

PARALLEL_ PARALLEL_ ILIM_CONFI INRUSH_ILI INRUSH_ILI

34 12

AUTO_RET WB_SVS_B WB_SVS_B SW_FS_CF FLT_BIT_LT

RY_DIS LANK1 LANK0 CH_DIS

MASK_SHR MASK_WB_ MASK_WB_ MASK_VSU

T_VS OFF ON

b3

b2

b1

b0

0x23

0x25

0x27

DEV_CONFI RSVD

G3

ILIM_SET

RSVD

G

M

DEV_CONFI RSVD

G5

RSVD

G

FAULT_MAS MASK_SPI_ MASK_WD_ MASK_ILIMI RSVD

ERR ERR

K

T

V

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11 TPS274C65 Registers

Table 11-1 lists the memory-mapped registers for the TPS274C65 registers. All register offset addresses not

listed in Table 11-1 should be considered as reserved locations and the register contents should not be modified.

The registers in the TPS274C65S device contain programmed information and operating status. Upon power-up

the registers are reset to the default values. Register addresses marked RESERVED or not shown in the register

map can be written with any value. Regardless of the data written to it, a read back from a RESERVED register

always returns the value of 0. Table lists the memory-mapped registers for the TPS274C65S device.

Table 11-1. TPS274C65 Registers

Offset

0h

Acronym

Register Name

Section

Go

FAULT_TYPE_STAT

FAULT_CH_STAT

Fault Type Register

1h

Faulted channel register

2h

FAULT_GLOBAL_TYPE

SHRT_VS_CH_STAT

WB_OFF_CH_STAT

WB_ON_CH_STAT

ILIMIT_CH_STAT

Global fault type register

3h

Short_to VS Faulted Channel Register

Off-state Wire-break faulted channel register

On-state Wire-break faulted channel register

Current Limit faulted channel register

Thermal Shutdown faulted channel register

Thermal warning threshold faulted channel register

Reverse Current flow (blocked) faulted channel register

ADC conversion result ISNS CH1

ADC conversion result ISNS CH1 LSBs

ADC conversion result ISNS CH2

ADC conversion result ISNS CH2 LSBs

ADC conversion result ISNS CH3

ADC conversion result ISNS CH3 LSBs

ADC conversion result ISNS CH4

ADC conversion result ISNS CH4 LSBs

ADC conversion result TSNS CH1

ADC conversion result TSNS CH2

ADC conversion result TSNS CH3

ADC conversion result TSNS CH4

ADC conversion result VSNS CH1

ADC conversion result VSNS CH2

ADC conversion result VSNS CH3

ADC conversion result VSNS CH4

ADC conversion result VS

4h

5h

6h

7h

THERMAL_SD_CH_STAT

THERMAL_WRN_CH_STAT

RVRS_BLK_CH_STAT

ADC_RESULT_CH1_I

ADC_RESULT_CH1_I_LSB

ADC_RESULT_CH2_I

ADC_RESULT_CH2_I_LSB

ADC_RESULT_CH3_I

ADC_RESULT_CH3_I_LSB

ADC_RESULT_CH4_I

ADC_RESULT_CH4_I_LSB

ADC_RESULT_CH1_T

ADC_RESULT_CH2_T

ADC_RESULT_CH3_T

ADC_RESULT_CH4_T

ADC_RESULT_CH1_V

ADC_RESULT_CH2_V

ADC_RESULT_CH3_V

ADC_RESULT_CH4_V

ADC_RESULT_VS

ADC_RESULT_VS_LSB

SW_STATE

8h

9h

Bh

Ch

Dh

Eh

Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

ADC conversion result VS

Switch state per channel register

LED1-LED4 Control

LED1_4_CTL

LED_5_8_CTL

LED5-LED8 Control

FS_SW_STATE

SPI/WD error state per channel register

Device Configuration Register #1

Device Configuration Register #2

Device Configuration Register #3

Device Configuration Register #4

Device Configuration Register #5

Device Configuration Register #6

DEV_CONFIG1

DEV_CONFIG2

DEV_CONFIG3

DEV_CONFIG4

DEV_CONFIG5

DEV_CONFIG6

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Table 11-1. TPS274C65 Registers (continued)

Offset

27h

Acronym

Register Name

Section

FAULT_MASK

EN_WB_OFF

Fault Mask register

Go

28h

Enable Off-state Wire-break fault per channel

Enable On-state Wire-break fault per channel

Enable Output Short_to-VS fault per channel

ADC conversion disable ISNS channels

ADC conversion disable TSNS channels

ADC conversion disable VSNS channels

ADC configuration - disable conversion

Configure CRC

29h

EN_WB_ON

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

EN_SHRT_VS

ADC_ISNS_DIS

ADC_TSNS_DIS

ADC_VSNS_DIS

ADC_CONFIG1

CRC_CONFIG

Complex bit access types are encoded to fit into small table cells. Table 11-2 shows the codes that are used for

access types in this section.

Table 11-2. TPS274C65 Access Type Codes

Access Type

Code

Description

Read Type

R

Read

RC

R

C

Read

to Clear

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

11.1 FAULT_TYPE_STAT Register (Offset = 0h) [Reset = 80h]

FAULT_TYPE_STAT is shown in Table 11-3.

Return to the Summary Table.

The register reports the fault type in any of the channels (OR of all channels)

Table 11-3. FAULT_TYPE_STAT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

SUPPLY_FLT

R

1h

The bit is set if either the VDD_UVLO or VS_UV are faults occur. If

FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared

only when the FLT_GLOBAL_TYPE register is read and the fault

condition no longer exists.

0h = no UV fault in VDD, VINT or VS

1h = UV fault in VDD, VINT or VS

6

5

RVRS_BLK_FLT

CHAN_TSD

R

0h

The bit is set if there is a reverse current fault in any one of the

channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and

is cleared only when the RVRS_BLK_CH_STAT register is read and

the fault condition no longer exists.

0h = no reverse current blocking fault in any of the channels

1h = reverse current blocking fault in one of the channels

The bit is set if there is a thermal shutdown fault due to thermal

overload in any one of the channels. If FLT_LTCH_DIS bit is

set, then the fault bit is latched and is cleared only when the

THERMAL_SD_CH_STAT register is read and the fault condition no

longer exists.

0h = no thermal shutdown fault in any of the channels

1h = thermal shutdown fault in one of the channels

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Table 11-3. FAULT_TYPE_STAT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

4

ILIMIT_FLT

R

0h

The bit is set if there is a current limit fault due to ovecurrent in any

one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit

is latched and is cleared only when the ILIMIT_CH_STAT register is

read and the fault condition no longer exists.

0h = no current limit (overcurrent) fault in any of the channels

1h = current limit (overcurrent) fault in one of the channels

3

2

1

0

WB_ON_FLT

R

0h

The bit is set if there is a wire break in the on state fault in any one of

the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched

and is cleared only when the WB_ON_CH_STAT register is read and

the fault condition no longer exists

0h = no on-state wire-break fault in any of the channels

1h = on-state wire-break fault in one of the channels

WB_OFF_FLT

The bit is set if either there is a wire break in the off-state fault in any

one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is

latched and is cleared only when the WB_OFF_CH_STAT register is

read and the fault condition no longer exists

0h = no off-state wire-break fault in any of the channels

1h = off-state wire-break fault in one of the channels

SHRT_VS_FLT

GLOBAL_ERR_WRN

The bit is set if there is a short to VS supply in the off-state fault

in any one of the channels. If FLT_LTCH_DIS bit is set, then the

fault bit is latched and is cleared only when the SHRT_VS_CH_STAT

register is read and the fault condition no longer exists

0h = no off-state short to VS fault in any of the channels

1h = off-state short to VS fault in one of the channels

The bit is set if there is a global fault reported in

the FLT_GLOBAL_TYPE register (SPI error, watchdog error,

VS_UV_WRN fault or chip thermal warning occurs. If

FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared

only when the FLT_GLOBAL_TYPE register is read and the fault

condition no longer exists.

0h = no global fault (SPI error, watchdog error, VS_UV_WRN fault or

chip thermal warning)

1h = One of the following errors have occurred: SPI error, watchdog

error, VS_UV_WRN fault or chip thermal warning

11.2 FAULT_CH_STAT Register (Offset = 1h) [Reset = 00h]

FAULT_CH_STAT is shown in Table 11-4.

Return to the Summary Table.

The register reports faulted channel(s) (OR of all fault types in each channel)

Table 11-4. FAULT_CH_STAT Register Field Descriptions

Bit

7-4

3

Field

Type

R

Reset

0h

Description

RESERVED

CH4

Reserved

R

0h

The bit is set if any type of fault (RVRS_BLK, THERMAL_SD_CH,

ILIMIT, WB_ON, WB_OFF, SHRT_VS) occurs in CH4

0h = No fault in CH4

1h = One or more fault has occurred in CH4

2

1

CH3

CH2

R

0h

The bit is set if any type of fault (RVRS_BLK, THERMAL_SD_CH,

ILIMIT, WB_ON, WB_OFF, SHRT_VS) occurs in CH3

0h = No fault in CH4

1h = One or more fault has occurred in CH2

The bit is set if any type of fault (RVRS_BLK, THERMAL_SD_CH,

ILIMIT, WB_ON, WB_OFF, SHRT_VS) occurs in CH2

0h = No fault in CH4

1h = One or more fault has occurred in CH3

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Table 11-4. FAULT_CH_STAT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

CH1

R

0h

The bit is set if any type of fault (RVRS_BLK, THERMAL_SD_CH,

ILIMIT, WB_ON, WB_OFF, SHRT_VS) occurs in CH1

0h = No fault in CH4

1h = One or more fault has occurred in CH1

11.3 FAULT_GLOBAL_TYPE Register (Offset = 2h) [Reset = 47h]

FAULT_GLOBAL_TYPE is shown in Table 11-5.

Return to the Summary Table.

The register reports the type of global fault that has occurred in the IC

Table 11-5. FAULT_GLOBAL_TYPE Register Field Descriptions

Bit

7

Field

Type

Reset

Description

RESERVED

POR

R

0h

Reserved

6

RC

1h

0h

The bit is indicative of whether a power on reset has occurred.

0h = There is no power-on reset anytime after the last register read

The register bit is cleared on read, so if read again and the bit is 0,

means that no power-on reset has occurred since the read.

1h = A power-on reset has occurred since the last register read.

5

4

CHIP_THERMALSD

SPI_ERR

The bit is set if the chip thermal warning is triggered at any time. The

fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and

the chip thermal shutdown error condition is removed

0h = No chip thermal warning

1h = Chip thermal warning threshold exceeded

The bit is set if there is an SPI communication error either from

format, clock or CRC errors.The fault bit is latched and cleared only

after read and the error is removed.

0h = No SPI communication error fault

1h = SPI communication error either from format, clock or CRC has

occurred

3

2

1

WD_ERR

RC

0h

1h

The bit is set if the watchdog timeout on SPI read or write occurs.

The fault bit is latched and cleared only after read and the error is

removed.

0h = No SPI interface watchdog error

1h = SPI watchdog timeout error has occurred

VDD_UVLO

VS_UV_WRN

The bit is set if VDD supply is below the UVLO threshold at any time.

The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read

and the UVLO condition is removed

0h = No VDD UVLO fault

1h = VDD UVLO fault

The bit is set if VS supply is below the UV warning

(UV_WRN) threshold at any time. The fault bit is cleared if the

GLOBAL_FAULT_TYPE register is read and the UV condition is

removed

0h = No VS UV_WRN fault

1h = VS UV_WRN fault

0

VS_UV

RC

1h

The bit is set if VS supply is below the UV threshold at any time. The

fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and

the UV condition is removed

0h = No VS UV fault

1h = VS UV fault

11.4 SHRT_VS_CH_STAT Register (Offset = 3h) [Reset = 00h]

SHRT_VS_CH_STAT is shown in Table 11-6.

Return to the Summary Table.

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The register reports faulted channel(s) with the off-state short-to-supply fault

Table 11-6. SHRT_VS_CH_STAT Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

RESERVED

SHRT_VS_CH4

R

0h

Reserved

RC

0h

The bit is set if any short to supply (VS) fault has occurred

at any time in CH4. The fault is latched and cleared when the

SHRT_VS_CH_STAT register is read and fault condition does not

exist anymore.

0h = No fault in CH4

1h = Short to VS fault has occurred in CH4

2

1

0

SHRT_VS_CH3

SHRT_VS_CH2

SHRT_VS_CH1

RC

0h

The bit is set if any short to supply (VS) fault has occurred

at any time in CH3. The fault is latched and cleared when the

SHRT_VS_CH_STAT register is read and fault condition does not

exist anymore.

0h = No fault in CH4

1h = Short to VS fault has occurred in CH3

The bit is set if any short to supply (VS) fault has occurred

at any time in CH2. The fault is latched and cleared when the

SHRT_VS_CH_STAT register is read and fault condition does not

exist anymore.

0h = No fault in CH4

1h = Short to VS fault has occurred in CH2

The bit is set if any short to supply (VS) fault has occurred

at any time in CH1. The fault is latched and cleared when the

SHRT_VS_CH_STAT register is read and fault condition does not

exist anymore.

0h = No fault in CH4

1h = Short to VS fault has occurred in CH1

11.5 WB_OFF_CH_STAT Register (Offset = 4h) [Reset = 00h]

WB_OFF_CH_STAT is shown in Table 11-7.

Return to the Summary Table.

The register reports faulted channel(s) with the off-state wire-break fault

Table 11-7. WB_OFF_CH_STAT Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

RESERVED

WB_OFF_CH4

R

0h

Reserved

RC

0h

The bit is set if the wire break (open load) fault in off-state has

occurred at any time in CH4. The fault is latched and cleared when

the WB_OFF_CH_STAT register is read and fault condition does not

exist anymore.

0h = No wire-break (off-state) fault in CH4

1h = Wire break (open load) fault in off-state has occurred in CH4

2

1

WB_OFF_CH3

WB_OFF_CH2

The bit is set if the wire break (open load) fault in off-state has

occurred at any time in CH3. The fault is latched and cleared when

the WB_OFF_CH_STAT register is read and fault condition does not

exist anymore.

0h = No wire-break (off-state) fault in CH3

1h = Wire break (open load) fault in off-state has occurred in CH3

The bit is set if the wire break (open load) fault in off-state has

occurred at any time in CH2. The fault is latched and cleared when

the WB_OFF_CH_STAT register is read and fault condition does not

exist anymore.

0h = No wire-break (off-state) fault in CH2

1h = Wire break (open load) fault in off-state has occurred in CH2

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Table 11-7. WB_OFF_CH_STAT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

WB_OFF_CH1

RC

0h

The bit is set if the wire break (open load) fault in off-state has

occurred at any time in CH1. The fault is latched and cleared when

the WB_OFF_CH_STAT register is read and fault condition does not

exist anymore.

0h = No wire-break (off-state) fault in CH1

1h = Wire break (open load) fault in off-state has occurred in CH1

11.6 WB_ON_CH_STAT Register (Offset = 5h) [Reset = 00h]

WB_ON_CH_STAT is shown in Table 11-8.

Return to the Summary Table.

The register reports faulted channel(s) with the on-state wire-break fault

Table 11-8. WB_ON_CH_STAT Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

RESERVED

WB_ON_CH4

R

0h

Reserved

RC

0h

The bit is set if the wire break (open load) fault in off-state has

occurred at any time in CH4. The fault is latched and cleared when

the WB_OFF_CH_STAT register is read and fault condition does not

exist anymore.

0h = No wire-break (on-state) fault in CH4

1h = Wire break (open load) fault in on-state has occurred in CH4

2

1

0

WB_ON_CH3

WB_ON_CH2

WB_ON_CH1

The bit is set if the wire break (open load) fault in off-state has

occurred at any time in CH3. The fault is latched and cleared when

the WB_OFF_CH_STAT register is read and fault condition does not

exist anymore.

0h = No wire-break (on-state) fault in CH3

1h = Wire break (open load) fault in on-state has occurred in CH3

The bit is set if the wire break (open load) fault in off-state has

occurred at any time in CH2. The fault is latched and cleared

when the WB_OFF_CH_STAT register is read and fault condition is

cleared.

0h = No wire-break (on-state) fault in CH2

1h = Wire break (open load) fault in on-state has occurred in CH2

The bit is set if the wire break (open load) fault in off-state has

occurred at any time in CH1. The fault is latched and cleared when

the WB_OFF_CH_STAT register is read and fault condition does not

exist anymore.

0h = No wire-break (on-state) fault in CH1

1h = Wire break (open load) fault in on-state has occurred in CH1

11.7 ILIMIT_CH_STAT Register (Offset = 6h) [Reset = 00h]

ILIMIT_CH_STAT is shown in Table 11-9.

Return to the Summary Table.

The register reports faulted channel(s) with the current limit fault

Table 11-9. ILIMIT_CH_STAT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R

0h

Reserved

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Table 11-9. ILIMIT_CH_STAT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

ILIMIT_CH4

RC

0h

The bit is set if current limiting due to overcurrent has occurred

at any time in CH4. The fault is latched and cleared when the

ILIMIT_CH_STAT register is read and fault condition does not exist

anymore.

0h = No current limit fault in CH4

1h = Current limit due to overcurrent fault has occurred in CH4

2

1

0

ILIMIT_CH3

ILIMIT_CH2

ILIMIT_CH1

RC

0h

The bit is set if current limiting due to overcurrent has occurred

at any time in CH3. The fault is latched and cleared when the

ILIMIT_CH_STAT register is read and fault condition does not exist

anymore.

0h = No current limit fault in CH3

1h = Current limit due to overcurrent fault has occurred in CH3

The bit is set if current limiting due to overcurrent has occurred

at any time in CH2. The fault is latched and cleared when the

ILIMIT_CH_STAT register is read and fault condition does not exist

anymore.

0h = No current limit fault in CH2

1h = Current limit due to overcurrent fault has occurred in CH2

The bit is set if current limiting due to overcurrent has occurred

at any time in CH1. The fault is latched and cleared when the

ILIMIT_CH_STAT register is read and fault condition does not exist

anymore.

0h = No current limit fault in CH1

1h = Current limit due to overcurrent fault has occurred in CH1

11.8 THERMAL_SD_CH_STAT Register (Offset = 7h) [Reset = 00h]

THERMAL_SD_CH_STAT is shown in Table 11-10.

Return to the Summary Table.

The register reports faulted channel(s) with the thermal shutdown fault

Table 11-10. THERMAL_SD_CH_STAT Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

RESERVED

THERMAL_SD_CH4

R

0h

Reserved

RC

0h

The bit is set if the thermal shutdown has occurred at any

time in CH4. The fault is latched and cleared when the

THERMAL_SD_CH_STAT register is read and channel temperature

has fallen below the thermal shutdown reset threshold.

0h = No thermal shutdown fault in CH4

1h = Thermal shudtwon has occurred in CH4

2

1

THERMAL_SD_CH3

THERMAL_SD_CH2

The bit is set if the thermal shutdown has occurred at any

time in CH3. The fault is latched and cleared when the

THERMAL_SD_CH_STAT register is read and channel temperature

has fallen below the thermal shutdown reset threshold.

0h = No thermal shutdown fault in CH3

1h = Thermal shudtwon has occurred in CH3

The bit is set if the thermal shutdown has occurred at any

time in CH2. The fault is latched and cleared when the

THERMAL_SD_CH_STAT register is read and channel temperature

has fallen below the thermal shutdown reset threshold.

0h = No thermal shutdown fault in CH2

1h = Thermal shudtwon has occurred in CH2

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Table 11-10. THERMAL_SD_CH_STAT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

THERMAL_SD_CH1

RC

0h

The bit is set if the thermal shutdown has occurred at any

time in CH1. The fault is latched and cleared when the

THERMAL_SD_CH_STAT register is read and channel temperature

has fallen below the thermal shutdown reset threshold.

0h = No thermal shutdown fault in CH1

1h = Thermal shudtwon has occurred in CH1

11.9 THERMAL_WRN_CH_STAT Register (Offset = 8h) [Reset = 00h]

THERMAL_WRN_CH_STAT is shown in Table 11-11.

Return to the Summary Table.

The register reports channel(s) with the temperature above thermal warning threshold

Table 11-11. THERMAL_WRN_CH_STAT Register Field Descriptions

Bit

7-4

3

Field

Type

R

Reset

0h

Description

RESERVED

Reserved

THERMAL_WRN_CH4

R

0h

The bit is set if FET temperature is above the overtemperature

warning threshold in CH4. The bit is cleared when over-temperature

earning condition does not exist anymore.

0h = FET temperatire below over-temperature warning threshold in

CH4

1h = FET temperatire above over-temperature warning threshold in

CH4

2

1

0

THERMAL_WRN_CH3

THERMAL_WRN_CH2

THERMAL_WRN_CH1

R

0h

The bit is set if FET temperature is above the overtemperature

warning threshold in CH3. The bit is cleared when over-temperature

earning condition does not exist anymore.

0h = FET temperatire below over-temperature warning threshold in

CH4

1h = FET temperatire above over-temperature warning threshold in

CH3

The bit is set if FET temperature is above the overtemperature

warning threshold in CH2. The bit is cleared when over-temperature

earning condition does not exist anymore.

0h = FET temperatire below over-temperature warning threshold in

CH2

1h = FET temperatire above over-temperature warning threshold in

CH2

The bit is set if FET temperature is above the overtemperature

warning threshold in CH1. The bit is cleared when over-temperature

earning condition does not exist anymore.

0h = FET temperatire below over-temperature warning threshold in

CH1

1h = FET temperatire above over-temperature warning threshold in

CH1

11.10 RVRS_BLK_CH_STAT Register (Offset = 9h) [Reset = 00h]

RVRS_BLK_CH_STAT is shown in Table 11-12.

Return to the Summary Table.

The register reports faulted channel(s) with the reverse current flow (blocked) fault

Table 11-12. RVRS_BLK_CH_STAT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R

0h

Reserved

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Table 11-12. RVRS_BLK_CH_STAT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

RVRS_BLK_CH4

RC

0h

The bit is set if the reverse current fault (blocked) has occurred

at any time in CH4. The fault is latched and cleared when the

RVRS_BLK_CH_STAT register is read.

0h = No reverse current fault in CH4

1h = Reverse current flow (blocked) fault in on-state has occurred in

CH4

2

1

0

RVRS_BLK_CH3

RVRS_BLK_CH2

RVRS_BLK_CH1

RC

0h

The bit is set if the reverse current fault (blocked) has occurred

at any time in CH3. The fault is latched and cleared when the

RVRS_BLK_CH_STAT register is read.

0h = No reverse current fault in CH3

1h = Reverse current flow (blocked) fault in on-state has occurred in

CH4

The bit is set if the reverse current fault (blocked) has occurred

at any time in CH2. The fault is latched and cleared when the

RVRS_BLK_CH_STAT register is read.

0h = No reverse current fault in CH2

1h = Reverse current flow (blocked) fault in on-state has occurred in

CH4

The bit is set if the reverse current fault (blocked) has occurred

at any time in CH1. The fault is latched and cleared when the

RVRS_BLK_CH_STAT register is read.

0h = No reverse current fault in CH1

1h = Reverse current flow (blocked) fault in on-state has occurred in

CH4

11.11 ADC_RESULT_CH1_I Register (Offset = Bh) [Reset = 00h]

ADC_RESULT_CH1_I is shown in Table 11-13.

Return to the Summary Table.

The register records ADC conversion result for current sense of CH1

Table 11-13. ADC_RESULT_CH1_I Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_ISNS_CH1

R

0h

ADC result (8-bits) from the conversion of the current in CH1

11.12 ADC_RESULT_CH1_I_LSB Register (Offset = Ch) [Reset = 00h]

ADC_RESULT_CH1_I_LSB is shown in Table 11-14.

Return to the Summary Table.

The register records ADC conversion result for current sense of CH1 (Two LSBs)

Table 11-14. ADC_RESULT_CH1_I_LSB Register Field Descriptions

Bit

7-2

1-0

Field

Type

R

Reset

0h

Description

RESERVED

ADC_ISNS_CH1_LSB

Reserved

R

0h

Least Significant Bits for ADC result from conversion of the current in

CH1

11.13 ADC_RESULT_CH2_I Register (Offset = Dh) [Reset = 00h]

ADC_RESULT_CH2_I is shown in Table 11-15.

Return to the Summary Table.

The register records ADC conversion result for current sense of CH2

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Table 11-15. ADC_RESULT_CH2_I Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_ISNS_CH2

R

0h

ADC result (8-bits) from the conversion of the current in CH2

11.14 ADC_RESULT_CH2_I_LSB Register (Offset = Eh) [Reset = 00h]

ADC_RESULT_CH2_I_LSB is shown in Table 11-16.

Return to the Summary Table.

The register records ADC conversion result for current sense of CH2 (Two LSBs)

Table 11-16. ADC_RESULT_CH2_I_LSB Register Field Descriptions

Bit

7-2

1-0

Field

Type

R

Reset

0h

Description

RESERVED

ADC_ISNS_CH2_LSB

Reserved

R

0h

Least Significant Bits for ADC result from conversion of the current in

CH2

11.15 ADC_RESULT_CH3_I Register (Offset = Fh) [Reset = 00h]

ADC_RESULT_CH3_I is shown in Table 11-17.

Return to the Summary Table.

The register records ADC conversion result for current sense of CH3

Table 11-17. ADC_RESULT_CH3_I Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_ISNS_CH3

R

0h

ADC result (8-bits) from the conversion of the current in CH3

11.16 ADC_RESULT_CH3_I_LSB Register (Offset = 10h) [Reset = 00h]

ADC_RESULT_CH3_I_LSB is shown in Table 11-18.

Return to the Summary Table.

The register records ADC conversion result for current sense of CH3 (Two LSBs)

Table 11-18. ADC_RESULT_CH3_I_LSB Register Field Descriptions

Bit

7-2

1-0

Field

Type

R

Reset

0h

Description

RESERVED

ADC_ISNS_CH3_LSB

Reserved

R

0h

Least Significant Bits for ADC result from conversion of the current in

CH3

11.17 ADC_RESULT_CH4_I Register (Offset = 11h) [Reset = 00h]

ADC_RESULT_CH4_I is shown in Table 11-19.

Return to the Summary Table.

The register records ADC conversion result for current sense of CH4

Table 11-19. ADC_RESULT_CH4_I Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_ISNS_CH4

R

0h

ADC result (8-bits) from the conversion of the current in CH4

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11.18 ADC_RESULT_CH4_I_LSB Register (Offset = 12h) [Reset = 00h]

ADC_RESULT_CH4_I_LSB is shown in Table 11-20.

Return to the Summary Table.

The register records ADC conversion result for current sense of CH4 (Two LSBs)

Table 11-20. ADC_RESULT_CH4_I_LSB Register Field Descriptions

Bit

7-2

1-0

Field

Type

R

Reset

0h

Description

RESERVED

ADC_ISNS_CH4_LSB

Reserved

R

0h

Least Significant Bits for ADC result from conversion of the current in

CH4

11.19 ADC_RESULT_CH1_T Register (Offset = 13h) [Reset = 00h]

ADC_RESULT_CH1_T is shown in Table 11-21.

Return to the Summary Table.

The register records ADC conversion result for temperature sense of CH1

Table 11-21. ADC_RESULT_CH1_T Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_TSNS_CH1

R

0h

ADC result (8-bits) from the conversion of the temperature in CH1

11.20 ADC_RESULT_CH2_T Register (Offset = 14h) [Reset = 00h]

ADC_RESULT_CH2_T is shown in Table 11-22.

Return to the Summary Table.

The register records ADC conversion result for temperature sense of CH2

Table 11-22. ADC_RESULT_CH2_T Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_TSNS_CH2

R

0h

ADC result (8-bits) from the conversion of the temperature in CH2

11.21 ADC_RESULT_CH3_T Register (Offset = 15h) [Reset = 00h]

ADC_RESULT_CH3_T is shown in Table 11-23.

Return to the Summary Table.

The register records ADC conversion result for temperature sense of CH3

Table 11-23. ADC_RESULT_CH3_T Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_TSNS_CH3

R

0h

ADC result (8-bits) from the conversion of the temperature in CH3

11.22 ADC_RESULT_CH4_T Register (Offset = 16h) [Reset = 00h]

ADC_RESULT_CH4_T is shown in Table 11-24.

Return to the Summary Table.

The register records ADC conversion result for temperature sense of CH4

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Table 11-24. ADC_RESULT_CH4_T Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_TSNS_CH4

R

0h

ADC result (8-bits) from the conversion of the temperature in CH4

11.23 ADC_RESULT_CH1_V Register (Offset = 17h) [Reset = 00h]

ADC_RESULT_CH1_V is shown in Table 11-25.

Return to the Summary Table.

The register records ADC conversion result for voltage sense of CH1

Table 11-25. ADC_RESULT_CH1_V Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_VSNS_CH1

R

0h

ADC result (8-bits) from the conversion of the voltage in CH1

11.24 ADC_RESULT_CH2_V Register (Offset = 18h) [Reset = 00h]

ADC_RESULT_CH2_V is shown in Table 11-26.

Return to the Summary Table.

The register records ADC conversion result for voltage sense of CH2

Table 11-26. ADC_RESULT_CH2_V Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_VSNS_CH2

R

0h

ADC result (8-bits) from the conversion of the voltage in CH2

11.25 ADC_RESULT_CH3_V Register (Offset = 19h) [Reset = 00h]

ADC_RESULT_CH3_V is shown in Table 11-27.

Return to the Summary Table.

The register records ADC conversion result for voltage sense of CH3

Table 11-27. ADC_RESULT_CH3_V Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_VSNS_CH3

R

0h

ADC result (8-bits) from the conversion of the voltage in CH3

11.26 ADC_RESULT_CH4_V Register (Offset = 1Ah) [Reset = 00h]

ADC_RESULT_CH4_V is shown in Table 11-28.

Return to the Summary Table.

The register records ADC conversion result for voltage sense of CH4

Table 11-28. ADC_RESULT_CH4_V Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_VSNS_CH4

R

0h

ADC result (8-bits) from the conversion of the voltage in CH4

11.27 ADC_RESULT_VS Register (Offset = 1Bh) [Reset = 00h]

ADC_RESULT_VS is shown in Table 11-29.

Return to the Summary Table.

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The register records ADC conversion result for supply voltage sense

Table 11-29. ADC_RESULT_VS Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC_VS_SNS

R

0h

ADC result (8-bits) from the conversion of the supply voltage input

(VS pin)

11.28 ADC_RESULT_VS_LSB Register (Offset = 1Ch) [Reset = 00h]

ADC_RESULT_VS_LSB is shown in Table 11-30.

Return to the Summary Table.

The register records ADC conversion result for supply voltage sense (Two LSBs)

Table 11-30. ADC_RESULT_VS_LSB Register Field Descriptions

Bit

7-2

1-0

Field

Type

R

Reset

0h

Description

RESERVED

Reserved

ADC_VS_SNS_CH4_LSB

R

0h

Least Significant Bits for ADC result from conversion of the supply

voltage input (VS pin)

11.29 SW_STATE Register (Offset = 1Dh) [Reset = 00h]

SW_STATE is shown in Table 11-31.

Return to the Summary Table.

The register sets the switch state (ON/OFF) of each output channel. The switch state bits in the SPI frame are

ignored when a write to this register is performed (only the contents of the DATA_IN field of the SPI frame are

used to update the switch state)

Table 11-31. SW_STATE Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

RESERVED

CH4_ON

R

0h

Reserved

R/W

0h

Set this bit to 1 to turn on the FET and CH4 output ON

0h = CH4 Output set to OFF (FET is OFF). The switch state bits in

the SPI frame are ignored

1h = CH4 Output set to ON (FET is ON). The switch state bits in the

SPI frame are ignored

2

1

0

CH3_ON

CH2_ON

CH1_ON

R/W

0h

Set this bit to 1 to turn on the FET and CH3 output ON

0h = CH3 Output set to OFF (FET is OFF). The switch state bits in

the SPI frame are ignored.

1h = CH3 Output set to ON (FET is ON). The switch state bits in the

SPI frame are ignored

Set this bit to 1 to turn on the FET and CH2 output ON

0h = CH2 Output set to OFF (FET is OFF). The switch state bits in

the SPI frame are ignored

1h = CH2 Output set to ON (FET is ON). The switch state bits in the

SPI frame are ignored

Set this bit to 1 to turn on the FET and CH1 output ON

0h = CH1 Output set to OFF (FET is OFF). The switch state bits in

the SPI frame are ignored

1h = CH1 Output set to ON (FET is ON). The switch state bits in the

SPI frame are ignored

11.30 LED1_4_CTL Register (Offset = 1Eh) [Reset = 00h]

LED1_4_CTL is shown in Table 11-32.

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Return to the Summary Table.

The register sets the LEDs ON or OFF

Table 11-32. LED1_4_CTL Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

RESERVED

LED4_CTL

R

0h

Reserved

R/W

0h

Set this bit to 1 to turn on the LED4 Output Status indicator

0h = LED set to OFF

1h = LED set to ON

2

1

0

LED3_CTL

LED2_CTL

LED1_CTL

R/W

0h

Set this bit to 1 to turn on the LED3 Output Status indicator

0h = LED set to OFF

1h = LED set to ON

Set this bit to 1 to turn on the LED2 Output Status indicator

0h = LED set to OFF

1h = LED set to ON

Set this bit to 1 to turn on the LED1 Output Status indicator

0h = LED set to OFF

1h = LED set to ON

11.31 LED_5_8_CTL Register (Offset = 1Fh) [Reset = 00h]

LED_5_8_CTL is shown in Table 11-33.

Return to the Summary Table.

The register sets the LEDs ON or OFF

Table 11-33. LED_5_8_CTL Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

RESERVED

LED8_CTL

R

0h

Reserved

R/W

0h

Set this bit to 1 to turn on the LED8 Output Status indicator

0h = LED set to OFF

1h = LED set to ON

2

1

0

LED7_CTL

LED6_CTL

LED5_CTL

R/W

0h

Set this bit to 1 to turn on the LED7 Output Status indicator

0h = LED set to OFF

1h = LED set to ON

Set this bit to 1 to turn on the LED6 Output Status indicator

0h = LED set to OFF

1h = LED set to ON

Set this bit to 1 to turn on the LED5 Output Status indicator

0h = LED set to OFF

1h = LED set to ON

11.32 FS_SW_STATE Register (Offset = 20h) [Reset = 00h]

FS_SW_STATE is shown in Table 11-34.

Return to the Summary Table.

The register sets the switch state (ON/OFF) of each output channel in case of SPI_ERR or WD_ERR

Table 11-34. FS_SW_STATE Register Field Descriptions

Bit

7-4

3

Field

Type

R

Reset

0h

Description

RESERVED

CH4_FS_ON

Reserved

R/W

0h

Set this bit to 1 to turn on the CH4 FET and CH4 Output ON when

WD_ERR fault has occurred

0h = CH4 Output set to OFF (FET is OFF) when WD_ERR occurs

1h = CH4 Output set to ON (FET is ON) when WD_ERR occurs

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Table 11-34. FS_SW_STATE Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2

CH3_FS_ON

R/W

0h

Set this bit to 1 to turn on the CH3 FET and CH4 Output ON when

WD_ERR fault has occurred

0h = CH3 Output set to OFF (FET is OFF) when WD_ERR occurs

1h = CH3 Output set to ON (FET is ON) when WD_ERR occurs

1

0

CH2_FS_ON

CH1_FS_ON

R/W

0h

Set this bit to 1 to turn on the CH2 FET and CH4 Output ON when

WD_ERR fault has occurred

0h = CH2 Output set to OFF (FET is OFF) whenWD_ERR occurs

1h = CH2 Output set to ON (FET is ON) when WD_ERR occurs

Set this bit to 1 to turn on the CH1 FET and CH4 Output ON when

WD_ERR fault has occurred

0h = CH1 Output set to OFF (FET is OFF) when WD_ERR occurs

1h = CH1 Output set to ON (FET is ON) when WD_ERR occurs

11.33 DEV_CONFIG1 Register (Offset = 21h) [Reset = 0Ah]

DEV_CONFIG1 is shown in Table 11-35.

Return to the Summary Table.

Current limit setting and duration of initial inrush level and time channel 1/2

Table 11-35. DEV_CONFIG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

ILIM_DURATION_12

R/W

0h

Sets the delay period during with inrush current limit level applies

(Ch1 and Ch2). See table of delay settings in the datasheet

3-0

ILIM_REG_12

R/W

Ah

Sets the current limit regulation value during overcurrent or shirt

circuit events (Ch1 and Ch2). See table of current limit settings in the

datasheet.

11.34 DEV_CONFIG2 Register (Offset = 22h) [Reset = 0Ah]

DEV_CONFIG2 is shown in Table 11-36.

Return to the Summary Table.

Current limit setting and duration of initial inrush level and time channel 3/4

Table 11-36. DEV_CONFIG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

ILIM_DURATION_34

R/W

0h

Sets the delay period during with inrush current limit level applies

(Ch3 and Ch4). See table of delay settings in the datasheet

3-0

ILIM_REG_34

R/W

Ah

Sets the current limit regulation value during overcurrent or shirt

circuit events(Ch3 and Ch4). See table of current limit settings in the

datasheet.

11.35 DEV_CONFIG3 Register (Offset = 23h) [Reset = 00h]

DEV_CONFIG3 is shown in Table 11-37.

Return to the Summary Table.

Device Configuration register - RCB function disable in all channels,Sense current range Inrush current Limit

level config, Parallel chanel config Inrush current Limit level config, ILIM type config inrush or current limit

duration

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Table 11-37. DEV_CONFIG3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RCB_DIS

R/W

0h

Setting this bit to 1, disable RCB function in all channels

0h = RCB FET gate output set per channel.

1h = Disables RCB function

6

ILIM_SET

R/W

0h

Set this bit to allow CH1/CH2 to have different current limit setting

than CH3/CH4

0h = Current Limit / inrush deay the same for all channels as in

register DEV_CONFIG1

1h = Current limit / inrsh delay set differenty for CH1/CH2 (as in

DEV_CONFIG1) and C3/CH4 (DEV_CONFIG2)

5

4

ISNS_RANGE

PARALLEL_34

R/W

0h

Sets the load current sense range - optimizing the current sense

output

0h = Load current to be sensed less than or equal to 800 mA

1h = Load current to be sensed more than 800 mA

Set this bit to 1 to signal that channels 3 and 4 (CH3 and CH4) are

paralleled. Write to this bit is valid only when all four SW_STATE bits

are 0 and not rewritten to 1 in the same frame.

0h = CH3 and CH4 are not paralleled together

1h = CH3 and CH4 are paralleled together

3

2

PARALLEL_12

ILIM_CONFIG

R/W

0h

Set this bit to 1 to signal that channels 1 and 2(CH1 and CH2) are

paralleled. Write to this bit is valid only when all four SW_STATE bits

are 0 and not rewritten to 1 in the same frame.

0h = CH1 and CH2 are not paralleled together

1h = CH1 and CH2 are paralleled together

Set this bit to 1 to have the ILIM duration applied as the period of

inrush current limit or to set as the duration of current limiting before

switching off the FET.

0h = ILIM duratiion set as the period of inrush current limit

1h = ILIM duration set as the period of current limiting before

switching off FET

1-0

INRUSH_LIMIT

R/W

0h

Sets the inrush current limit level that applies during the duration of

ILIM inrush duration. See table of inrush current limit level settings in

the datasheet

11.36 DEV_CONFIG4 Register (Offset = 24h) [Reset = 02h]

DEV_CONFIG4 is shown in Table 11-38.

Return to the Summary Table.

Device Configuration register - Configuring WB_on_threshold current. WB_off PU current, Watchdog enable and

timer duration

Table 11-38. DEV_CONFIG4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

WD_EN

R/W

0h

The bit is set to enable the watchdog function

0h = Watchdog is disabled

1h = Watchdog function is enabled

6-5

4-3

WD_TO

R/W

0h

Sets the timeout period for the SPI watchdog monitor

0h = Watchdog timeout 400 us

1h = Watchdog timeout is 400 ms

2h = Watchdog timeout is 800 ms

3h = Watchdog timeout is 1200 ms

WB_OFF_PU

Sets the pullup current value (at the OUTx pins) by the off-state

wire-break (open load) detection circuit.

0h = I_pu is 50 uA

1h = I_pu is 100 uA

2h = I_pu is 200 uA

3h = I_pu is 500 uA

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Table 11-38. DEV_CONFIG4 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2-0

WB_ON_THD

R/W

2h

Sets the current threshold for on-state wire-break (open load)

detection. See table of settings in the datasheet

11.37 DEV_CONFIG5 Register (Offset = 25h) [Reset = 00h]

DEV_CONFIG5 is shown in Table 11-39.

Return to the Summary Table.

Device Configuration register - Device Configuration register - Fault bit LATCH_mode enable, ,Wire break or

short to VS blanking time in off-state,Sw_STATE config, fault latch with retry only on enable toggle.

Table 11-39. DEV_CONFIG5 Register Field Descriptions

Bit

7-6

5

Field

Type

Reset

Description

RESERVED

ADC_EN

R

0h

Reserved

R/W

0h

Setting this bit to 1, enables the ADC function

0h = ADC function disabled

1h = ADC enabled

4

3-2

1

AUTO_RETRY_DIS

WB_SVS_BLANK

SW_FS_CFG

R/W

0h

Setting this bit to 1, disables the auto-retry and latches the channel

Output OFF on thermal shutdown of the channel occurs. Retry can

be attempted by toggling enable.

0h = Auto-retry on thermal shutdown of the channel

1h = Latches the channel output off on thermal shutdown - retry on

toggling enable.

Sets the blanking time for wire-break (ON-state and OFF-state) and

the short_to_VS faults before the fault is registered.

0h = Blanking time is 0.4 ms

1h = Blanking time is 1.0 ms

2h = Blanking time is 2.0 ms

3h = Blanking time is 4.0 ms

Set this bit to 1 to have the outputs hold state when WD_ERR

faults have occurred. Otherwise the device uses the FS_SW_STATE

register bits.

0h = Switch (output) holds state

1h = Switch (output) state set by Sw_FS_STATE register when

WD_ERR occurs

0

FLT_LTCH_DIS

Set this bit to 1 to not latch the fault bits in the register and cleared

on read.

0h = Fault bits latched and cleared only on read

1h = Fault bits not latched, cleared when the fault disappears

11.38 DEV_CONFIG6 Register (Offset = 26h) [Reset = 0Fh]

DEV_CONFIG6 is shown in Table 11-40.

Return to the Summary Table.

Device Configuration register - Per Channel RCB FET gate off configuration

Table 11-40. DEV_CONFIG6 Register Field Descriptions

Bit

7-4

3

Field

Type

R

Reset

0h

Description

RESERVED

RCB_CH4

Reserved

R/W

1h

Bit determines the reverse current blocking FET gate control in CH4

0h = Reverse current blocking FET gate pulldown (CH4) is enabled

(if RCB_DIS bit is not set)

1h = Reverse current blocking function in CH4 enabled (if RCB_DIS

bit is not set)

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Table 11-40. DEV_CONFIG6 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2

RCB_CH3

R/W

1h

Bit determines the reverse current blocking FET gate control in CH3

0h = Reverse current blocking FET gate pulldown (CH3) is enabled

(if RCB_DIS bit is not set)

1h = Reverse current blocking function in CH3 enabled (if RCB_DIS

bit is not set)

1

0

RCB_CH2

RCB_CH1

R/W

1h

Bit determines the reverse current blocking FET gate control in CH2

0h = Reverse current blocking FET gate pulldown (CH2) is enabled

(if RCB_DIS bit is not set)

1h = Reverse current blocking function in CH2 enabled (if RCB_DIS

bit is not set)

Bit determines the reverse current blocking FET gate control in CH1

0h = Reverse current blocking FET gate pulldown (CH1) is enabled

(if RCB_DIS bit is not set)

1h = Reverse current blocking function in CH1 enabled (if RCB_DIS

bit is not set)

11.39 FAULT_MASK Register (Offset = 27h) [Reset = 00h]

FAULT_MASK is shown in Table 11-41.

Return to the Summary Table.

The register allows masking of certain types of faults.

Table 11-41. FAULT_MASK Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MASK_SPI_ERR

R/W

0h

The bit is set to mask the SPI error (SPI_ERR) signaling in the FLT

pin output and FAULT_TYPE_STAT register

0h = SPI error is signaled in FAULT_TYPE_STAT register and FLT

1h = FAULT_TYPE_STAT register and FLT pin not impacted by SPI

error

6

MASK_WD_ERR

R/W

0h

The bit is set to mask the SPI watchdog error (WD_ERR) signaling in

the FLT pin output and FAULT_TYPE_STAT register

0h = SPI watchdog error is signaled in FAULT_TYPE_STAT register

and FLT pin

1h = FAULT_TYPE_STAT register and FLT pin not impacted by SPI

watchdog error

5

4

MASK_ILIMIT

R/W

0h

The bit is set to mask the signaling ILIMIT fault on the FLT pin

0h = Fault is signaled on the FLT pin on current limit occuring

1h = Current limit fault is not signaled (masked from) on the FLT pin

MASK_RVRS_BLK

The bit is set to mask the signaling reverse current fault on the FLT

0h = Fault is signaled on the FLT pin on reverse current fault

occuring

1h = Reverse current fault is not signaled (masked from) on the FLT

3

2

MASK_SHRT_VS

MASK_WB_OFF

R/W

0h

The bit is set to mask the signaling off-state Short to VS fault on the

FLT pin

0h = Short to VS Fault is signaled on the FLT pin on detecting the

fault with the diagnostic

1h = Short to VS fault is not signaled (masked from) on the FLT pin

The bit is set to mask the signaling off-state wire-break fault on the

FLT pin

0h = Off-state wire-break fault is signaled on the FLT pin on detecting

the fault with the diagnostic

1h = Off-state wire-break fault is not signaled (masked from) on the

FLT pin

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Table 11-41. FAULT_MASK Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

MASK_WB_ON

R/W

0h

The bit is set to mask the signaling on-state wire-break fault on the

FLT pin

0h = On-state wire-break fault is signaled on the FLT pin on detecting

the fault with the diagnostic

1h = On-state wire-break fault is not signaled (masked from) on the

FLT pin

0

MASK_VS_UV

R/W

0h

The bit is set to mask the supply voltage VS UV fault signaling on the

FLT pin output.

0h = VS UV fault is signaled on the FLT pin on detecting the fault

with the diagnostic

1h = VS UV fault is not signaled (masked from) on the FLT pin

11.40 EN_WB_OFF Register (Offset = 28h) [Reset = 00h]

EN_WB_OFF is shown in Table 11-42.

Return to the Summary Table.

Enables diagnostic of the wire-break (off-state) faults in the fault registers

Table 11-42. EN_WB_OFF Register Field Descriptions

Bit

7-4

3

Field

Type

R

Reset

0h

Description

RESERVED

WB_OFF_CH4_EN

Reserved

R/W

0h

Set this bit to 1 to enable the wire-break (off-state) fault in CH4

0h = Wire-break (off-state) fault diagnostic in CH4 not enabled

1h = Wire-break (off-state) fault diagnostic in CH4 is enabled

2

1

0

WB_OFF_CH3_EN

WB_OFF_CH2_EN

WB_OFF_CH1_EN

R/W

0h

Set this bit to 1 to enable the wire-break (off-state) fault in CH3

0h = Wire-break (off-state) fault diagnostic in CH3 not enabled

1h = Wire-break (off-state) fault diagnostic in CH3 is enabled

Set this bit to 1 to enable the wire-break (off-state) fault in CH2

0h = Wire-break (off-state) fault diagnostic in CH2 not enabled

1h = Wire-break (off-state) fault diagnostic in CH2 is enabled

Set this bit to 1 to enable the wire-break (off-state) fault in CH1

0h = Wire-break (off-state) fault diagnostic in CH1 not enabled

1h = Wire-break (off-state) fault diagnostic in CH1 is enabled

11.41 EN_WB_ON Register (Offset = 29h) [Reset = 00h]

EN_WB_ON is shown in Table 11-43.

Return to the Summary Table.

The register allows masking of On-state Wire-break fault per channel

Table 11-43. EN_WB_ON Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

0h

Description

Reserved

RESERVED

WB_ON_CH4_EN

R

R/W

0h

Set this bit to 1 to enable the wire-break (off-state) fault diagnostic in

CH4

0h = Wire-break (off-state) fault diagnostic in CH4 not enabled

1h = Wire-break (off-state) fault diagnostic in CH4 is enabled

2

WB_ON_CH3_EN

R/W

0h

Set this bit to 1 to enable the wire-break (off-state) fault diagnostic in

CH3

0h = Wire-break (off-state) fault diagnostic in CH3 not enabled

1h = Wire-break (off-state) fault diagnostic in CH3 is enabled

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Table 11-43. EN_WB_ON Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

WB_ON_CH2_EN

R/W

0h

Set this bit to 1 to enable the wire-break (off-state) fault diagnostic in

CH2

0h = Wire-break (off-state) fault diagnostic in CH2 not enabled

1h = Wire-break (off-state) fault diagnostic in CH2 is enabled

0

WB_ON_CH1_EN

R/W

0h

Set this bit to 1 to enable the wire-break (off-state) fault diagnostic in

CH1

0h = Wire-break (off-state) fault diagnostic in CH1 not enabled

1h = Wire-break (off-state) fault diagnostic in CH1 is enabled

11.42 EN_SHRT_VS Register (Offset = 2Ah) [Reset = 00h]

EN_SHRT_VS is shown in Table 11-44.

Return to the Summary Table.

The register allows masking of output short to supply (VS) fault per channel

Table 11-44. EN_SHRT_VS Register Field Descriptions

Bit

7-4

3

Field

Type

R

Reset

0h

Description

RESERVED

SHRT_VS_CH4_EN

Reserved

R/W

0h

Set this bit to 1 to enable the short_to_VS (off-state) fault diagnostic

in CH4

0h = short_to_VS (off-state) fault diagnostic in CH4 not enabled

1h = short_to_VS (off-state) fault diagnostic in CH4 enabled

2

1

0

SHRT_VS_CH3_EN

SHRT_VS_CH2_EN

SHRT_VS_CH1_EN

R/W

0h

Set this bit to 1 to enable the short_to_VS (off-state) fault diagnostic

in CH3

0h = short_to_VS (off-state) fault diagnostic in CH3 not enabled

1h = short_to_VS (off-state) fault diagnostic in CH3 enabled

Set this bit to 1 to enable the short_to_VS (off-state) fault diagnostic

in CH2

0h = short_to_VS (off-state) fault diagnostic in CH2 not enabled

1h = short_to_VS (off-state) fault diagnostic in CH2 enabled

Set this bit to 1 to enable the short_to_VS (off-state) fault diagnostic

in CH1

0h = short_to_VS (off-state) fault diagnostic in CH1 not enabled

1h = short_to_VS (off-state) fault diagnostic in CH1 enabled

11.43 ADC_ISNS_DIS Register (Offset = 2Bh) [Reset = 00h]

ADC_ISNS_DIS is shown in Table 11-45.

Return to the Summary Table.

Allows disabling the ADC conversion of ISNS on a per channel basis

Table 11-45. ADC_ISNS_DIS Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

RESERVED

ISNS_DIS_CH4

R

0h

Reserved

R/W

0h

Set this bit to 1 disable ISNS_CH4 conversion

0h = ISNS_CH4 ADC conversion included

1h = ISNS_CH4 ADC conversion disabled

2

1

ISNS_DIS_CH3

ISNS_DIS_CH2

Set this bit to 1 disable ISNS_CH3 conversion

0h = ISNS_CH3 ADC conversion included

1h = ISNS_CH3 ADC conversion disabled

Set this bit to 1 disable ISNS_CH2 conversion

0h = ISNS_CH2 ADC conversion included

1h = ISNS_CH2 ADC conversion disabled

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Table 11-45. ADC_ISNS_DIS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

ISNS_DIS_CH1

R/W

0h

Set this bit to 1 disable ISNS_CH1 conversion

0h = ISNS_CH1 ADC conversion included

1h = ISNS_CH1 ADC conversion disabled

11.44 ADC_TSNS_DIS Register (Offset = 2Ch) [Reset = 00h]

ADC_TSNS_DIS is shown in Table 11-46.

Return to the Summary Table.

Allows disabling the ADC conversion of TSNS on a per channel basis

Table 11-46. ADC_TSNS_DIS Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

RESERVED

TSNS_DIS_CH4

R

0h

Reserved

R/W

0h

Set this bit to 1 disable TSNS_CH4 conversion

0h = TSNS_CH4 ADC conversion included

1h = TSNS_CH4 ADC conversion disabled

2

1

0

TSNS_DIS_CH3

TSNS_DIS_CH2

TSNS_DIS_CH1

Set this bit to 1 disable TSNS_CH3 conversion

0h = TSNS_CH3 ADC conversion included

1h = TSNS_CH3 ADC conversion disabled

Set this bit to 1 disable TSNS_CH2 conversion

0h = TSNS_CH2 ADC conversion included

1h = TSNS_CH2 ADC conversion disabled

Set this bit to 1 disable TSNS_CH1 conversion

0h = TSNS_CH1 ADC conversion included

1h = TSNS_CH1 ADC conversion disabled

11.45 ADC_VSNS_DIS Register (Offset = 2Dh) [Reset = 00h]

ADC_VSNS_DIS is shown in Table 11-47.

Return to the Summary Table.

Allows disabling the ADC conversion of VSNS on a per channel basis

Table 11-47. ADC_VSNS_DIS Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

RESERVED

VSNS_DIS_CH4

R

0h

Reserved

R/W

0h

Set this bit to 1 disable VSNS_CH4 conversion

0h = VSNS_CH4 ADC conversion included

1h = VSNS_CH4 ADC conversion disabled

2

1

0

VSNS_DIS_CH3

VSNS_DIS_CH2

VSNS_DIS_CH1

Set this bit to 1 disable VSNS_CH3 conversion

0h = VSNS_CH3 ADC conversion included

1h = VSNS_CH3 ADC conversion disabled

Set this bit to 1 disable VSNS_CH2 conversion

0h = VSNS_CH2 ADC conversion included

1h = VSNS_CH2 ADC conversion disabled

Set this bit to 1 disable VSNS_CH1 conversion

0h = VSNS_CH1 ADC conversion included

1h = VSNS_CH1 ADC conversion disabled

11.46 ADC_CONFIG1 Register (Offset = 2Eh) [Reset = 00h]

ADC_CONFIG1 is shown in Table 11-48.

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Return to the Summary Table.

ADC configuration - disable conversion of measurements not needed.

Table 11-48. ADC_CONFIG1 Register Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

RESERVED

ADC_TSNS_DIS

R

0h

Reserved

R/W

0h

Set this bit to 1 to disable the ADC TSNS functionality

0h = TSNS ADC functionality enabled

1h = TSNS ADC functionality is disabled

2

1

0

ADC_VSNS_DIS

ADC_ISNS_DIS

ADC_VS_DIS

Set this bit to 1 to disable the VSNS ADC functionality

0h = VSNS ADC functionality enabled

1h = VSNS ADC functionality is disabled

Set this bit to 1 to disable ISNS ADC functionality

0h = ISNS ADC functionality enabled

1h = ISNS ADC functionality is disabled

Set this bit to 1 to disable supply voltage V_VS conversion in the

ADC conversion sequence.

0h = Include supply voltage V_VS conversion in the sequence

1h = No conversion of suppy voltage V_VS

11.47 CRC_CONFIG Register (Offset = 2Fh) [Reset = 00h]

CRC_CONFIG is shown in Table 11-49.

Return to the Summary Table.

Configure CRC

Table 11-49. CRC_CONFIG Register Field Descriptions

Bit

7-2

1

Field

Type

Reset

Description

RESERVED

D24BIT

R

0h

Reserved

R/W

0h

Set this bit to 1 to use 24-bit SPI command frame in daisy chain

mode

0h = 16-bit frame and No CRC check of SPI command frame

1h = 24-bit frame with the possibility of CRC check

0

CRC_EN

R/W

0h

Set this bit to 1 to enable CRC check of SPI command frame.

0h = No CRC check of SPI command frame

1h = CRC check of SPI command frame enabled

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12 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

12.1 Application Information

Figure 12-1 shows the schematic of a typical application of the TPS274C65. It includes all standard external

components. This section of the data sheet discusses the considerations in implementing commonly required

application functionality.

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+3.3V/5.5V

+24V

C_VIN1

C_VIN2

C_VDD

Z_TVS

VDD

FLT

VS

Q_RCB

Load1

C_OUT

OUT1

DO_EN

READY

REG_EN

RCB1

OUT2

Q_RCB

Load2

C_OUT

RCB2

OUT3

Q_RCB

ADDCFG

DSPI

SCLK

SDI

Load3

C_OUT

RCB3

OUT4

Q_RCB

Load4

C_OUT

SDO

RCB4

GND

CS

ISNS

LEDOUT4

LEDOUT1

LEDOUT2 LEDOUT3

R_S

R_F

D2

Optional

Reverse

Polarity

D7

D1

D8

D4

D3

D5

D6

Figure 12-1. Typical Application Circuit

Table 12-1. Recommended External Components

COMPONENT

R_SNS

TYPICAL VALUE

PURPOSE

1 kΩ

Translate the sense current into sense voltage.

Low-pass filter for the ADC input.

C_SNS

100 pF

R_ILIMx

5 kΩ to 80 kΩ

Set current limit threshold, connect from pin to IC GND.

Filtering of voltage transients (for example, ESD, IEC 61000-4-5) and improved

emissions.

C_Vin1

4.7 nF to Device GND

C_Vin2

C_VDD

100 nF to Module GND Stabilize the input supply and filter out low frequency noise.

2.2 µF to Module GND Stabilize the input supply and limit supply excursions.

70

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Table 12-1. Recommended External Components (continued)

COMPONENT

TYPICAL VALUE

PURPOSE

C_OUT

22 nF

Filtering of voltage transients (for example, ESD, RF transients).

Clamp surge voltages at the supply input.

Z_TVS

36-V TVS

Diode + max 10 Ω from

Device GND to Module

GND

Optional for reverse polarity protection - if needed. Series resistor needed for surge

events.

D_GND, Z_GND

R_GND

Q_RCB

R_S

4.7 kΩ

20-nC FET

490 Ω

Stabilize IC GND in the event of negative output swings.

Optional for Reverse current blocking.

Limiting the current flowing through the LEDs.

R_F

490 Ω

12.1.1 IEC 61000-4-5 Surge

The TPS274C65 is designed to survive against IEC 61000-4-5⁽¹⁾surge using external TVS clamps. The device

is rated to 48 V ensuring that external TVS diodes can clamp below the rated maximum voltage of the

TPS274C65. Above 48V, the device includes V_DSclamps to help shunt current and ensure that the device

will survive the transient pulses. Depending on the class of the output, it is recommend that the system has a

SMBJ36A or SMCJ36A between VS and module GND.

12.1.2 Loss of GND

The ground connection may be lost either on the device level or on the module level. If the ground connection

is lost, both the channel outputs will be disabled irrespective of the EN input level. If the switch was already

disabled when the ground connection was lost, the outputs will remain disabled even when the channels are

enabled. The steady state current from the output to the load that remains connected to the system ground is

below the level specified in the Specifications section of this document. When the ground is reconnected, normal

operation will resume.

12.1.3 Paralleling Channels

If an application requires lower power dissipation than is possible with a 65 mΩ switch, the TPS274C65 can

have up to two channel outputs (CH1 and CH2 OR CH3 and CH4) tied together to function as a single 32.5

mΩ high side switch. In this case, there will be some decrease in I_SNSand I_LIMaccuracy, however the device

will function properly. The max contious load current per channel while channels are paralleled is defined in

Electrical Characteristics.

12.1.4 Current Silicon Limitations

There are some known limitations with the current silicon. These limitations will be addressed in the next revision

of the silicon. Please contact TI for more information.

Table 12-2. Current Silicon Limitations

Known Limitations with the Current

Silicon

System Workaround with the Current

Silicon

Behavior with the Next Revision of Silicon

Device might get damaged when a negative Add Schottky diode at the input (SL44) or

Device will survive the negative surge

at the output without additional external

components

surge is applied at the output

add enough capacitance at the input so the

supply doesn't dip more negative than -1V

when the surge is applied

Device might malfunction when in daisy chain Use addressable SPI version for evaluation

mode

Device will function normally with daisy chain

mode

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12.2 Power Supply Recommendations

Table 12-3. Operating Voltage Range

V_SVoltage Range

Note

Nominal supply voltage, all

parametric specifications apply.

The device is completely short-

circuit protected up to 125°C

6 V to 36 V

Functional operation per data

sheet (switch may turn-off),

but may not meet parametric

specifications.

36 V to 48 V

12.3 Layout

12.3.1 Layout Guidelines

To achieve optimal thermal performance, connect the exposed pad to a large copper pour. On the top PCB layer,

the pour may extend beyond the package dimensions as shown in the example below. In addition to this, it is

recommended to also have a V_Splane either on one of the internal PCB layers or on the bottom layer.

Vias should connect this plane to the top V_Spour.

Ensure that all external components are placed close to the pins. Device current limiting performance can be

harmed if the R_ILIMis far from the pins and extra parasitics are introduced.

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12.3.2 Layout Example

40

39

38

37

36

35

34

33

32

31

1

2

READY

30

29

28

ADDCFG

REG_EN

FLT

DO_EN

VDD

3

DSPI

4

27 DNC

5

26

25

24

23

22

21

DNC

GND

ISNS

PowerPad

6

LEDOUT4

SDO

7

LEDOUT3

LEDOUT2

LEDOUT1

8

SDI

SCLK

9

10

CS

GND

12

13

14

15

16

17

18

19

20

11

Figure 12-2. Layout Example

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13 Device and Documentation Support

13.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

13.2 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.5 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

74

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

14.1 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

K0

P1

W

B0

Reel

Diameter

Cavity

A0

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

W

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

Device

Pins

SPQ

TPS274C65ASRHAR

TPS274C65ASRHAT

VQFN

RHA

40

2500

250

330

180

16.4

6.3

1.1

12

16

Q2

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

H

W

L

Device

Package Type

VQFN

Package Drawing Pins

SPQ

2500

250

Length (mm) Width (mm)

Height (mm)

TPS274C65ASRHAR

RHA

40

367

210

367

185

35

TPS274C65ASRHAT

VQFN

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PACKAGE OUTLINE

RHA0040B

VQFN - 1 mm max height

S

C

A

L

E

2

.

2

0

PLASTIC QUAD FLATPACK - NO LEAD

6.1

5.9

B

A

PIN 1 INDEX AREA

6.1

5.9

1 MAX

C

SEATING PLANE

0.08

0.05

0.00

2X 4.5

4.15 0.1

(0.2) TYP

11

20

36X 0.5

10

21

EXPOSED

THERMAL PAD

2X

SYMM

41

4.5

30

0.27

40X

1

0.17

PIN 1 ID

(OPTIONAL)

0.1

C A B

40

31

SYMM

0.05

0.5

0.3

40X

4219052/A 06/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RHA0040B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.15)

SYMM

40X (0.6)

40

31

40X (0.22)

1

30

(0.25) TYP

36X (0.5)

SYMM

41

(5.8)

(0.685)

TYP

(1.14)

TYP

(

0.2) TYP

VIA

10

21

(R0.05) TYP

11

20

(0.685)

TYP

(1.14)

TYP

(5.8)

LAND PATTERN EXAMPLE

SCALE:12X

0.07 MIN

ALL SIDES

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4219052/A 06/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

RHA0040B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

9X ( 1.17)

(1.37) TYP

40X (0.6)

40X (0.22)

31

40

1

30

41

(1.37)

TYP

(0.25) TYP

SYMM

(5.8)

36X (0.5)

(R0.05) TYP

10

21

11

20

METAL

TYP

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 41:

72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4219052/A 06/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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GENERIC PACKAGE VIEW

RHA 40

6 x 6, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225870/A

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS274C65
厂家：	TEXAS INSTRUMENTS
描述：	具有 SPI 接口和集成式 ADC 的 12V 至 36V 65mΩ 四通道高侧开关开关
文件：	总82页 (文件大小：2455K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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