TPS2832DRG4 [TI]
Non-inverting Fast Synchronous Buck MOSFET Drivers 8-SOIC -40 to 125;
| 型号： | TPS2832DRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Non-inverting Fast Synchronous Buck MOSFET Drivers 8-SOIC -40 to 125 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总16页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢇꢈꢂꢀ ꢂꢉ ꢊꢋꢌꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏꢋꢒ ꢓ ꢎꢂ ꢇꢔ ꢀ ꢕ ꢍꢖ ꢗ ꢔꢍ ꢂ
ꢘ ꢖꢀ ꢌ ꢕꢔꢈ ꢕꢐꢀ ꢖꢓ ꢔ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢙ
SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
D PACKAGE
(TOP VIEW)
D
Floating Bootstrap or Ground-Reference
High-Side Driver
IN
PGND
DT
BOOT
D
Adaptive Dead-Time Control
1
2
3
4
8
7
6
5
HIGHDR
BOOTLO
LOWDR
D
50-ns Max Rise/Fall Times and 100-ns Max
Propagation Delay − 3.3-nF Load
V
CC
D
Ideal for High-Current Single or Multiphase
Power Supplies
D
D
D
D
D
2.4-A Typical Peak Output Current
4.5-V to 15-V Supply Voltage Range
Internal Schottky Bootstrap Diode
Low Supply Current....3-mA Typical
−40°C to 125°C Operating Virtual Junction
Temperature
D
Available in SOIC Package
description
The TPS2832 and TPS2833 are MOSFET drivers for synchronous-buck power stages. These devices are ideal
for designing a high-performance power supply using switching controllers that do not have MOSFET drivers.
The drivers are designed to deliver 2.4-A peak currents into large capacitive loads. The high-side driver can be
configured as a ground-reference driver or as a floating bootstrap driver. An adaptive dead-time control circuit
eliminates shoot-through currents through the main power FETs during switching transitions and provides high
efficiency for the buck regulator.
The TPS2832 has a noninverting input. The TPS2833 has an inverting input. The TPS2832/33 drivers, available
in 8-terminal SOIC packages, operate over a junction temperature range of −40°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
J
SOIC
(D)
TPS2832D
TPS2833D
−40°C to 125°C
The D package is available taped and reeled. Add R
suffix to device type (e.g., TPS2832DR)
Related Synchronous MOSFET Drivers
DEVICE NAME
TPS2830
TPS2831
TPS2834
TPS2835
TPS2836
TPS2837
ADDITIONAL FEATURES
INPUTS
Noninverted
ENABLE, SYNC and CROWBAR
ENABLE, SYNC and CROWBAR
W/O ENABLE, SYNC and CROWBAR
CMOS
TTL
Inverted
Noninverted
Inverted
Noninverted
Inverted
TTL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2001, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢘꢖ ꢀ ꢌ ꢕ ꢔꢈ ꢕꢐ ꢀ ꢖꢓ ꢔ ꢋꢎ ꢊꢀ ꢍꢎ ꢙ
SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
functional block diagram
4
8
V
CC
BOOT
7
6
(TPS2832 Only)
HIGHDR
BOOTLO
1
IN
V
CC
(TPS2833 Only)
5
2
LOWDR
PGND
3
DT
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
BOOT
NO.
8
I
Bootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTLO terminals to develop
the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 µF
and 1 µF. A 1-MΩ resistor should be connected across the bootstrap capacitor to provide a discharge path
when the driver has been powered down.
BOOTLO
DT
6
3
7
1
5
2
4
O
I
This terminal connects to the junction of the high-side and low-side MOSFETs.
Dead-time control terminal. Connect DT to the junction of the high-side and low-side MOSFETs
Output drive for the high-side power MOSFET
HIGHDR
IN
O
I
Input signal to the MOSFET drivers (noninverting input for the TPS2832; inverting input for the TPS2833).
Output drive for the low-side power MOSFET
LOWDR
PGND
O
Power ground. Connect to the FET power ground.
V
CC
I
Input supply. Recommended that a 1 µF capacitor be connected from V
to PGND.
CC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢘ ꢖꢀ ꢌ ꢕꢔꢈ ꢕꢐꢀ ꢖꢓ ꢔ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢙ
SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
detailed description
low-side driver
The low-side driver is designed to drive low Rds(on) N-channel MOSFETs. The current rating of the driver is
2 A, source and sink.
high-side driver
The high-side driver is designed to drive low Rds(on) N-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured as a ground-reference driver or a floating bootstrap
driver. The internal bootstrap diode, is a Schottky for improved drive efficiency. The maximum voltage that can
be applied between the BOOT terminal and ground is 30 V.
†
dead-time (DT) control
Dead-time control prevents shoot through current from flowing through the main power FETs during switching
transitions by controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed to turn
on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until
the voltage at the junction of the power FETs (Vdrain) is low; the DT terminal connects to the junction of the power
FETs.
†
IN
The IN terminal is a digital terminal that is the input control signal for the drivers. The TPS2832 has a noninverting
input; the TPS2833 has an inverting input.
†
High-level input voltages on IN and DT must be greater than or equal to 0.7V
CC
.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
CC
Input voltage range:BOOT to PGND (high-side driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V
BOOTLO to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
IN (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
DT (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Unless otherwise specified, all voltages are with respect to PGND.
2. High-level input voltages on the IN and DT terminals must be less than or equal to V
.
CC
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
D
600 mW
6.0 mW/°C
330 mW
240 mW
recommended operating conditions
MIN NOM
MAX
15
UNIT
V
Supply voltage, V
Input voltage
4.5
4.5
CC
BOOT to PGND
28
V
electrical characteristics over recommended operating virtual junction temperature range,
= 6.5 V, C = 3.3 nF (unless otherwise noted)
V
CC
L
supply current
PARAMETER
Supply voltage range
TEST CONDITIONS
MIN
TYP
MAX
15
UNIT
V
4.5
V
=15 V
=12 V,
100
µA
CC
V
CC
V
f
BOOTLO grounded,
= 50 pF,
CC
SWX
Quiescent current
= 200 kHz,
= 50 pF,
3
mA
C
LOWDR
See Note 3
C
HIGHDR
NOTE 3: Ensured by design, not production tested.
4
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ꢘ ꢖꢀ ꢌ ꢕꢔꢈ ꢕꢐꢀ ꢖꢓ ꢔ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢙ
SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
electrical characteristics over recommended operating virtual junction temperature range,
= 6.5 V, C = 3.3 nF (unless otherwise noted) (continued)
V
CC
L
output drivers
PARAMETER
TEST CONDITIONS
MIN
0.7
1.1
2
TYP
1.1
1.5
2.4
1.4
1.6
2.7
1.8
2.5
3.5
1.7
2.4
3
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
– V
– V
– V
– V
– V
– V
= 4.5 V, V
= 4 V
BOOT
BOOT
BOOT
BOOT
BOOT
BOOT
BOOTLO
BOOTLO
BOOTLO
BOOTLO
BOOTLO
BOOTLO
HIGHDR
HIGHDR
HIGHDR
HIGHDR
HIGHDR
HIGHDR
LOWDR
LOWDR
LOWDR
LOWDR
LOWDR
LOWDR
HIGHDR
HIGHDR
HIGHDR
HIGHDR
HIGHDR
HIGHDR
LOWDR
LOWDR
LOWDR
LOWDR
LOWDR
LOWDR
Duty cycle < 2%,
High-side sink
(see Note 4)
= 6.5 V, V
= 5 V
t
< 100 µs
A
pw
(see Note 3)
= 12 V, V
= 10.5 V
= 0.5V
= 1.5 V
= 1.5 V
= 4 V
= 4.5 V, V
1.2
1.3
2.3
1.3
2
High-side
source
(see Note 4)
Duty cycle < 2%,
= 6.5 V, V
t
< 100 µs
A
A
A
Ω
Ω
Ω
Ω
pw
(see Note 3)
= 12 V, V
Peak output-
current
= 4.5 V,
= 6.5 V,
= 12 V,
= 4.5 V,
= 6.5 V,
= 12 V,
V
CC
Duty cycle < 2%,
Low-side sink
(see Note 4)
V
= 5 V
t
< 100 µs
CC
pw
(see Note 3)
V
= 10.5 V
= 0.5V
= 1.5 V
= 1.5 V
= 0.5 V
= 0.5 V
= 0.5 V
= 4 V
3
CC
V
1.4
2
CC
Low-side
source
(see Note 4)
Duty cycle < 2%,
V
t
< 100 µs
CC
pw
(see Note 3)
V
2.5
CC
– V
– V
– V
– V
– V
– V
= 4.5 V, V
5
5
BOOT
BOOT
BOOT
BOOT
BOOT
BOOT
BOOTLO
BOOTLO
BOOTLO
BOOTLO
BOOTLO
BOOTLO
= 6.5 V, V
High-side sink (see Note 4)
High-side source (see Note 4)
Low-side sink (see Note 4)
Low-side source (see Note 4)
= 12 V, V
5
= 4.5 V, V
75
75
75
9
= 6.5 V, V
= 6 V
= 12 V, V
=11.5 V
= 0.5 V
= 0.5 V
= 0.5 V
= 4 V
Output
resistance
= 4.5 V,
= 6.5 V
= 12 V,
= 4.5 V,
= 6.5 V,
= 12 V,
V
V
V
V
V
V
DRV
DRV
DRV
DRV
DRV
DRV
7.5
6
75
75
75
= 6 V
= 11.5 V
NOTES: 3. Ensured by design, not production tested.
4. The pull-up/pull-down circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
dead time
PARAMETER
High-level input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
IH
V
IL
V
IH
V
IL
0.7V
CC
LOWDR
DT
Over the V
range (see Note 3)
range
V
CC
CC
Low-level input voltage
High-level input voltage
Low-level input voltage
1
1
0.7V
CC
Over the V
V
NOTE 3: Ensured by design, not production tested.
digital control terminals
PARAMETER
TEST CONDITIONS
MIN
0.7V
TYP
MAX
UNIT
V
V
V
High-level input voltage
Low-level input voltage
IH
CC
Over the V
CC
range
1
V
IL
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
switching characteristics over recommended operating virtual junction temperature range,
C = 3.3 nF (unless otherwise noted)
L
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
60
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 4.5 V,
= 6.5 V,
= 12 V,
V
V
V
= 0 V
= 0 V
= 0 V
BOOT
BOOT
BOOT
BOOTLO
BOOTLO
BOOTLO
50
HIGHDR output (see Note 3)
ns
50
Rise time
= 4.5 V
40
CC
CC
CC
= 6.5 V
= 12 V
30
LOWDR output (see Note 3)
ns
ns
ns
ns
ns
ns
ns
30
= 4.5 V,
= 6.5 V,
= 12 V,
V
= 0 V
= 0 V
= 0 V
60
BOOT
BOOT
BOOT
BOOTLO
BOOTLO
BOOTLO
V
V
50
HIGHDR output (see Note 3)
50
Fall time
= 4.5 V
40
CC
CC
CC
= 6.5 V
= 12 V
30
LOWDR output (see Note 3)
30
= 4.5 V,
= 6.5 V,
= 12 V,
= 4.5 V,
= 6.5 V,
= 12 V,
V
V
V
V
V
V
= 0 V
= 0 V
= 0 V
= 0 V
= 0 V
= 0 V
130
100
75
BOOT
BOOT
BOOT
BOOT
BOOT
BOOT
BOOTLO
BOOTLO
BOOTLO
BOOTLO
BOOTLO
BOOTLO
HIGHDR going low
(excluding dead time) (see Note 3)
Propagation delay time
80
LOWDR going high
(excluding dead time) (see Note 3)
70
60
= 4.5 V
80
CC
CC
CC
CC
CC
CC
LOWDR going low
(excluding dead time) (see Note 3)
= 6.5 V
70
Propagation delay time
= 12 V
= 4.5 V
= 6.5 V
= 12 V
60
40
25
15
170
135
85
DT to LOWDR and
Driver nonoverlap time
LOWDR to HIGHDR (see Note 3)
NOTE 3: Ensured by design, not production tested.
6
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ꢘ ꢖꢀ ꢌ ꢕꢔꢈ ꢕꢐꢀ ꢖꢓ ꢔ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢙ
SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
TYPICAL CHARACTERISTICS
FALL TIME
vs
RISE TIME
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
50
45
40
50
45
40
C
T
= 3.3 nF
= 25°C
C
T
= 3.3 nF
= 25°C
L
J
L
J
High Side
Low Side
35
30
35
30
High Side
Low Side
25
20
25
20
15
10
15
10
4
5
6
7
8
9
10 11 12 13 14 15
4
5
6
7
8
9
10 11 12 13 14 15
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 1
Figure 2
RISE TIME
vs
JUNCTION TEMPERATURE
FALL TIME
vs
JUNCTION TEMPERATURE
50
45
40
50
45
40
V
C
= 6.5 V
= 3.3 nF
CC
L
V
C
= 6.5 V
= 3.3 nF
CC
L
High Side
High Side
Low Side
35
30
35
30
Low Side
25
20
25
20
15
10
15
10
−50
−25
0
25
50
75
100
125
0
25
50
75
100
125
−50
−25
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 3
Figure 4
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢅ
ꢇꢈꢂ ꢀ ꢂꢉ ꢊꢋ ꢌ ꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏ ꢋꢒ ꢓꢎ ꢂꢇ ꢔ ꢀ ꢕꢍꢖ ꢗꢔ ꢍꢂ
ꢘꢖ ꢀ ꢌ ꢕ ꢔꢈ ꢕꢐ ꢀ ꢖꢓ ꢔ ꢋꢎ ꢊꢀ ꢍꢎ ꢙ
SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
TYPICAL CHARACTERISTICS
HIGH-TO-LOW PROPAGATION DELAY TIME
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
vs
SUPPLY VOLTAGE, HIGH TO LOW LEVEL
SUPPLY VOLTAGE, LOW TO HIGH LEVEL
150
140
130
150
140
130
C
T
= 3.3 nF
= 25°C
C
T
= 3.3 nF
= 25°C
L
J
L
J
120
110
100
120
110
100
90
80
90
80
High Side
Low Side
High Side
Low Side
70
60
50
40
70
60
50
40
30
20
30
20
4
5
6
7
8
9
10 11 12 13 14 15
4
5
6
7
8
9
10 11 12 13 14 15
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 5
Figure 6
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
150
150
140
130
V
C
= 6.5 V
= 3.3 nF
V
C
= 6.5 V
140
130
CC
L
CC
= 3.3 nF
L
120
110
100
120
110
100
High Side
90
80
90
80
High Side
70
60
50
40
70
60
50
40
Low Side
Low Side
30
20
30
20
−50
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 7
Figure 8
8
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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢇꢈꢂꢀ ꢂꢉ ꢊꢋꢌꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏꢋꢒ ꢓ ꢎꢂ ꢇꢔ ꢀ ꢕ ꢍꢖ ꢗ ꢔꢍ ꢂ
ꢘ ꢖꢀ ꢌ ꢕꢔꢈ ꢕꢐꢀ ꢖꢓ ꢔ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢙ
SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
TYPICAL CHARACTERISTICS
FALL TIME
vs
RISE TIME
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1000
1000
V
T
= 6.5 V
V
T
= 6.5 V
CC
= 25°C
CC
= 25°C
J
J
100
10
100
10
High Side
High Side
Low Side
Low Side
1
1
0.1
1
10
100
0.1
1
10
100
C
− Load Capacitance − nF
C
− Load Capacitance − nF
L
L
Figure 9
Figure 10
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
25
6000
5500
5000
4500
4000
T
C
= 25°C
= 50 pF
T
C
= 25°C
= 50 pF
J
L
J
L
20
15
500 kHz
2 MHz
300 kHz
200 kHz
3500
3000
2500
2000
1500
1000
100 kHz
50 kHz
25 kHz
10
5
1 MHz
500
0
0
4
6
8
10
12
14
16
4
6
8
10
12
14
16
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 11
Figure 12
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢅ
ꢇꢈꢂ ꢀ ꢂꢉ ꢊꢋ ꢌ ꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏ ꢋꢒ ꢓꢎ ꢂꢇ ꢔ ꢀ ꢕꢍꢖ ꢗꢔ ꢍꢂ
ꢘꢖ ꢀ ꢌ ꢕ ꢔꢈ ꢕꢐ ꢀ ꢖꢓ ꢔ ꢋꢎ ꢊꢀ ꢍꢎ ꢙ
SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
TYPICAL CHARACTERISTICS
PEAK SOURCE CURRENT
PEAK SINK CURRENT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
4
3.5
3
4
3.5
3
T
J
= 25°C
T = 25°C
J
Low Side
Low Side
2.5
2
2.5
2
High Side
High Side
1.5
1
1.5
1
0.5
0
0.5
0
4
6
8
10
12
14
16
4
6
8
10
− Supply Voltage − V
CC
12
14
16
V
− Supply Voltage − V
V
CC
Figure 13
Figure 14
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
9
T
J
= 25°C
8
7
6
5
4
3
2
1
0
4
6
8
10
12
14
16
V
CC
− Supply Voltage − V
Figure 15
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢇꢈꢂꢀ ꢂꢉ ꢊꢋꢌꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏꢋꢒ ꢓ ꢎꢂ ꢇꢔ ꢀ ꢕ ꢍꢖ ꢗ ꢔꢍ ꢂ
ꢘ ꢖꢀ ꢌ ꢕꢔꢈ ꢕꢐꢀ ꢖꢓ ꢔ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢙ
SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
APPLICATION INFORMATION
Figure 16 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A
pulse-width-modulation (PWM) controller and a TPS2833 driver. The converter operates over an input range from
4.5 V to 12 V and has a 3.3 V output. The circuit can supply 3 A continuous load and the transient load is 5 A. The
converter achieves an efficiency of 94% for V = 5 V, I
=1 A, and 93% for V = 5 V, I = 3 A.
IN
load
in load
V
IN
+
C10
C5
100 µF
100 µF
+
C11
0.47 µF
R5
0 Ω
R1
1 kΩ
U1
TPS2833
R6
1 MΩ
1
2
3
4
8
7
6
5
C15
1.0 µF
IN
BOOT
Q1
Si4410
L1
27 µH
PGND HIGHDR
DT
BOOTLO
LOWDR
3.3 V
V
CC
C13
R7
3.3 Ω
10 µF
R11
4.7 Ω
C7
100 µF
+
C12
100 µF
+
Q2
C14
Si4410
C6
1 µF
1000 pF
RTN
GND
C8
0.1 µF
C3
0.0022 µF
U2
TL5001A
C2
0.033 µF
2
C4
0.022 µF
R3
180 Ω
V
CC
R2
1.6 kΩ
3
1
6
COMP
OUT
DTC
4
7
FB
RT
R4
2.32 kΩ
C9
0.22 µF
5
SCP
R8
121 kΩ
GND
8
R9
90.9 kΩ
R10
1.0 kΩ
C1
1 µF
Figure 16. 3.3 V 3 A Synchronous-Buck Converter Circuit
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢅ
ꢇꢈꢂ ꢀ ꢂꢉ ꢊꢋ ꢌ ꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏ ꢋꢒ ꢓꢎ ꢂꢇ ꢔ ꢀ ꢕꢍꢖ ꢗꢔ ꢍꢂ
ꢘꢖ ꢀ ꢌ ꢕ ꢔꢈ ꢕꢐ ꢀ ꢖꢓ ꢔ ꢋꢎ ꢊꢀ ꢍꢎ ꢙ
SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001
APPLICATION INFORMATION
Great care should be taken when laying out the pc board. The power-processing section is the most critical and
will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very
tight. The connection from Q1 drain to the positive sides of C5, C10, and C11 and the connection from Q2 source
to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and
C12 should also be connected to Q2 source.
Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from
the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive
traces. The bypass capacitor (C14) should be tied directly across V
and PGND.
CC
The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A) This node is very
sensitive to noise pickup and should be isolated from the high-current power stage and be as short as possible.
The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these
three areas are properly laid out, the rest of the circuit should not have any other EMI problems and the power
supply will be relatively free of noise.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
PACKAGING INFORMATION
Orderable Device
TPS2832D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2832DG4
TPS2832DR
TPS2832DRG4
TPS2833D
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2833DG4
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Dec-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2832DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Dec-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
340.5 338.1 20.6
TPS2832DR
D
8
2500
Pack Materials-Page 2
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