TPS2901 [TI]

SIMPLE -48-V HOT SWAP CONTROLLER; SIMPLE -48 V热插拔控制器


型号：	TPS2901
厂家：	TEXAS INSTRUMENTS
描述：	SIMPLE -48-V HOT SWAP CONTROLLER SIMPLE -48 V热插拔控制器控制器
文件：	总21页 (文件大小：653K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

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FEATURES

DESCRIPTION

Wide Input Supply Range: −36 V to −80 V

Transient Rating to −100 V

The TPS2390 and TPS2391 integrated circuits

are hot swap power managers optimized for use

in nominal −48-V systems. They are designed for

supply voltage ranges up to −80 V, and are rated

to withstand spikes to −100 V. In conjunction with

an external N-channel FET and sense resistor,

they can be used to enable live insertion of plug-in

cards and modules in powered systems. Both

devices provide load current slew rate and peak

magnitude limiting, easily programmed by sense

resistor value and a single-external capacitor.

They also provide single-line fault reporting,

electrical isolation of faulty cards, and protection

against nuisance overcurrent trips. The TPS2390

latches off in response to current faults, while the

TPS2391 periodically retries the load in the event

of a fault.

Programmable Current Limit

Programmable Current Slew Rate

Enable Input (EN)

Fault Timer to Eliminate Nuisance Trips

Open-Drain Fault Output (FAULT)

Requires Few External Components

8-Pin MSOP Package

⋅APPLICATIONS

−48-V Distributed Power Systems

Central Office Switching

Wireless Base Station

APPLICATION DIAGRAM

OUT

10 kΩ

1 W

−48V_RTN

DC/DC

CONVERTER

MODULE

OUT

100 µF

100 V

OUT

−

TPS2390/1

FAULT

RTN

100 kΩ

IRF530

DGK PACKAGE

(TOP VIEW)

GATE

FAULT

RTN

FLTTIME

IRAMP

ISENSE

−VIN

GATE

ISENS

−VIN

0.1 µF

0.02 Ω

1/4 W 1%

FLTTIME

IRAMP

−48V_IN

3900 pF

UDG−02085

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

ABSOLUTE MAXIMUM RATINGS (See Note 1)

TPS2390/1

−0.3 V to 15

UNIT

(2)

Input voltage range, all pins except RTN, EN, FAULT

(2)

Input voltage range, RTN

−0.3 V to 100

(2)(3)

Input voltage range, EN

(2)(4)

Output voltage range, FAULT

Continuous output current, FAULT

Continuous total power dissipation

Operating junction temperature range, T

see Dissipation Rating Table

−55_C to 125_C

−65_C to 150_C

260_C

Storage temperature range, T

stg

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds

NOTES 1: Stresses beyond those listed under ”absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating

conditions” is not implied. Exposure to absolute−maximum−rated conditions for extended periods may affect device reliability.

2: All voltages are with respect to −VIN (unless otherwise noted).

3: With 100-kΩ minimum input series resistance, −0.3 V to 15 V with low impedance.

4: With 10-kΩ minimum series resistance, −0.3 V to 80 V with low impedance.

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

MIN

1.5

UNIT

Human Body Model (HBM)

Charged Device Model (CDM)

1.5

RECOMMENDED OPERATING CONDITIONS†

MIN

−80

−40

NOM

MAX

UNIT

Nominal input supply, −VIN to RTN

Operating junction temperature range

−36

†

All voltages are with respect to −VIN (unless otherwise noted)

DISSIPATION RATING TABLE

PACKAGE

MSOP-8

< 25_C

DERATING FACTOR

= 85_C

POWER RATING

ABOVE T = 25_C

POWER RATING

420 mW

4.3 mW/_C

160 mW

AVAILABLE OPTIONS

OPERATING

FAULT

PACKAGED DEVICES

OPERATION

MSOP (DGK)

TPS2390DGK

TPS2391DGK

Latch off

−40

C to 85

Periodically retry

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

ELECTRICAL CHARACTERISTICS

= −48 V with respect to RTN, V

(1)(2)

= 2.8 V, V

= 0, all outputs unloaded, T = −40_C to 85_C

I(−VIN)

I(EN)

I(ISENS)

(unless otherwise noted)

input supply

PARAMETER

TEST CONDITIONS

MIN

TYP

700

MAX

1000

1500

−25

UNIT

µA

Supply current, RTN

= 48 V

= 80 V

CC1

I(RTN)

Supply current, RTN

1000

−30

2.3

CC2

I(RTN)

UVLO threshold, input voltage rising

UVLO hysteresis

To GATE pull-up, referenced to RTN

−36

1.8

UVLO_L

3.0

HYS

enable input (EN)

PARAMETER

Threshold voltage, input voltage rising

TEST CONDITIONS

MIN

TYP

1.4

MAX

1.5

UNIT

To GATE pull-up

1.3

−2

EN hysteresis

µA

HYS_EN

High-level input current

I(EN)

= 5 V

linear current amplifier (LCA)

PARAMETER

TEST CONDITIONS

= 0 V

MIN

TYP

MAX

UNIT

High-level output, GATE

Output sink current

−1

−7

SINK

I(ISENS)

= 80 mV, V

O(GATE)

= 5V, Fault mode

100

µA

I(ISENS)

Input current, ISENS

Reference clamp voltage

Input offset voltage

0 V < V

I(ISENS)

< 0.2 V

= open

= 2 V

REF_K

O(IRAMP)

ramp generator

PARAMETER

TEST CONDITIONS

= 0.25 V

MIN

TYP

MAX

UNIT

IRAMP source current, slow turn-on rate

IRAMP source current, normal rate

Low-level output voltage

−850 −600 −400

SRC1

O(IRAMP)

= 1 V, 3 V

−11

−10

−9

µA

SRC2

O(IRAMP)

= 0 V

I(EN)

Voltage gain, relative to ISENS

= 1 V, 3 V

9.5

10.0

10.5 mV/V

O(IRAMP)

overload comparator

PARAMETER

TEST CONDITIONS

MIN

TYP

100

MAX

120

UNIT

µs

Current overload threshold, ISENS

Glitch filter delay time

TH_OL

= 200 mV

DLY

I(ISENS)

fault timer

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

µA

Low-level output voltage

V (EN) = 0 V

Charging current, current limit mode

Fault threshold voltage

= 80 mV, V

= 2 V

−55

−50

4.00

0.38

−45

4.25

0.75

1.5

CHG

I(ISENS)

O(FLTTIME)

FLT

3.75

Discharge current, retry mode

Output duty cycle

TPS2391

= 80 mV, V

µA

DSG

I(ISENS)

Discharge current, timer reset mode

= 2 V,V

I(ISENS)

= 0 V

RST

O(FLTTIME)

NOTES 1: All voltages are with respect to the −VIN terminal unless otherwise stated.

2: Currents are positive into and negative out of the specified terminal.

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

ELECTRICAL CHARACTERISTICS (continued)

= −48 V with respect to RTN, V

(1)(2)

= 2.8 V, V

= 0, all outputs unloaded, T = −40_C to 85_C

I(−VIN)

I(EN)

I(ISENS)

(unless otherwise noted)

FAULT output

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

µA

High-level output (leakage) current

Driver ON resistance

= 0 V,

= 65 V

I(EN)

O(FAULT)

= 80 mV, V

= 1 mA

= 5V,

Ω

DS(ON)

I(ISENS)

O(FLTTIME)

O(FAULT)

NOTES 1: All voltages are with respect to the −VIN terminal unless otherwise stated.

2: Currents are positive into and negative out of the specified terminal.

TERMINAL FUNCTIONS

TERMINAL

NAME

I/O

DESCRIPTION

NO.

I/O

Enable input to turn on/off power to the load.

FAULT

FLTTIME

GATE

IRAMP

ISENS

RTN

Open-drain, active-low indication of a load fault condition.

Connection for user-programming of the fault timeout period.

Gate drive for external N-channel FET.

Programming input for setting the inrush current slew rate.

Current sense input.

Positive supply input for the TPS2390 and TPS2391.

−VIN

Negative supply input and reference pin for the TPS2390 and TPS2391.

DETAILED PIN DESCRIPTIONS

EN: Enable input to turn on/off power to the load. The EN pin is referenced to the −VIN potential of the circuit.

When this input is pulled high (above the nominal 1.4-V threshold) the device enables the GATE output, and

begins the ramp of current to the load. When this input is low, the linear current amplifier (LCA) is disabled, and

a large pull-down device is applied to the FET gate, disabling power to the load.

FAULT: Open-drain, active-low indication of a load fault condition. When the device EN is deasserted, or when

enabled and the load current is less than the programmed limit, this output is high impedance. If the device

remains in current regulation mode at the expiration of the fault timer, or if a fast-acting overload condition

causes greater than 100-mV drop across the sense resistor, the fault is latched, the load is turned off, and the

FAULT pin is pulled low (to −VIN). The TPS2390 remains latched off for a fault, and can be reset by cycling either

the EN pin or power to the device. The TPS2391 retries the load at approximately a 1% duty cycle.

FLTTIME: Connection for user-programming of the fault timeout period. An external capacitor connected from

FLTTIME to −VIN establishes the timeout period to declare a fault condition. This timeout protects against

indefinite current sourcing into a faulted load, and also provides a filter against nuisance trips from momentary

current spikes or surges. The TPS2390 and TPS2391 define a fault condition as voltage at the ISENS pin at

or greater than the 40-mV fault threshold. When a fault condition exists, the timer is active. The devices manage

fault timing by charging the external capacitor to the 4-V fault threshold, then subsequently discharging it to reset

the timer (TPS2390), or discharging it at approximately 1% the charge rate to establish the duty cycle for retrying

the load (TPS2391). Whenever the internal fault latch is set (timer expired), the pass FET is rapidly turned off,

and the FAULT output is asserted.

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DETAILED PIN DESCRIPTIONS (continued)

GATE: Gate drive for external N-channel FET. When enabled, and the input supply is above the UVLO

threshold, the gate drive is enabled and the device begins charging an external capacitor connected to the

IRAMP pin. This pin voltage is used to develop the reference voltage at the non-inverting input of the internal

LCA. The inverting input is connected to the current sense node, ISENS. The LCA acts to slew the pass FET

gate to force the ISENS voltage to track the reference. The reference is internally clamped at 40 mV, so the

maximum current that can be sourced to the load is determined by the sense resistor value as IMAX ≤ 40

mV/R

. Once the load voltage has ramped up to the input dc potential, and current demand drops off, the

SENSE

LCA drives the GATE output to about 14 V to fully enhance the pass FET, completing the low-impedance supply

return path for the load.

IRAMP: Programming input for setting the inrush current slew rate. An external capacitor connected between

this pin and −VIN establishes the load current slew rate whenever power to the load is enabled. The device

charges the external capacitor to establish the reference input to the LCA. The closed-loop control of the LCA

and pass FET acts to maintain the current sense voltage at ISENS at the reference potential. Since the sense

voltage is developed as the drop across a resistor, the charging current ramp rate is set by the voltage ramp

rate at the IRAMP pin. When the output is disabled via the EN input or due to a load fault, the capacitor is

discharged and held low to initialize for the next turn-on.

ISENS: Current sense input. An external low value resistor connected between this pin and −VIN is used to feed

back current magnitude information to the TPS2390/91. There are two internal device thresholds associated

with the voltage at the ISENS pin. During ramp-up of the load’s input capacitance, or during other periods of

excessive demand, the HSPM acts to limit this voltage to 40 mV. Whenever the LCA is in current regulation

mode, the capacitor at FLTTIME is charged to activate the timer. If, when the LCA is driving to its supply rail,

a fast-acting fault such as a short-circuit, causes the ISENS voltage to exceed 100 mV (the overload threshold),

the GATE pin is pulled low rapidly, bypassing the fault timer.

RTN: Positive supply input for the TPS2390/91. For negative voltage systems, the supply pin connects directly

to the return node of the input power bus. Internal regulators step down the input voltage to generate the various

supply levels used by the TPS2390 and TPS2391.

−VIN: Negative supply input and reference pin for the TPS2390/91. This pin connects directly to the input supply

negative rail. The input and output pins and all internal circuitry are referenced to this pin, so it is essentially the

GND or VSS pin of the device.

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

TYPICAL CHARACTERISTICS

LIVE INSERTION EVENT

VIN = −48 V

LIVE INSERTION EVENT

VIN = −80 V

EN (20 V/div.)

(50 V/div.)

DRAIN

(20 V/div.)

DRAIN

Power Applied

= 100 µF

LOAD

= 3900 pF

IRAMP

LOAD

= 0.1 µF

= 50 µF

FLT

(500 mA/div.)

LOAD

(500 mA/div.)

LOAD

t − TIme − 1 ms/div

Figure 1

Figure 2

START-UP FROM ENABLE ASSERTION

LOAD CURRENT RAMP PROFILES

IRAMP (2 V/div.)

EN (5 V/div.)

= .022µF

IRAMP

50 V/div.

(5 V/div.)

DRAIN

IRAMP

= .047 µF

IRAMP

3900 pF

RAMP

(1 A/div.)

LOAD

= 100 µF

LOAD

(500 mA/div.)

= 0.33 µF

FLT

LOAD

EN driven from logic-

= 600 µF

level signal, ref to −VIN

t − TIme − 1 ms/div

t − TIme − 10 ms/div

Figure 3

Figure 4

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

TYPICAL CHARACTERISTICS

TURN-ON INTO SHORTED LOAD

(TPS2391)

TURN-ON INTO SHORTED LOAD

(TPS2390)

(50 V/div.)

DRAIN

(50 V/div.)

DRAIN

FLTTIME (2 V/div.)

(1 A/div.)

LOAD

(1 A/div.)

LOAD

FAULT (20 V/div.)

= 3900 pF

IRAMP

= 0.047 µF

= 3900 pF

IRAMP

= 0.047 µF

FLT

t − TIme − 1 ms/div

Figure 5

Figure 6

FAULT RETRY OPERATION

(TPS2391)

RECOVERY FROM A FAULT − LARGE SCALE VIEW

(TPS2391)

FAULT (50 V/div.)

FLTTIME (2 V/div.)

DRAIN

(20 V/div.)

FLTTIME (2 V/div.)

(20 V/div.)

DRAIN

= 3900 pF

IRAMP

= 0.047 µF

= 100 µF

I (1 A/div.)

LOAD

FLT

= 3900 pF

IRAMP

LOAD

= 0.047 µF

= 100 µF

= 12.5 Ω

FLT

LOAD

(1 A/div.)

LOAD

t − TIme − 50 ms/div

Figure 7

Figure 8

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

AMBIENT TEMPERATURE

RECOVERY FROM A FAULT − EXPANDED VIEW

(TPS2391)

1200

1000

FAULT (50 V/div)

RTN

= 80 V

800

600

400

FLTTIME (2 V/div.)

(20 V/div)

DRAIN

RTN

= 40 V

RTN

= 36 V

= 3900 pF

IRAMP

= 0.047 µF

= 100 µF

FLT

200

LOAD

(1 A/div)

LOAD

−40

−15

t − TIme − 1 ms/div

− Ambient Temperature − °C

Figure 9

Figure 10

IRAMP OUTPUT CURRENT

AMBIENT TEMPERATURE, SLOW TURN-ON

GATE HIGH-LEVEL OUTPUT

AMBIENT TEMPERATURE

−0.50

−0.54

−0.58

−0.62

−066

17.0

16.5

= 0 V

I(ISENS)

= 80 V

RTN

= 80 V

RTN

16.0

15.5

15.0

= 48 V

RTN

= 48 V

RTN

= 36 V

14.5

14.0

= 36 V

= 0.25 V

RTN

O(IRAMP)

−15

−40

−15

− Ambient Temperature − °C

Figure 11

Figure 12

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TYPICAL CHARACTERISTICS

IRAMP OUTPUT CURRENT

TIMER CHARGING CURRENT

AMBIENT TEMPERATURE

AMBIENT TEMPERATURE, NORMAL RATE

−9.5

−9.7

−45

−47

−49

−51

−53

−55

= 80 mV

Average for V

O(IRAMP)

RTN

= 1 V, 3 V

I(ISENS)

=2V

= 36 V to 80 V

O(FLTTIME)

= 80 V

RTN

−9.9

−10.1

−10.3

−10.5

RTN

= 36 V

RTN

= 48 V

−40

−15

−40

−15

− Ambient Temperature − °C

Figure 13

Figure 14

FLTTIME DISCHARGE CURRENT

FAULT LATCH THRESHOLD

AMBIENT TEMPERATURE (TPS2391)

AMBIENT TEMPERATURE

4.25

4.13

4.00

3.88

3.75

0.50

0.47

0.44

0.41

0.38

0.35

0.32

0.29

0.26

RTN

= 48 V

= 80 mV

I(ISENS)

= 2 V

= 36 V to 80 V

O(FLTTIME)

RTN

−40

−15

−40

−15

− Ambient Temperature − °C

Figure 15

Figure 16

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

APPLICATION INFORMATION

When a plug-in module or printed circuit card is inserted into a live chassis slot, discharged supply bulk

capacitance on the board can draw huge transient currents from the system supplies. Without some form of

inrush limiting, these currents can reach peak magnitudes ranging up to several hundred amps, particularly in

high-voltage systems. Such large transients can damage connector pins, PCB etch, and plug-in and supply

components. In addition, current spikes can cause voltage droops on the power distribution bus, causing other

boards in the system to reset.

The TPS2390 and TPS2391 are hot swap power managers designed to limit these peaks to preset levels, as

well as control the slew rate (di/dt) at which charging current ramps to the programmed limit. These devices use

an external N-Channel pass FET and sense element to provide closed-loop control of current sourced to the

load. Input supply undervoltage lockout (UVLO) protection allows hot swap circuits to turn on automatically with

the application of power, or to be controlled with a system command via the EN input. External capacitors control

both the current ramp rate, and the time−out period for load voltage ramping. In addition, an internal overload

comparator provides circuit breaker protection against shorts occurring during steady-state (post-turn-on)

operation of the card.

The TPS2390 and TPS2391 operate directly from the input supply (nominal −48 VDC rail). The −VIN pin

connects to the negative voltage rail, and the RTN pin connects to the supply return. Internal regulators convert

input power to the supply levels required by the device circuitry. An input UVLO circuit holds the GATE output

low until the supply voltage reaches a nominal 30-V level. A second comparator monitors the EN input; this pin

must be pulled above the 1.4-V enable threshold to turn on power to the load.

Once enabled, and when the input supply is above the UVLO threshold, the GATE pull-down is removed, the

linear control amplifier (LCA) is enabled, and a large discharge device in the RAMP CONTROL block is turned

off. Subsequently, a small current source is now able to charge an external capacitor connected to the IRAMP

pin. This results in a linear voltage ramp at IRAMP. The voltage ramp on the capacitor actually has two discrete

slopes. As shown in Figure 17, charging current is supplied from either of two sources. Initially at turn-on, the

600-nA source is selected, to provide a slow turn-on rate. This slow turn-on helps ensure that the LCA is pulled

out of saturation, and is slewing to the voltage at its non-inverting input before normal rate load charging is

allowed. This mechanism helps reduce current steps at turn-on. Once the voltage at the IRAMP pin reaches

approximately 0.5 V, an internal comparator deasserts the SLOW signal, and the 10-µA source is selected for

the remainder of the ramp period.

The voltage at IRAMP is divided down by a factor of 100, and applied to the non-inverting input of the LCA. Load

current magnitude information at the ISENS pin is applied to the inverting input. This voltage is developed by

connecting the current sense resistor between ISENS and −VIN. The LCA slews the gate of the external pass

FET to force the ISENS voltage to track the divided down IRAMP voltage. Consequently, the load current slew

rate tracks the linear voltage ramp at the IRAMP pin, producing a linear di/dt of the load current. The IRAMP

capacitor is charged to about 6.5 V; however, the LCA input is clamped at 40 mV. Therefore, the current sourced

to the load during turn-on is limited to a value given by IMAX ≤ 40 mV/R

the sense resistor.

, where R

is the value of

SENSE

The resultant load current, regulated by the controller, charges the module’s input bulk capacitance in a safe

fashion. Under normal conditions, this capacitance eventually charges up to the dc input potential. At this point,

the load demand drops off, and the voltage at ISENS decreases. The LCA now drives the GATE output to its

supply rail. The 14-V typical output level ensures sufficient overdrive to fully enhance the external FET, while

not exceeding the typical 20-V V

rating of common N-Channel power FETs.

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

APPLICATION INFORMATION

600 nA

VDD

SLOW

LCA

GATE

IRAMP

RAMP

CONTROL

40mV

ISENS

EN_A

1.4V

100mV

OVERLOAD

COMP

FLTTIME

RTN

FAULT

0.4

0.5V

30 V

DCHG

RETRY

VDD

FAULT

LOGIC

TIMER

BLOCK

14V

’91 ONLY

−VIN

UDG−02091

Figure 17. Block Diagram

Fault timing is accomplished by connecting a capacitor between the FLTTIME and −VIN pins, allowing

user-programming of the timeout period. Whenever the hot swap controller is in current control mode as

described above, the LCA asserts an overcurrent indication (OC in the Figure 17 diagram). Overcurrent fault

timing is inhibited during the slow turn-on portion of the IRAMP waveform. However, once the device transitions

to the normal rate current ramp (V (IRAMP) ≥ 0.5 V), the external capacitor is charged by a 50-µA source,

generating a voltage ramp at the FLTTIME pin. If this voltage reaches the 4-V fault threshold, the fault is latched,

and the open-drain driver is turned on to assert the external FAULT output. Fault capacitor charging ceases,

and the capacitor is now discharged. In addition, latching of a fault condition causes rapid discharge of the

IRAMP capacitor. In this manner, the soft-start function is now reset and ready for the next output enable, if and

when conditions permit.

The TPS2390 latches off in response to faults; once a fault timeout occurs, the discharge signal (DCHG) turns

on a large NMOS device to rapidly discharge the external capacitor, resetting the timer for any subsequent

device reset. The TPS2390 can only be reset by cycling power to the device, or by cycling the EN input.

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APPLICATION INFORMATION

In response to a latched fault condition, the TPS2391 enters a fault retry mode, wherein it periodically retries

the load to test for continued existence of the fault. In this mode, the FLTTIME capacitor is discharged slowly

by a about a 0.4-µA constant-current sink. When the voltage at the FLTTIME pin decays below 0.5 V, the LCA

and RAMP CONTROL circuits are re-enabled, and a normal turn-on current ramp ensues. Again, during the

load charging, the OC signal causes charging of the FLTTIME capacitor until the next delay period elapses. The

sequential charging and discharging of the FLTTIME capacitor results in a typical 1% retry duty cycle. If the fault

subsides (GATE pin drives to high-level output), the timing capacitor is rapidly discharged, duty-cycle operation

stops, and the fault latch is reset.

Note that because of the timing inhibit during the initial slow ramp period, the duty cycle in practice is slightly

greater than the nominal 1% value. However, sourced current during this period peaks at only about one-eighth

the maximum limit. The duty cycle of the normal ramp and constant-current periods is approximately 1%.

The FAULT LOGIC within the TIMER BLOCK automatically manages capacitor charge and discharge rates

(DCHG signal), and the enabling of the GATE output (ON signal). For the TPS2391, the FAULT output remains

asserted continuously during retry mode; it is only released if the fault condition clears.

These hot swap controllers contain an OVERLOAD COMPARATOR which also monitors the ISENS voltage.

If sense voltage excursions above 100 mV are detected, the fault is latched, LCA disabled, and the FET gate

is rapidly pulled down, bypassing the fault timer. The timer block does apply a 4-µs deglitch filter to the OL signal

to help reduce nuisance trips. As with overcurrent faults, the TPS2390 latches the output off. For the TPS2391,

an overload fault causes charging of the timer capacitor, to initiate fault retry timing.

setting the sense resistor value

Due to the current-limiting action of the internal LCA, the maximum allowable load current for an implementation

is easily programmed by selecting the appropriate sense resistor value. The LCA acts to limit the sense voltage

V (ISENS) to its internal reference. Once the voltage at the IRAMP pin exceeds approximately 4 V, this limit is

the clamp voltage, V

. Therefore, a maximum sense resistor value can be determined from equation (1).

REF_K

33 mV

IMAX

SENSE

(1)

where:

• R

is the resistor value, and

SENSE

• IMAX is the desired current limit.

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

APPLICATION INFORMATION

When setting the sense resistor value, it is important to consider two factors, the minimum current that may be

imposed by the TPS2390 or TPS2391, and the maximum load under normal operation of the module. For the

first factor, the specification minimum clamp value is used, as seen in equation (1). This method accounts for

the tolerance in the sourced current limit below the typical level expected (40 mV/R

). (The clamp

SENSE

measurement includes LCA input offset voltage; therefore, this offset does not have to be factored into the

current limit again.) Second, if the load current varies over a range of values under normal operating conditions,

then the maximum load level must be allowed for by the value of R

. One example of this is when the load

SENSE

is a switching converter, or brick, which draws higher input current, for a given power output, when the

distribution bus is at the low end of its operating range, with decreasing draw at higher supply voltages. To avoid

current-limit operation under normal loading, some margin should be designed in between this maximum

anticipated load and the minimum current limit level, or IMAX > I

, for equation (1).

LOAD(max)

For example, using a 20-mΩ sense resistor for a nominal 1-A load application provides a minimum of 650 mA

of overhead for load variance/margin. Typical bulk capacitor charging current during turn-on is 2 A

(40 mV/20 mΩ).

setting the inrush slew rate

The TPS2390 and TPS2391 devices enable user-programming of the maximum current slew rate during load

start-up events. A capacitor tied to the IRAMP pin (C2 in the typical application diagram) controls the di/dt rate.

Once the sense resistor value has been established, a value for ramp capacitor C

determined from equation (2).

, in microfarads, can be

IRAMP

ǒ Ǔ

100 R

SENSE

MAX

(2)

where:

• R

• (di/dt)

is in ohms, and

SENSE

is the desired maximum slew rate, in amps/second.

MAX

For example, if the desired slew rate for the typical application shown is 1500 mA/ms, the calculated value for

is about 3700 pF. Selecting the next larger standard value of 3900 pF (as shown in the diagram) provides

IRAMP

some margin for capacitor and sense resistor tolerances.

As described earlier in this section, the TPS2390 and TPS2391 initiate ramp capacitor charging, and

consequently, load current di/dt at a reduced rate. This reduced rate applies until the voltage on the IRAMP pin

is about 0.5 V. The maximum di/dt rate, as set by equation (2), is effective once the device has switched to the

10-µA charging source.

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

APPLICATION INFORMATION

setting the fault timing capacitor

The fault timeout period is established by the value of the capacitor connected to the FLTTIME pin, C . The

FLT

timeout period permits riding out spurious current glitches and surges that may occur during operation of the

system, and prevents indefinite sourcing into faulted loads swapped into a live system. However, to ensure

smooth voltage ramping under all conditions of load capacitance and input supply potential, the minimum

timeout should be set to accommodate these system variables. To do this, a rough estimate of the maximum

voltage ramp time for a completely discharged plug-in card provides a good basis for setting the minimum timer

delay.

Due to the three-phase nature of the load current at turn-on, the load voltage ramp potentially has three distinct

phases ( compare Figures 1 and 2). This profile depends on the relative values of load capacitance, input dc

potential, maximum current limit and other factors. The first two phases are characterized by the two different

slopes of the current ramp; the third phase, if required for bulk capacitance charging, is the constant-current

charging at IMAX. Considering the two current ramp phases to be one period at an average di/dt simplifies

calculation of the required timing capacitor.

For the TPS2390 and TPS2391, the typical duration of the soft-start ramp period, t , is given by equation (3).

+ 1183 C

IRAMP

(3)

where:

• t is the soft-start period in ms, and

• C

is given in µF

IRAMP

During this current ramp period, the load voltage magnitude which is attained is estimated by equation (4).

AVG

100 R

ǒ_tǓ

LSS

2 C C

IRAMP

SENSE

(4)

where:

is the load voltage reached during soft-start,

LSS

is 3.38 µA for the TPS2390 and TPS2391,

• C is the amount of the load capacitance, and

• t is the soft-start period, in seconds

The quantity i

in equation (4) is a weighted average of the two charge currents applied to C

during

AVG

IRAMP

turn-on, considering the typical output values.

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SLUS471D − JUNE 2002 − REVISED JANUARY 2008

APPLICATION INFORMATION

If the result of equation (4) is larger than the maximum input supply value, then the load can be expected to

charge completely during the inrush slewing portion of the insertion event. However, if this voltage is less than

the maximum supply input, V

remaining amount of time required at IMAX is determined from equation (5).

, the HSPM transitions to the constant-current charging of the load. The

IN(max)

_Cǒ_V

* V

IN (max)

LSS

REF_K (min)

ǒ Ǔ

SENSE

(5)

where:

• t is the constant-current voltage ramp time, in seconds, and

• V

is the minimum clamp voltage, 33 mV.

REF_K(min)

With this information, the minimum recommended value timing capacitor C

time needed is either t or the sum of t and t , according to the estimated time to charge the load. Since

fault timing is generated by the constant-current charging of C , the capacitor value is determined by equation

(6) or (7).

can be determined. The delay

FLT

55 t

3.75

(

)

MIN +

FLT

(6)

(7)

₅₅ǒ_tSS

) t

)

MIN +

3.75

where:

• C

is the recommended capacitor value, in microfarads,

FLT(min)

• t is the result of equation (3), in seconds, and

• t is the result of equation (5), in seconds.

For the typical application example, with the 100-µF filter capacitor in front of the dc-to-dc converter, equations

(3) and (4) estimate the load voltage ramping to −46 V during the soft-start period. If the module should operate

down to −72-V input supply, approximately another 1.58 ms of constant-current charging may be required.

Therefore, equation 7 is used to determine C

, and the result is approximately 0.1 µF.

FLT(min)

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PACKAGE OPTION ADDENDUM

www.ti.com

18-Oct-2013

PACKAGING INFORMATION

Orderable Device

TPS2390DGK

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

VSSOP

DGK

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

Level-2-260C-1 YEAR

2390

2391

TPS2390DGKG4

TPS2390DGKR

TPS2390DGKRG4

TPS2391DGK

ACTIVE

DGK

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU NIPDAUAG

Green (RoHS

& no Sb/Br)

TPS2391DGKG4

TPS2391DGKR

TPS2391DGKRG4

Green (RoHS

& no Sb/Br)

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Oct-2013

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Aug-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS2390DGKR

TPS2391DGKR

VSSOP

DGK

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Aug-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS2390DGKR

TPS2391DGKR

VSSOP

DGK

2500

366.0

364.0

50.0

Pack Materials-Page 2

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TPS2901 [TI]

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