TPS3430WDRCR_技术文档

TPS3430

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

具有可编程复位延迟功能的 TPS3430 窗口看门狗计时器

1 特性

3 说明

•

出厂编程的精密看门狗计时器：

TPS3430 是一款具有可编程看门狗窗口和可编程看

门狗复位延迟的独立窗口看门狗计时器，适用于各种应

用。TPS3430 窗口看门狗可实现 2.5% 的计时精度

（25°C 时的典型值），而且可通过出厂编程的默认延

迟设置来设置看门狗输出 (WDO) 复位延迟，或通过外

部电容器进行编程。在开发过程中或上电期间，可以通

过 SET 引脚将监视器禁用，从而避免出现不必要的监

视器超时。

– 可在 25°C 下实现 ±2.5% 的看门狗超时和看门狗

复位延迟精度（典型值）

看门狗禁用功能

•

用户可编程看门狗超时

用户可编程看门狗复位延迟

输入电压范围：VDD = 1.6V 至 6.5V

低电源电流：I_DD= 10µA（典型值）

开漏输出

TPS3430 采用小型 3.00mm ×

3.00mm 10 引脚 VSON 封装。

小型 3mm × 3mm 10 引脚 VSON 封装

工作结温范围：

–40°C 至 +125°C

器件信息

器件型号

TPS3430

封装 ⁽¹⁾

封装尺寸（标称值）

2 应用

VSON (10)

3.00mm × 3.00mm

•

智能显示屏

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

电池组：电动自行车/电动踏板车/轻型电动车辆

(LEV)

附录。

•

断路器（ACB、MCCB、VCB）

电动自行车/脚踏电动自行车

交流充电（桩）站

多功能继电器

视觉计算机

10

3.3V

Lower Boundary (t_WDL

Upper Boundary (t_WDL

)

7.5

5

TPS3430

VDD2

V_CORE

2.5

0

VDD1

NC

Microcontroller

SET1

SET0

CRST

CWD

-2.5

-5

NMI

GPIO

WDO

NC

WDI

-7.5

-10

GND

-50

-25

0

25

50

75

100

125

Temperature (èC)

TPS3

工作温度范围内的标准化监视器超时精度（SET0 = 1，

SET1 = 1，CWD = NC）

窗口监视器计时器电路

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS366

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

Table of Contents

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Timing Requirements..................................................6

6.7 Timing Diagrams ........................................................7

6.8 Typical Characteristics................................................9

7 Detailed Description......................................................10

7.1 Overview...................................................................10

7.2 Functional Block Diagrams....................................... 10

7.3 Feature Description...................................................10

7.4 Device Functional Modes..........................................15

8 Application and Implementation..................................16

8.1 Application Information............................................. 16

8.2 Typical Applications.................................................. 19

9 Power Supply Recommendations................................26

10 Layout...........................................................................27

10.1 Layout Guidelines................................................... 27

10.2 Layout Example...................................................... 27

11 Device and Documentation Support..........................28

11.1 Device Support........................................................28

11.2 Documentation Support.......................................... 28

11.3 接收文档更新通知................................................... 28

11.4 支持资源..................................................................28

11.5 Trademarks............................................................. 28

11.6 Electrostatic Discharge Caution..............................28

11.7 术语表..................................................................... 28

12 Mechanical, Packaging, and Orderable

Information.................................................................... 28

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (July 2018) to Revision A (October 2021)

Page

•

更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

删除了“可在工作温度范围内实现 ±15% 的监视器超时和监视器复位延迟精度”.................................................. 1

删除了“15% 计时精度（–40°C 至 +125°C”.........................................................................................................1

Updated ESD Ratings.........................................................................................................................................4

Updated I_CWDmin and max spec........................................................................................................................5

Updated V_CWDmin and max spec...................................................................................................................... 5

Added a footnote to for t_INIT............................................................................................................................... 6

Changed minimum and maximum specifications of 2nd, 5th, 6th, and 8th rows of t_WDLparameter ................. 6

Changed minimum and maximum specifications of 2nd and last rows of t_WDUparameter ............................... 6

Updated WDO delay time values for various capacitors in Watchdog Reset Delay Time for Common Ideal

Capacitor Values table......................................................................................................................................16

Changed minimum and maximum specifications for NC SETx 01 setting for both upper and lower watchdog

boundaries, 10 kΩ to VDD SETx 00 and 01 settings for lower watchdog boundary, and 10 kΩ to VDD SETx

11 setting for both upper and lower watchdog boundaries in Factory-Programmed Watchdog Timing table...18

Updated t_WDUmin and max values for all capacitors........................................................................................18

Updated t_WDUmin and max boundry values from 0.85 and 1.15 to 0.905 and 1.095 respectively...................18

•

2

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

5 Pin Configuration and Functions

VDD1

CWD

SET0

CRST

GND

1

2

3

4

5

10

9

VDD2

NC

Thermal

Pad

8

WDO

WDI

7

6

SET1

Not to scale

图 5-1. DRC Package

3-mm × 3-mm VSON-10

Top View

表 5-1. Pin Functions

I/O

DESCRIPTION

NAME

VDD1

NO.

1

I

Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended.

Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin

and ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected

(NC) further enables the selection of the preset watchdog timeouts; see the 节 6.6 table.

When using a capacitor, the TPS3430 determines the window watchdog upper boundary with 方程式 4. The

lower watchdog boundary is set by the SET pins, see and 表 8-5 the 节 8.1.2 section for additional information.

CWD

2

I

Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog;

see the 节 6.6 table.

SET0

CRST

3

4

I

Programmable watchdog reset delay pin. Connect a capacitor between this pin and GND to program the

watchdog reset delay period. This pin can also be connected by a 10-kΩ pull-up resistor to VDD, or left

unconnected (NC) for various factory programmed watchdog reset delay options; see the 节 8.1.1 section.

When using an external capacitor, use 方程式 1 to determine the watchdog reset delay.

GND

5

6

—

I

Ground pin

Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog;

see the 节 6.6 table.

SET1

Watchdog input. A falling transition (edge) must occur at this pin within the watchdog timeout between the

lower (t_WDL(max)) and upper (t_WDU(min)) window boundaries in order for WDO to not assert. During power up, all

pulses to WDI are ignored before t_RSTexpires and the watchdog is disabled.

When the watchdog is not in use, the SET pins can be used to disable the watchdog. The input at WDI is

ignored when WDO is low (asserted) and also when the watchdog is disabled. If the watchdog is disabled,

then WDI cannot be left unconnected and must be driven to either VDD or GND.

WDI

7

8

I

Watchdog open-drain active-low output. Connect WDO with a 1-kΩ to 100-kΩ resistor to VDD or another

power supply. WDO goes low (asserts) when a watchdog timeout occurs. When a watchdog timeout occurs,

WDO goes low (asserts) for the set WDO reset delay (t_RST). When the watchdog is disabled, WDO remains

logic high regardless of WDI.

WDO

O

NC

9

NC This pin is no-connect and must be left floating.

Connect this pin to VDD1. The device will not function properly if VDD1 and VDD2 are not externally

connected.

VDD2

10

I

Thermal pad

—

Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

Submit Document Feedback

3

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

V

Supply voltage range

Output voltage range

VDD1, VDD2

WDO

7

V

SET0, SET1, WDI,

CWD, CRST

WDO

7

VDD + 0.3⁽³⁾

±20

Voltage ranges

V

Output pin current

mA

Input current (all pins)

±20

Continuous total power dissipation

See 节 6.4

(2)

Operating junction, T_J

–40

–65

150

(2)

Temperature

Operating free-air temperature, T_A

Storage, T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) T_J= T_Aas a result of the low dissipated power in this device.

(3) The absolute maximum rating is V_DD+ 0.3 V or 7.0 V, whichever is smaller.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC

JS-001⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC

specification JESD22-C101⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.6

0

NOM

MAX

6.5

UNIT

V

VDD1, VDD2 Supply pin voltage

V_SET0

V_SET1

C_CRST

R_CRST

C_CWD

CWD

R_PU

SET0 pin voltage

6.5

V

SET1 pin voltage

0

6.5

V

WD reset delay capacitor

Pull-up resistor to VDD

Watchdog timing capacitor

Pull-up resistor to VDD

Pull-up resistor, WDO

Watchdog output current

Junction Temperature

0.1⁽¹⁾

1000⁽¹⁾

nF

kΩ

nF

kΩ

mA

°C

9

10

11

0.1⁽²⁾

9

1000⁽²⁾

11

10

1

100

10

I_WDO

T_J

–40

125

(1) Using a C_CRSTcapacitor of 0.1 nF or 1000 nF gives a reset delay of 703 µs or 3.22 seconds, respectively.

(2) Using a C_CWDcapacitor of 0.1 nF or 1000 nF gives a t_WDU(typ)of 62.74 ms or 77.45 seconds, respectively.

4

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

6.4 Thermal Information

TPS3430

THERMAL METRIC⁽¹⁾

DRC (VSON)

10 PINS

50.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

50.6

25.4

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.2

ψ_JB

25.5

R_θJC(bot)

7.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

at 1.6 V ≤ V_DD≤ 6.5 V over the operating temperature range of –40°C ≤ T_J≤ +125°C (unless otherwise noted); typical values

are at T_J= 25°C

PARAMETER

GENERAL CHARACTERISTICS

VDD1,VDD2

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply voltage

1.6

6.5

V

(1) (3)

I_DD

Supply current

10

19

0.8

µA

V

(2)

V_POR

I_CRST

V_CRST

Power-on reset voltage

CRST pin charge current

CRST pin threshold voltage

V_OL(MAX)= 0.25 V

CRST = 0.5 V

337

375

413

nA

V

1.192

1.21

1.228

WINDOW WATCHDOG FUNCTION

I_CWD

V_CWD

V_OL

CWD pin charge current

CWD = 0.5 V

347

375

403

1.224

0.4

nA

V

CWD pin threshold voltage

WDO output low

1.196

1.21

VDD = 5 V, I_SINK= 3 mA

V

I_D

WDO output leakage current

Low-level input voltage (SET0, SET1)

High-level input voltage (SET0, SET1)

WDO output low

VDD = 1.6 V, V_WDO= 6.5 V

1

µA

V

V_IL

0.25

V_IH

0.8

V

V_IL(WDI)

V_IH(WDI)

0.3 × V_DD

V

WDO output leakage current

0.8 × V_DD

V

(1) When V_DDfalls below V_UVLO, WDI is ignored

(2) When V_DDfalls below V_POR, WDO is undefined.

(3) During power-on, V_DDmust be a minimum 1.6 V for at least 300 µs.

Submit Document Feedback

5

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

6.6 Timing Requirements

at 1.6 V ≤ V_DD≤ 6.5 V over the operating temperature range of –40°C ≤ T_A, T_J≤ +125°C (unless otherwise noted); the

open-drain pullup resistors are 10 kΩ for each output; typical values are at T_J= 25°C

MIN

TYP

MAX

UNIT

GENERAL

t_INIT

CWD, CRST pin evaluation period⁽¹⁾

Time required between changing SET0 and SET1 pins

SET0, SET1 pin setup time

381

500

1

µs

t_SET

Startup delay ⁽³⁾

300

DELAY FUNCTION

CRST = NC

170

8.5

200

10

230

ms

t_RST

Watchdog reset delay

CRST = 10 kΩ to VDD

11.5

WINDOW WATCHDOG FUNCTION

CWD = programmable, SET0 = 0, SET1 = 0⁽²⁾

CWD = programmable, SET0 = 1, SET1 = 1⁽²⁾

CWD = programmable, SET0 = 0, SET1 = 1^{(2) (4)}

CWD = NC, SET0 = 0, SET1 = 0

1/8

1/2

Window watchdog ratio of

WD ratio lower boundary to upper

boundary

3/4

19.1

1.48

22.5

1.85

25.9

2.22

ms

CWD = NC, SET0 = 0, SET1 = 1

CWD = NC, SET0 = 1, SET1 = 0

Watchdog disabled

CWD = NC, SET0 = 1, SET1 = 1

680

7.65

800

9.0

920

10.35

ms

Window watchdog lower

boundary

t_WDL

CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 0

CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 1

CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 0

CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 1

CWD = NC, SET0 = 0, SET1 = 0

Watchdog disabled

1.48

46.8

1.85

55.0

27.5

2.22

63.3

ms

CWD = NC, SET0 = 0, SET1 = 1

23.375

31.625

CWD = NC, SET0 = 1, SET1 = 0

Watchdog disabled

CWD = NC, SET0 = 1, SET1 = 1

1360

92.7

1600

109.0

195.0

1840

125.4

224.3

ms

Window watchdog upper

boundary

t_WDU

CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 0

CWD = 10 kΩ to VDD, SET0 = 0, SET1 = 1

CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 0

CWD = 10 kΩ to VDD, SET0 = 1, SET1 = 1

165.8

Watchdog disabled

9.35

11.0

150

50

12.65

ms

µs

ns

t_WD-setupSetup time required for device to respond to changes on WDI after being enabled

Minimum WDI pulse duration

t_WD-del

WDI to WDO delay

50

(1) Refer to 节 8.1.2.2

(2) 0 refers to VSET ≤ VIL, 1 refers to VSET ≥ VIH.

(3) During power-on, VDD must be a minimum 1.6 V for at least 300 µs

(4) If this watchdog ratio is used, then tWDL(max) can overlap tWDU(min).

6

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

6.7 Timing Diagrams

(1)

VDD1 = VDD2

t_WDL< t < t_WDU

t < t_WDU

WDI

X

t < t_WDL

WDO

t_RST

A. See 图 6-2 for WDI timing requirements.

图 6-1. Timing Diagram

WDI

Early Fault

WDO

Correct Operation

WDI

WDO

Late Fault

WDI

WDO

Valid

Window

Timing

t_WDL(min)

t_WDL(typ)

t_WDL(max)

t_WDU(min)

t_WDU(typ)

t_WDU(max)

= Tolerance Window

图 6-2. TPS3430 Window Watchdog Timing

Submit Document Feedback

7

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

VDD1 = VDD2

SET0

t_SET

t_WD-setup

SET1

RATIO

1:8

1:2

Disabled

图 6-3. Changing SET0 and SET1 Pins

8

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

6.8 Typical Characteristics

all curves are taken at T_A= 25°C with 1.6 V ≤ V_DD≤ 6.5 V (unless otherwise noted)

380

376

372

368

364

16

12

8

-40èC

0èC

25èC

105èC

125èC

4

1.6 V

6.5 V

0

-50

-25

0

25

50

75

100

125

0

1

2

3

4

5

6

7

Temperature (èC)

VDD (V)

图 6-4. CWD Charging Current vs Temperature

图 6-5. Supply Current vs Power-Supply Voltage

10

Lower Boundary (t_WDL

Upper Boundary (t_WDL

)

Lower Boundary (t_WDL

Upper Boundary (t_WDL

)

7.5

5

7.5

5

2.5

0

2.5

0

-2.5

-5

-2.5

-5

-7.5

-10

-7.5

-10

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

TPS3

图 6-6. Normalized Watchdog Timeout Accuracy

Over Temperature (SET0 = 1, SET1 = 1, CWD = NC)

图 6-7. Normalized Watchdog Timeout Accuracy

Over Temperature (SET0 = 1, SET1 = 1, CWD =

10kΩ to VDD)

Submit Document Feedback

9

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

7 Detailed Description

7.1 Overview

The TPS3430 is a high-accuracy programmable window watchdog timer with watchdog disable feature that

achieves 15% watchdog timing accuracy over the specified temperature range of –40°C to +125°C.

7.2 Functional Block Diagrams

(1)

VDD1

(1)

Precision

Clock

VDD2

VDD

WDO

State

Machine

Cap

Control

CWD

VDD

Cap

Control

CRST

WDI SET0 SET1

GND

A. VDD1 and VDD2 are not internally connected and must be connected externally for the device to function.

图 7-1. TPS3430 Block Diagram

7.3 Feature Description

7.3.1 CRST

The CRST pin provides the user the functionality of both high-precision, factory-programmed watchdog reset

delay timing options and user-programmable watchdog reset delay timing. The CRST pin can be pulled up to

VDD through a resistor, have an external capacitor to ground, or can be left unconnected. The configuration

of the CRST pin is re-evaluated by the device every time the voltage on VDD comes up. The pin evaluation

is controlled by an internal state machine that determines which option is connected to the CRST pin. The

sequence of events takes 381 μs (t_INIT) to determine if the CRST pin is left unconnected, pulled up through a

resistor, or connected to a capacitor. If the CRST pin is being pulled up to VDD, then a

10-kΩ pull-up resistor is required.

7.3.2 Window Watchdog

7.3.2.1 SET0 and SET1

When changing the SET0 or SET1 pins, there are two cases to consider: enabling and disabling the watchdog,

and changing the SET0 or SET1 pins when the watchdog is enabled. In case 1 where the watchdog is being

enabled or disabled, the changes take effect immediately. However, in case 2, a WDO fault event must occur in

order for the changes to take place.

10

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

7.3.2.1.1 Enabling the Window Watchdog

The TPS3430 features the ability to enable and disable the watchdog timer. This feature allows the user to start

with the watchdog timer disabled and then enable the watchdog timer using the SET0 and SET1 pins. The

ability to enable and disable the watchdog is useful to avoid undesired watchdog trips during initialization and

shutdown. When the SETx pins are changed to disable the watchdog timer, changes on the pins are responded

to immediately (as shown in 图 7-2). When the watchdog goes from disabled to enabled, there is a 150 μs

(t_WD-setup) transition period where the device does not respond to changes on WDI. After this 150-μs period, the

device begins to respond to changes on WDI again.

VDD1 = VDD2

SET0

t_WD-setup

SET1

RATIO

1:8

Disabled

1:8

图 7-2. Enabling the Watchdog Timer

7.3.2.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor

When using the TPS3430 with fixed timing options, if the watchdog is disabled and reenabled while WDO is

asserted (logic low) the watchdog performs as described in the 节 7.3.2.1.1 section. However, if there is a

capacitor on the CRST pin, and the watchdog is disabled and reenabled when WDO is asserted (logic low), then

the watchdog behaves as shown in 图 7-3. When the watchdog is disabled, WDO goes high impedance (logic

high). However, when the watchdog is enabled again, the t_RSTperiod must expire before the watchdog resumes

normal operation.

VDD1 = VDD2

t_WDU

WDO

t_RST

Disabling and

Enabling

watchdog

SET1

SET0

There is no WDI signal in this figure, WDI is always at GND.

图 7-3. Enabling and Disabling the Watchdog Timer During a WDO Reset Event

Submit Document Feedback

11

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

7.3.2.1.3 SET0 and SET1 During Normal Watchdog Operation

The SET0 and SET1 pins can be used to control the window watchdog ratio of the lower boundary to the upper

boundary. There are four possible modes for the watchdog (see 表 8-5 ): disabled, 1:8 ratio, 3:4 ratio, and 1:2

ratio. If SET0 = 1 and SET1 = 0, then the watchdog is disabled. When the watchdog is disabled WDO does

not assert, and the TPS3430 ignores all inputs to WDI. The SET0 and SET1 pins can be changed when the

device is operational, but cannot be changed at the same time. If these pins are changed when the device is

operational, then there must be a 500-µs (t_SET) delay between switching the two pins. If the SET0 and SET1 are

used to change the reset timing, then a reset event must occur before the new timing condition is latched. This

reset can be triggered by bringing VDD below V_UVLO. 图 7-4 shows how the SET0 and SET1 pins do not change

the watchdog timing option until a reset event has occurred.

VDD 1 = VDD 2

SET0

t_SET

SET1

RATIO

1:2

1:8

图 7-4. Changing SET0 and SET1 Pins

12

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

7.3.3 Window Watchdog Timer

This section provides information for the window watchdog modes of operation. A window watchdog is typically

employed in safety critical applications where a traditional watchdog timer is inadequate. In a traditional

watchdog, there is a maximum time in which a pulse must be issued to prevent the reset from occurring.

However, in a window watchdog the pulse must be issued between a maximum lower window time (t_WDL(max)

)

and the minimum upper window time (t_WDU(min)) set by the CWD pin and the SET0 and SET1 pins. 表 8-5

describes how t_WDUcan be used to calculate the timing of t_WDL. The t_WDLtiming can also be changed by

adjusting the SET0 and SET1 pins. 图 7-5 shows the valid region for a WDI pulse to be issued to prevent the

WDO from being triggered and being pulled low.

WDI

Early Fault

WDO

Correct Operation

WDI

WDO

Late Fault

WDI

WDO

Valid

Window

Timing

t_WDL(min)

t_WDL(typ)

t_WDL(max)

t_WDU(min)

t_WDU(typ)

t_WDU(max)

= Tolerance Window

图 7-5. TPS3430 Window Watchdog Timing

Submit Document Feedback

13

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

7.3.3.1 CWD

The CWD pin provides the user the functionality of both high-precision, factory-programmed watchdog timeout

options and user-programmable watchdog timeout. The TPS3430 features three options for setting the watchdog

window: connecting a capacitor to the CWD pin, connecting CWD to a pull-up resistor to VDD, and leaving the

CWD pin unconnected. The configuration of the CWD pin is evaluated by the device every time the voltage on

VDD rises above V_{DD (min)}. The pin evaluation is controlled by an internal state machine that determines which

option is connected to the CWD pin. The sequence of events takes 381 μs (t_INIT) to determine if the CWD pin is

left unconnected, pulled up through a resistor, or connected to a capacitor. If the CWD pin is being pulled up to

VDD using a pull-up resistor, then a 10-kΩ resistor is required.

7.3.3.2 WDI Functionality

WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge

of the input signal. For the first pulse, the watchdog acts as a traditional watchdog timer; thus, the first pulse

must be issued before t_WDU(min). After the first pulse, to ensure proper functionality of the watchdog timer, always

issue the WDI pulse within the window of t_WDL(max)and t_WDU(min). If the pulse is issued in this region, then WDO

remains unasserted. Otherwise, the device asserts WDO, putting the WDO pin into a low-impedance state.

The watchdog input (WDI) is a digital pin. To ensure there is no increase in I_DD, drive the WDI pin to either

VDD or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply current

(I_DD) because of the architecture of the digital logic gates. When WDO is asserted, the watchdog is disabled and

all signals input to WDI are ignored until the WDO reset delay expires. When WDO is no longer asserted, the

device resumes normal operation and no longer ignores the signal on WDI. If the watchdog is disabled, drive the

WDI pin to either VDD or GND.

7.3.3.3 WDO Functionality

The TPS3430 features a programmable window watchdog timer with an programmable watchdog output

( WDO). The watchdog output can flag a fault whenever the watchdog input is outside of the watchdog window.

When WDO is not asserted (high), the WDO signal maintains normal operation. When asserted, WDO remains

down for t_RSTand WDI is ignored during the watchdog reset delay. When the watchdog is disabled, WDO

remains high regardless of WDI.

14

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

7.4 Device Functional Modes

表 7-1 summarizes the functional modes of the TPS3430.

表 7-1. Device Functional Modes

VDD

WDI

WDO

—

V_DD< V_POR

—

V_POR< V_DD< V_{DD (min)}

Ignored

High

Low

t_WDL(max)≤ t_pulse⁽¹⁾≤ t_WDU(min)

(1)

V_DD≥ V_{DD (min)}

t_WDL(max)> t_pulse

(1)

t_WDU(min)< t_pulse

(1) Where t_pulseis the time between falling edges on WDI.

7.4.1 V_DDis Below V_POR( V_DD< V_POR

)

When V_DDis less than V_POR, WDO is undefined and can be either high or low. The state of WDO largely

depends on the load that the WDO pin is experiencing.

7.4.2 V_DDis Above V_PORAnd Below V_{DD (min)}( V_POR< V_DD< V_{DD (min)}

When V_DDis above V_PORand below V_{DD (min)}, the watchdog is disabled, WDO is logic high and WDI is ignored.

7.4.3 Normal Operation (V_DD≥ V_{DD (min)}

)

When V_DDis greater than or equal to V_{DD (min)}, the WDO signal is determined by WDI if the watchdog is enabled.

During power up, the watchdog is disabled until t_RSTexpires. While the watchdog is enabled, the first falling edge

on WDI must occur before t_WDU(max)to prevent WDO from asserting. If the first falling edge on WDI occurs after

t_WDU(max), WDO is asserted (active and low) for t_RST. If any falling edge after the first falling edge occurs on WDI

before t_WDU(min)or after t_WDU(max), WDO is asserted (active and low) for t_RST

.

Submit Document Feedback

15

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

8 Application and Implementation

Note

以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The following sections describe in detail proper device implementation, depending on the final application

requirements.

8.1.1 CRST Delay

The TPS3430 features three options for setting the reset delay (t_RST): connecting a capacitor to the CRST

pin, connecting a pull-up resistor to VDD, and leaving the CRST pin unconnected. 图 8-1 shows a schematic

drawing of all three options. To determine which option is connected to the CRST pin, an internal state machine

controls the internal pulldown device and measures the pin voltage. This sequence of events takes 381 μs (t_INIT

)

to determine which timing option is used. Every time WDO is asserted, the state machine determines what is

connected to the pin.

VDD

TPS3430

VDD

375 nA

CRST

C_CRST

CRST

Cap

Control

Cap

Control

Cap

Control

User Programmable

Capacitor to GND

CRST

Unconnected

10 kΩ Resistor

to VDD

图 8-1. CRST Charging Circuit

8.1.1.1 Factory-Programmed Watchdog Reset Delay Timing

To use the factory-programmed timing options, the CRST pin must either be left unconnected or pulled up to

VDD through a 10-kΩ pull-up resistor. Using these options enables a high-precision, 15% accurate reset delay

timing, as shown in 表 8-1.

表 8-1. Watchdog Reset Delay Time for Factory-Programmed Timing

WDO DELAY TIME (t_RST

)

CRST

UNIT

MIN

TYP

200

10

MAX

230

NC

170

8.5

ms

10 kΩ to VDD

11.5

8.1.1.2 CRST Programmable Watchdog Reset Delay

The TPS3430 uses a CRST pin charging current (I_CRST) of 375 nA. When using an external capacitor, the rising

WDO delay time can be set to any value between 700 µs (C_CRST= 100 pF) and 3.2 seconds (C_CRST= 1 µF).

The typical ideal capacitor value needed for a given delay time can be calculated using 方程式 1, where C_CRSTis

in microfarads and t_RSTis in seconds:

16

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

t_RST= 3.22 × C_CRST+ 0.000381

(1)

To calculate the minimum and maximum watchdog reset delay time use 方程式 2 and 方程式 3, respectively.

t_RST(min)= 2.8862 × C_CRST+ 0.000324

t_RST(max)= 3.64392 × C_CRST+ 0.000438

(2)

(3)

The slope of 方程式 1 is determined by the time the CRST charging current (I_CRST) takes to charge the external

capacitor up to the CRST comparator threshold voltage (V_CRST). When WDO is asserted, the capacitor is

discharged through the internal CRST pulldown resistor. When the WDO conditions are cleared, the internal

precision current source is enabled and begins to charge the external capacitor; when V_CRST= 1.21 V, WDO

is unasserted. Note to minimize the difference between the calculated WDO delay time and the actual WDO

delay time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board

capacitance around this pin. 表 8-2 lists the watchdog reset delay time ideal capacitor values for C_CRST

.

表 8-2. Watchdog Reset Delay Time for Common Ideal Capacitor Values

WDO DELAY TIME (t_RST

)

C_CRST

UNIT

MIN⁽¹⁾

TYP

0.70

3.61

32.6

323

MAX⁽¹⁾

0.80

100 pF

1 nF

0.61

3.21

29.2

289

ms

4.08

10 nF

100 nF

1 μF

36.8

364

2886

3227

3644

(1) Minimum and maximum values are calculated using ideal capacitors.

8.1.2 CWD Functionality

The TPS3430 features three options for setting the watchdog window: connecting a capacitor to the CWD pin,

connecting a pull-up resistor to VDD, and leaving the CWD pin unconnected. 图 8-2 shows a schematic drawing

of all three options. If this pin is connected to VDD through a 10-kΩ pull-up resistor or left unconnected (high

impedance), then the factory-programmed watchdog timeouts are enabled; see the 节 6.6 table. Otherwise, the

watchdog timeout can be adjusted by placing a capacitor from the CWD pin to ground.

VDD

TPS3430

VDD

375 nA

CWD

C_CWD

CWD

Cap

Control

Cap

Control

Cap

Control

User Programmable

Capacitor to GND

CWD

Unconnected

10 kΩ Resistor

to VDD

图 8-2. CWD Charging Circuit

Submit Document Feedback

17

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

8.1.2.1 Factory-Programmed Timing Options

If using the factory-programmed timing options (listed in 表 8-3), the CWD pin must either be unconnected

or pulled up to VDD through a 10-kΩ pull-up resistor. Using these options enables high-precision, factory-

programmed watchdog timing.

表 8-3. Factory-Programmed Watchdog Timing

INPUT

WATCHDOG LOWER BOUNDARY (t_WDL

)

WATCHDOG UPPER BOUNDARY (t_WDU)

UNIT

CWD

SET0 SET1

MIN

19.1

1.48

TYP

22.5

1.85

MAX

25.9

2.22

MIN

46.8

TYP

55.0

27.5

MAX

63.3

0

1

0

1

0

1

0

1

0

1

0

1

ms

23.375

31.625

NC

Watchdog disabled

680

800

9.0

920

10.35

1360

1600

109.0

195.0

1840

125.4

224.3

ms

7.65

92.7

165.8

10 kΩ to VDD

Watchdog disabled

1.48 1.85

Watchdog disabled

9.35 11.0

2.22

12.65

ms

8.1.2.2 CWD Adjustable Capacitor Watchdog Timeout

Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected

to CWD, then a 375-nA constant-current source charges C_CWDuntil V_CWD= 1.21 V. The TPS3430 determines

the window watchdog upper boundary with the formula given in 方程式 4, where C_CWDis in microfarads and

t_WDUis in seconds.

t_WDU(typ)= 77.4 × C_CWD+ 0.055

(4)

The TPS3430 is designed and tested using C_CWDcapacitors between 100 pF and 1 µF. Note that 方程式 4 is

for ideal capacitors, capacitor tolerances cause the actual device timing to vary. For the most accurate timing,

use ceramic capacitors with COG dielectric material. As shown in 表 8-4, when using the minimum capacitor of

100 pF, the watchdog upper boundary is 62.74 ms; whereas with a 1-µF capacitor, the watchdog upper boundary

is 77.455 seconds. If a C_CWDcapacitor is used, 方程式 4 can be used to set t_WDUthe window watchdog upper

boundary. The window watchdog lower boundary is dependent on the SET0 and SET1 pins because these pins

set the window watchdog ratio of the lower boundary to upper boundary; 表 8-5 shows how t_WDUcan be used to

calculate t_WDLbased on the SET0 and SET1 pins.

表 8-4. t_WDUValues for Common Ideal Capacitor Values

WATCHDOG UPPER BOUNDARY (t_WDU

)

C_CWD

UNIT

MIN ⁽¹⁾

56.77

119.82

750

TYP

62.74

132.4

829

MAX ⁽¹⁾

68.7

100 pF

1 nF

ms

144.98

908

10 nF

100 nF

1 µF

7054

7795

77455

8536

70096

84814

(1) Minimum and maximum values are calculated using ideal capacitors.

表 8-5. Programmable CWD Timing

INPUT

SET0 SET1

WATCHDOG LOWER BOUNDARY (t_WDL

)

WATCHDOG UPPER BOUNDARY (t_WDU)

UNIT

CWD

MIN

t_WDU(min)x 0.125

t_WDU(min)x 0.75

TYP

MAX

MIN

TYP

MAX

(1)

0

1

0

1

0

1

t_WDUx 0.125 t_WDU(max)x 0.125 0.905 x t_WDU(typ)

t_WDU(typ)

1.095 x t_WDU(typ)

s

(1)

t_WDUx 0.75

Watchdog disabled

t_WDUx 0.5

t_WDU(max)x 0.75 0.905 x t_WDU(typ)

t_WDU(typ)

C_CWD

Watchdog disabled

(1)

t_WDU(min)x 0.5

t_WDU(max)x 0.5 0.905 x t_WDU(typ)

t_WDU(typ)

1.095 x t_WDU(typ)

s

(1) Calculated from 方程式 4 using ideal capacitors.

18

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

8.2 Typical Applications

8.2.1 Monitoring Microcontroller with Watchdog Timer - Design 1

A basic application for the TPS3430 is shown in 图 8-8. The TPS3430 is used to monitor the activity of the

microcontroller via the WDI pin. Design 1 utilizes the simplest TPS3430 configuration with factory-programmed

timing options by leaving the CRST and CWD timing pins floating (NC - no connect)

3.3V

TPS3430

VDD2

V_CORE

VDD1

NC

Microcontroller

SET1

SET0

CRST

CWD

NMI

GPIO

WDO

NC

WDI

GND

图 8-3. Monitoring Microcontroller using a Window Watchdog Timer

8.2.1.1 Design Requirements - Design 1

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

Use factory-programmed timing option by leaving

CRST as NC. Watchdog reset delay: 170 ms (min),

200 ms (typ), 230 ms (max)

Watchdog Reset delay

Reset delay of 200 ms

Leaving the CWD pin unconnected with SET0 = 1

and SET1 = 1 produces a window with a t_WDL(max)

of 920 ms and a t_WDU(min)of 1360 ms

Functions with a 1-Hz pulse-width modulation

(PWM) signal with a 20% duty cycle

Watchdog window

Output logic voltage

3.3-V Open-Drain

200 µA

3.3-V Open-Drain

Maximum device current

consumption

10 µA of current consumption, typical worst-case of

199 µA when WDO is asserted

8.2.1.2 Detailed Design Procedure - Design 1

8.2.1.2.1 Meeting the Minimum Watchdog Reset Delay - Design 1

To achieve the 200 ms Watchdog Reset Delay requirement, this design simply leaves CRST pin floating (NC

- No Connect) to set the Watchdog Reset Delay (t_RST) to the factory-programmed delay of 200 ms. Refer to

section 8.1.1 CRST Delay to learn more about the factory-programmed timing options and how to program the

Watchdog Reset Delay using an external capacitor.

In 图 8-4 below, the Watchdog Reset Delay of 200 ms is shown by causing a watchdog timing fault. No

watchdog pulse comes on WDI within the Watchdog Timeout so WDO activates for t_RSTof 200 ms. Then after

three watchdog faults, a watchdog pulse at 1Hz and 20% duty cycle arrives on WDI causing WDO to deactive

and remain high.

Submit Document Feedback

19

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

VDD

No pulse on WDI before WDU(max) so WDO asserts

Falling edge on WDI occurs within WDL and WDU

WDI

WDO remains unasserted while

WDI is within watchdog window

WDO

图 8-4. Watchdog Fault Caused by Missing WDI Pulse Until WDI pulses Arrive Within Watchdog Window

to Deactivate WDO Fault

8.2.1.2.2 Setting the Watchdog Window - Design 1

The Watchdog Window is set via the CWD, SET0, and SET1 pin configurations. To achieve a Watchdog Timeout

of 1 second, this design simply leaves CWD pin floating (NC - No Connect) and ties SET0 and SET1 to

VDD to set these SET pins to logic high. With this configuration, the Watchdog Lower Boundary t_{WDL (typ)}is

set for 800ms and the Watchdog Upper Boundary t_{WDU (typ)}is set for 1.6 seconds. Refer to Table 6.6 Timing

Requirements to see the factory-programmed window watchdog timing configurations.

In 图 8-5 and 图 8-6 below, the watchdog window timing is shown by causing watchdog faults from pulses on

WDI arriving too early and too late, respectively. When a pulse on WDI arrives too early, that is before t_{WDL (min)}

or too late, that is after t_{WDU (max)}, a watchdog fault occurs and WDO activates to logic low.

20

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

VDD

Ignore all pulses that occur before t_RST

First falling edge must occur before WDU

Second falling edge occurs before WDL triggering a watchdog reset

WDI

WDO

WDO resets for t_RST

图 8-5. Watchdog Fault Caused by WDI Pulse Arriving Too Early (Before t_{WDL (min)}

)

VDD

Ignore all pulses that occur before t_RST

First falling edge must occur before WDU

Second falling edge occurs after WDU(max) triggering a watchdog reset

WDI

WDO

WDO resets for t_RST

图 8-6. Watchdog Fault Caused by WDI Pulse Arriving Too Late (After t_{WDU (max)}

)

Submit Document Feedback

21

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

8.2.1.2.3 Calculating the WDO Pull-up Resistor - Design 1

图 8-7 shows the TPS3430 uses an open-drain configuration for the WDO circuit. When the FET is off, the

resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the

drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure

that V_OLis below its maximum value. To choose the proper pull-up resistor, there are three key specifications

to keep in mind: the pull-up voltage (V_PU), the recommended maximum WDO pin current (I_WDO), and V_OL. The

maximum V_OLis 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage on

the reset pin below 0.4 V with I_WDOkept below 10 mA. For this example, with a V_PUof 3.3 V, a resistor must be

chosen to keep I_WDObelow 200 μA because this value is the maximum consumption current allowed. To ensure

this specification is met, a pull-up resistor value of 16.5 kΩ is selected, which sinks a maximum of 200 μA when

WDO is asserted. WDO current is at 200 μA and the low-level output voltage is approximately zero.

VDD

WDO

WATCHDOG

CONTROL

图 8-7. Open-Drain WDO Configuration

8.2.2 Monitoring Microcontroller with a Programmed Window Watchdog Timer - Design 2

A typical application for the TPS3430 is shown in 图 8-8. The TPS3430 is used to monitor the activity of the

microcontroller via the WDI pin.

1.8 V

TPS3430

V_CORE

VDD2

SET1

SET0

CRST

CWD

VDD1

NC

Microcontroller

NMI

GPIO

WDO

WDI

0.1 µF

GND

图 8-8. Monitoring Microcontroller Using a Window Watchdog Timer with Programmable Watchdog Reset

Delay

8.2.2.1 Design Requirements - Design 2

PARAMETER

DESIGN REQUIREMENT

Minimum reset delay of 250 ms

DESIGN RESULT

Minimum reset delay of 260 ms, reset delay of 322

ms (typical)

Watchdog Reset delay

Leaving the CWD pin unconnected with SET0 = 0

and SET1 = 0 produces a window with a t_WDL(max)

of 25.9 ms and a t_WDU(min)of 46.8 ms

Functions with a 30-Hz pulse-width modulation

(PWM) signal with a 50% duty cycle

Watchdog window

Output logic voltage

1.8-V CMOS

200 µA

1.8-V CMOS

Maximum device current

consumption

10 µA of current consumption, typical worst-case of

199 µA when WDO is asserted

22

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

8.2.2.2 Detailed Design Procedure - Design 2

8.2.2.2.1 Meeting the Minimum Watchdog Reset Delay - Design 2

The TPS3430 features three options for setting the watchdog reset delay: connecting a capacitor to the CRST

pin, connecting a pull-up resistor, and leaving the CRST pin unconnected. If the CRST pin is either unconnected

or pulled up the minimum timing requirement cannot be met, thus an external capacitor must be connected

to the CRST pin. Because a minimum time is required, the worst-case scenario is a supervisor with a high

CRST charging current (I_CRST) and a low CRST comparator threshold (V_CRST). For applications with ambient

temperatures ranging from –40°C to +125°C, C_CRSTcan be calculated using I_CRST(MAX), V_CRST(MIN), and solving

for C_CRSTin 方程式 5:

I

CRST (MAX)

C_{RST (MIN)}

x

=

(t _RST

-

t_INIT

)

V _{CRST (MIN)}

(5)

When solving 方程式 5, the minimum capacitance required at the CRST pin is 0.086 μF. If standard capacitors

with ±10% tolerances are used, then the minimum CRST capacitor required can be found in 方程式 6:

C_{RST(min)_ideal}

0.086 mF

1- 0.1

C_RST(min)

=

1- C_tolerance

(6)

Solving 方程式 6 where C_toleranceis 0.1 or 10%, the minimum C_CRSTcapacitor is 0.096 μF. This value is

then rounded up to the nearest standard capacitor value, so a 0.1-μF capacitor must be used to achieve this

reset delay timing. If voltage and temperature derating are being considered, then also include these values in

C_tolerance

.

8.2.2.2.2 Setting the Watchdog Window - Design 2

In this application, the window watchdog timing options are based on the PWM signal that is provided to the

TPS3430. A window watchdog setting must be chosen such that the falling edge of the PWM signal always falls

within the window. A nominal window must be designed with t_WDL(max)less than 33.33 ms and t_WDU(min)greater

than 33.33 ms. There are several options that satisfy this window option. An external capacitor can be placed on

the CWD pin and calculated to have a sufficient window. Another option is to use one of the factory-programmed

timing options. An additional advantage of choosing one of the factory-programmed options is the ability to

reduce the number of components required, thus reducing overall BOM cost. Leaving the CWD pin unconnected

(NC) with SET0 = 0 and SET1 = 0 produces a t_WDL(max)of 25.9 ms and a t_WDU(min)of 46.8 ms; see 节 8.1.2.

8.2.2.2.3 Calculating the WDO Pull-up Resistor - Design 2

The TPS3430 uses an open-drain configuration for the WDO circuit, as shown in 图 8-7. When the FET is off,

the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the

drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure

that V_OLis below its maximum value. To choose the proper pull-up resistor, there are three key specifications

to keep in mind: the pull-up voltage (V_PU), the recommended maximum WDO pin current (I_WDO), and V_OL. The

maximum V_OLis 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage on

the reset pin below 0.4 V with I_WDOkept below 10 mA. For this example, with a V_PUof 1.8 V, a resistor must be

chosen to keep I_WDObelow 200 μA because this value is the maximum consumption current allowed. To ensure

this specification is met, a pull-up resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when

WDO is asserted.

8.2.3 Monitoring Microcontroller with a Latching Window Watchdog Timer - Design 3

A safety critical application for the TPS3430 is shown in 图 8-9. The TPS3430 is used to monitor the activity of

the microcontroller via the WDI pin and upon a watchdog fault, this design latches the WDO pin until the device

VDD drops below V_{DD (min)}

.

Submit Document Feedback

23

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

3.3V

TPS3430

VDD2

V_CORE

VDD1

NC

Microcontroller

SET1

SET0

CRST

CWD

NMI

GPIO

WDO

WDI

NC

GND

5nF

Open-drain Buffer

GND

图 8-9. Monitoring Microcontroller Using a Latching Window Watchdog Timer

8.2.3.1 Design Requirements - Design 3

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

Latching watchdog functionality that keeps WDO

logic low when fault occurs

Watchdog Reset delay

Latch WDO upon watchdog fault

Leaving the CWD pin unconnected with SET0 = 1

and SET1 = 1 produces a window with a t_WDL(max)

of 920 ms and a t_WDU(min)of 1360 ms

Functions with a 1-Hz pulse-width modulation

(PWM) signal with a 50% duty cycle

Watchdog window

Output logic voltage

3.3-V Open-Drain

200 µA

3.3-V Open-Drain

Maximum device current

consumption

10 µA of current consumption, typical worst-case of

199 µA when WDO is asserted

8.2.3.2 Detailed Design Procedure - Design 3

8.2.3.2.1 Meeting the Latching Output Requirement - Design 3

To achieve the latching watchdog feature, an open-drain buffer is connected from WDO to CRST with a small

value capacitor connected from the Anode of the buffer connected to CRST to GND. The capacitor must be a

small value to prevent additional delay when triggering WDO to active low during watchdog fault. A capacitor

between 150 pF and 5 nF is recommended.

In 图 8-10 below, the latching watchdog feature is shown by causing a watchdog fault and observing WDO.

Because no pulse arrived on WDI within the Watchdog Timeout, WDO activates and goes logic low and remains

low. To reset the watchdog, the device must be restarted by dropping VDD below V_{DD (min)}

.

8.2.3.2.2 Setting the Watchdog Window - Design 3

The Watchdog Window is set via the CWD, SET0, and SET1 pin configurations. To achieve a Watchdog Timeout

of 1 second corresponding to a 1-Hz WDI signal, this design simply leaves CWD pin floating (NC - No Connect)

and ties SET0 and SET1 to VDD to set the SET pins to logic high. With this configuration, the Watchdog Lower

Boundary t_{WDL (typ)}is set for 800 ms and the Watchdog Upper Boundary t_{WDU (typ)}is set for 1.6 seconds. Refer to

Table 6.6 Timing Requirements to see the factory-programmed window watchdog timing configurations.

24

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

8.2.3.3 Application Curve - Design 3

VDD

No WDI falling edge occurs before WDU(max) so WDO asserts and latches

WDI

WDO

图 8-10. Watchdog Fault Caused by Missing WDI Pulse Shows WDO Latching

Submit Document Feedback

25

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

9 Power Supply Recommendations

This device is designed to operate from an input supply with a voltage range between 1.6 V and 6.5 V. An input

supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is

to place a 0.1-µF capacitor between the VDD pin and the GND pin. Please be sure to externally connect VDD1

to VDD2 as the device will not function if these pins are not connected.

26

Submit Document Feedback

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

10 Layout

10.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends

placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the

CRST pin, then minimize parasitic capacitance on this pin so the WDO delay time is not adversely affected.

•

Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a

0.1-µF ceramic capacitor as near as possible to the VDD pin.

•

If a C_CRSTcapacitor or pull-up resistor is used, place these components as close as possible to the CRST

pin. If the CRST pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the

pin.

•

If a C_CWDcapacitor or pull-up resistor is used, place these components as close as possible to the CWD pin.

If the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.

Place the pull-up resistor on WDO as close to the pin as possible.

10.2 Layout Example

C_VDD

GND Plane

1

2

3

4

5

10

9

VDD2

NC

Vin

C_CWD

VDD1

CWD

SET0

CRST

8

WDO

WDI

R_PU2

C_CRST

7

6

GND

SET1

Vin

Denotes a via.

图 10-1. Typical Layout for the TPS3430

Submit Document Feedback

27

Product Folder Links: TPS3430

TPS3430

www.ti.com.cn

ZHCSIK0A – JULY 2018 – REVISED OCTOBER 2021

11 Device and Documentation Support

11.1 Device Support

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•

TPS3430EVM Window Watchdog Timer with Programmable Timeout Delay User Guide

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI

的《使用条款》。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28

Submit Document Feedback

Product Folder Links: TPS3430

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS3430WDRCR

VSON

DRC

10

3000

330.0

12.4

3.3

1.1

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VSON DRC 10

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

TPS3430WDRCR

3000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

DRC 10

3 x 3, 0.5 mm pitch

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226193/A

www.ti.com

PACKAGE OUTLINE

DRC0010J

VSON - 1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

B

A

PIN 1 INDEX AREA

3.1

2.9

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

1.65 0.1

2X (0.5)

(0.2) TYP

EXPOSED

THERMAL PAD

4X (0.25)

5

6

2X

2

11

SYMM

2.4 0.1

10

1

8X 0.5

0.30

0.18

10X

SYMM

PIN 1 ID

0.1

C A B

C

(OPTIONAL)

0.05

0.5

0.3

10X

4218878/B 07/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRC0010J

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

(0.5)

10X (0.6)

1

10

10X (0.24)

11

(2.4)

(3.4)

SYMM

(0.95)

8X (0.5)

6

5

(R0.05) TYP

(

0.2) VIA

TYP

(0.25)

(0.575)

SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218878/B 07/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DRC0010J

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)

(0.5)

SYMM

EXPOSED METAL

TYP

11

10X (0.6)

1

10

(1.53)

10X (0.24)

2X

(1.06)

SYMM

(0.63)

8X (0.5)

6

5

(R0.05) TYP

4X (0.34)

4X (0.25)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4218878/B 07/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS3430WDRCR
厂家：	TEXAS INSTRUMENTS
描述：	具备可编程复位延迟功能的窗口看门狗计时器 \| DRC \| 10 \| -40 to 125
文件：	总37页 (文件大小：2701K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS3430WDRCR [TI]

相关型号：

TPS3430WQDRCRQ1

TPS3431

TPS3431-Q1

TPS3431SDRBR

TPS3431SQDRBRQ1

TPS3435

TPS3435-Q1

TPS3435CAKAGDDFR

TPS3436-Q1

TPS35-Q1

TPS350

TPS350-10