TPS3700QDDCRQ1 [TI]
用于过压和欠压监测的汽车类高电压 (18V) 窗口电压检测器 | DDC | 6 | -40 to 125;
| 型号： | TPS3700QDDCRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于过压和欠压监测的汽车类高电压 (18V) 窗口电压检测器 | DDC | 6 | -40 to 125 光电二极管 |
| 文件： | 总28页 (文件大小：1014K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS3700
SBVS187D –FEBRUARY 2012–REVISED JANUARY 2015
TPS3700 Window Comparator With Internal Reference
for Overvoltage and Undervoltage Detection
1 Features
3 Description
The
TPS3700
wide-supply
voltage
window
1
•
•
•
Wide Supply Voltage Range: 1.8 V to 18 V
Adjustable Threshold: Down to 400 mV
High Threshold Accuracy:
comparator operates over a 1.8-V to 18-V range. The
device has two high-accuracy comparators with an
internal 400-mV reference and two open-drain
outputs rated to 18 V for over- and undervoltage
detection. The TPS3700 can be used as a window
comparator or as two independent voltage monitors;
the monitored voltage can be set with the use of
external resistors.
–
–
1.0% Over Temperature
0.25% (Typical)
•
•
Low Quiescent Current: 5.5 µA (Typical)
Open-Drain Outputs for Overvoltage and
Undervoltage Detection
OUTA is driven low when the voltage at INA+ drops
below (VITP – VHYS), and goes high when the voltage
returns above the respective threshold (VITP). OUTB
is driven low when the voltage at INB– rises above
VITP, and goes high when the voltage drops below the
respective threshold (VITP – VHYS). Both comparators
in the TPS3700 include built-in hysteresis for filtering
to reject brief glitches, thereby ensuring stable output
operation without false triggering.
•
•
•
Internal Hysteresis: 5.5 mV (Typ)
Temperature Range: –40°C to 125°C
Packages:
–
–
SOT-6
1.5-mm × 1.5-mm WSON-6
2 Applications
The TPS3700 is available in a SOT-6 and a 1.5-mm
× 1.5-mm WSON-6 package and is specified over the
junction temperature range of –40°C to 125°C.
•
•
•
•
Industrial Control Systems
Automotive Systems
Embedded Computing Modules
Device Information(1)
DSP, Microcontroller, or Microprocessor
Applications
PART NUMBER
PACKAGE
SOT (6)
WSON (6)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
1.50 mm × 1.50 mm
•
•
•
Notebook and Desktop Computers
Portable- and Battery-Powered Products
FPGA and ASIC Applications
TPS3700
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
VMON
1.8 V to 18 V
0.1 µF
VDD
R1
RP1
INA+
OUTA
VIT+
RP2
INA+
INB±
VIT+
To a reset
or enable
input of
R2
Device
the system.
INB–
OUTB
R3
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3700
SBVS187D –FEBRUARY 2012–REVISED JANUARY 2015
www.ti.com
Table of Contents
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 15
9.3 Do's and Don'ts....................................................... 17
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Simplified Schematic............................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Switching Characteristics.......................................... 6
7.8 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
9
10 Power-Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1 Device Support...................................................... 19
12.2 Documentation Support ........................................ 19
12.3 Trademarks........................................................... 19
12.4 Electrostatic Discharge Caution............................ 19
12.5 Glossary................................................................ 19
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2013) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 4
Changed HBM maximum specification from 2 kV to 2.5 kV in ESD Ratings......................................................................... 4
Changed Functional Block Diagram; added hysteresis symbol ............................................................................................ 9
•
•
Changes from Revision B (April 2012) to Revision C
Page
•
•
•
•
•
Changed Packages Features bullet ....................................................................................................................................... 1
Added SON-6 package option to Description section ............................................................................................................ 1
Added DSE pin out graphic to front page............................................................................................................................... 1
Added DSE pin out graphic .................................................................................................................................................... 3
Added DSE package to Thermal Information table................................................................................................................ 4
Changes from Revision A (February 2012) to Revision B
Page
•
Moved to Production Data...................................................................................................................................................... 1
2
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SBVS187D –FEBRUARY 2012–REVISED JANUARY 2015
6 Pin Configuration and Functions
DDC Package
SOT-6
(Top View)
DSE Package
WSON-6
(Top View)
OUTA
GND
INA+
1
2
3
6
5
4
OUTB
VDD
OUTB
VDD
1
2
3
6
5
4
OUTA
GND
INA+
INB-
INB-
Pin Functions
PIN
DDC
2
I/O
DESCRIPTION
NAME
GND
DSE
5
—
Ground
This pin is connected to the voltage to be monitored with the use of an external resistor
INA+
INB–
OUTA
3
4
1
4
3
6
I
I
divider. When the voltage at this terminal drops below the threshold voltage (VITP
VHYS), OUTA is driven low.
–
This pin is connected to the voltage to be monitored with the use of an external resistor
divider. When the voltage at this terminal exceeds the threshold voltage (VITP), OUTB is
driven low.
INA+ comparator open-drain output. OUTA is driven low when the voltage at this
comparator is below (VITP – VHYS). The output goes high when the sense voltage returns
above the respective threshold (VITP).
O
INB– comparator open-drain output. OUTB is driven low when the voltage at this
comparator exceeds VITP. The output goes high when the sense voltage returns below
the respective threshold (VITP – VHYS).
OUTB
VDD
6
5
1
2
O
I
Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. Good
analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
20
UNIT
V
VDD
Voltage(2)
OUTA, OUTB
20
V
INA+, INB–
7
V
Current
Output terminal current
40
mA
°C
°C
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–65
125
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-
001, all pins(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
1.8
0
NOM
MAX UNIT
VDD
VI
Supply voltage
Input voltage
Output voltage
18
6.5
18
V
V
V
INA+, INB–
VO
OUTA, OUTB
0
7.4 Thermal Information
TPS3700
THERMAL METRIC(1)
DDC (SOT)
6 PINS
204.6
50.5
DSE (WSON)
6 PINS
194.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
128.9
54.3
153.8
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
11.9
ψJB
52.8
157.4
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
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7.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to 125°C, and 1.8 V < VDD < 18 V, unless otherwise noted.
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER
Supply voltage range
Power-on reset voltage(1)
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDD
1.8
18
0.8
404
404
400
400
12
V
V
V(POR)
VOLmax = 0.2 V, I(OUTA/B) = 15 µA
VDD = 1.8 V
396
396
387
387
400
400
394.5
394.5
5.5
VIT+
Positive-going input threshold voltage
Negative-going input threshold voltage
mV
mV
VDD = 18 V
VDD = 1.8 V
VIT–
VDD = 18 V
Vhys
Hysteresis voltage (hys = VIT+ – VIT–
Input current (at the INA+ terminal)
Input current (at the INB– terminal)
)
I(INA+)
I(INB–)
VDD = 1.8 V and 18 V, VI = 6.5 V
VDD = 1.8 V and 18 V, VI = 0.1 V
VDD = 1.3 V, IO = 0.4 mA
VDD = 1.8 V, IO = 3 mA
VDD = 5 V, IO = 5 mA
VDD = 1.8 V and 18 V, VO = VDD
VDD = 1.8 V, VO = 18 V
VDD = 1.8 V, no load
VDD = 5 V
–25
–15
1
25
nA
nA
1
15
250
250
250
300
300
11
VOL
Low-level output voltage
mV
nA
Ilkg(OD)
Open-drain output leakage-current
5.5
6
13
IDD
Supply current
µA
VDD = 12 V
6
13
VDD = 18 V
7
13
Start-up delay(2)
Undervoltage lockout(3)
150
µs
V
UVLO
VDD falling
1.3
1.7
(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
(2) During power on, VDD must exceed 1.8 V for at least 150 µs before the output is in a correct state.
(3) When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined below V(POR)
.
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7.6 Timing Requirements
Over operating temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 1
tPHL
High-to-low propagation delay(1)
Low-to-high propagation delay(1)
18
µs
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 1
tPLH
29
µs
(1) High-to-low and low-to-high refers to the transition at the input terminals (INA+ and INB–).
VDD
VIT+
Vhys
INA+
OUTA
tPHL
tPLH
tPLH
VIT+
Vhys
INB–
OUTB
tPLH
tPHL
Figure 1. Timing Diagram
7.7 Switching Characteristics
Over operating temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
tr
tf
Output rise time
2.2
µs
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
Output fall time
0.22
µs
6
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7.8 Typical Characteristics
At TJ = 25°C and VDD = 5 V, unless otherwise noted.
10
9
8
7
6
5
4
3
2
1
0
401
400.6
400.2
399.8
399.4
399
VDD = 1.8 V
VDD = 5 V
VDD = 1.2 V
VDD = 18 V
ꢀ40qC
0qC
25qC
85qC
125qC
0
2
4
6
8
10
12
14
16
18
-40 -25 -10
5
20 35 50 65 80 95 110 125
Supply Voltage (V)
Temperature (qC)
D001
D003
Figure 2. Supply Current (IDD) vs Supply Voltage (VDD
)
Figure 3. Rising Input Threshold Voltage (VIT+) vs
Temperature
9
8
7
6
5
4
3
31
29
27
25
23
21
19
17
15
13
11
9
VDD = 1.8 V, INBꢀ to OUTB
VDD = 18 V, INBꢀ to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (qC)
Temperature (qC)
D005
D004
Figure 5. Propagation Delay vs Temperature
(High-to-Low Transition at the Inputs)
Figure 4. Hysteresis (Vhys) vs Temperature
30
28
26
24
22
20
18
16
14
12
10
8
20
18
16
14
12
10
8
INA+
INB–
6
VDD = 1.8 V, INBꢀ to OUTB
VDD = 18 V, INBꢀ to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
4
2
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.5
4
5.5
7
8.5
Positive-Going Input Threshold Overdrive (%)
10 11.5
13 14.5 16
Temperature (qC)
D006
D007
INA+ = negative spike below VIT–
INB– = positive spike above VIT+
Figure 6. Propagation Delay vs Temperature
(Low-to-High Transition at the Inputs)
Figure 7. Minimum Pulse Width vs
Threshold Overdrive Voltage
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Typical Characteristics (continued)
At TJ = 25°C and VDD = 5 V, unless otherwise noted.
11
2000
1750
1500
1250
1000
750
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
10
9
8
7
6
5
4
3
2
1
ꢀ40qC
0qC
25qC
85qC
125qC
500
250
0
0
4
8
12
16
20
24
28
32
36
40
0
0
0
5
10
15
20
25
30
35
40
Output Sink Current (mA)
Output Sink Current (mA)
D008
D009
Figure 8. Supply Current (IDD) vs
Output Sink Current
Figure 9. Output Voltage Low (VOL) vs
Output Sink Current (–40°C)
2000
1750
1500
1250
1000
750
2000
1750
1500
1250
1000
750
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
500
500
250
250
0
0
0
5
10
15
20
25
30
35
40
5
10
15
20
25
30
35
40
Output Sink Current (mA)
Output Sink Current (mA)
D010
D011
Figure 10. Output Voltage Low (VOL) vs
Output Sink Current (0°C)
Figure 11. Output Voltage Low (VOL) vs
Output Sink Current (25°C)
2000
1750
1500
1250
1000
750
2000
1750
1500
1250
1000
750
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
500
500
250
250
0
0
0
5
10
15
20
25
30
35
40
5
10
15
20
25
30
35
40
Output Sink Current (mA)
Output Sink Current (mA)
D012
D013
Figure 12. Output Voltage Low (VOL) vs
Output Sink Current (85°C)
Figure 13. Output Voltage Low (VOL) vs
Output Sink Current (125°C)
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8 Detailed Description
8.1 Overview
The TPS3700 device combines two comparators for overvoltage and undervoltage detection. The TPS3700
device is a wide-supply voltage range (1.8 V to 18 V) device with a high-accuracy rising input threshold of
400 mV (1% over temperature) and built-in hysteresis. The outputs are also rated to 18 V and can sink up to 40
mA.
The TPS3700 device is designed to assert the output signals, as shown in Table 1. Each input terminal can be
set to monitor any voltage above 0.4 V using an external resistor divider network. With the use of two input
terminals of different polarities, the TPS3700 device forms a window comparator. Broad voltage thresholds can
be supported that allow the device to be used in a wide array of applications.
Table 1. TPS3700 Truth Table
CONDITION
INA+ > VIT+
INA+ < VIT–
INB– > VIT+
INB– < VIT–
OUTPUT
OUTA high
OUTA low
OUTB low
OUTB high
STATUS
Output A not asserted
Output A asserted
Output B asserted
Output B not asserted
8.2 Functional Block Diagram
VDD
INA+
OUTA
OUTB
INB–
Reference
GND
8.3 Feature Description
8.3.1 Inputs (INA+, INB–)
The TPS3700 device combines two comparators. Each comparator has one external input (inverting and
noninverting); the other input is connected to the internal reference. The comparator rising threshold is designed
and trimmed to be equal to the reference voltage (400 mV). Both comparators also have a built-in falling
hysteresis that makes the device less sensitive to supply rail noise and ensures stable operation.
The comparator inputs can swing from ground to 6.5 V, regardless of the device supply voltage used. Although
not required in most cases, good analog design practice is to place a 1-nF to 10-nF bypass capacitor at the
comparator input for extremely noisy applications to reduce sensitivity to transients and layout parasitics.
For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA+ voltage drops
below (VIT+ – Vhys). When the voltage exceeds VIT+, the output (OUTA) goes to a high-impedance state; see
Figure 1.
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Feature Description (continued)
For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB–
exceeds VIT+. When the voltage drops below VIT+ – Vhys the output (OUTB) goes to a high-impedance state; see
Figure 1. Together, these comparators form a window-detection function as discussed in Window Comparator.
8.3.2 Outputs (OUTA, OUTB)
In a typical TPS3700 application, the outputs are connected to a reset or enable input of the processor (such as
a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or
application-specific integrated circuit [ASIC]) or the outputs are connected to the enable input of a voltage
regulator (such as a DC-DC or low-dropout regulator [LDO]).
The TPS3700 device provides two open-drain outputs (OUTA and OUTB). Pullup resistors must be used to hold
these lines high when the output goes to high impedance (not asserted). By connecting pullup resistors to the
proper voltage rails, the outputs can be connected to other devices at the correct interface-voltage levels. The
TPS3700 outputs can be pulled up to 18 V, independent of the device supply voltage. By using wired-OR logic,
OUTA and OUTB can merge into one logic signal that goes low if either outputs are asserted because of a fault
condition.
Table 1 and Inputs (INA+, INB–) describe how the outputs are asserted or deasserted. See Figure 1 for a timing
diagram that describes the relationship between threshold voltages and the respective output.
8.3.3 Window Comparator
The inverting and noninverting configuration of the comparators forms a window-comparator detection circuit
using a resistor divider network, as shown in Figure 14 and Figure 15. The input terminals can monitor any
system voltage above 400 mV with the use of a resistor divider network. The INA+ and INB– terminals monitor
for undervoltage and overvoltage conditions, respectively.
VMON
1.8 V to 18 V
R1
VDD
RP1
(50 kW)
(2.21 MW)
IN
INA+
OUTA
Voltage
Regulator
VO
R2
EN
UV VMON OV
(13.7 kW)
Device
OUT
INB–
OUTB
R3
GND
(69.8 kW)
Figure 14. Window Comparator Block Diagram
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Feature Description (continued)
Overvoltage
Limit
VMON
Undervoltage
Limit
OUTB
OUTA
Figure 15. Window Comparator Timing Diagram
8.3.4 Immunity to Input Terminal Voltage Transients
The TPS3700 device is relatively immune to short voltage transient spikes on the input terminals. Sensitivity to
transients depends on both transient duration and amplitude; see the Minimum Pulse Width vs Threshold
Overdrive Voltage curve (Figure 7) in Typical Characteristics.
8.4 Device Functional Modes
8.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than 1.8 V for at least 150 µs, the OUTA and OUTB signals correspond to
the voltage on INA+ and INB– as listed in Table 1.
8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,
V(POR), the OUTA and OUTB signals are asserted and high impedance, respectively, regardless of the voltage on
INA+ and INB–.
8.4.3 Power-On Reset (VDD < V(POR)
)
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (V(POR)),
both outputs are in a high-impedance state.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS3700 device is a wide-supply voltage window comparator that operates over a VDD range of 1.8 V to
18 V. The device has two high-accuracy comparators with an internal 400-mV reference and two open-drain
outputs rated to 18 V for overvoltage and undervoltage detection. The device can be used either as a window
comparator or as two independent voltage monitors. The monitored voltages are set with the use of external
resistors.
9.1.1 VPULLUP to a Voltage Other Than VDD
The outputs are often tied to VDD through a resistor. However, some applications may require the outputs to be
pulled up to a higher or lower voltage than VDD to correctly interface with the reset and enable terminals of other
devices.
VPULLUP
1.8 V to 18 V
(Up To 18 V)
VDD
INA+
OUTA
To a reset or enable input
of the system.
Device
OUTB
INB–
GND
Figure 16. Interfacing to Voltages Other Than VDD
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Application Information (continued)
9.1.2 Monitoring VDD
Many applications monitor the same rail that is powering VDD. In these applications the resistor divider is simply
connected to the VDD rail.
1.8 V to 18 V
VDD
INA+
OUTA
To a reset or enable input
of the system.
Device
INB–
OUTB
GND
Figure 17. Monitoring the Same Voltage as VDD
9.1.3 Monitoring a Voltage Other Than VDD
Some applications monitor rails other than the one that is powering VDD. In these types of applications the
resistor divider used to set the desired thresholds is connected to the rail that is being monitored.
VMON
(26.4 V to 21.7 V)
1.8 V to 18 V
R1
VDD
Device
GND
(2.61 MW)
INA+
OUTA
R2
(8.06 kW)
To a reset or enable input
of the system.
INB–
OUTB
R3
(40.2 kW)
NOTE: The inputs can monitor a voltage higher than VDDmax with the use of an external resistor divider network.
Figure 18. Monitoring a Voltage Other Than VDD
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Application Information (continued)
9.1.4 Monitoring Overvoltage and Undervoltage for Separate Rails
Some applications may want to monitor for overvoltage conditions on one rail while also monitoring for
undervoltage conditions on a different rail. In these applications two independent resistor dividers must be used.
1.8 V to 18 V
VDD
5 V
INA+
OUTA
INA+
VIT+
To a reset or enable
input of the system.
Device
12 V
INB–
OUTB
INB–
VIT+
GND
NOTE: In this case, OUTA is driven low when an undervoltage condition is detected at the 5-V rail and OUTB is
driven low when an overvoltage condition is detected at the 12-V rail.
Figure 19. Monitoring Overvoltage for One Rail and Undervoltage for a Different Rail
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9.2 Typical Application
The TPS3700 device is a wide-supply voltage window comparator that operates over a VDD range of 1.8 to 18 V.
The monitored voltages are set with the use of external resistors, so the device can be used either as a window
comparator or as two independent overvoltage and undervoltage monitors.
V
V
DD
PULLUP
C1
R4
R5
0.1 µF
49.9 kꢀ
49.9 kꢀ
U1
R1
2.21 Mꢀ
TPS3700DDC
V
DD
OUTA
5
1
INA+
OUTB
GND
3
4
6
2
INB±
R2
13.7 kꢀ
R3
69.8 kꢀ
Figure 20. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the values summarized in Table 2 as the input parameters.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
12-V nominal rail with maximum rising and
falling thresholds of ±10%
VMON(UV)= 10.99 V (8.33%) ±2.94%,
VMON(OV)= 13.14 V (8.33%) ±2.94%
Monitored voltage
9.2.2 Detailed Design Procedure
9.2.2.1 Resistor Divider Selection
Use Equation 1 through Equation 4 to calculate the resistor divider values and target threshold voltages.
RT = R1 + R2 + R3
(1)
Select a value for RT such that the current through the divider is approximately 100 times higher than the input
current at the INA+ and INB– terminals. The resistors can have high values to minimize current consumption as
a result of low-input bias current without adding significant error to the resistive divider. See the application note
Optimizing Resistor Dividers at a Comparator Input (SLVA450) for details on sizing input resistors.
Use Equation 2 to calculate the value of R3.
RT
R3 =
´ VIT+
VMON(OV)
where:
VMON(OV) is the target voltage at which an overvoltage condition is detected
(2)
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Use Equation 3 or Equation 4 to calculate the value of R2.
RT
R2 =
´ VIT+ - R3
VMON (no UV)
where:
VMON(no UV) is the target voltage at which an undervoltage condition is removed as VMON rises
(3)
(4)
RT
R2 =
´ (VIT+ - Vhys
)
- R3
VMON(UV)
where:
VMON(UV) is the target voltage at which an undervoltage condition is detected
The worst-case tolerance can be calculated by referring to Equation 13 in application report SLVA450,
Optimizing Resistor Dividers at a Comparator Input (available for download at www.ti.com). An example of the
rising threshold error, VMON(OV), is given in Equation 5.
VIT+(INB)
0.4
13.2
% ACC = % TOL(VIT+(INB)) + 2 ´
´ % TOLR = 1% + 2 ´
1-
1-
´ 1% = 2.94%
VMON(OV)
(5)
9.2.2.2 Pullup Resistor Selection
To ensure proper voltage levels, the pullup resistor value is selected by ensuring that the pullup voltage divided
by the resistor does not exceed the sink-current capability of the device. This confirmation is calculated by
verifying that the pullup voltage minus the output-leakage current (Ilkg(OD)) multiplied by the resistor is greater the
desired logic-high voltage. These values are specified in the Electrical Characteristics.
Use Equation 6 to calculate the value of the pullup resistor.
(VHI - VPU)
VPU
IO
³ RPU
³
Ilkg(OD)
(6)
9.2.2.3 Input Supply Capacitor
Although an input capacitor is not required for stability, connecting a 0.1-μF low equivalent series resistance
(ESR) capacitor across the VDD terminal and GND terminal is good analog design practice. A higher-value
capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located
close to the power source.
9.2.2.4 Input Capacitors
Although not required in most cases, for extremely noisy applications, placing a 1-nF to 10-nF bypass capacitor
from the comparator inputs (INA+, INB–) to the GND terminal is good analog design practice. This capacitor
placement reduces device sensitivity to transients.
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9.2.3 Application Curves
At TJ = 25°C
OUTB
C2
C2
OUTB
(2 V/div)
(2 V/div)
OUTA
C1
OUTA
C1
(2 V/div)
(2 V/div)
C3
C3
VDD
VDD
(2 V/div)
(2 V/div)
Time (100 µs/div)
Time (100 µs/div)
G013
G014
VDD = 5 V
V(INA+) = 390 mV
V(INB–) = 410 mV
VDD = 5 V
V(INA+) = 410 mV
V(INB–) = 390 mV
Figure 21. Start-Up Delay
(Outputs Pulled Up to VDD
Figure 22. Start-Up Delay
(Outputs Pulled Up to VDD
)
)
9.3 Do's and Don'ts
It is good analog design practice to have a 0.1-µF decoupling capacitor from VDD to GND.
If the monitored rail is noisy, connect decoupling capacitors from the comparator inputs to GND.
Do not use resistors for the voltage divider that cause the current through them to be less than 100 times the
input current of the comparators without also accounting for the effect to the accuracy.
Do not use pullup resistors that are too small, because the larger current sunk by the output then exceeds the
desired low-level output voltage (VOL).
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10 Power-Supply Recommendations
These devices are designed to operate from an input voltage supply range between 1.8 V and 18 V.
11 Layout
11.1 Layout Guidelines
Placing a 0.1-µF capacitor close to the VDD terminal to reduce the input impedance to the device is good analog
design practice. The pullup resistors can be separated if separate logic functions are needed (see Figure 23) or
both resistors can be tied to a single pullup resistor if a logical AND function is desired.
11.2 Layout Example
Figure 23. TPS3700 Layout Schematic
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Evaluation Modules
Two evaluation modules (EVMs) are available to assist in the initial circuit performance evaluation using the
TPS3700. The TPS3700EVM-114 evaluation module and the TPS3700EVM-202 evaluation module (and the
related user's guides) can be requested at the Texas Instruments website through the TPS3700 product folder or
purchased directly from the TI eStore.
12.1.2 Device Nomenclature
Table 3. Device Nomenclature
PRODUCT
DESCRIPTION
yyy is package designator
z is package quantity
TPS3700yyyz
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
Application report, Using the TPS3700 as a Negative Rail Over- and Undervoltage Detector, SLVA600
Application report,Optimizing Resistor Dividers at a Comparator Input, SLVA450
TPS3700EVM-114 Evaluation Module User Guide, SLVU683
TPS3700EVM-202 Evaluation Module User Guide, SLVU950
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
TPS3700DDCR
TPS3700DDCR2
TPS3700DDCT
TPS3700DSER
TPS3700DSET
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOT
SOT
DDC
6
6
6
6
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
PXVQ
PB4Q
PXVQ
BE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDC
DDC
DSE
DSE
3000
250
Green (RoHS
& no Sb/Br)
SOT
Green (RoHS
& no Sb/Br)
WSON
WSON
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
BE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2014
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3700 :
Automotive: TPS3700-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3700DDCR
TPS3700DDCR2
TPS3700DDCT
TPS3700DSER
TPS3700DSET
SOT
SOT
DDC
DDC
DDC
DSE
DSE
6
6
6
6
6
3000
3000
250
179.0
179.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
1.8
1.8
3.2
3.2
3.2
1.8
1.8
1.4
1.4
1.4
1.0
1.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q2
Q3
Q2
Q2
SOT
WSON
WSON
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3700DDCR
TPS3700DDCR2
TPS3700DDCT
TPS3700DSER
TPS3700DSET
SOT
SOT
DDC
DDC
DDC
DSE
DSE
6
6
6
6
6
3000
3000
250
195.0
195.0
195.0
203.0
203.0
200.0
200.0
200.0
203.0
203.0
45.0
45.0
45.0
35.0
35.0
SOT
WSON
WSON
3000
250
Pack Materials-Page 2
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