TPS3703A5330DSER
更新时间:2024-09-18 23:19:29
品牌:TI
描述:TPS3703 High Accuracy Overvoltage and Undervoltage Reset IC With Time Delay and Manual Reset
TPS3703A5330DSER 概述
TPS3703 High Accuracy Overvoltage and Undervoltage Reset IC With Time Delay and Manual Reset
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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020
TPS3703 High Accuracy Overvoltage and Undervoltage Reset IC With Time Delay and
Manual Reset
1 Features
3 Description
•
•
•
•
Input voltage range: 1.7 V to 5.5 V
Undervoltage lockout (UVLO): 1.7 V
Low quiescent current: 7 µA (Max)
High threshold accuracy:
– ± 0.25% (typical)
– ± 0.7% (–40°C to +125°C)
The TPS3703 device is an integrated overvoltage
(OV) and undervoltage (UV) monitor or reset IC in
industry’s smallest 6-pin DSE package. This highly
accurate voltage supervisor is ideal for systems that
operate on low-voltage supply rails and have narrow
margin supply tolerances. Low threshold hysteresis
prevent false reset signals when the monitored
voltage supply is in its normal range of operation.
Internal glitch immunity and noise filters further
eliminate false resets resulting from erroneous
signals.
•
Fixed window threshold levels
– 50-mV steps from 500 mV to 1.3 V
– 1.5 V, 1.8 V, 2.5 V, 2.8 V, 2.9 V 3.3 V, 5 V
– Available in UV threshold only
– Window tolerance available from ±3% to ±7%
User adjustable voltage threshold levels
Internal glitch immunity and hysteresis
Fixed time delay options: 50 µs, 1 ms, 5 ms, 10
ms, 20 ms, 100 ms, 200 ms
Programmable time delay option with a single
external capacitor
Open-drain active low UV and OV monitor
RESET voltage latching output mode
The TPS3703 does not require any external resistors
for setting overvoltage and undervoltage reset
thresholds, which further optimizes overall accuracy,
cost, solution size, and improves reliability for safety
systems. The Capacitor Time (CT) pin is used to
select between the two available reset time delays
designed into each device and also to adjust the reset
time delay by connecting a capacitor. A separate
SENSE input pin and VDD pin allow for the
redundancy sought by high-reliability systems.
•
•
•
•
•
•
2 Applications
This device has a low typical quiescent current
specification of 4.5 µA (typical). The TPS3703 is
suitable for industrial applications and applications
that require accurate undervoltage and overvoltage
monitoring.
•
•
•
•
•
Motor drives
Factory automation and control
Home theater and entertainment
Grid infrastructure
Data center and enterprise computing
Device Information
PART NUMBER
TPS3703
PACKAGE(1)
BODY SIZE (NOM)
WSON (6)
1.50 mm × 1.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
35
30
25
20
15
10
5
OV Threshold
Monitor Voltage
VCORE
UV Threshold
TPS3703
1
SENSE
6
5
MR
Processor
VDD
GND
2
3
10k ꢀ
CT
RESET
4
RESET
0
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
Optional
VIT+(OV) Accuracy (%)
D004
Integrated Overvoltage and Undervoltage
Detection
Typical Overvoltage Accuracy Distribution
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3703
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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................6
7.6 Timing Requirements .................................................7
7.7 Timing Diagrams ........................................................8
7.8 Typical Characteristics..............................................10
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................14
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................17
9 Application and Implementation..................................18
9.1 Application Information............................................. 18
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................27
10.1 Power Supply Guidelines........................................27
11 Layout...........................................................................27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 27
12 Device and Documentation Support..........................28
12.1 Device Nomenclature..............................................28
12.2 Documentation Support.......................................... 30
12.3 Receiving Notification of Documentation Updates..30
12.4 Support Resources................................................. 30
12.5 Trademarks.............................................................30
12.6 Electrostatic Discharge Caution..............................30
12.7 Glossary..................................................................30
13 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2020) to Revision B (November 2020)
Page
•
Added Added VIT < 800 mV threshold option to Electrical Characteristics table ............................................... 6
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5 Device Comparison
Figure 5-1 shows the device nomenclature of the TPS3703. For all possible voltages, window tolerance, time
delays, and UV threshold options, see Table 12-1. Contact TI sales representatives or on TI's E2E forum for
details and availability of other options; minimum order quantities apply.
TPS 3703 X X XXX XXX
Time Delay Op on
Tolerance Op on
3: UV/OV = 3%
4: UV/OV = 4%
5: UV/OV = 5%
6: UV/OV = 6%
7: UV/OV = 7%
Nominal Threshold Op on
Package
DSE: WSON (6-pin)
A: CT (open) 10 ms, CT (VDD) = 200 ms
B: CT (open) 1 ms, CT (VDD) = 20 ms
C: CT (open) 5 ms, CT (VDD) = 100 ms
D: CT (open) 50 µs, CT (VDD) = 50 µs
…
050: 0.50V
...
500: 5.00V
Figure 5-1. TPS3703 Device Nomenclature
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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020
6 Pin Configuration and Functions
SENSE
MR
VDD
CT
GND
RESET
Figure 6-1. DSE Package
6-Pin WSON
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
Input for the monitored supply voltage rail. When the SENSE voltage goes above the overvoltage
threshold or below the undervoltage threshold, the RESET pin is driven low. Connect to VDD pin if
monitoring VDD supply voltage.
1
SENSE
I
I
I
Supply voltage input pin. Good analog design practice is to place a 0.1-μF ceramic capacitor close to
this pin.
2
3
VDD
CT
Capacitor time delay pin. The CT pin offers two fixed time delays by connecting CT pin to VDD or
leaving it floating. Delay time can be programmed by connecting an external capacitor reference to
ground.
Active-low, open-drain output. This pin goes low when the SENSE voltage rises above the internally
overvoltage threshold (VIT+) or below the undervoltage threshold (VIT–). See the timing diagram in
Figure 8-2 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up
voltage.
4
RESET
O
5
6
GND
MR
—
I
Ground
Manual reset (MR), pull this pin to a logic low (VMR_L) to assert a reset signal . After the MR pin is
deasserted the output goes high after the reset delay time(tD) expires. MR can be left floating when not
in use.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX UNIT
Voltage
Voltage
Voltage
Voltage
Voltage
Current
VDD
6
6
V
V
VRESET
VCT
6
V
VSENSE
6
V
VMR
6
V
IRESET
±40
mA
Continuous total power dissipation
Operating junction temperature, TJ
Operating free-air temperature, TA
Storage temperature, Tstg
See the Thermal Information
-40
-40
-65
150
150
150
°C
°C
°C
Temperature (2)
(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(1)
(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
1.7
0
NOM
MAX
5.5
UNIT
V
VDD
Supply pin voltage
VSENSE
VCT
VRESET
VMR
IRESET
TJ
Input pin voltage
5.5
V
CT pin voltage (1) (3)
VDD
5.5
V
Output pin voltage
0
0
V
MR pin Voltage (2)
5.5
V
Output pin current
0.3
-40
10
mA
℃
Junction temperature (free-air temperature)
125
(1) CT pin connected to VDD pin requires a pullup resistor; 10 kΩ is recommended.
(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
(3) The maximum rating is VDD or 5.5 V, whichever is smaller.
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UNIT
SBVS249B – MAY 2020 – REVISED NOVEMBER 2020
7.4 Thermal Information
TPS3703
DSE (WSON)
PINS
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
184.2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
30.6
86.4
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
13.4
ΨJB
86.1
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩ to VDD, RESET load = 10 pF, and over the
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical
conditions at VDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5.5
1.7
1
UNIT
VDD
Supply Voltage
1.7
V
UVLO
VPOR
Under Voltage Lockout(3)
Power on reset voltage(2)
Positive- going threshold accuracy
Negative-going threshold accuracy
Hysteresis Voltage(1)
VDD falling below 1.7 V
1.2
V
VOL(max) = 0.25 V, IOUT = 15 µA
V
VIT+(OV)
VIT-(UV)
VHYS
-0.7
-0.7
0.3
-1
±0.25
±0.25
0.55
0.7
0.7
0.8
1
%
%
%
VIT+(OV)
VIT-(UV)
VHYS
Positive- going threshold accuracy
Negative-going threshold accuracy
Hysteresis Voltage(1)
VIT < 800 mV
%
VIT < 800 mV
-1
1
%
VIT < 800 mV
0.2
0.7
7
%
IDD
Supply current
VDD ≤ 5.5 V
4.5
1
µA
µA
mV
mV
mV
nA
V
ISENSE
Input current, SENSE pin
VSENSE = 5 V
1.5
250
250
250
300
0.3
VDD = 1.7 V, IOUT = 0.4 mA
VDD = 2 V, IOUT = 3 mA
VDD = 5 V, IOUT = 5 mA
VDD = VRESET = 5.5 V
VOL
Low level output voltage
ILKG
Open drain output leakage current
MR logic low input
VMR_L
VMR_H
VCT_H
RMR
MR logic high input
1.4
1.4
V
High level CT pin voltage
V
Manual reset Internal pullup resistance
CT pin charge current
100
375
KΩ
nA
V
ICT
337
413
VCT
CT pin comparator threshold voltage(4)
1.133
1.15
1.167
(1) Hysteresis is with respect of the tripoint (VIT-(UV), VIT+(OV)).
(2) VPOR is the minimum VDD voltage level for a controlled output state.
(3) RESET pin is driven low when VDD falls below UVLO.
(4) VCT voltage refers to the comparator threshold voltage that measures the voltage level of the external capacitor at CT pin.
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7.6 Timing Requirements
At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩ to VDD, RESET load = 10 pF, and over the
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical
conditions at VDD = 3.3 V.
TEST
CONDITIONS
PARAMETER
MIN
NOM
MAX UNIT
tD
tD
tD
tD
tD
tD
Reset time delay, TPS3703A, TPS3703E
Reset time delay, TPS3703A, TPS3703E
Reset time delay, TPS3703B, TPS3703F
Reset time delay, TPS3703B, TPS3703F
Reset time delay, TPS3703C, TPS3703G
Reset time delay, TPS3703C, TPS3703G
CT = Open
7
140
0.7
14
10
200
1
13
260
1.3
26
ms
ms
ms
ms
ms
ms
CT = 10 kΩ to VDD
CT = Open
CT = 10 kΩ to VDD
CT = Open
20
5
3.5
70
6.5
130
CT = 10 kΩ to VDD
100
CT = 10 kΩ to VDD
CT = Open
tD
Reset time delay, TPS3703D, TPS3703H
50
µs
tPD
Propagation detect delay(1) (2)
15
2.2
0.2
300
3.5
3.5
30
µs
µs
µs
µs
µs
µs
ns
ns
µs
ms
tR
Output rise time(1) (3)
tF
Output fall time(1) (3)
tSD
Startup delay(4)
tGI (VIT-)
tGI (VIT+)
tGI (MR)
tPD (MR)
tMR_W
tD (MR)
Glitch Immunity undervoltage VIT-(UV), 5% Overdrive(1)
Glitch Immunity overvoltage VIT+(OV), 5% Overdrive(1)
Glitch Immunity MR pin
25
Propagation delay from MR low to assert RESET
MR pin pulse width duration to assert RESET
MR reset time delay
500
tD
1
(1) 5% Overdrive from threshold. Overdrive % = [VSENSE - VIT] / VIT; Where VIT stands for VIT-(UV) or VIT+(OV)
(2) tPD measured from threhold trip point (VIT-(UV) or VIT+(OV)) to RESET VOL voltage
(3) Output transitions from VOL to 90% for rise times and 90% to VOL for fall times.
(4) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD + tD before the output is in the correct state.
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7.7 Timing Diagrams
Overdrive[2.5%] above VIT+(OV)
[0.7%]
[ 0.4% = 0.7%-0.3%) ]
[ 0.15% = 0.7%-0.55%) ]
[ -0.1% = 0.7%-0.8%) ]
0.5%
VIT+(OV)
[-0.3%]
[-0.55%]
VIT+(OV) - VHYS
Hys band for VIT+(OV)
[-0.8%]
[ -1.0% = -0.7%-0.3%) ]
[ -1.25% = -0.7%-0.55%) ]
[ -1.5% = -0.7%-0.8%) ]
0.5%
[ 1.25% = 0.7%+0.55%) ]
0.5%
[ 1.0% = 0.7%+0.3%) ]
[0.8%]
[0.55%]
[0.3%]
[0.7%]
VIT-(UV) + VHYS
Hys band for VIT-(UV)
[ 0.1% = -0.7%+0.8%) ]
VIT-(UV)
[ -0.15% = -0.7%+0.55%) ]
[ -0.4% = -0.7%+0.3% ]
0.5%
Overdrive [2.5%] below VIT-(UV)
Figure 7-1. Voltage Threshold and Hysteresis Accuracy
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VDD(MIN)
UVLO
VDD
VPOR
VIT+(OV)
Hysteresis
Hysteresis
VIT+(OV) - VHYS
VIT
VIT-(UV) + VHYS
VIT-(UV)
SENSE
RESET
tD
tD
tPD
tPD
tD
tSD
Figure 7-2. SENSE Timing Diagram
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7.8 Typical Characteristics
At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
0.2
0.2
0.15
0.1
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
0.15
0.1
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.05
-0.1
-0.15
-0.2
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D002
D001
Tested across multiple voltage options
Figure 7-4. Overvoltage Accuracy vs Temperature
Tested across multiple voltage options
Figure 7-3. Undervoltage Accuracy vs Temperature
35
35
30
25
20
15
10
5
30
25
20
15
10
5
0
-0.4
0
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
VIT-(UV) Accuracy (%)
VIT+(OV) Accuracy (%)
D003
D004
Sample Size of 100 TPS3703A7125 units
Figure 7-5. Undervoltage Accuracy Distribution
Sample Size of 100 TPS3703A7125 units
Figure 7-6. Overvoltage Accuracy Distribution
0.6
0.6
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
0.58
0.56
0.54
0.52
0.5
0.58
0.56
0.54
0.52
0.5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D005
D006
Tested across multiple voltage options
Tested across multiple voltage options
Figure 7-7. Undervoltage Hysteresis Voltage Accuracy vs
Temperature
Figure 7-8. Overvoltage Hysteresis Voltage Accuracy vs
Temperature
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7.8 Typical Characteristics (continued)
At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
7
6
5
4
3
2
6
5
4
VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V
VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V
3
2
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D007
D008
Output ( RESET Pin) = High
Figure 7-9. Supply Current vs Temperature
Output ( RESET Pin) = Low
Figure 7-10. Supply Current vs Temperature
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
-40èC
-40èC
25èC
25èC
125èC
125èC
0
5
10 15 20 25 30 35 40 45 50 55
Overdrive (%)
0
5
10 15 20 25 30 35 40 45 50 55
Overdrive (%)
D009
D010
VDD = 1.7 V
VDD = 1.7 V
Figure 7-11. SENSE Glitch Immunity (VIT-) vs Overdrive
Figure 7-12. SENSE Glitch Immunity (VIT+) vs Overdrive
9
9
-40èC
25èC
125èC
-40èC
25èC
125èC
8
8
7
6
5
4
3
7
6
5
4
3
0
5
10 15 20 25 30 35 40 45 50 55
Overdrive (%)
0
5
10 15 20 25 30 35 40 45 50 55
Overdrive (%)
D011
D012
VDD = 5.5 V
VDD = 5.5 V
Figure 7-13. SENSE Glitch Immunity (VIT-) vs Overdrive
Figure 7-14. SENSE Glitch Immunity (VIT+) vs Overdrive
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7.8 Typical Characteristics (continued)
At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
0.3
0.25
0.2
0.15
0.1
0.05
0
0.25
0.2
0.15
0.1
-40èC
-40èC
25èC
125èC
0.05
25èC
125èC
0
0
1
2
3
4
5
0
1
2
3
4
5
IRESET (mA)
IRESET (mA)
D013
D014
VDD = 1.7 V
VDD = 5.5 V
Figure 7-15. Low-Level Output Voltage vs RESET current
Figure 7-16. Low-Level Output Voltage vs RESET current
0.6
1.16
VMR_H
VMR_L
VMR_H
VMR_L
1.14
1.12
1.1
0.5
0.4
0.3
1.08
1.06
1.04
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D016
D015
VDD = 5.5 V
VDD = 1.7 V
Figure 7-18. SET Threshold vs Temperature
Figure 7-17. SET Threshold vs Temperature
390
3.5
3
25°C
-40°C
125°C
385
380
375
370
365
2.5
2
1.5
1
1.7 V
5.5 V
0.5
0
-50
-25
0
25
50
75
100
125
0.1 0.2 0.5
1
2 3 45 7 10 2030 50 100 200 5001000
Capacitor Value (nF)
Temperature (èC)
D017
tD_r
Figure 7-19. CT Current vs CT value
Figure 7-20. RESET Timeout vs CT Capacitor
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7.8 Typical Characteristics (continued)
At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
35
12
10
8
25°C
-40°C
125°C
30
25
20
15
10
5
6
4
VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V
2
0
0
-50
-25
0
25
50
75
100
125
0.1
0.2 0.3
0.5 0.7
1
2
Capacitor Value (nF)
3
4 5 6 7 8 10
Temperature (èC)
D020
tD_r
Figure 7-22. Detect Propagation Delay vs Temperature
Figure 7-21. Timeout vs CT Capacitor (0.1 to 10 nF)
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8 Detailed Description
8.1 Overview
The TPS3703 family of devices combines two voltage comparators and a precision voltage reference for
overvoltage and undervoltage detection. The TPS3703 features a highly accurate window threshold voltages
(±0.7% over temperature) and a variety voltage threshold variants.
The TPS3703 includes the resistors used to set the overvoltage and undervoltage thresholds internal to the
device. These internal resistors allow for lower component counts and greatly simplifies the design because no
additional margins are needed to account for the accuracy of external resistors.
TPS3703 version A, B and C has three time delay settings, two fixed by connecting CT pin to VDD through a
resistor and leaving CT floating and a programmable time delay setting that only requires a single capacitor
connected from CT pin to ground.
Manual Reset (MR) allows for sequencing or hard reset by driving the MR pin below VMR_L
.
The TPS3703 is designed to assert active low output signals when the monitored voltage is outside the safe
window. The relationship between the monitored voltage and the states of the outputs is shown in Table 8-1.
8.2 Functional Block Diagram
VDD
CT
VDD
CT
VCT
VCT
50mV
50mV
ICT
ICT
Cap
Control
Cap
Control
SENSE
SENSE
UV Comparator
UV Comparator
Vref_OV
Time Delay
Logic
RESET
Time Delay
Logic
RESET
Vref
Vref
Vref_UV
VDD
VDD
OV Comparator
RMR
RMR
GND
GND
MR
MR
Window Version
Undervoltage Only Version
*For all possible voltages, window tolerance, time delays, and UV threshold options, see Table 12-1.
8.3 Feature Description
8.3.1 VDD
The TPS3703 is designed to operate from an input voltage supply range between 1.7 V to 5.5 V. An input supply
capacitor is not required for this device; however, if the input supply is noisy good analog practice is to place a 1-
µF capacitor between the VDD pin and the GND pin.
VDD needs to be at or above VDD(MIN) for at least the start-up delay (tSD+ tD) for the device to be fully functional.
8.3.2 SENSE
The TPS3703 combines two comparators with a precision reference voltage and a trimmed resistor divider. This
configuration optimizes device accuracy because all resistor tolerances are accounted for in the accuracy and
performance specifications. Both comparators also include built-in hysteresis that provides noise immunity and
ensures stable operation.
Although not required in most cases, for noisy applications good analog design practice is to place a 1-nF to 10-
nF bypass capacitor at the SENSE input in order to reduce sensitivity to transient voltages on the monitored
signal.
When monitoring VDD supply voltage, the SENSE pin can be connected directly to VDD. The output (RESET) is
high impedance when voltage at the SENSE pin is between upper and lower boundary of threshold.
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8.3.3 RESET
In a typical TPS3703 application, the RESET output is connected to a reset or enable input of a processor [such
as a digital signal processor (DSP), application-specific integrated circuit (ASIC), or other processor type] or the
enable input of a voltage regulator [such as a DC-DC converter or low-dropout regulator (LDO)].
The TPS3703 has an open drain active low output that requires a pull-up resistor to hold these lines high to the
required voltage logic. Connect the pull-up resistor to the proper voltage rail to enable the output to be
connected to other devices at the correct interface voltage levels. To ensure proper voltage levels, give some
consideration when choosing the pull-up resistor values. The pull-up resistor value is determined by VOL, output
capacitive loading, and output leakage current. These values are specified in Section 7.5. The open drain output
can be connected as a wired-OR logic with other open drain signals such as another TPS3703 RESET pin.
Table 8-1 describes the scenarios when the output (RESET) is either asserted low or high impedance.
VIT+(OV)
OV Limit
VIT+(OV) - VHYS
VSENSE
VIT-(UV) + VHYS
UV Limit
VIT-(UV)
RESET
tD
tPD
tD
tPD
Figure 8-1. RESET output
8.3.4 Capacitor Time (CT)
The CT pin provides the user the functionality of both high-precision, factory-programmed, reset delay timing
options and user-programmable, reset delay timing. The CT pin can be pulled up to VDD through a resistor, have
an external capacitor to ground, or can be left unconnected. The configuration of the CT pin is re-evaluated by
the device every time the voltage on the SENSE line enters the valid window (VIT-(UV) < VSENSE < VIT+(OV)). The
pin evaluation is controlled by an internal state machine that determines which option is connected to the CT pin.
The sequence of events takes 450 μs to determine if the CT pin is left unconnected, pulled up through a resistor,
or connected to a capacitor. If the CT pin is being pulled up to VDD, then a pull-up resistor is required, 10 kΩ is
recommended.
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8.3.5 Manual Reset (MR)
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR
causes RESET to assert. After MR returns to a logic high and the SENSE pin voltage is within a valid window ((V
IT-(UV) < VSENSE < VIT+(OV)), RESET is deasserted after the reset delay time (tD). If MR is not controlled externally,
then MR can either be connected to VDD or left floating because the MR pin is internally pulled up to VDD. Figure
8-2 shows the relation between MR and RESET.
VIT+(OV)
Hysteresis
VIT+(OV) - VHYS
SENSE
VIT-(UV) + VHYS
Hysteresis
VIT-(UV)
Pulse < VMR_L
Pulse < tGI (MR)
MR
VMR_H
VMR_L
tMR_W
RESET
tD(MR)
tPD (MR)
A. RESET pulls up to VDD with 10 kΩ.
B. To initiate and continue time reset counter both conditions must be met MR pin above VMR_H or floating and VSENSE between VIT-(UV) + V
HYS and VIT+(OV) - VHYS
C. MR is ignored during output RESET low event
Figure 8-2. Manual Reset Timing Diagram
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8.4 Device Functional Modes
Table 8-1. Functional Mode Truth Table
OUTPUT
(RESET PIN)
DESCRIPTION
CONDITION
VIT–(UV) < SENSE < VIT+(OV)
SENSE > VIT-(UV)
MR PIN
VDD PIN
Normal Operation
Open or above VMR_H
Open or above VMR_H
VDD > VDD(MIN)
VDD > VDD(MIN)
VDD > VDD(MIN)
VDD > VDD(MIN)
High
High
Normal Operation
(UV Only)
Over Voltage
detection
SENSE > VIT+(OV)
SENSE < VIT-(UV)
Open or above VMR_H
Open or above VMR_H
Low
Low
Under Voltage
detection
Manual reset
VIT–(UV) < SENSE < VIT+(OV)
VIT–(UV) < SENSE < VIT+(OV)
Below VMR_L
VDD > VDD(MIN)
Low
Low
UVLO engaged
Open or above VMR_H
VPOR < VDD < UVLO
8.4.1 Normal Operation (VDD > VDD(MIN)
)
When the voltage on VDD is greater than VDD(MIN) for approximately (tSD+ tD), the RESET output state will
correspond to the SENSE pin voltage with respect to the threshold limits, when SENSE voltage is outside of
threshold limits the RESET voltage will be low (VOL).
8.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage but greater than the power-on reset voltage (V
POR), the RESET pin will be held low , regardless of the voltage on SENSE pin.
8.4.3 Power-On Reset (VDD < VPOR
)
When the voltage on VDD is lower than the required voltage (VPOR) to internally pull the asserted output to GND,
RESET signal is undefined and is not to be relied upon for proper device function.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Voltage Threshold Accuracy
Voltage monitoring requirements vary depending on the voltage supply tolerance of the device being powered.
Due to the high precision of the TPS3703 (±0.7% Max), the device allows for a wider supply voltage margins and
threshold headroom for tight tolerance applications.
For example, take a DC/DC regulator providing power to a core voltage rail of an MCU. The MCU has a
tolerance of ±5% of the nominal output voltage of the DC/DC. The user sets an ideal voltage threshold of ±4%
which allows for ±1% of threshold accuracy. Since the TPS3703 threshold accuracy is higher than ±1%, the user
has more supply voltage margin which can allow for a relaxed power supply design. This gives flexibility to the
DC/DC to use a smaller output capacitor or inductor because of a larger voltage window for voltage ripple and
transients. There is also headroom between the minimum system voltage and voltage tolerance of the MCU to
ensure that the voltage supply will never be in the region of potential failure of malfunction without the TPS3703
asserting a reset signal.
Figure 9-1 illustrates the supply undervoltage margin and accuracy of the TPS3703 for the example explained
above. Using a low accuracy supervisor will eat into the available budget for the power supply ripple and
transient response. This gives less flexibility to the user and a more stringent DC/DC converter design.
DC/DC nominal output
0%
Supply
Regulator output voltage accuracy
Voltage
Margin
Margin for ripple and transients
Voltage
Threshold
Accuracy
0.7% Allowed threshold tolerance
+
4%
5%
- 0.7% Minimum system voltage
Potential Failure or Malfunction
Figure 9-1. TPS3703 Voltage Threshold Accuracy
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9.1.2 CT Reset Time Delay
The TPS3703 features three options for setting the reset delay (t D): connecting a capacitor to the CT pin,
connecting a pull-up resistor to VDD, and leaving the CT pin unconnected. Figure 9-2 shows a schematic
drawing of all three options. To determine which option is connected to the CT pin, an internal state machine
controls the internal pulldown device and measures the pin voltage. This sequence of events takes 450 μs to
determine which timing option is used. Every time the voltage on the SENSE line enters the valid window (V
IT-(UV) + VHYS < VSENSE < VIT+(OV) -VHYS, the state machine determines the CT option.
VDD
VDD
VDD
VDD
VDD
VDD
CT
ICT
ICT
ICT
CT
CT
Cap
Control
Cap
Control
Cap
Control
User Programmable
Capacitor to GND
CT Unconnected
10 kΩ Resistor to VDD
Figure 9-2. CT Charging Circuit
9.1.2.1 Factory-Programmed Reset Delay Timing
To use the factory-programmed timing options, the CT pin must either be left unconnected or pulled up to VDD
through a 10 kΩ pull-up resistor. Using these options enables a high-precision reset delay timing, as shown in
Table 9-1.
Table 9-1. Reset Delay Time for Factory-Programmed Reset Delay Timing
RESET DELAY TIME (tD)
VARIANT
VALUE
CT = Capacitor to GND
Programmable tD
Programmable tD
Programmable tD
N/A
CT = Floating
CT = 10 kΩ to VDD
TPS3703A
TPS3703B
TPS3703C
TPS3703D
10
1
200
20
ms
ms
ms
µs
5
100
50
50
9.1.2.2 Programmable Reset Delay-Timing
The TPS3703 reset time delay is based on internal current source (ICT) to charge external capacitor (CCT) and
read capacitor voltage with internal comparator. The minium value capacitor is 250 pF. There is no limitation on
maximum capacitor the only constrain is imposed by the initial voltage of the capacitor, if CT cap is zero or near
to zero then ideally there is no other constraint on the max capacitor. The typical ideal capacitor value needed
for a given delay time can be calculated using Equation 1, where CCT is in nanofarads (nF) and tD is in ms:
tD = 3.066 × CCT + 0.5 ms
(1)
To calculate the minimum and maximum-reset delay time use Equation 2 and Equation 3, respectively.
tD(min) = 2.7427 × CCT + 0.3 ms
tD(max) = 3.4636 × CCT + 0.7 ms
(2)
(3)
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The slope of the equation is determined by the time the CT charging current (ICT) takes to charge the external
capacitor up to the CT comparator threshold voltage (V CT). When RESET is asserted, the capacitor is
discharged through the internal CT pulldown resistor. When the RESET conditions are cleared, the internal
precision current source is enabled and begins to charge the external capacitor; when VCT = 1.15 V, RESET is
unasserted. Note that in order to minimize the difference between the calculated RESET delay time and the
actual RESET delay time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize
parasitic board capacitance around this pin. Table 9-2 lists the reset delay time ideal capacitor values for CCT
.
Table 9-2. Reset Delay Time for Ideal Capacitor Values
CCT
250 pF
1 nF
RESET DELAY TIME (tD), TYPICAL
1.27 ms
3.57 ms
3.26 nF
32.6 nF
65.2 nF
1uF
10.5 ms
100.45 ms
200.40 ms
3066.50 ms
9.1.3 RESET Latch Mode
The TPS3703 features a voltage latch mode on the RESET pin when connecting the CT pin to common ground .
A pull-down resistor is recommended to limit current consumption of the system. In latch mode, if the RESET pin
is low or triggers low, the pin will stay low regardless if VSENSE is within the acceptable voltage boundaries (V
IT–(UV) < VSENSE < VIT+(OV)). To unlatch the device provide a voltage to the CT pin that is greater than the CT pin
comparator threshold voltage, VCT. The RESET pin will trigger high instantaneously without any reset delay. A
voltage greater than 1.2 V to recommended to ensure a proper unlatch. Use a series resistance to limit current
when an unlatch voltage is applied. For more information, Section 9.2.2 gives an example of a typical latch
application.
VDD
VDD
ICT
10 kꢀ
CT
V > VCT
Voltage at CT
to Unlatch
Cap
Control
10 kꢀ Resistor to
GND to Latch
Figure 9-3. RESET Latch Circuit
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9.1.4 Adjustable Voltage Thresholds
The TPS3703 0.7% maximum accuracy allows for adjustable voltage thresholds using external resistors without
adding major inaccuracies to the device. In case that the desired monitored voltage is not available, external
resistor dividers can be used to set the desired voltage thresholds. Figure 9-4 illustrates an example of how to
adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the
desired voltage threshold and device part number. TI recommends using the 0.8V voltage threshold device such
as the TPS3703B3080 because of the bypass mode of internal resistor ladder.
For example, consider a 2.0 V rail being monitored (VMON) using the TPS3703B3080 variant. Using Equation 4,
R1 = 15 kΩ given that R2 = 10 kΩ, VMON = 2 V, and VSENSE = 0.8 V. This device is typically meant to monitor a
0.8 V rail with ±3% voltage thresholds. This means that the device undervoltage threshold (V IT-(UV)) and
overvoltage threshold (VIT-(OV)) is 0.776 V and 0.824 V respectively. Using Equation 4, VMON = 1.94 V when V
= VIT-(UV). This can be denoted as VMON-, the monitored undervoltage threshold where the device will
SENSE
assert a reset signal. Using Equation 4 again, the monitored overvoltage threshold (VMON+) = 2.06 V when V
SENSE = VIT+(OV). If a wider tolerance or UV only threshold is desired, use a device variant shown on Table 12-1
to determine what device part number matches your application.
VSENSE = VMON × (R2 ÷ (R1 + R2))
(4)
There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the
tolerance of the resistor divider, there is an internal resistance of the SENSE pin that may affect the accuracy of
the resistor divider. Although expected to be very high impedance, users are recommended to calculate the
values for design specifications. The internal sense resistance (RSENSE) can be calculated by the sense voltage
(VSENSE) divided by the sense current (ISENSE) as shown in Equation 6. VSENSE can be calculated using
Equation 4 depending on the resistor divider and monitored voltage. ISENSE can be calculated using Equation 5.
ISENSE = (VMON – VSENSE) ÷ R1 – (VSENSE ÷ R2)
(5)
(6)
RSENSE = VSENSE ÷ ISENSE
VMON
VDD
R1
10 lQ
TPS3703
Vsense
SENSE
RESET
VDD
VDD
CT
MR
R2
GND
Figure 9-4. Adjustable Voltage Threshold with External Resistor Dividers
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9.1.5 Immunity to SENSE Pin Voltage Transients
The TPS3703 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends on
both transient duration and overdrive (amplitude) of the transient.
Overdrive is defined by how much the V SENSE exceeds the specified threshold, and is important to know
because the smaller the overdrive, the slower the response of the outputs (RESET). Threshold overdrive is
calculated as a percent of the threshold in question, as shown in Equation 7:
Overdrive % = | (VSENSE - (VIT-(UV) or VIT+(OV))) / VIT (Nominal) × 100% |
(7)
where:
•
•
•
VSENSE is the voltage at the SENSE pin
VIT (Nominal) is the nominal threshold voltage
VIT-(UV) and VIT+(OV) represent the actual undervoltage or overvoltage tripping voltage
9.1.5.1 Hysteresis
Overvoltage and undervoltage comparators include built-in hysteresis that provides noise immunity and ensures
stable operation. For example if the voltage on the SENSE pin falls below VIT-(UV) or above VIT+(OV), then RESET
is asserted (driven low), then when the voltage on the SENSE pin is between the positive and negative threshold
voltages, RESET deasserts after the user-defined RESET delay time. Figure 9-5 shows the relation between V
IT-(UV),VIT+(OV) and hysteresis voltage (VHYS).
VRESET
Window
(VIT)
VOL
VSENSE
VIT-(UV)
VIT-(UV) + VHYS
VIT+(OV) - VHYS
VIT+(OV)
Figure 9-5. SENSE Pin Hysteresis
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9.2 Typical Application
9.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails
A typical application for the TPS3703 is shown in Figure 9-6. The TPS3703 is used to monitor two PMIC voltage
rails that powers the core and I/O voltage of the microcontroller that requires accurate reset delay and voltage
supervision. It utilizes the TPS3703 to monitor the core voltage rail of a MCU similar to the circuit below.
VDD
VOUT
VOUT
VCORE
VI/O
VIN
VDD
10 lQ
PMIC
Microcontroller
RESET
TPS3703
TPS3703
SENSE
VDD
CT
RESET
MR
SENSE
VDD
CT
RESET
MR
VDD
VDD
GND
GND
10 lQ
Figure 9-6. Two TPS3703 Monitoring Two Microcontroller Power Rails
9.2.1.1 Design Requirements
Table 9-3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
3.3-VI/O nominal, with alerts if outside of ±8% of 3.3
V (including device accuracy), 200 ms reset delay
Worst case VIT+(OV) = 3.554 V (7.7%),
Worst case VIT–(UV) = 3.046 V (-7.7%)
Monitored rails
1.2-VCORE nominal, with alerts if outside of ±5% of
1.2 V (including device accuracy), 10 ms reset
delay
Worst case VIT+(OV) = 1.256 V (4.7%),
Worst case VIT–(UV) = 1.144 V (-4.7%)
Output logic voltage
5-V CMOS
50 µA
5-V CMOS
Maximum system supervision
current consumption
14 µA (7 µA Max each)
9.2.1.2 Detailed Design Procedure
Determine which version of the TPS3703 best suits the monitored rail (VMON) and window tolerances found on
Table 12-1. The TPS3703 allows overvoltage and undervoltage monitoring for precise voltage supervision of
common rails between 0.5 V and 5.0 V. This application calls for very tight monitoring of the rail with only ±5% of
variation allowed on the 1.2V core rail. To ensure this requirement is met, the TPS3703 was chosen for its ±4%
thresholds. The 3.3V I/O is more flexible and can operate up to 8% variance. Since the TPS3703 comes in
various tolerance options, the ±7% thresholds can be chosen for this voltage rail. To calculate the worst-case for
VIT+(OV) and VIT-(UV), the accuracy must also be taken into account. The worst-case for VIT+(OV) and VIT-(UV) can
be calculated shown in Equation 8 and Equation 9 respectively:
VIT+(OV-Worst Case) = VMON × (%Threshold + 0.7%) = 1.2 × (+4.7%) = 1.256 V
VIT-(UV-Worst Case) = VMON × (%Threshold - 0.7%) = 1.2 × (-4.7%) = 1.144V
(8)
(9)
When the outputs switch to a high impedance state, the rise time of the RESET pin depends on the pull-up
resistance and the capacitance on that node. Choose pull-up resistors that satisfy both the downstream timing
requirements and the sink current required to have a VOL low enough for the application; 10 kΩ to 1 MΩ resistors
are a good choice for low-capacitive loads.
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9.2.1.3 Application Curves
VSENSE Start up from 0 V to 1.2 V, VDD = 3.3 V, CT = OPEN
VRESET = VDD = 3.3 V, TPS3703A4120
VDD Start up from 0 V to 3.3 V, VSENSE = 1.2 V, CT = OPEN
VRESET = VDD = 3.3 V, TPS3703A4120
Figure 9-7. TPS3703 SENSE Start Up Function
Figure 9-8. TPS3703 VDD Start Up Function
VSENSE ramp from 0 V to 1.4 V, VDD = 3.3 V, CT = OPEN
VRESET = VDD = 3.3 V, TPS3703A4120
VDD ramp from 0 V to 3.3 V, VSENSE = 1.2 V, CT = OPEN
VRESET = VDD = 3.3 V,TPS3703A4120
Figure 9-9. TPS3703 Overvoltage and Undervoltage
Function
Figure 9-10. TPS3703 VDD Ramp Up Function
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9.2.2 Design 2: RESET Latch Mode
Another typical application for the TPS3703 is shown in Figure 9-11. The TPS3703 is used in a RESET latch
output mode. In latch mode, once RESET driven logic low, it will stay low regardless of the sense voltage. If the
RESET pin is low on start up, it will also stay low regardless of sense voltage.
VCORE
VCORE
VDD
Microcontroller
10 lQ
TPS3703
VGPIO
SENSE
VDD
CT
RESET
MR
VDD
Microcontroller
10 lQ
VGPIO
GND
10 lQ
Figure 9-11. Window Voltage Monitoring with RESET Latch
9.2.2.1 Design Requirements
Table 9-4. Design Parameters
PARAMETER
Monitored Rail
DESIGN REQUIREMENT
DESIGN RESULT
1.2-VCORE nominal, with alerts if outside of ±5% of
1.2 V (including device accuracy), Latch when
RESET is low, until voltage is applied on CT pin.
Worst case VIT+(OV) = 1.256 V (4.7%),
Worst case VIT–(UV) = 1.144 V (-4.7%)
Output logic voltage
5-V CMOS
15 µA
5-V CMOS
Maximum device current
consumption
4.5 µA (Typ), 7 µA (Max)
9.2.2.2 Detailed Design Procedure
The RESET pin can be latched when the CT pin is connected to a common ground with a pull-down resistor. A
10 kΩ resistors is recommended to limit current consumption. To unlatch the device provide a voltage to the CT
pin that is greater than the CT pin comparator threshold voltage, V CT. A voltage greater than 1.15 V to
recommended to ensure a proper unlatch. Use a series resistance to limit current when an unlatch voltage is
applied. To go back into latch operation, disconnect the voltage on the CT pin. The RESET pin will trigger high
instanously without any reset delay.
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9.2.2.3 Application Curves
VSENSE ramp from 0 V to 1.4V, VDD = 3.3 V, VCT = 0 V
VRESET = VDD = 3.3 V, TPS3703A4120
VCT biased at least to 1.15 V , VSENSE = 1.2 V
VRESET = VDD = 3.3 V, TPS3703A4120
Figure 9-12. TPS3703 SENSE Ramp Latch Function
Figure 9-13. TPS3703 CT Bias Unlatch Function
VSense ramp from 0 V to 1.4 V , VDD = 3.3 V, VRESET = VDD
CT is pulled down after RESET is low, RESET becomes
latched TPS3703A4120
VDD ramp up from 0 V to 3.3 V , VSENSE = 1.2 V, CT = 0 V
VRESET = VDD = 3.3 V, TPS3703A4120
Figure 9-15. TPS3703 VDD Ramp Latch Function
Figure 9-14. TPS3703 Overvoltage and
Undervoltage Latch Function
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10 Power Supply Recommendations
10.1 Power Supply Guidelines
This device is designed to operate from an input supply with a voltage range between 1.7 V to 5.5 V. It has a 6-V
absolute maximum rating on the VDD pin. It is good analog practice to place a 0.1-µF to 1-µF capacitor between
the VDD pin and the GND pin depending on the input voltage supply noise. If the voltage supply providing power
to VDD is susceptible to any large voltage transient that exceed maximum specifications, additional precautions
must be taken. See SNVA849 for more information.
11 Layout
11.1 Layout Guidelines
•
Place the external components as close to the device as possible. This configuration prevents parasitic errors
from occurring.
•
Avoid using long traces for the VDD supply node. The VDD capacitor, along with parasitic inductance from
the supply to the capacitor, can form an LC circuit and create ringing with peak voltages above the maximum
VDD voltage.
•
•
Avoid using long traces of voltage to the sense pin. Long traces increase parasitic inductance and cause
inaccurate monitoring and diagnostics.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
11.2 Layout Example
Pull-Up Voltage
V_Sense
VDD
MR
GND
Sense
VDD
CT
10 kΩ
RESET
1 …F
GND
Figure 11-1. Recommended Layout
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SBVS249B – MAY 2020 – REVISED NOVEMBER 2020
12 Device and Documentation Support
12.1 Device Nomenclature
Table 12-1 shows how to decode the function of the device based on its part number.
Table 12-1. Device Naming Convention
DESCRIPTION
NOMENCLATURE
VALUE
TPS3703
TPS3703
CT pin open = 10 ms, CT pin tied to VDD = 200 ms
CT programable with external capacitor
A
B
C
D
E
F
CT pin open = 1 ms, CT pin tied to VDD = 20 ms
CT programable with external capacitor
Window
(OV & UV)
CT pin open = 5 ms, CT pin tied to VDD = 100 ms
CT programable with external capacitor
CT pin open = 50 µs, CT pin tied to VDD = 50 µs
CT not programable
Time delay options: Every part
has two fixed time delay and
adjustable delay option via
CT pin open = 10 ms, CT pin tied to VDD = 200 ms
CT programable with external capacitor
external capacitor part number
CT pin open = 1 ms, CT pin tied to VDD = 20 ms
CT programable with external capacitor
UV only
CT pin open = 5 ms, CT pin tied to VDD = 100 ms
CT programable with external capacitor
G
H
CT pin open = 50 µs, CT pin tied to VDD = 50 µs
CT not programable
3
4
5
6
7
Window threshold from nominal value = OV : 3%; UV: –3%
Window threshold from nominal value = OV : 4%; UV: –4%
Window threshold from nominal value = OV : 5%; UV: –5%
Window threshold from nominal value = OV : 6%; UV: –6%
Window threshold from nominal value = OV : 7%; UV: –7%
Tolerance options: Trigger or threshold
voltage as a percentage of the monitored
threshold voltage
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Table 12-1. Device Naming Convention
(continued)
DESCRIPTION
NOMENCLATURE
VALUE
Nominal monitor threshold voltage option
050
055
060
065
070
075
080
085
090
095
100
105
110
115
120
125
130
150
180
250
280
290
330
500
DSE
R
0.50 V
0.55 V
0.60 V
0.65 V
0.70 V
0.75 V
0.80 V
0.85 V
0.90 V
0.95 V
1.00 V
1.05 V
1.10 V
1.15 V
1.20 V
1.25 V
1.30 V
1.50 V
1.80 V
2.50 V
2.80 V
2.90 V
3.30 V
5.00 V
Package
Reel
WSON - 6 pin (1.5 mm × 1.5 mm)
Large reel
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12.2 Documentation Support
12.2.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS3703.
The TPS3703 evaluation module (and related user guide) can be requested at the Texas Instruments website
through the product folders or purchased directly from the TI eStore .
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
P3703B6050DSER
ACTIVE
WSON
DSE
6
3000 RoHS (In work)
& Non-Green
Call TI
Call TI
-40 to 125
TPS3703A4080DSER
TPS3703A4110DSER
PREVIEW
ACTIVE
WSON
WSON
DSE
DSE
6
6
3000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
JQ
IL
TPS3703A4330DSER
ACTIVE
WSON
DSE
6
3000 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
JU
TPS3703A5075DSER
TPS3703A5085DSER
TPS3703A5120DSER
PREVIEW
PREVIEW
ACTIVE
WSON
WSON
WSON
DSE
DSE
DSE
6
6
6
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
JS
JR
J7
TPS3703A5180DSER
TPS3703A5330DSER
TPS3703A5500DSER
TPS3703A6330DSER
TPS3703A7330DSER
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
DSE
DSE
DSE
DSE
DSE
6
6
6
6
6
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
JT
J6
J8
JV
K5
NIPDAUAG
NIPDAUAG
NIPDAUAG
TPS3703B6050DSER
TPS3703F6050DSER
PREVIEW
PREVIEW
WSON
WSON
DSE
DSE
6
6
3000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
J9
JZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2020
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3703 :
Automotive: TPS3703-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3703A4110DSER
TPS3703A4330DSER
TPS3703A5180DSER
TPS3703A5500DSER
TPS3703A6330DSER
TPS3703A7330DSER
WSON
WSON
WSON
WSON
WSON
WSON
DSE
DSE
DSE
DSE
DSE
DSE
6
6
6
6
6
6
3000
3000
3000
3000
3000
3000
178.0
178.0
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
8.4
8.4
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
0.95
0.95
0.95
0.95
0.95
0.95
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3703A4110DSER
TPS3703A4330DSER
TPS3703A5180DSER
TPS3703A5500DSER
TPS3703A6330DSER
TPS3703A7330DSER
WSON
WSON
WSON
WSON
WSON
WSON
DSE
DSE
DSE
DSE
DSE
DSE
6
6
6
6
6
6
3000
3000
3000
3000
3000
3000
205.0
205.0
205.0
205.0
205.0
205.0
200.0
200.0
200.0
200.0
200.0
200.0
33.0
33.0
33.0
33.0
33.0
33.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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