TPS3704-Q1 [TI]

TPS3704x Quad, Triple, Dual, Single Window or Standard Voltage Supervisor;


型号：	TPS3704-Q1
厂家：	TEXAS INSTRUMENTS
描述：	TPS3704x Quad, Triple, Dual, Single Window or Standard Voltage Supervisor
文件：	总34页 (文件大小：3014K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS3704

SNVSBZ2B – MARCH 2021 – REVISED DECEMBER 2021

TPS3704x Quad, Triple, Dual, Single Window or Standard Voltage Supervisor

1 Features

3 Description

•

Designed for high performance and safety:

– Input current (4 channels): I_DD= 15 μA

(maximum)

– High threshold accuracy: ±1% (maximum)

– Built-in precision hysteresis:

V_HYS(V_IT> 800 mV) = 0.75% (typical)

Designed for a wide range of applications:

– Quad, triple, dual, or single voltage supervisor

The TPS3704x is a low-power precision window or

standard voltage supervisor that can be configured as

a quad, triple, dual, or single channel. Each channel

has a threshold accuracy of ±1% in an 8-pin

(1.6 mm x 2.9 mm) SOT-23 package offering a small

solution size. The TPS3704x includes a very accurate

threshold detection, with high resolution, that is ideal

for systems that operate on low-voltage supply rails

and have narrow margin supply tolerances. Built-in

low threshold hysteresis and a fixed reset delay (t_D

options from 20 μs to 1200 ms) prevent false reset

signals when monitoring multiple voltage rails.

•

TPS37044, 3, 2, 1: 4, 3, 2, 1 - channels

– Input voltage range, V_DD= 1.7 V to 6 V

– (UV / OV) threshold accuracy: ±0.1% (typical)

•

Each channel can be configured

independently: window, UV, or OV

Window tolerance: ±3% to ±11%

(can be programmed asymmetrical)

High threshold resolution:

The TPS3704x does not require any external

resistors for setting the over and under voltage

reset thresholds, which further optimizes overall high

accuracy, cost, solution size, and improves reliability

for safety systems.

V_IT≤ 0.8 V: 20 mV steps

V_IT> 0.8 V: lower of 0.5% or 20 mV steps

V_ITthreshold voltages for each individual

channel can be set independently

Separate VDD and SENSEx pins allow monitoring of

rail voltages other than VDD or can be used as a

push-button input. Optional use of external resistors

are supported by the SENSEx pins. Each channel on

the TPS3704x can be customized to its own over and

under voltage window detection with an upper and

lower threshold tolerance that can be symmetric or

asymmetric.

•

– Push-button monitor on all channels

– Reset time delay (t_D): fixed time delay options

Options: 23-fixed time options ranging from

20 µs (minimum) to 1200 ms (maximum)

– Temperature range: –40°C to +125°C

Multiple output topologies:

– TPS3704xxxO: open-drain, active-low (RESET)

– TPS3704xxxL: push-pull, active-low (RESET)

– TPS3704xxxH: push-pull, active-high (RESET)

•

Device Information

PART NUMBER

PACKAGE ⁽¹⁾

BODY SIZE (NOM)

TPS3704x

DDF (SOT-23 8-pin)

1.6 mm × 2.9 mm

2 Applications

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

Factory automation

Building automation

Medical

VDD

RESET1

RESET2

RESET3

R_{PULL_UP}

RESET

Microcontroller

Motor drives

TPS37043

Grid infrastructure

Wireless infrastructure

Data center & enterprise computing

SENSE1 SENSE2 SENSE3

3.3 V

1.8 V

24 V V_IN

Wide V_IN

Buck

V_I/O

D_VDD

DC/DC

1.2 V

V_CORE

Typical Application Circuit

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS3704

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SNVSBZ2B – MARCH 2021 – REVISED DECEMBER 2021

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Nomenclature......................................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings............................................................... 6

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................7

7.5 Electrical Characteristics.............................................7

7.6 Timing Requirements..................................................8

7.7 Timing Diagrams ........................................................9

7.8 Typical Characteristics.............................................. 11

8 Detailed Description......................................................15

8.1 Overview...................................................................15

8.2 Functional Block Diagram.........................................15

8.3 Feature Description...................................................17

8.4 Device Functional Modes..........................................19

9 Application and Implementation..................................20

9.1 Application Information............................................. 20

9.2 Typical Application.................................................... 22

10 Power Supply Recommendations..............................25

10.1 Power Supply Guidelines........................................25

11 Layout...........................................................................26

11.1 Layout Guidelines................................................... 26

11.2 Layout Example...................................................... 26

12 Device and Documentation Support..........................27

12.1 Device Nomenclature..............................................27

12.2 Receiving Notification of Documentation Updates..28

12.3 Support Resources................................................. 28

12.4 Trademarks.............................................................28

12.5 Electrostatic Discharge Caution..............................28

12.6 Glossary..................................................................28

13 Mechanical, Packaging, and Orderable

Information.................................................................... 28

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (July 2021) to Revision B (November 2021)

Page

•

Change from Advance Information to Production Data...................................................................................... 1

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5 Device Nomenclature

Figure 5-1 shows the device naming nomenclature to compare the different device variants. See Table 12-1 for a

more detailed explanation. See Table 12-2 for the available device variants.

TPS3704 X XX X X XXXR

DETECTION OPTIONS

Example:

** - Threshold (Tolerance%)

*J – Adjustable Variant

OUTPUT TYPE

RESET TIME DELAY PACKAGE

NUMBER OF CHANNELS

1: Single

2: Dual

3: Triple

4: Quad

O: Open Drain – Ac ve Low

L: Push Pull – Ac ve Low

H: Push Pull – Ac ve High

20 µs

1 ms

2 ms

3 ms

5 ms

DDF = SOT-23 8-pin

R = Large reel

A1 (Window)

CH1 = 3.4085 V / 3.184 V

CH2 = 1.245 V / 1.152 V

10 ms

15 ms

20 ms

25 ms

35 ms

40 ms

50 ms

70 ms

100 ms

140 ms

150 ms

200 ms

280 ms

400 ms

560 ms

800 ms

A2 (Window)

CH1 = 5.0 V (±4%)

...

A3 (Window)

CH1 = 3.3 V (±4%)

CH2 = 2.9 V (±4%)

CH3 = 1.8 V (±4%)

CH4 = 1.2 V (±4%)

…

AJ (Window) - Adjustable Variant

CH1 = 0.4 V (±4%)

CH2 = 0.8 V (±4%)

CH3 = 0.8 V (±4%)

CH4 = 0.8 V (±4%)

W: 1120 ms

X: 1200 ms

…

BJ (Window) - Adjustable Variant

CH1 = 0.8 V (±4%)

CH2 = 0.8 V (±4%)

CH3 = 0.8 V (±4%)

CH4 = 0.8 V (±4%)

…

Figure 5-1. Device Naming Nomenclature

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6 Pin Configuration and Functions

VDD

SENSE1

SENSE2

GND

VDD

SENSE1

RESET1

RESET2

GND

Not to scale

Figure 6-1. SOT-23 8-PIN DDF Package

Figure 6-2. SOT-23 8-PIN DDF Package

TPS37041

(Top View)

TPS37042

(Top View)

VDD

SENSE1

SENSE2

GND

VDD

SENSE1

SENSE2

GND

RESET1

RESET2

RESET3

SENSE3

RESET2

SENSE4

SENSE3

Not to scale

Figure 6-3. SOT-23 8-PIN DDF Package

Figure 6-4. SOT-23 8-PIN DDF Package

TPS37043

(Top View)

TPS37044

(Top View)

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Table 6-1. Pin Functions

I/O

DESCRIPTION

NAME TPS37041 TPS37042 TPS37043 TPS37044

VDD

Supply Input. Bypass with a 0.1 µF capacitor to GND.

Connect directly to monitored voltage. RESET1/RESET1 is asserted when

SENSE1 falls outside of window threshold. No external capacitor is required

for this SENSE1 pin. For TPS37044 (quad version) RESET1/RESET1

asserts when either SENSE1 or SENSE2 falls outside of window threshold.

For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close

to this pin may be needed for optimum performance. If the input pin is not

being used, it can be left floating.

SENSE1

Connect directly to monitored voltage. RESET2/RESET2 is asserted when

SENSE2 falls outside of window threshold. No external capacitor is required

for SENSE2 pin. For TPS37044 (quad version) RESET1/RESET1 asserts

when either SENSE1 or SENSE2 falls outside of window threshold. For

noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this

pin may be needed for optimum performance. If the input pin is not being

used, it can be left floating.

SENSE2

Connect directly to monitored voltage. RESET3/RESET3 is asserted when

SENSE3 falls outside of window threshold. No external capacitor is required

for SENSE3 pin. For TPS37044 (quad version) RESET2/RESET2 asserts

when either SENSE3 or SENSE4 falls outside of window threshold. For

noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this

pin may be needed for optimum performance. If the input pin is not being

used, it can be left floating.

SENSE3

SENSE4

Connect directly to monitored voltage. For TPS37044 (quad version)

RESET2/RESET2 asserts when either SENSE3 or SENSE4 falls outside of

window threshold. For noisy applications, placing a 10 nF to 100 nF ceramic

capacitor close to this pin may be needed for optimum performance. If the

input pin is not being used, it can be left floating.

RESET1/RESET1 asserts when SENSE1 falls outside of the over-voltage or

under-voltage threshold window.

RESET1/RESET1 stays asserted for the reset timeout period after SENSE1

fall back within the window threshold. Active-low, open-drain reset output,

requires an external pullup resistor. For TPS37044, RESET1/RESET1

asserts when either SENSE1 or SENSE2 fall outside of the window

threshold. The pin can be left floating if it is unused.

RESET1

RESET2/RESET2 asserts when SENSE2 falls outside of the overvoltage or

undervoltage threshold window.

RESET2/RESET2 stays asserted for the reset timeout period after SENSE2

fall back within the window threshold. Active-low, open-drain reset output,

requires an external pullup resistor. For TPS37044, RESET2/RESET2

asserts when either SENSE3 or SENSE4 fall outside of the window

threshold. The pin can be left floating if it is unused.

RESET2

RESET3/RESET3 asserts when SENSE3 falls outside of the overvoltage or

undervoltage threshold window.

RESET3/RESET3 stays asserted for the reset timeout period after SENSE3

fall back within the window threshold. Active-low, open-drain reset output,

requires an external pullup resistor. The pin can be left floating if it is

unused.

RESET3

GND

Ground

3, 5, 6, 7

5, 6

No Connect

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7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.3

MAX UNIT

V_DD

6.5

±20

Voltage

Current

V_RESET1, V_RESET2, V_RESET3

V_SENSE1,V_SENSE2, V_SENSE3, V_SENSE4

I_RESET1,I_RESET2,I_RESET3SINK

Continuous total power dissipation

Operating junction temperature, T_J

Operating free-air temperature, T_A

Storage temperature, T_stg

See the Thermal Information

-40

-65

150

°C

Temperature ⁽²⁾

(1) Stresses beyond values listed under Absolute Maximum Ratings (AMR) may cause permanent damage to the device. These are

stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to AMR-rated conditions for extended periods may affect device reliability.

(2) As a result of the low dissipated power in this device, it is assumed that T_J= T_A.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/

JEDEC JS-001 ⁽¹⁾

±2000

Electrostatic

discharge

V_(ESD)

Charged device model (CDM), per JEDEC

specification JESD22-C101 ⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process

7.3 Recommended Operating Conditions

MIN

1.7

NOM

MAX

6.0

UNIT

V_DD

Supply pin voltage

V_SENSE1,2,3,4

Input pin voltage

V_RESET1,V_RESET2,V_RESET3

I_RESET1, I_RESET2, I_RESET3SINK

T_A

Output pin voltage

Output pin current sink

Operating free air temperature

0.3

-40

℃

125

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7.4 Thermal Information

TPS3704x

THERMAL METRIC ⁽¹⁾

DDF

PINS

121.5

60.6

42.3

2.2

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JB

42.1

N/A

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

At 1.7 V ≤ V_DD≤ 6.0 V, RESETx Voltage (V_RESETx) = 10 kΩ to V_DD, RESETx load = 10 pF, and over the operating free-air

temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at T_A= 25°C, typical conditions at V_DD

3.3 V.

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

V_DD

Supply Voltage

1.7

1.2

6.0

1.6

UVLO

Under Voltage Lockout ⁽¹⁾

UVLO Hysteresis ⁽²⁾

V_DDfalling below 1.7 V

1.4

UVLO_(HYS)

V_POR

V_DDrising below 1.7 V

Power on reset voltage ⁽³⁾

Threshold Programming Range

UV accuracy (25℃)

V_{OL (MAX)}= 0.3 V, I_OUT= 15 µA

0.7

V_ITRange

V_{IT- (UV)}

V_{IT+ (OV)}

TOL_min

TOL_max

0.4

5.55

0.1

OV accuracy (25℃)

Tolerance Programming minimum

Tolerance Programming maximum

THR RES Low Threshold Programming Resolution Low V_IT≤ 0.8 V

THR RES Mid Threshold Programming Resolution Mid 0.8 V < V_IT≤ 4.0 V

Threshold Programming Resolution

0.5

mV / step

% / step

THR RES High

V_IT> 4.0 V

mV / step

High

Accuracy for absolute threshold

including tolerance

V_IT

V_IT< 0.8 V

-1.6

1.6

Accuracy for absolute threshold

including tolerance

V_IT= 0.8 V - 5.55 V

-1

V_HYS

I_DD

V_IT< 0.80V

1.1

1.4

1.7

V_IT≥ 0.80V

0.40 0.75

TPS3704x

V_DD≤ 6.0V

5.5

2.5

µA

I_SENSEx

Input current, SENSEx pin

V_SENSEx= 5.5 V

Input current, SENSE pin (Bypass

internal resistor divider)- Adjustible

version

I_{SENSE_ADJ}

V_SENSEx= 5.5 V

350

V_OL

I_(lkg)

Low level output voltage

VDD = 1.7 V, I_SINK= 0.4 mA

VDD = 2 V, I_SINK= 3 mA

VDD = 6.0 V, I_SINK= 5 mA

V_DD= V_RESETx= 6.0 V

300

350

Low level output voltage

Open drain output leakage current

(1) RESETx pin is driven low when V_DDfalls below UVLO.

(2) Hysteresis is with respect of the tripoint (V_{IT- (UV)}, V_{IT+ (OV)}).

(3) V_PORis the minimum V_DDvoltage level for a controlled output state. Slew rate = 100 mV / µs.

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7.6 Timing Requirements

At 1.7 V ≤ V_DD≤ 6.0 V, RESETx voltage (V_RESETx) = 10 kΩ to V_DD, RESETx load = 10 pF, and over the operating free-air

temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at T_A= 25°C, typical conditions at V_DD

3.3 V.

PARAMETER

Reset release time delay

Propagation detect delay ⁽¹⁾

TEST CONDITIONS

MIN NOM MAX UNIT

t_D

Fixed delay option t_D< 4 ms, overdrive = 10%

Fixed delay option t_D> 5 ms, overdrive = 10%

Fixed time delay t_D> 1 ms, overdrive 10%

-40

-30

t_D

t_PD

10 µs

µs

t_GI(VIT-)Glitch Immunity Undervoltage (5% overdrive) ⁽²⁾

t_GI(VIT+)Glitch Immunity Overvoltage (5% overdrive) ⁽²⁾

µs

t_R

Ouptut rise (Push-Pull) ^{(2) (3)}

Output rise time (Open-Drain) ^{(2) (3)}

Output fall time ^{(2) (3)}

2.2

0.2

t_R

µs

t_F

µs

t_STRT

Startup delay ⁽⁴⁾

(1) t_PDmeasured from threshold trip point (V_IT-(UV)or V_IT+(OV)) to RESETx V_OLvoltage

(2) 5% Overdrive from threshold. Overdrive % = [(V_SENSEx- V_IT) / V_IT]; Where V_ITstands for V_IT-(UV)or V_IT+(OV)

(3) Output transitions from V_OLto V_OHor (V_RESETx) for rise times and V_OHor (V_RESETx) to V_OLfor fall times.

(4) During the power-on sequence, V_DDmust be at or above V_DD(MIN)for at least t_STRT+ t_Dbefore the output is in the correct state. when

VDD is between V_DD(MIN)and VPOR the RESETx pin will be engaged

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7.7 Timing Diagrams

Highest Absolute Limit for the Monitored Voltage Rail

[1%]

V_IT+(OV)MAX

Accuracy band across

(-40ºC to 125ºC)

V_IT+(OV)[typical]

V_IT+(OV)MIN

[0.4% * (V_IT+(OV)MIN)]

Hys band for V_IT+(OV)

[V_HYSMAX= 1% * (V_IT+(OV)MIN)]

Power

Supply

Tolerance

Window

[V_HYSMAX= 1% * (V_IT-(UV)MIN)]

[0.4% * (V_IT-(UV)MIN)]

Hys band for V_IT-(UV)

[1%]

V_IT-(UV)MIN

[0.25%

Accuracy band across

(-40ºC to 125ºC)

]

V_IT-(UV)[typical]

[-0.25%]

V_IT-(UV)MAX

Lowest Absolute Limit for the Monitored Voltage Rail

Figure 7-1. Voltage Threshold and Hysteresis Accuracy

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V_DD(MIN)

UVLO

UVLO - UVLO_(HYS)

V_DD

V_POR

V_IT+(OV)

Hysteresis

V_IT+(OV)- V_HYS

SENSEx

V_IT

V_IT-(UV)+ V_HYS

V_IT-(UV)

Hysteresis

*See

Note C

RESETx

(-O: open-drain)

t_STRT+ t_D

t_PD

t_D

t_PD

t_D

A. Open-Drain timing diagram assumes the RESETx / RESETx pin is connected via an external pull-up resistor to VDD.

B. Be advised that Figure 7-2 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (t_PD) time.

C. RESETx/RESETx is asserted after a time delay, typical value of 100 μs, when VDD goes below the UVLO-UVLO_(HYS)threshold.

Figure 7-2. SENSEx Timing Diagram

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7.8 Typical Characteristics

Typical characteristics show the typical performance of the TPS3704x device. Test conditions are T_A= 25°C, V_DD= 3.3 V,

and R_pull-upx= 10 kΩ, C_LOAD= 50 pF, unless otherwise noted.

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

CH 1 - 5.0 V

CH 2 - 1.8 V

CH 3 - 0.8 V

CH 4 - 0.4 V

CH 1 - 5.0 V

CH 2 - 1.8 V

CH 3 - 0.8 V

CH 4 - 0.4 V

-50

-25

100

125

-50

-25

100

125

Temperature (èC)

UV_a

OV_a

Figure 7-3. Undervoltage Accuracy vs Temperature

Figure 7-4. Overvoltage Accuracy vs Temperature

1.80

1.70

1.60

1.50

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

1.80

1.70

1.60

1.50

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

CH 1 - 5.0 V

CH 2 - 1.8 V

CH 3 - 0.8 V

CH 4 - 0.4 V

CH 1 - 5.0 V

CH 2 - 1.8 V

CH 3 - 0.8 V

CH 4 - 0.4 V

-50

-25

100

125

-50

-25

100

125

Temperature (èC)

UV_H

OV_H

Figure 7-5. Undervoltage Hysteresis Voltage Accuracy vs

Temperature

Figure 7-6. Overvoltage Hysteresis Voltage Accuracy vs

Temperature

0.06

VDD = 3.3 V

-40èC

25èC

125èC

0.05

0.04

0.03

0.02

0.01

-50

-25

100

125

150

0.001

0.002

0.003

0.004

0.005

0.006

0.007

VOLV

Temperature (èC)

I_RESET1(A)

IDD_

Output ( RESETx Pin) = High

Figure 7-7. Supply Current vs Temperature

VDD = 1.7 V

Figure 7-8. Low-Level CH 1 Output Voltage vs RESET1 Current

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7.8 Typical Characteristics (continued)

Typical characteristics show the typical performance of the TPS3704x device. Test conditions are T_A= 25°C, V_DD= 3.3 V,

and R_pull-upx= 10 kΩ, C_LOAD= 50 pF, unless otherwise noted.

0.06

0.05

0.04

0.03

0.02

0.01

0.06

0.05

0.04

0.03

0.02

0.01

-40èC

25èC

125èC

-40èC

25èC

125èC

0.001

0.002

0.003

0.004

0.005

0.006

0.007

VOLV

0.001

0.002

0.003

0.004

0.005

0.006

0.007

VOLV

I_RESET1(A)

I_RESET2(A)

VDD = 5 V

VDD = 1.7 V

Figure 7-9. Low-Level CH 1 Output Voltage vs RESET1 Current Figure 7-10. Low-Level CH 2 Output Voltage vs RESET2 Current

0.06

0.05

0.04

0.03

0.02

0.01

0.06

0.05

0.04

0.03

0.02

0.01

-40èC

25èC

125èC

-40èC

25èC

125èC

0.001

0.002

0.003

0.004

0.005

0.006

0.007

VOLV

0.001

0.002

0.003

0.004

0.005

0.006

0.007

VOLV

I_RESET2(A)

I_RESET3(A)

VDD = 5 V

VDD = 1.7 V

Figure 7-11. Low-Level CH 2 Output Voltage vs RESET2 Current Figure 7-12. Low-Level CH 3 Output Voltage vs RESET3 Current

0.06

0.05

0.04

0.03

0.02

0.01

0.06

0.05

0.04

0.03

0.02

0.01

-40èC

25èC

125èC

-40èC

25èC

125èC

0.001

0.002

0.003

0.004

0.005

0.006

0.007

VOLV

0.001

0.002

0.003

0.004

0.005

0.006

0.007

VOLV

I_RESET3(A)

I_RESET4(A)

VDD = 5 V

VDD = 1.7 V

Figure 7-13. Low-Level CH 3 Output Voltage vs RESET3 Current Figure 7-14. Low-Level CH 4 Output Voltage vs RESET4 Current

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7.8 Typical Characteristics (continued)

Typical characteristics show the typical performance of the TPS3704x device. Test conditions are T_A= 25°C, V_DD= 3.3 V,

and R_pull-upx= 10 kΩ, C_LOAD= 50 pF, unless otherwise noted.

0.06

-40èC

-40^oC

25èC

25^oC

125èC

0.05

125^oC

0.04

0.03

0.02

0.01

0.001

0.002

0.003

0.004

0.005

0.006

0.007

VOLV

I_RESET4(A)

Overdrive (%)

VDD = 5 V

VDD = 1.7 V

Figure 7-15. Low-Level CH 4 Output Voltage vs RESET4 Current

Figure 7-16. SENSE1 Glitch Immunity (V_IT-) vs Overdrive

-40^oC

25^oC

-40^oC

25^oC

125^oC

Overdrive (%)

VDD = 1.7 V

VDD = 3.3 V

Figure 7-17. SENSE1 Glitch Immunity (V_IT+) vs Overdrive

Figure 7-18. SENSE1 Glitch Immunity (V_IT-) vs Overdrive

-40^oC

25^oC

-40^oC

25^oC

125^oC

Overdrive (%)

VDD = 3.3 V

VDD = 5 V

Figure 7-19. SENSE1 Glitch Immunity (V_IT+) vs Overdrive

Figure 7-20. SENSE1 Glitch Immunity (V_IT-) vs Overdrive

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7.8 Typical Characteristics (continued)

Typical characteristics show the typical performance of the TPS3704x device. Test conditions are T_A= 25°C, V_DD= 3.3 V,

and R_pull-upx= 10 kΩ, C_LOAD= 50 pF, unless otherwise noted.

-40^oC

25^oC

125^oC

Overdrive (%)

VDD = 5 V

Figure 7-21. SENSE1 Glitch Immunity (V_IT+) vs Overdrive

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8 Detailed Description

8.1 Overview

TPS3704x is a family of quad, triple, dual, and single precision voltage supervisors where each channel has

overvoltage and undervoltage detection capability. The TPS3704x features a highly accurate window threshold

voltage where the upper and lower thresholds can be customized for symmetric or asymmetric tolerances. The

reset signal for the TPS3704x is asserted, with a fault detection time delay (t_PD= 10 μs maximum), when the

sense voltage is outside of the overvoltage and undervoltage thresholds.

TPS3704x includes the resistors used to set the overvoltage and undervoltage thresholds internal to the

device. These internal resistors allow for lower component counts and greatly simplifies the design because

no additional margins are needed to account for the accuracy of external resistors. The level of integration in the

TPS3704x enables a total small solution size for any application.

The TPS3704x is capable to monitor any voltage rail with high resolution (V_IT≤ 0.8 V: 20 mV steps /

V_IT> 0.8 V: 0.5% or 20 mV steps whichever is lower). Each channel in the TPS3704x can be configured

independently as a window, OV or UV supervisor. Also, the V_ITthreshold voltage for each channel can be

asymmetric. For example, a channel that is configured as an overvoltage supervisor can be setup with a +5%

tolerance whereas an undervoltage channel supervisor can be programmed with a -4% tolerance. If a window

supervisor is configured, the voltage threshold tolerance can either be symmetrical or asymmetrical.

The TPS3704x includes fixed reset time delay (t_D) options ranging from 20 μs to 1200 ms and can monitor up to

four channels while maintaining an ultra-low I_Qcurrent of 15 μA (maximum).

8.2 Functional Block Diagram

POR

OTP

BANDGAP

OSCILLATOR

VDD

GND

VDD

VBG

CLK

–

VBG

UVLO

V_{REF_UVLO}

SENSE1

CLK

UNDERVOLTAGE

VBG

RESET1

TIME DELAY

(counter)

–

V_{REF_UV}

OTP_{UV_EN}

OTP_{OV_EN}

V_{REF_OV}

SENSE1

UVLO

–

OVERVOLTAGE

Figure 8-1. TPS37041 Single-Channel Functional Block Diagram

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POR

OTP

BANDGAP

OSCILLATOR

VDD

GND

VDD

VBG

CLK

VBG

UVLO

–

V_{REF_UVLO}

SENSE1

SENSE2

CLK

UNDERVOLTAGE

VBG

RESET1

RESET2

TIME DELAY

(counter)

–

V_{REF_UV}

OTP_{UV_EN}

OTP_{OV_EN}

V_{REF_OV}

SENSE1

UVLO

–

OVERVOLTAGE

Figure 8-2. TPS37042 Dual-Channel Functional Block Diagram

POR

OTP

BANDGAP

OSCILLATOR

VDD

GND

VDD

VBG

CLK

–

VBG

UVLO

V_{REF_UVLO}

SENSE1

SENSE2

SENSE3

CLK

UNDERVOLTAGE

VBG

RESET1

RESET2

RESET3

TIME DELAY

(counter)

–

V_{REF_UV}

OTP_{UV_EN}

OTP_{OV_EN}

V_{REF_OV}

SENSE1

UVLO

–

OVERVOLTAGE

Figure 8-3. TPS37043 Triple-Channel Functional Block Diagram

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POR

OTP

BANDGAP

OSCILLATOR

VDD

GND

VDD

VBG

CLK

–

VBG

UVLO

V_{REF_UVLO}

SENSE1

SENSE3

CLK

UNDERVOLTAGE

VBG

TIME DELAY

(counter)

–

V_{REF_UV}

OTP_{UV_EN}

OTP_{OV_EN}

V_{REF_OV}

SENSE1

UVLO

–

OVERVOLTAGE

RESET1

(SENSE1 and SENSE2)

RESET2

(SENSE3 and SENSE4)

SENSE2

SENSE4

CLK

UNDERVOLTAGE

VBG

TIME DELAY

(counter)

–

V_{REF_UV}

OTP_{UV_EN}

OTP_{OV_EN}

V_{REF_OV}

SENSE2

UVLO

–

OVERVOLTAGE

Figure 8-4. TPS37044 Quadruple-Channel Functional Block Diagram

*For available voltages, window tolerance, time delays, and UV/OV threshold options, see Table 12-2.

8.3 Feature Description

8.3.1 VDD

The TPS3704x is designed to operate from an input voltage supply range between 1.7 V to 6 V. The SENSEx

pins is monitored by the internal comparator. VDD also functions as the supply for the internal bandgap, internal

regulator, state machine, buffers and other control blocks. The reset signal is at a known state when VDD >

V_POR. Undervoltage lockout forces the reset output to be asserted when VDD falls below the minimum VDD

voltage.

VDD capacitor is not required for this device; however, if the input supply is noisy, then it is good design practice

to place a 0.1 μF to 1 µF bypass capacitor between the VDD pin and the GND pin to ensure enough charge is

available for the device to power up correctly. VDD needs to be at or above V_DD(MIN)for start-up delay

(t_STRT+ t_D) to begin and for the device to be fully functional.

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8.3.2 SENSEx Input

The SENSEx input can monitor supply rails from 0 V to 5.55 V, regardless of the device supply voltage used.

The SENSEx pins are used to monitor critical voltage rails or push-button inputs. If the voltage on this pin drops

below V_IT-(UV)or goes above V_IT+(OV), then RESETx/RESETx is asserted. When the voltage on the SENSEx pin

rises above the positive threshold voltage V_IT-(UV)+ V_HYSor goes below the negative threshold voltage V_IT+(OV)

V_HYS

RESETx/RESETx deasserts after the set RESETx/RESETx delay time. The internal comparators have built-in

hysteresis to ensure well-defined RESETx/RESETx assertions and deassertions even when there are small

changes on the voltage rail being monitored.

The TPS3704x combines comparators with a precision reference voltage and a trimmed resistor divider. This

configuration optimizes device accuracy because all resistor tolerances are accounted for in the accuracy and

performance specifications. The TPS3704x device is relatively immune to short transients on the SENSEx pin.

Although not required in most cases, for noisy applications, good analog design practice is to place a 10-nF

to 100-nF bypass capacitor at the SENSEx inputs to reduce sensitivity to transient voltages on the monitored

signals.

8.3.2.1 Immunity to SENSEx Pins Voltage Transients

The TPS3704x is immune to short voltage transient spikes on the input SENSEx pins. Sensitivity to transients

depends on both transient duration and overdrive (amplitude) of the transient.

Overdrive is defined by how much the V_SENSExexceeds the specified threshold, and is important to know

because the smaller the overdrive, the slower the response of the (RESETx/RESETx) outputs. Threshold

overdrive is calculated as a percent of the threshold in question, as shown in Equation 1:

Overdrive % = | (V_SENSEx- (V_IT-(UV)or V_IT+(OV))) / V_IT(Nominal) × 100% |

(1)

where:

•

V_SENSExis the voltage at the SENSEx pin

V_IT(Nominal) is the nominal threshold voltage

V_IT-(UV)and V_IT+(OV)represent the actual undervoltage or overvoltage tripping voltage

8.3.2.1.1 SENSEx Hysteresis

Overvoltage and undervoltage comparators include built-in hysteresis that provides noise immunity and ensures

stable operation. For example, if the voltage on the SENSEx pin falls below V_IT-(UV)or above V_IT+(OV), then

RESETx/RESETx is asserted. When the voltage on the SENSEx pin is between the positive and negative

threshold voltages, RESETx/RESETx deasserts after the set RESETx/RESETx delay time. Figure 8-5 shows the

relation between V_IT-(UV),V_IT+(OV)and the hysteresis voltage (V_HYS).

V_RESETx

Window

(V_IT)

VOL

V_SENSEx

VIT-(UV)

VIT-(UV) + VHYS

VIT+(OV) - VHYS

VIT+(OV)

Figure 8-5. SENSEx Pin Hysteresis

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8.3.3 RESETx/RESETx

In a typical TPS3704x application, the RESETx/RESETx output is connected to a reset or enable input of

a processor [such as a digital signal processor (DSP), application-specific integrated circuit (ASIC), or other

processor type] or the enable input of a voltage regulator [such as a DC-DC converter or low-dropout regulator

(LDO)].

The TPS3704x has open drain active low outputs that requires an external pull-up resistor to hold these lines

high to the required voltage logic. Connect the external pull-up resistor to the proper voltage rail to enable the

output to be connected to other devices at the correct interface voltage levels. To ensure proper voltage levels,

give some consideration when choosing the external pull-up resistor values. The external pull-up resistor value is

determined by V_OL, output capacitive loading, and output leakage current. These values are specified in

Section 7.5. The open drain output can be connected as a wired-OR logic with the other RESETx/RESETx open

drain pins.

V_IT+(OV)

OV Limit

V_IT+(OV)- V_HYS

V_SENSEx

V_IT-(UV)+ V_HYS

UV Limit

V_IT-(UV)

RESETx

t_D

t_PD

Figure 8-6. RESETx output

8.4 Device Functional Modes

Table 8-1. Functional Mode Truth Table

OUTPUT RESETx /

(RESETx) PIN

DESCRIPTION

CONDITION

VDD PIN

V_DD> V_DD(MIN)

Normal Operation

V_IT–(UV)< SENSEx < V_IT+(OV)

High / (Low)

Low / (High)

Normal Operation (UV Only) SENSEx > V_IT-(UV)

V_DD> V_DD(MIN)

V_POR< V_DD< UVLO

Over Voltage detection

Under Voltage detection

UVLO engaged

SENSEx > V_IT+(OV)

SENSEx < V_IT-(UV)

V_IT–(UV)< SENSEx < V_IT+(OV)

8.4.1 Normal Operation (V_DD> V_DD(MIN)

)

When the voltage on V_DDis greater than V_DD(MIN)for approximately (t_STRT+ t_D), the RESETx/RESETx output

state will correspond to the SENSEx pin voltage with respect to the threshold limits, when SENSEx voltage is

outside of threshold limits the RESETx/RESETx voltage will be asserted.

8.4.2 Undervoltage Lockout (V_POR< V_DD< UVLO)

When the voltage on V_DDis less than the device UVLO voltage but greater than the power-on reset voltage

(V_POR), the RESETx/RESETx pin will be asserted, regardless of the voltage on SENSEx pin.

8.4.3 Power-On Reset (V_DD< V_POR

)

When the voltage on V_DDis lower than the required voltage (V_POR) to internally pull the asserted output to GND,

RESETx/RESETx signal is undefined and is not to be relied upon for proper device function.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

9.1.1 Voltage Threshold Accuracy

Voltage monitoring requirements vary depending on the voltage supply tolerance of the device being powered.

Due to the high precision of the TPS3704x (±1% maximum), the device allows for a wider supply voltage

margins and threshold headroom for tight tolerance applications.

For example, take a DC/DC regulator providing power to a core voltage rail of an MCU. The MCU has a

tolerance of ±5% of the nominal output voltage of the DC/DC. The user sets an ideal voltage threshold of ±4%

which allows for ±1% of threshold accuracy. Since the TPS3704x threshold accuracy is ±1%, the user has more

supply voltage margin which can allow for a relaxed power supply design. This gives flexibility to the DC/DC to

use a smaller output capacitor or inductor because of a larger voltage window for voltage ripple and transients.

There is also headroom between the minimum system voltage and voltage tolerance of the MCU to ensure that

the voltage supply will never be in the region of potential failure of malfunction without the TPS3704x asserting a

reset signal.

Figure 9-1 illustrates the supply undervoltage margin and accuracy of the TPS3704x for the example explained

above. Using a low accuracy supervisor will eat into the available budget for the power supply ripple and

transient response. This gives less flexibility to the user and a more stringent DC/DC converter design.

DC/DC nominal output

Supply

Regulator output voltage accuracy

Voltage

Margin

Margin for ripple and transients

Voltage

Threshold

Accuracy

+ 1% Allowed threshold tolerance

- 1% Minimum system voltage

Potential Failure or Malfunction

Figure 9-1. TPS3704x Voltage Threshold Accuracy

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9.1.2 Adjustable Voltage Thresholds

The TPS3704x maximum accuracy (1%) allows for adjustable voltage thresholds using external resistors without

adding major inaccuracies to the device. In case that the desired monitored voltage is not available, external

resistor dividers can be used to set the desired voltage thresholds. Figure 9-2 illustrates an example of how to

adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the

desired voltage threshold and device part number. TI recommends using an adjustable voltage threshold device

variant because of the bypass mode of internal resistor ladder.

For example, consider a 2.0 V rail being monitored (V_MON) using the TPS3704 0.8 V adjustable variant. Using

Equation 2, R1 = 15 kΩ given that R2 = 10 kΩ, V_MON= 2 V, and V_SENSE1= 0.8 V. This device is typically meant

to monitor a 0.8 V rail with ±4% voltage thresholds. This means that the device undervoltage threshold (V_IT-(UV)

)

and overvoltage threshold (V_IT+(OV)) is 0.768 V and 0.832 V respectively. Using Equation 2, V_MON= 1.92 V

when V_SENSE1= V_IT-(UV). This can be denoted as V_MON-, the monitored undervoltage threshold where the device

will assert a reset signal. Using Equation 2 again, the monitored overvoltage threshold (V_MON+) = 2.08 V when

V_SENSE1= V_IT+(OV). If a wider tolerance or UV only threshold is desired, use a device variant shown on

Table 12-2 to determine what device part number matches your application.

V_SENSE1= V_MON× (R₂/ (R₁+ R₂))

(2)

There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the

tolerance of the resistor divider, there is an internal resistance of the SENSE1 pin that may affect the accuracy

of the resistor divider. Although expected to be very high impedance, users are recommended to calculate the

values for design specifications. The internal sense resistance R_SENSE1can be calculated by the sense voltage

V_SENSE1divided by the sense current I_SENSE1as shown in Equation 4. V_SENSE1can be calculated using

Equation 2 depending on the resistor divider and monitored voltage. I_SENSE1can be calculated using Equation 3.

I_SENSE1= [(V_MON– V_SENSE1) / R₁] – (V_SENSE1/ R₂)

R_SENSE1= V_SENSE1/ I_SENSE1

(3)

(4)

VDD

V_MON

10 k

VDD

RESET1

V_SENSE1

SENSE1

TPS37041

GND

Figure 9-2. Adjustable Voltage Threshold with External Resistor Dividers

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9.2 Typical Application

9.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails

A typical application for the TPS37042 is shown in Figure 9-3. The TPS37042 is used to monitor two PMIC

voltage rails that powers the core and I/O voltage of the microcontroller that requires accurate reset delay and

voltage supervision. It utilizes the TPS37042 to monitor the core voltage rail of a MCU similar to the circuit below.

VDD

V_OUT1

V_CORE

V_I/O

Microcontroller

V_IN

V_OUT2

VDD

PMIC

10 kΩ

RESET

VDD

TPS37042

VDD

RESET1

RESET2

SENSE1

SENSE2

GND

Figure 9-3. TPS37042 Dual-Channel Monitoring Two Microcontroller Power Rails

9.2.1.1 Design Requirements

Table 9-1. Design Requirements

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

3.3-V_I/Onominal, with alerts if outside of ±8% of 3.3 V

(including device accuracy), 10 ms reset delay

Worst case V_IT+(OV)= 3.533 V (7.06%)

Worst case V_IT–(UV)= 3.071 V (-6.94%)

Monitored rails

1.2-V_COREnominal, with alerts if outside of ±5% of 1.2 V Worst case V_IT+(OV)= 1.2484 V (4.03%)

(including device accuracy), 10 ms reset delay

Worst case V_IT–(UV)= 1.1524 V (-3.97%)

Output logic voltage

5-V CMOS

Maximum system supervision

current consumption

25 µA

5.5 µA (15 µA max)

9.2.1.2 Detailed Design Procedure

Determine which version of the TPS3704x best suits the monitored rail (V_MON) and window tolerances found on

Table 12-2. The TPS3704x allows overvoltage and undervoltage monitoring for precise voltage supervision of

common rails between 0.4 V and 5.55 V. This application calls for very tight monitoring of the rail with only ±5%

of variation allowed on the 1.2-V_CORErail. To ensure this requirement is met, the TPS37042 was chosen for its

±3% thresholds. The 3.3-V_I/Ois more flexible and can operate up to 8% variance. Since the TPS3704x comes in

various tolerance options, the ±6% thresholds can be chosen for this voltage rail. To calculate the worst-case for

V_IT+(OV)and V_IT-(UV), the accuracy must also be taken into account. The worst-case for V_IT+(OV)and V_IT-(UV)can

be calculated shown in Equation 5 and Equation 6 respectively:

V_{IT+(OV-Worst Case)}= V_MON× (1 + %Threshold ) × (1 + %Accuracy) = 1.2 × (1.03) × (1.01) = 1.2484 V

V_{IT-(UV-Worst Case)}= V_MON× (1 - %Threshold) × (1 - %Accuracy) = 1.2 × (0.97) × (0.99) = 1.1524V

(5)

(6)

Hysteresis is also needed to be taken into account when determining the OV and UV thresholds such that the

release point after the fault is higher than the power supply tolerance limits. Refer to Figure 7-1 for more details.

When the outputs switch to a high impedance state, the rise time of the RESETx/RESETx pin depends on the

pull-up resistance and the capacitance on that node. Choose pull-up resistors that satisfy both the downstream

timing requirements and the sink current required to have a V_OLlow enough for the application; 10 kΩ to 1 MΩ

resistors are a good choice for low-capacitive loads.

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9.2.2 Application Curves

These application curves were taken with the TPS3704Q1EVM. Please see the TPS3704Q1EVM User Guide for

more information.

VDD

t_D= 20.4 ms

RESET1

SENSE1

Reset Delay (t_D) = 21.2 ms

RESET1

RESET2

V_SENSE1start up 0 V to 3.3 V, V_DD= 3.3 V, V_RESET1= 3.3 V,

V_DDstart up 0 V to 3.3 V, V_SENSE1= 3.3 V, V_SENSE2= 1.8 V,

TPS37044A7OHDDFR

V_{SENSE3_4}= 1.15 V, V_{RESET1_2}= 3.3 V, TPS37044A7OHDDFR

Figure 9-4. TPS37044 SENSE1 Start Up Function

Figure 9-5. TPS37044 VDD Start Up Function

VDD

V_IT+(OV)

3.57 V

V_IT-(UV)

V_IT+(OV)

1.82 V

V_IT-(UV)

1.70 V

SENSE1

RESET1

SENSE2

RESET1

3.02 V

V_SENSE2ramp 0 V to 2 V, OV/UV Threshold = 1.8 V

(+4%, -3.5%), V_SENSE1= 3.3 V, V_DD= 3.3 V,

V_RESET1= 3.3 V, TPS37044A7OHDDFR

V_SENSE1ramp 0 V to 3.75 V, OV/UV Threshold = 3.3 V

(±8%), V_SENSE2= 1.8 V, V_DD= 3.3 V, V_RESET1= 3.3 V,

TPS37044A7OHDDFR

Figure 9-7. TPS37044 Overvoltage and

Undervoltage Function

Figure 9-6. TPS37044 Overvoltage and

Undervoltage Function

VDD

SENSE3 = SENSE4

VDD

V_IT+(OV)

1.22 V

V_IT-(UV)

1.05 V

RESET2

SENSE3 = SENSE4

RESET2

V_{SENSE3_4}ramp 0 V to 1.5 V, OV/UV Threshold = 1.15

V (+7.5%, -5.5%), V_DD= 3.3 V, V_RESET2= 3.3 V,

TPS37044A7OHDDFR

V_DDramp 0 V to 5 V, V_{SENSE3_4}= 1.2 V, V_RESET2= 3.3 V,

TPS37044A7OHDDFR

Figure 9-9. TPS37044 VDD Ramp Up Function

Figure 9-8. TPS37044 Overvoltage and

Undervoltage Function

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SENSE1

SENSE3

SENSE2

RESET1

SENSE4

RESET2

V_SENSE3toggling 0 V to 1.15 V [OV/UV Threshold = 1.15 V

V_SENSE1toggling 0 V to 3.3 V [OV/UV Threshold = 3.3 V

(±8%)], V_SENSE2toggling from 0 V to 1.8 V [OV/UV

Threshold = 1.8 V (+4%, -3.5%)], V_DD= 3.3 V,

V_RESET1= 3.3 V, TPS37044A7OHDDFR

(+7.5%, -5.5%)], V_SENSE4toggling from 0 V to 1.15 V

[OV/UV Threshold = 1.15 V (+7.5%, -5.5%)], V_DD= 3.3 V,

V_RESET1= 3.3 V, TPS37044A7OHDDFR

Figure 9-11. TPS37044 SENSE 3 and

SENSE 4 Toggling

Figure 9-10. TPS37044 SENSE 1 and

SENSE 2 Toggling

VDD

1 ms

SENSE1

RESET1

t_{PD =}1.32

RESET1

t_D= 21.5 ms

V_SENSE1= 3.3 V, V_SENSE1= 0 V via push-button for 1 ms,

V_DD= 3.3 V, V_RESET1= 3.3 V, TPS37044A7OHDDFR

V_SENSE1toggling from 3.3 V to 0 V, V_DD= 3.3 V, V_RESET1

toggling from 3.3 V to 0 V, TPS37044A7OHDDFR

Figure 9-12. TPS37044 SENSE1 Push-Button

Monitoring Function with Reset Time Delay

Figure 9-13. TPS37044 SENSE1

Propagation Delay Function

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10 Power Supply Recommendations

10.1 Power Supply Guidelines

This device is designed to operate from an input supply with a voltage range between 1.7 V to 6 V. It has a 6.5 V

absolute maximum rating on the VDD pin. It is good analog practice to place a 0.1 µF to 1 µF capacitor between

the VDD pin and the GND pin depending on the input voltage supply noise. If the voltage supply providing power

to VDD is susceptible to any large voltage transient that exceed maximum specifications, additional precautions

must be taken. See SNVA849 for more information.

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11 Layout

11.1 Layout Guidelines

•

Place the external components as close to the device as possible. This configuration prevents parasitic errors

from occurring.

•

Avoid using long traces for the VDD supply node. The VDD capacitor, along with parasitic inductance from

the supply to the capacitor, can form an LC circuit and create ringing with peak voltages above the maximum

VDD voltage.

•

Avoid using long traces of voltage to the sense pin. Long traces increase parasitic inductance and cause

inaccurate monitoring and diagnostics.

If SENSEx capacitors (C_SENSEx) are used, place the capacitors as close as possible to the SENSEx pins to

further improve the noise immunity on the SENSEx pins. Placing a 10 nF to 100 nF capacitors between the

SENSEx pins and GND can reduce the sensitivity to transient voltages on the monitored signal.

Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when absolutely necessary.

•

11.2 Layout Example

C_IN

R_pull-up1R_pull-up2

VDD

RESET1

*C_SENSE1

SENSE1

SENSE2

GND

RESET2

SENSE4

*C_SENSE4

SENSE3

*C_SENSE2

*C_SENSE3

GND

Vias used to connect pins for application-specific connections

*C_SENSExcapacitors can be added for improve noise immunity

Figure 11-1. Recommended Layout

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TPS3704

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SNVSBZ2B – MARCH 2021 – REVISED DECEMBER 2021

12 Device and Documentation Support

12.1 Device Nomenclature

Figure 5-1 in Section 5 and Table 12-1 shows how to decode the function of the device based on its part number

shown in Table 12-2.

Table 12-1. Device Naming Convention

DESCRIPTION

Generic Part number

NOMENCLATURE

VALUE

TPS3704x

Channel Option

One-channel option

Dual-channel option

Triple-channel option

Quad-channel option

Please refer to Table 12-2

Open-Drain, Active-Low

Push-Pull, Active-Low

Push-Pull, Active-High

20 μs reset time delay

1 ms reset time delay

2 ms reset time delay

3 ms reset time delay

5 ms reset time delay

10 ms reset time delay

15 ms reset time delay

20 ms reset time delay

25 ms reset time delay

35 ms reset time delay

40 ms reset time delay

50 ms reset time delay

70 ms reset time delay

100 ms reset time delay

140 ms reset time delay

150 ms reset time delay

200 ms reset time delay

280 ms reset time delay

400 ms reset time delay

560 ms reset time delay

800 ms reset time delay

1120 ms reset time delay

1200 ms reset time delay

SOT-23 8-pin (1.6 mm × 2.9 mm)

Large Reel

Detection Options

Ax, Bx, Cx,...

Variant code (Output Topology)

Reset Time Delay Option

DDF

Package

Reel

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SNVSBZ2B – MARCH 2021 – REVISED DECEMBER 2021

Table 12-2. Device Threshold Table

NUM

CHAN.

ORDERABLE PART

NAME

RESET

TIME

VARIANT

SENSE1

SENSE2

SENSE3

SENSE4

0.8 V (±4%)

TPS37044BJOFDDFR TPS37044

10 ms

0.8 V (±4%)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: TPS3704

PACKAGE OPTION ADDENDUM

www.ti.com

4-Dec-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PS37044AJOFDDFR

TPS37044BJOFDDFR

ACTIVE SOT-23-THIN

DDF

3000

TBD

Call TI

-40 to 125

Call TI

4BJOF

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

4-Dec-2021

OTHER QUALIFIED VERSIONS OF TPS3704 :

Automotive : TPS3704-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE OUTLINE

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

2.95

2.65

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

6X 0.65

2.95

2.85

NOTE 3

1.95

0.4

0.2

0.1

C A

1.65

1.55

1.1 MAX

0.20

0.08

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.1

0.0

0 - 8

0.6

0.3

DETAIL A

TYPICAL

4222047/B 11/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

8X (0.45)

SYMM

6X (0.65)

(R0.05)

TYP

(2.6)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222047/B 11/2015

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

(R0.05) TYP

8X (0.45)

SYMM

6X (0.65)

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4222047/B 11/2015

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS3704-Q1 [TI]

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