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TPS3760-Q1 [TI]

具有感应功能、超低 IQ 和延迟的汽车类 65V 过压或欠压监控器;
TPS3760-Q1
型号： TPS3760-Q1
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有感应功能、超低 IQ 和延迟的汽车类 65V 过压或欠压监控器

监控
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中文：  中文翻译
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TPS3760-Q1  
ZHCSLL3 –MARCH 2022  
TPS3760-Q1 适用于汽车、具有可编程检测和  
复位延迟功能的高电压监控器  
1 特性  
3 说明  
• 具有符合AEC-Q100 标准的下列特性：  
TPS3760-Q1 是一款 65V 输入电压检测器，IDD 为 1  
μA，精度为 1%，检测时间短。该器件可直接连接到  
12V/24V 汽车电池系统，用于持续监测过压 (OV) 或欠  
压 (UV) 情况；由于使用内部电阻分压器，它的总体解  
决方案尺寸非常小。由于提供了广泛的迟滞电压选项，  
可以忽略冷启动、启停和各种汽车电池电压瞬变。  
SENSE 引脚上的内置迟滞特性有助于在监测电源电压  
轨时防止出现错误的复位信号。  
– 器件温度等级1：–40°C 至+125°C 环境工作  
温度范围TA  
– 器件HBM ESD 分类等级2  
– 器件CDM ESD 分类等级C7B  
• 提供功能安全  
– 有助于进行功能安全系统设计的文档  
• 宽电源电压范围：2.7V 至65V  
• SENSE 和RESET 引脚为65V 等级  
• 低静态电流：1 µA（典型值）  
• 灵活而广泛的电压阈值选项  
表12-1  
通过单独的 VDD 和 SENSE 引脚，可实现高可靠性汽  
车系统所需的冗余，并且 SENSE 引脚可以监控比  
VDD 更高和更低的电压。SENSE 引脚的高阻抗输入  
支持使用可选的外部电阻器。通过 CTS 和 CTR 引  
脚，可以对 RESET 信号的上升沿和下降沿进行延迟调  
整。此外，CTS 可忽略受监控电压轨上产生的电压干  
扰，从而充当去抖动器；CTR 具有手动复位 (MR) 的  
作用，可用于强制系统复位。  
– 2.7V 至36V（最高精度1.5%）  
– 800 mV 选项（最高精度1%）  
• 内置迟滞(VHYS  
)
– 百分比选项：2% 至13%（阶跃1%）  
– 固定选项：VTH < 8V = 0.5V、1V、1.5V、  
2V、2.5V  
TPS3760 采用 4.1mm × 1.9mm 14 引脚 SOT 封装。  
TPS3760 工作温度范围为–40°C 至+125°C TA。  
• 可编程复位延时时间  
器件信息  
封装(  
– 10nF = 12.8ms、10μF = 12.8s  
• 可编程感测延时时间  
(1)  
)
封装尺寸（标称值）  
器件型号  
TPS3760-Q1  
SOT-23 (14) (DYY)  
4.1 mm × 1.9 mm  
– 10nF = 1.28ms、10μF = 1.28s  
• 手动复位(MR) 特性  
• 输出复位锁存特性  
(1) 如需了解封装详细信息，请参阅数据表末尾的机械制图附录。  
• 输出拓扑：开漏或推挽  
2 应用  
• 远程信息处理控制单元  
• 紧急呼叫系统  
• 音频放大器  
• 音响主机和组合仪表  
• 传感器融合和摄像头  
• 车身控制模块  
Low Iq, No external  
resistors needed  
0.95  
0.90  
0.85  
0.80  
0.75  
0.70  
0.65  
DC/DC  
MCU  
VDD  
VDD  
MCU Flag  
GPIO  
SENSE  
RESET  
TPS3760-Q1  
GND  
GND  
0.60  
-40oC  
25oC  
0.55  
0.50  
125oC  
Backup  
Vba  
Boost  
Converter  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
Supply Voltage (V)  
典型应用电路  
典型IDD 与VDD  
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问  
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。  
English Data Sheet: SBVS419  
 
 
 
TPS3760-Q1  
ZHCSLL3 –MARCH 2022  
www.ti.com.cn  
Table of Contents  
9 Application and Implementation..................................24  
9.1 Application Information............................................. 24  
9.2 Adjustable Voltage Thresholds................................. 24  
9.3 Typical Application.................................................... 25  
10 Power Supply Recommendations..............................28  
10.1 Power Dissipation and Device Operation............... 28  
11 Layout...........................................................................29  
11.1 Layout Guidelines................................................... 29  
11.2 Layout Example...................................................... 29  
11.3 Creepage Distance................................................. 30  
12 Device and Documentation Support..........................31  
12.1 Device Nomenclature..............................................31  
12.2 接收文档更新通知................................................... 32  
12.3 支持资源..................................................................32  
12.4 Trademarks.............................................................32  
12.5 Electrostatic Discharge Caution..............................32  
12.6 术语表..................................................................... 32  
13 Mechanical, Packaging, and Orderable  
1 特性................................................................................... 1  
2 应用................................................................................... 1  
3 说明................................................................................... 1  
4 Revision History.............................................................. 2  
5 Device Comparison.........................................................3  
6 Pin Configuration and Functions...................................4  
7 Specifications.................................................................. 5  
7.1 Absolute Maximum Ratings........................................ 5  
7.2 ESD Ratings .............................................................. 5  
7.3 Recommended Operating Conditions.........................5  
7.4 Thermal Information....................................................5  
7.5 Electrical Characteristics.............................................6  
7.6 Timing Requirements..................................................8  
7.7 Timing Diagrams ........................................................9  
7.8 Typical Characteristics.............................................. 11  
8 Detailed Description......................................................14  
8.1 Overview...................................................................14  
8.2 Functional Block Diagram.........................................14  
8.3 Feature Description...................................................15  
8.4 Device Functional Modes..........................................23  
Information.................................................................... 32  
4 Revision History  
注：以前版本的页码可能与当前版本的页码不同  
DATE  
REVISION  
NOTES  
March 2022  
*
Initial Release  
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5 Device Comparison  
Voltage Threshold Hysteresis  
TPS3760X  
XX X DYY R-Q1  
1. Sense logic: OV = overvoltage; UV = undervoltage  
2. Reset topology: PP = Push-Pull; OD = Open-Drain  
3. Reset logic: L = Active-Low; H = Active-High  
4. A to I hysteresis options are only available for 2.9 V to 8V threshold options  
5. Suffix 01 with VIT of 800mV corresponds to the adjustable variant, does not have internal voltage divider  
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6 Pin Configuration and Functions  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
NC  
VDD  
NC  
GND  
NC  
SENSE  
NC  
NC  
CTS  
CTR  
GND  
NC  
RESET  
NC  
8
图6-1. DYY Package,  
14-Pin SOT-23,  
TPS3760-Q1 (Top View)  
表6-1. Pin Functions  
PIN  
I/O  
DESCRIPTION  
NAME  
NO.  
VDD  
1
I
Input Supply Voltage: Bypass with a 0.1 µF capacitor to GND.  
Sense Voltage: The voltage monitored by this pin is compared to the internal voltage  
threshold, Vth, that is determined by an internal voltage divider for fixed variants or an  
external voltage divider for adjustable variants. When the SENSE pin detects a fault,  
RESET/RESET asserts after the sense time delay, set by CTS. When the voltage on the  
SENSE pin transitions back past Vth and hysteresis, VHYS, RESET/RESET deasserts after  
the reset time delay, set by CTR. For noisy applications, placing a 10 nF to 100 nF ceramic  
capacitor close to this pin may be needed for optimum performance.  
SENSE  
3
I
Sensing Topology: Overvoltage (OV) or Undervoltage (UV)  
Output Reset Signal: See Device Comparison for output topology options. RESET/RESET  
asserts when SENSE crosses the voltage threshold after the sense time delay, set by CTS.  
RESET/RESET remains asserted for the reset time delay period after SENSE transitions  
out of a fault condition. For active low open-drain reset output, an external pullup resistor is  
required. Do not place external pullup resistors on push-pull outputs.  
RESET/RESET  
6
O
Output topology: Open Drain or Push Pull, Active Low or Active High  
SENSE Time Delay: Capacitor programmable sense delay: CTS pin offers a user-  
adjustable sense delay time when asserting a reset condition. Connecting this pin to a  
ground-referenced capacitor sets the RESET/RESET delay time to assert.  
CTS  
CTR  
10  
O
-
RESET Time Delay: User-programmable reset time delay for RESET/RESET. Connect an  
external capacitor for adjustable time delay or leave the pin floating for the shortest delay.  
Manual Reset: If this pin is driven low, the RESET/RESET output will reset and become  
asserted. The pin can be left floating or be connected to a capacitor. This pin should not be  
driven high.  
9
GND  
NC  
8, 13  
-
-
Ground. All GND pins must be electrically connected to the board ground.  
NC stands for “No Connect.”The pins are to be left floating.  
2, 4, 5, 7,  
11,12, 14  
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7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range, unless otherwise noted (1)  
MIN  
–0.3  
–0.3  
MAX  
70  
UNIT  
V
Voltage  
VDD, VSENSE, VRESET, VRESET  
VCTS, VCTR  
Voltage  
6
V
Current  
IRESET, IRESET  
10  
mA  
°C  
°C  
°C  
Temperature (2)  
Temperature (2)  
Temperature (2)  
Operating junction temperature, TJ  
Operating Ambient temperature, TA  
Storage, Tstg  
150  
150  
150  
–40  
–40  
–65  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under  
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device  
reliability.  
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.  
7.2 ESD Ratings  
VALUE UNIT  
Human body model (HBM), per AEC Q100-002 (1)  
Charged device model (CDM), per AEC Q100-011  
±2000  
±750  
V(ESD) Electrostatic discharge  
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.  
7.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
MIN  
2.7  
0
NOM  
MAX  
65  
UNIT  
Voltage  
Voltage  
Voltage  
Current  
TJ  
VDD  
V
V
VSENSE, VRESET, VRESET  
VCTS, VCTR  
65  
0
5.5  
±5  
V
IRESET, IRESET  
0
mA  
°C  
Junction temperature (free air temperature)  
125  
–40  
7.4 Thermal Information  
TPS3760-Q1  
DYY  
THERMAL METRIC (1)  
UNIT  
14-PIN  
131.5  
61.1  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
56.6  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
3.4  
ψJT  
56.5  
ψJB  
RθJC(bot)  
N/A  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
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7.5 Electrical Characteristics  
At VDD(MIN) ≤VDD ≤VDD (MAX), CTR/MR = CTS = open, output reset pull-up resistor RPU = 10 kΩ, voltage VPU = 5.5 V, and  
load CLOAD = 10 pF. The operating free-air temperature range TA = –40°C to 125°C, unless otherwise noted. Typical values  
are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to VITN or VITP).  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VDD  
VDD  
Supply Voltage  
2.7  
65  
V
V
UVLO (1)  
Under Voltage Lockout  
VDD Falling below VDD (MIN)  
2.7  
Power on Reset Voltage (2)  
RESET, Active Low  
(Open-Drain, Push-Pull )  
VOL(MAX) = 300 mV  
IOUT (Sink) = 15 µA  
VPOR  
1.4  
1.4  
V
V
Power on Reset Voltage (2)  
RESET, Active High  
(Push-Pull )  
VOH(MIN) = 0.8 x VDD  
IOUT (Source) = 15 µA  
VPOR  
VIT = 800 mV  
1
1
2.6  
2
µA  
µA  
V
DD (MIN) ≤VDD ≤VDD  
(MAX)  
(MAX)  
IDD  
Supply current into VDD pin  
VIT = 2.7 V to 36 V  
DD (MIN) ≤VDD ≤VDD  
V
SENSE (Input)  
ISENSE  
Input current  
Input current  
VIT = 800 mV  
VIT < 10 V  
100  
0.8  
nA  
µA  
ISENSE  
ISENSE  
ISENSE  
10 V < VIT < 26 V  
VIT > 26 V  
Input current  
Input current  
1.2  
2
µA  
µA  
VIT = 2.7 V to 36 V  
VIT = 800 mV (3)  
-1.5  
0.792  
-1.5  
1.5  
0.808  
1.5  
%
V
Input Threshold Negative  
(Undervoltage)  
VITN  
0.800  
0.800  
Input Threshold Positive  
(Overvoltage)  
VIT = 2.7 V to 36 V  
%
VITP  
VIT = 800 mV (3)  
0.792  
0.808  
V
VIT = 0.8 V and 2.7 V to 36 V  
VHYS Range = 2% to 13%  
(1% step)  
-1.5  
1.5  
%
VHYS  
Hysteresis Accuracy (4)  
VIT = 2.7 V to 8 V  
VHYS = 0.5 V, 1 V, 1.5 V, 2 V,  
2.5 V  
-1.5  
1.5  
%
VIT-VHYS ≥2.4 V  
RESET (Output)  
VRESET = 5.5 V  
VITN < VSENSE < VITP  
300  
300  
300  
nA  
nA  
Ilkg(OD)  
Open-Drain leakage  
VRESET = 65 V  
VITN < VSENSE < VITP  
2.7 V ≤VDD ≤65 V  
IRESET = 5 mA  
(5)  
VOL  
Low level output voltage  
mV  
High level output voltage  
dropout  
2.7 V ≤VDD ≤65 V  
IRESET = 500 uA  
VOH_DO  
(VDD - VOH = VOH_DO  
(Push-Pull only)  
)
100  
mV  
V
High level output voltage  
(Push-Pull only)  
2.7 V ≤VDD ≤65 V  
IRESET = 5 mA  
(5)  
VOH  
0.8VDD  
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7.5 Electrical Characteristics (continued)  
At VDD(MIN) ≤VDD ≤VDD (MAX), CTR/MR = CTS = open, output reset pull-up resistor RPU = 10 kΩ, voltage VPU = 5.5 V, and  
load CLOAD = 10 pF. The operating free-air temperature range TA = –40°C to 125°C, unless otherwise noted. Typical values  
are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to VITN or VITP).  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Capacitor Timing (CTS, CTR)  
Internal resistance  
(CTR / MR)  
RCTR  
877  
88  
1000  
100  
1147  
122  
Kohms  
Kohms  
RCTS  
Manual Reset (MR)  
Internal resistance (CTS)  
VMR_IH  
VMR_IH  
VMR_IL  
VMR_IL  
CTR / MR pin logic high input VDD = 2.7 V  
CTR / MR pin logic high input VDD = 65 V  
CTR / MR pin logic low input VDD = 2.7 V  
CTR / MR pin logic low input VDD = 65 V  
2000  
2500  
mV  
mV  
mV  
mV  
1300  
1300  
(1) When VDD voltage falls below UVLO, reset is asserted for Output. VDD slew rate ≤100 mV / µs  
(2) VPOR is the minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined. VDD dv/dt ≤100mV/µs  
(3) For adjustable voltage guidelines and resistor selection refer to Adjustable Voltage Thresholds in Application and Implementation  
section  
(4) Hysteresis is with respect to VITP and VITN voltage threshold. VITP has negative hysteresis and VITN has positive hysteresis.  
(5) For VOH and VOL relation to output variants refer to Timing Figures after the Timing Requirement Table  
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7.6 Timing Requirements  
At VDD(MIN) ≤VDD ≤VDD (MAX), CTR/MR = CTS = open (1), output reset pull-up resistor RPU = 10 kΩ, voltage VPU = 5.5V,  
and CLOAD = 10 pF. VDD and SENSE slew rate = 1V / µs. The operating free-air temperature range TA = –40°C to 125°C,  
unless otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to either VITN or VITP).  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Common timing parameters  
VIT = 2.7 V to 36 V  
CCTR = Open  
20% Overdrive from Hysteresis  
100  
40  
µs  
µs  
µs  
Reset release time delay  
tCTR  
(CTR/MR) (2)  
VIT = 800 mV  
CCTR = Open  
20% Overdrive from Hysteresis  
VIT = 2.7 V to 36 V  
CCTS = Open  
20% Overdrive from VIT  
34  
8
90  
Sense detect time delay  
(CTS) (3)  
tCTS  
VIT = 800 mV  
CCTS = Open  
20% Overdrive from VIT  
17  
2
µs  
CCTR/MR = Open  
tSD  
Startup Delay (4)  
ms  
(1) CCTR = Reset delay channel  
CCTS = Sense delay channel  
(2) CTR Reset detect time delay:  
Overvoltage active-LOW output is measure from VITP - HYS to VOH  
Undervoltage active-LOW output is measure from VITN + HYS to VOH  
Overvoltage active-HIGH output is measure from VITP - HYS to VOL  
Undervoltage active-HIGH output is measure from VITN + HYS to VOL  
(3) CTS Sense detect time delay:  
Active-low output is measure from VIT to VOL (or VPullup  
Active-high output is measured from VIT to VOH  
VIT refers to either VITN or VITP  
)
(4) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD before the output is in the correct state based on  
VSENSE  
.
tSD time includes the propagation delay (CCTR = Open). Capaicitor on CCTR will add time to tSD.  
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7.7 Timing Diagrams  
VDD(MIN)  
VDD  
UVLO(MIN)  
VPOR  
SENSE  
VSENSE  
VITN (UV) + VHYS  
VITN (UV)  
Hysteresis  
*See  
Note C  
t < tCTS  
RESET_UVxx  
tSD + tCTR  
tCTS  
tCTR  
*See  
Note C  
RESET_UVxx  
tSD + tCTR  
tCTS  
tCTR  
A. For open-drain output option, the timing diagram assumes the RESET_UVOD / RESET_UVOD pin is connected via an external pull-up resistor to VDD.  
B. Be advised that 图7-1 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTR) time.  
C. RESET_UVxx / RESET_UVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTR, is reached.  
图7-1. SENSE Undervoltage (UV) Timing Diagram  
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VDD(MIN)  
VDD  
UVLO(MIN)  
VPOR  
VITP (OV)  
VITP (OV) - VHYS  
VSENSE  
SENSE  
Hysteresis  
*See  
Note C  
t < tCTS  
RESET_OVxx  
tSD + tCTR  
tCTS  
tCTR  
*See  
Note C  
RESET_OVxx  
tSD + tCTR  
tCTS  
tCTR  
A. For open-drain output option, the timing diagram assumes the RESET_OVOD / RESET_OVOD pin is connected via an external pull-up resistor to VDD.  
B. Be advised that 图7-2 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTR) time.  
C. RESET_OVxx / RESET_OVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTR, is reached.  
图7-2. SENSE Overvoltage (OV) Timing Diagram  
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7.8 Typical Characteristics  
Typical characteristics show the typical performance of the TPS3760-Q1 device. Test conditions are TA = 25°C, RPU = 100  
kΩ, CLoad = 50 pF, unless otherwise noted.  
0.95  
0.90  
0.85  
0.80  
0.75  
0.70  
0.65  
0.60  
0.55  
0.50  
0.90  
0.85  
0.80  
0.75  
0.70  
0.65  
0.60  
0.55  
0.50  
-40oC  
25oC  
-40oC  
25oC  
125oC  
125oC  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
Supply Voltage (V)  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
Supply Voltage (V)  
RESET = High, VIT = 2.7 V  
RESET = Low, VIT = 2.7 V  
图7-3. VDD vs IDD (RESET = High, VIT = 2.7 V)  
图7-4. VDD vs IDD (RESET = Low, VIT = 2.7 V)  
1.30  
1.25  
1.20  
1.15  
1.10  
1.05  
1.00  
0.95  
0.90  
0.85  
0.80  
1.40  
1.35  
1.30  
1.25  
1.20  
1.15  
1.10  
1.05  
1.00  
0.95  
0.90  
-40oC  
25oC  
-40C  
25oC  
125C  
125oC  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
Supply Voltage (V)  
Supply Voltage (V)  
RESET = High, VIT = 0.8 V  
RESET = Low, VIT = 0.8 V  
图7-5. VDD vs IDD (RESET = High, VIT = 0.8 V)  
图7-6. VDD vs IDD (RESET = Low, VIT = 0.8 V)  
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
-40oC  
25oC  
-40oC  
25oC  
125oC  
125oC  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
Sense Voltage (V)  
Sense Voltage (V)  
VDD = 2.7 V  
VDD = 65 V  
图7-7. VSENSE vs ISENSE  
图7-8. VSENSE vs ISENSE  
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7.8 Typical Characteristics (continued)  
Typical characteristics show the typical performance of the TPS3760-Q1 device. Test conditions are TA = 25°C, RPU = 100  
kΩ, CLoad = 50 pF, unless otherwise noted.  
0.21  
0.18  
0.15  
0.12  
0.09  
0.06  
0.03  
0
0.21  
0.18  
0.15  
0.12  
0.09  
0.06  
0.03  
0.00  
-40oC  
25oC  
-40oC  
25oC  
125oC  
125oC  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
IRESET (mA)  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
IRESET (mA)  
VDD = 2.7 V  
VDD = 65 V  
图7-9. Open-Drain Active Low VOL vs IRESET  
图7-10. Open-Drain Active Low VOL vs IRESET  
0.21  
0.21  
-40oC  
25oC  
-40oC  
25oC  
0.18  
0.15  
0.12  
0.09  
0.06  
0.03  
0
0.18  
0.15  
0.12  
0.09  
0.06  
0.03  
0
125oC  
125oC  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
IRESET (mA)  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
IRESET (mA)  
VDD = 2.7 V  
VDD = 65 V  
图7-11. Open-Drain Active High VOL vs IRESET  
图7-12. Open-Drain Active High VOL vs IRESET  
0.21  
0.21  
-40oC  
25oC  
-40oC  
25oC  
0.18  
0.15  
0.12  
0.09  
0.06  
0.03  
0
0.18  
0.15  
0.12  
0.09  
0.06  
0.03  
0
125oC  
125oC  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
IRESET (mA)  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
IRESET (mA)  
VDD = 2.7 V  
VDD = 65 V  
图7-13. Push-Pull Active High VOL vs IRESET  
图7-14. Push-Pull Active High VOL vs IRESET  
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7.8 Typical Characteristics (continued)  
Typical characteristics show the typical performance of the TPS3760-Q1 device. Test conditions are TA = 25°C, RPU = 100  
kΩ, CLoad = 50 pF, unless otherwise noted.  
0.21  
0.18  
0.15  
0.12  
0.09  
0.06  
0.03  
0
0.21  
0.18  
0.15  
0.12  
0.09  
0.06  
0.03  
0
-40oC  
25oC  
-40oC  
25oC  
125oC  
125oC  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
Supply Voltage (V)  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
Supply Voltage (V)  
图7-15. Open-Drain Active Low VOL vs VDD  
图7-16. Open-Drain Active High VOL vs VDD  
0.21  
0.18  
0.15  
0.12  
0.09  
0.06  
0.03  
0
0.21  
0.18  
0.15  
0.12  
0.09  
0.06  
0.03  
0
-40oC  
25oC  
-40oC  
25oC  
125oC  
125oC  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
Supply Voltage (V)  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
Supply Voltage (V)  
图7-17. Push-Pull Active Low VOL vs VDD  
图7-18. Push-Pull Active High VOL vs VDD  
70  
60  
50  
40  
30  
20  
10  
0
70  
60  
50  
40  
30  
20  
10  
0
-40oC  
25oC  
-40oC  
25oC  
125oC  
125oC  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
Supply Voltage (V)  
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
Supply Voltage (V)  
图7-19. Push-Pull Active Low VOH vs VDD  
图7-20. Push-Pull Active High VOH vs VDD  
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8 Detailed Description  
8.1 Overview  
The TPS3760-Q1 is a family of high voltage and low quiescent current reset ICs with fixed threshold voltage. A  
voltage divider is integrated to eliminate the need for external resistors and eliminate leakage current that comes  
with resistor dividers. However, it can also support an external resistor if required by the application. The lowest  
threshold 800 mV (bypass internal resistor ladder) is recommenced for external resistors use case to take  
advantage of faster detection time and lower ISENSE current.  
VDD, SENSE and RESET pins can support 65 V continuous operation; both VDD and SENSE voltage levels can  
be independent of each other, meaning VDD pin can be connected at 2.7 V while SENSE pins are connected to  
a higher voltage. Note, the TPS3760-Q1 does not have clamps within the device so external circuits or devices  
must be added to limit the voltages to the absolute maximum limit.  
Additional features include programmable sense time delay (CTS) and reset delay time and manual reset (CTR /  
MR).  
8.2 Functional Block Diagram  
VDD  
CTS  
CTR / MR  
*Device Op ons  
Boxes shaded in blue  
See Device Nomenclature  
IQ  
SubReg  
POR  
VDD  
Voltage  
Divider  
SENSE  
-
Output  
Logic select  
(High/Low)  
OV or UV  
Select  
Sense  
Delay  
Manual  
Reset  
Reset  
Delay  
RESET  
V
Ref Divider  
+
REFERENCE  
GND  
图8-1. Functional Block Diagram 1  
1
Refer to 节5 for complete list of topologies and output logic combination  
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8.3 Feature Description  
8.3.1 Input Voltage (VDD)  
VDD operating voltage ranges from 2.7 V to 65 V. An input supply capacitor is not required for this device;  
however, if the input supply is noisy good analog practice is to place a 0.1 µF capacitor between the VDD and  
GND.  
VDD needs to be at or above VDD(MIN) for at least the start-up time delay (tSD) for the device to be fully functional.  
VDD voltage is independent of VSENSE and VRESET, meaning that VDD can be higher or lower than the other  
pins.  
8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)  
When the voltage on VDD is less than the UVLO voltage, but greater than the power-on reset voltage (VPOR),  
the output pins will be in reset, regardless of the voltage at SENSE pins.  
8.3.1.2 Power-On Reset (VDD < VPOR  
)
When the voltage on VDD is lower than the power on reset voltage (VPOR), the output signal is undefined and is  
not to be relied upon for proper device function.  
Note: 图8-2 and 图8-3 assume an external pull-up resistor is connected to the reset pin via VDD.  
SENSE VOLTAGE OUTSIDE OF THRESHOLD  
VSENSE  
VITN > VSENSE > VITP  
VDD(MIN)  
VDD  
UVLO(MIN)  
VPOR  
RESET  
Active Low  
Output stays low since VSENSE  
is outside of threshold  
VOL  
RESET  
Active High  
VOL  
Undefined  
Undefined  
tSD+ CTR  
t
图8-2. Power Cycle (SENSE Outside of Nominal Voltage)  
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SENSE VOLTAGE WITH IN THRESHOLD  
VITN < VSENSE < VITP  
VSENSE  
VDD(MIN)  
VDD  
UVLO(MIN)  
VPOR  
RESET  
Active Low  
VOL  
RESET  
Active High  
VOL  
Undefined  
Undefined  
tSD+ CTR  
t
图8-3. Power Cycle (SENSE Within Nominal Voltage)  
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8.3.2 SENSE  
The TPS3760-Q1 high voltage family integrates a voltage comparator, a precision reference voltage and a  
trimmed resistor divider. This configuration optimizes device accuracy because all resistor tolerances are  
accounted for in the accuracy and performance specifications. Device also has built-in hysteresis that provides  
noise immunity and ensures stable operation.  
Although not required in most cases, for noisy applications good analog design practice is to place a 10 nF to  
100 nF bypass capacitor at the SENSE inputs in order to reduce sensitivity to transient voltages on the  
monitored signal. SENSE can be connected directly to VDD pin.  
8.3.2.1 SENSE Hysteresis  
Built-in hysteresis to avoid erroneous output reset release. The hysteresis is opposite to the threshold voltage;  
for overvoltage options the hysteresis is subtracted from the positive threshold (VITP), for undervoltage options  
hysteresis is added to the negative threshold (VITN).  
VRESET  
VRESET  
VSENSE  
VSENSE  
VITP - VHYS  
VITP  
VITP - VHYS  
VITP  
图8-4. Hysteresis (Overvoltage Active-Low)  
VRESET  
图8-5. Hysteresis (Overvoltage Active-High)  
VRESET  
VSENSE  
VSENSE  
VITN  
VITN  
VITN+VHYS  
VITN+VHYS  
图8-6. Hysteresis (Undervoltage Active-High)  
图8-7. Hysteresis (Undervoltage Active-Low)  
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表8-1. Common Hysteresis Lookup Table  
TARGET  
DEVICE ACTUAL HYSTERESIS OPTION  
DETECT THRESHOLD  
TOPOLOGY  
Overvoltage  
Overvoltage  
Overvoltage  
Overvoltage  
Overvoltage  
Undervoltage  
Undervoltage  
Undervoltage  
Undervoltage  
RELEASE VOLTAGE (V)  
18.0 V  
18.0 V  
17.0 V  
16.0 V  
15.0 V  
6.0 V  
5.5 V  
8 V  
17.5 V  
16.0 V  
16.5 V  
15.0 V  
14.0 V  
6.5 V  
6 V  
-3%  
-11%  
-3%  
-6%  
-7%  
0.5 V  
0.5 V  
1 V  
9 V  
5 V  
7.5 V  
2.5 V  
表 8-1 shows a sample of hysteresis and voltage options for the TPS3760-Q1. For threshold voltages ranging  
from 2.7 V to 8 V, one option is to select a fixed hysteresis value ranging from 0.5 V to 2.5 V in increments of 0.5  
V. Additionally, a second option can be selected where the hysteresis value is a percentage of the threshold  
voltage. The percentage of voltage hysteresis ranges from 2% to 13%.  
Knowing the amount of hysteresis voltage, the release voltage for the undervoltage (UV) channel is  
(VITN (UV) + VHYS) and for the overvoltage (OV) channel is (VITP (OV) - VHYS). The accuracy of the release voltage,  
or stated in the Electrical Characteristics as Hysteresis Accuracy is ±1.5%. Expanding what is shown in 表 8-1,  
below are a few voltage hysteresis examples that include the hysteresis accuracy:  
Undervoltage (UV) Channel  
VITN = 0.8 V  
Voltage Hysteresis (VHYS) = 5% = 40 mV  
Hysteresis Accuracy = ±1.5% = 39.4 mV or 40.6 mV  
Release Voltage = VITN + VHYS = 839.4 mV to 840.6 mV  
Overvoltage (OV) Channel  
VITP = 8 V  
Voltage Hysteresis (VHYS) = 2 V  
Hysteresis Accuracy = ±1.5% = 1.97 V or 2.03 V  
Release Voltage = VITN - VHYS = 5.97 V to 6.03 V  
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8.3.3 Output Logic Configurations  
TPS3760-Q1 is a single channel device that has a single input sense pin and a single reset pin. The single  
channel is available as Open-Drain and Push-Pull.  
The available output logic configuration combinations are shown in 表8-2.  
表8-2. TPS3760-Q1 Output Logic  
DESCRIPTION  
GPN  
NOMENCLATURE  
TPS3760-Q1 (+ topology)  
TPS3760A-Q1  
VALUE  
CHANNEL CONFIGURATION  
UV OD L  
Topology (OV and UV only)  
•
•
•
•
•
•
UV = Undervoltage  
OV = Overvoltage  
PP = Push-Pull  
OD = Open-Drain  
L = Active low  
TPS3760B-Q1  
UV PP L  
TPS3760C-Q1  
UV OD H  
TPS3760D-Q1  
UV PP H  
TPS3760E-Q1  
OV OD L  
TPS3760F-Q1  
OV PP L  
H = Active high  
TPS3760G-Q1  
OV OD H  
TPS3760H-Q1  
OV PP H  
8.3.3.1 Open-Drain  
Open-drain output requires an external pull-up resistor to hold the voltage high to the required voltage logic.  
Connect the pull-up resistor to the proper voltage rail to enable the output to be connected to other devices at  
the correct interface voltage levels.  
To select the right pull-up resistor consider system VOH and the (Ilkg) current provided in the electrical  
characteristics, high resistors values will have a higher voltage drop affecting the output voltage high. The open-  
drain output can be connected as a wired-AND logic with other open-drain signals such as another TPS3760-Q1  
open-drain output pin.  
8.3.3.2 Push-Pull  
Push-Pull output does not require an external resistor since is the output is internally pulled-up to VDD during  
VOH condition and output will be connected to GND during VOH condition.  
8.3.3.3 Active-High (RESET)  
RESET (active-high), denoted with no bar above the pin label. RESET remains low (VOL, deasserted) as long as  
sense voltage is in normal operation within the threshold boundaries and VDD voltage is above UVLO. To assert  
a reset sense pins needs to meet the condition below:  
• For undervoltage variant the SENSE voltage need to cross the lower boundary (VITN).  
• For overvoltage variant the SENSE voltage needs to cross the upper boundary (VITP).  
8.3.3.4 Active-Low (RESET)  
RESET (active low) denoted with a bar above the pin label. RESET remains high voltage (VOH, deasserted)  
(open-drain variant VOH is measured against the pullup voltage) as long as sense voltage is in normal operation  
within the threshold boundaries and VDD voltage is above UVLO. To assert a reset sense pins needs to meet  
the condition below:  
• For undervoltage variant the SENSE voltage need to cross the lower boundary (VITN).  
• For overvoltage variant the SENSE voltage needs to cross the upper boundary (VITP).  
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8.3.4 User-Programmable Reset Time Delay  
TPS3760-Q1 has adjustable reset release time delay with external capacitors.  
• A capacitor in CTR / MR programs the reset time delay of the output.  
• No capacitor on this pin gives the fastest reset delay time indicated in the 节7.6.  
8.3.4.1 Reset Time Delay Configuration  
The time delay (tCTR) can be programmed by connecting a capacitor between CTR pin and GND.  
The relationship between external capacitor CCTR_EXT (typ) and the time delay tCTR (typ) is given by 方程式1.  
tCTR (typ) = -ln (0.28) x RCTR (typ) x CCTR_EXT (typ) + tCTR (no cap)  
(1)  
RCTR (typ) = is in kilo ohms (kOhms)  
CCTR_EXT (typ) = is given in microfarads (μF)  
tCTR (typ) = is the reset time delay (ms)  
The reset delay varies according to three variables: the external capacitor (CCTR_EXT), CTR pin internal  
resistance (RCTR) provided in 节 7, and a constant. The minimum and maximum variance due to the constant is  
show in 方程式2 and 方程式3:  
tCTR (min) = -ln (0.31) x RCTR (min) x CCTR_EXT (min) + tCTR (no cap (min))  
tCTR (max) = -ln (0.25) x RCTR (max) x CCTR_EXT (max) + tCTR (no cap (max))  
(2)  
(3)  
The recommended maximum reset delay capacitor for the TPS3760-Q1 is limited to 10 μF as this ensures  
enough time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a  
capacitor value can cause very slow charge up (rise times) due to capacitor leakage and system noise can  
cause the the internal circuit to trip earlier or later near the threshold. This leads to variation in time delay where  
it can make the delay accuracy worse in the presence of system noise.  
When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns  
from the fault condition before the delay capacitor discharges completely, the delay will be shorter than  
expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected  
time delay. A larger delay capacitor can be used so long as the capacitor has enough time to fully discharge  
during the duration of the voltage fault. To ensure the capacitor is fully discharged, the time period or duration of  
the voltage fault needs to be greater than 5% of the programmed reset time delay.  
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8.3.5 User-Programmable Sense Delay  
TPS3760-Q1 has adjustable sense release time delay with external capacitors.  
• A capacitor in CTS programs the excursion detection on SENSE.  
• No capacitor on these pins gives the fastest detection time indicated in the 节7.6.  
8.3.5.1 Sense Time Delay Configuration  
The time delay (tCTS) can be programmed by connecting a capacitor between CTS pin and GND.  
The relationship between external capacitor CCTS_EXT (typ) and the time delay tCTS (typ) is given by 方程式4.  
tCTS (typ) = -In (0.28) x RCTS (typ) x CCTS_EXT (typ) + tCTS (no cap)  
(4)  
RCTS = is in kilo ohms (kOhms)  
CCTS_EXT = is given in microfarads (μF)  
tCTS = is the sense time delay (ms)  
The sense delay varies according to three variables: the external capacitor (CCTS_EXT), CTS pin internal  
resistance (RCTS) provided in Electrical Characteristics, and a constant. The minimum and maximum variance  
due to the constant is show in 方程式5 and 方程式6:  
tCTS (min) = -ln (0.31) x RCTS (min) x CCTS_EXT (min) + tCTS (no cap (min))  
tCTR (max) = -ln (0.25) x RCTS (max) x CCTS_EXT (max) + tCTSx (no cap (max))  
(5)  
(6)  
The recommended maximum sense delay capacitor for the TPS3760-Q1 is limited to 10 μF as this ensures  
enough time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a  
capacitor value can cause very slow charge up (rise times) and system noise can cause the the internal circuit to  
trip earlier or later near the threshold. This leads to variation in time delay where it can make the delay accuracy  
worse in the presence of system noise.  
When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns  
from the fault condition before the delay capacitor discharges completely, the delay will be shorter than  
expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected  
time delay. A larger delay capacitor can be used so long as the capacitor has enough time between fault events  
to fully discharge during the duration of the voltage fault. To ensure the capacitor is fully discharged, the time  
period or time duration between fault events needs to be greater than 10% of the programmed sense time delay.  
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8.3.6 Manual RESET (CTR / MR) Input  
The manual reset input allows a processor or other logic circuits to initiate a reset. In this section MR is a generic  
reference to (CTR / MR). A logic low on MR causes RESET to assert on reset output. After MR is left floating,  
RESET will release the reset if the voltage at SENSE pin is at nominal voltage. MR should not be driven high,  
this pin should be left floating or connected to a capacitor to GND, this pin can be left unconnected if is not used.  
If the logic driving the MR cannot tri-state (floating and GND) then a logic-level FET should be used as illustrated  
in 图8-8.  
Low Voltage  
High Voltage  
VDD  
MCU  
CTR  
Ac ve low  
Logic  
Reset  
Delay  
GPIO  
Low or Floa ng  
图8-8. Manual Reset Implementation  
SENSE VOLTAGE WITH IN THRESHOLD  
VITN < VSENSE < VITP  
VSENSE  
CTR/MR  
< VMR  
MR floating or  
connected to capacitor  
MR floating or  
connected to capacitor  
RESET  
Active-High  
RESET  
Active-Low  
图8-9. Manual Reset Timing Diagram  
表8-3. MR Functional Table  
SENSE ON NOMINAL VOLTAGE  
Yes  
MR  
RESET STATUS  
Low  
Reset asserted  
Fast reset release when SENSE  
voltage goes back to nominal  
voltage  
Floating  
Yes  
Capacitor  
High  
Yes  
Yes  
Programmable reset time delay  
NOT Recommended  
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8.4 Device Functional Modes  
表8-4. Undervoltage Detect Functional Mode Truth Table  
SENSE  
OUTPUT (2)  
(RESET PIN)  
DESCRIPTION  
CTR (1) / MR PIN  
VDD PIN  
PREVIOUS  
CONDITION  
CURRENT CONDITION  
Open or capacitor  
connected  
Normal Operation  
SENSE > VITN(UV)  
SENSE > VITN(UV)  
SENSE < VITN(UV)  
SENSE > VITN(UV)  
SENSE < VITN(UV)  
SENSE > VITN(UV)  
VDD > VDD(MIN)  
VDD > VDD(MIN)  
VDD > VDD(MIN)  
High  
Low  
Low  
Undervoltage  
Detection  
Open or capacitor  
connected  
Undervoltage  
Detection  
Open or capacitor  
connected  
Open or capacitor  
connected  
Normal Operation  
Manual Reset  
SENSE < VITN(UV) SENSE > VITN(UV) + HYS  
VDD > VDD(MIN)  
VDD > VDD(MIN)  
VPOR < VDD < VDD(MIN)  
VDD < VPOR  
High  
Low  
SENSE > VITN(UV)  
SENSE > VITN(UV)  
SENSE > VITN(UV)  
SENSE > VITN(UV)  
Low  
Open or capacitor  
connected  
UVLO Engaged  
Low  
Below VPOR  
,
Open or capacitor  
connected  
SENSE > VITN(UV)  
SENSE > VITN(UV)  
Undefined  
Undefined Output  
(1) Reset time delay is ignored in the truth table.  
(2) Open-drain active low output requires an external pull-up resistor to a pull-up voltage.  
表8-5. Overvoltage Detect Functional Mode Truth Table  
SENSE  
OUTPUT (2)  
(RESET PIN)  
DESCRIPTION  
CTR (1) / MR PIN  
VDD PIN  
PREVIOUS  
CONDITION  
CURRENT CONDITION  
SENSE < VITN(OV)  
SENSE > VITN(OV)  
SENSE < VITN(OV)  
Open or capacitor  
connected  
Normal Operation  
SENSE < VITN(OV)  
SENSE < VITN(OV)  
SENSE > VITN(OV)  
VDD > VDD(MIN)  
VDD > VDD(MIN)  
VDD > VDD(MIN)  
High  
Low  
Low  
Overvoltage  
Detection  
Open or capacitor  
connected  
Overvoltage  
Detection  
Open or capacitor  
connected  
Open or capacitor  
connected  
Normal Operation  
Manual Reset  
SENSE > VITN(OV)  
SENSE < VITN(OV)  
SENSE < VITN(OV)  
SENSE < VITN(OV) - HYS  
SENSE < VITN(OV)  
VDD > VDD(MIN)  
VDD > VDD(MIN)  
High  
Low  
Low  
Low  
Open or capacitor  
connected  
UVLO Engaged  
SENSE < VITN(OV)  
VPOR < VDD < UVLO  
Below VPOR  
Undefined Output  
,
Open or capacitor  
connected  
SENSE < VITN(OV)  
SENSE < VITN(OV)  
VDD < VPOR  
Undefined  
(1) Reset time delay is ignored in the truth table.  
(2) Open-drain active low output requires an external pull-up resistor to a pull-up voltage.  
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9 Application and Implementation  
备注  
Information in the following applications sections is not part of the TI component specification, and TI  
does not warrant its accuracy or completeness. TI’s customers are responsible for determining  
suitability of components for their purposes, as well as validating and testing their design  
implementation to confirm system functionality.  
9.1 Application Information  
The following sections describe in detail how to properly use this device. As this device has many applications  
and setups, there are many situations that this datasheet can not characterize in detail and will vary from these  
applications depending on the requirements of the final application  
9.2 Adjustable Voltage Thresholds  
方程式7 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The  
resistors can be calculated depending on the desired voltage threshold and device part number. TI recommends  
using the 0.8 V voltage threshold device when using an adjustable voltage variant. This variant bypasses the  
internal resistor ladder.  
For example, consider a 12 V rail being monitored VMON for undervoltage (UV) using of the  
TPS3760A0012DYYRQ1 variant. Using 方程式 7 and shown in 方程式 8, R1 is the top resistor of the resistor  
divider that is between VMON and VSENSE, R2 is the bottom resistor that is between VSENSE and GND, VMON is  
the voltage rail that is being monitored and VSENSE is the input threshold voltage. The monitored UV threshold,  
denoted as VMON-, where the device will assert a reset signal occurs when VSENSE = VIT-(UV) or, for this example,  
V
MON- = 10.8V which is 90% from 12 V. Using 方程式 7 and assuming R2 = 10kΩ , R1 can be calculated shown  
in 方程式8 where IR1 is represented in 方程式9:  
VSENSE = VMON- × (R2 ÷ (R1 + R2))  
R1 = (VMON- - VSENSE) ÷ IR1  
IR1 = IR2 = VSENSE ÷ R2  
(7)  
(8)  
(9)  
Substituting 方程式 9 into 方程式 8 and solving for R1 in 方程式 7, R1 = 125kΩ. The TPS3760A012DYYRQ1 is  
typically meant to monitor a 0.8 V rail with ±2% voltage threshold hysteresis. For the reset signal to become  
deasserted, VMON would need to go above VIT- + VHYS. For this example,  
VMON = 11.016 V when the reset signal becomes deasserted.  
There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the  
tolerance of the resistor divider, there is an internal resistance of the SENSE pin that may affect the accuracy of  
the resistor divider. Although expected to be very high impedance, users are recommended to calculate the  
values for the design specifications. The internal SENSE resistance RSENSE can be calculated by the SENSE  
voltage VSENSE divided by the SENSE current ISENSE as shown in 方程式 11. VSENSE can be calculated using 方  
程式7 depending on the resistor divider and monitored voltage. ISENSE can be calculated using 方程式10.  
ISENSE = [(VMON - VSENSE) ÷ R1] - (VSENSE ÷ R2)  
RSENSE = VSENSE ÷ ISENSE  
(10)  
(11)  
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VMON  
VDD  
VDD  
VDD  
R1  
10 kΩ  
VSENSE2  
RESET  
SENSE  
TPS3760-Q1  
R2  
CTS  
CTR  
GND  
图9-1. Adjustable Voltage Threshold with External Resistor Dividers  
9.3 Typical Application  
9.3.1 Design 1: Off-Battery Monitoring  
This application is intended for the initial power stage in applications with the 12 V batteries. Variation of the  
battery voltage is common between 9 V and 16 V. Furthermore, if cold-cranking and load dump conditions are  
considered, voltage transients can occur as low as 3 V and as high as 42 V. In this design example, we are  
highlighting the ability for low power, direct off-battery voltage supervision.  
图 11-1 illustrates an example of how the TPS3760 Q1 is monitoring the battery voltage while being powered by  
it, as well.  
Low Iq, No external  
resistors needed  
DC/DC  
MCU  
VDD  
VDD  
GPIO  
MCU Flag  
SENSE  
RESET  
TPS3760-Q1  
GND  
GND  
Backup  
Vba  
Boost  
Converter  
图9-2. TPS3760-Q1 Overvoltage Supervisor with Direct Off-Battery Monitoring  
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9.3.1.1 Design Requirements  
This design requires voltage supervision on a 12 V power supply voltage rail with possibility of the 12 V rail rising  
up as high as 42 V. The undervoltage fault occurs when the power supply voltage drops below 7.7 V.  
PARAMETER  
Power Rail Voltage Supervision  
Maximum Input Power  
Output logic voltage  
DESIGN REQUIREMENT  
DESIGN RESULT  
TPS3760-Q1 provides voltage monitoring with  
1.5% max accuracy with adjustable/non-adjustable  
variations.  
Monitor 12-V power supply for undervoltage  
condition, trigger a undervoltage fault at 7.7 V.  
Operate with power supply input up to 42 V.  
Open-Drain Output Topology  
The TPS3760-Q1 can support a VDD of up to 65 V.  
An open-drain output is recommended to provide  
the correct reset signal, but a push-pull can also be  
used.  
TPS3760-Q1 allows for IQ to remain low with  
support of up to 65 V. This allows for no external  
resistor divider to be required.  
Maximum system current  
consumption  
2 µA max when power supply is at 12 V typical  
Maximum voltage monitor accuracy of 1.5%.  
The TPS3760-Q1 has 1.5% maximum voltage  
monitor accuracy.  
Voltage Monitor Accuracy  
Delay when returning from fault  
condition  
RESET delay of at least 12.8 ms when returning  
from a undervoltage fault.  
CCTR = 10 nF sets 12.8 ms delay  
9.3.1.2 Detailed Design Procedure  
The primary advantage of this application is being able to directly monitor a voltage on an automotive battery  
without needing external an resistor dividers on the SENSE input. This keeps the overall IQ of the design low  
while still achieving the desired rail monitoring.  
Voltage rail monitoring is done by connecting the SENSE input directly to the battery rail after the TVS protection  
diodes. The TPS3760-Q1 that is being used in this example is a fixed voltage variant where theSENSE threshold  
voltage has been set internally. Word of caution, the TVS protection diodes must be chosen such that the  
transient voltages on the monitored rails do not exceed the absolute max limit listed in 节7.1.  
To use this configuration, the specific voltage threshold variation of the device must be chosen according to the  
application. In this configuration, the '77' variation must be chosen for 7.7 V as shown in 节5.  
The device being able to handle 65 V on VDD means the monitored voltage rail can go as high as 42 V for the  
application transients and not violate the recommended maximum for the supervisor as it usually would. This is  
useful when monitoring a voltage rail that has a wide range that may go much higher than the nominal rail  
voltage such as in this case. Good design practice recommends using a 0.1 µF capacitor on the VDD pin and  
this capacitance may need to increase if using an adjustable version with a resistor divider.  
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9.3.1.3 Application Curves  
V_SENSE  
RESET_B  
图9-3. Undervoltage Reset Waveform  
V_SENSE  
RESET_B  
图9-4. Undervoltage Recovery Waveform  
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10 Power Supply Recommendations  
These devices are designed to operate from an input supply with a voltage range between 1.4 V (VPOR) to 65 V  
(maximum operation). Good analog design practice recommends placing a minimum 0.1 µF ceramic capacitor  
as near as possible to the VDD pin.  
10.1 Power Dissipation and Device Operation  
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from  
the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power  
dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces  
between the die junction and ambient air.  
The maximum continuous allowable power dissipation for the device in a given package can be calculated using  
方程式12:  
PD-MAX = ((TJ-MAX –TA) / RθJA  
)
(12)  
(13)  
The actual power being dissipated in the device can be represented by 方程式13:  
PD = VDD × IDD + pRESET  
pRESET is calculated by 方程式14 or 方程式15  
pRESET (PUSHPULL) = VDD - VRESET x IRESET  
pRESET (OPEN-DRAIN) = VRESET x IRESET  
(14)  
(15)  
方程式 12 and 方程式 13 establish the relationship between the maximum power dissipation allowed due to  
thermal consideration, the voltage drop across the device, and the continuous current capability of the device.  
These two equations should be used to determine the optimum operating conditions for the device in the  
application.  
In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is  
present, the maximum ambient temperature (TA-MAX) may be increased.  
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum  
ambient temperature (TA-MAX) may have to be de-rated. TA-MAX is dependent on the maximum operating junction  
temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the  
application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application  
(RθJA), as given by 方程式16:  
TA-MAX = (TJ-MAX-OP –(RθJA × PD-MAX))  
(16)  
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11 Layout  
11.1 Layout Guidelines  
• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a  
greater than 0.1 µF ceramic capacitor as near as possible to the VDD pin.  
• To further improve the noise immunity on the SENSE pins, placing a 10 nF to 100 nF capacitor between the  
SENSE pin and GND can reduce the sensitivity to transient voltages on the monitored signal.  
• If a capacitor is used on CTS or CTR, place these components as close as possible to the respective pins. If  
the capacitor adjustable pins are left unconnected, make sure to minimize the amount of parasitic  
capacitance on the pins to less than 5 pF.  
• For open-drain variants, place the pull-up resistors on RESET as close to the pin as possible.  
• When laying out metal traces, separate high voltage traces from low voltage traces as much as possible. If  
high and low voltage traces need to run close by, spacing between traces should be greater than 20 mils (0.5  
mm).  
• Do not have high voltage metal pads or traces closer than 20 mils (0.5 mm) to the low voltage metal pads or  
traces.  
11.2 Layout Example  
The layout example in 图11-1 shows how the TPS3760-Q1 is laid out on a printed circuit board (PCB) with user-  
defined delays.  
CVDD  
VDD  
1
2
3
14  
13  
12  
NC  
NC  
GND  
TPS3760-Q1  
DYY Package  
Monitored Voltage  
NC  
NC  
4
5
6
7
11  
10  
9
NC  
NC  
CSENSE  
GND  
Reset Flag  
8
GND  
NC  
RPU  
VPULL-UP  
Vias used to connect pins for application-specific connections  
图11-1. TPS3760-Q1 Recommended Layout  
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11.3 Creepage Distance  
Per IEC 60664 Creepage is the shortest distance between two conductive parts or as shown in 图 11-2 the  
distance between high voltage conductive parts and grounded parts, the floating conductive part is ignored and  
subtracted from the total distance.  
a
b
A
C
B
图11-2. Creepage Distance  
图11-2 details  
• A = Left pins (high voltage)  
• B = Central pad (conductive not internally connected, can be left floating or connected to GND)  
• C = Right pins (low voltages)  
• Creepage distance = a + b  
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12 Device and Documentation Support  
12.1 Device Nomenclature  
节5 shows how to decode the function of the device based on its part number  
表 12-1 shows TPS3760-Q1 possible voltage options per channel. Contact TI sales representatives or on TI's  
E2E forum for details and availability of other options; minimum order quantities apply.  
表12-1. Voltage Options  
100 mV STEPS  
400 mV STEPS  
500 mV STEPS  
1 V STEPS  
NOMEN-  
CLATURE  
VOLTAGE  
OPTIONS  
NOMEN-  
CLATURE  
VOLTAGE  
OPTIONS  
NOMEN-  
CLATURE  
VOLTAGE  
OPTIONS  
NOMEN-  
CLATURE  
VOLTAGE  
OPTIONS  
NOMEN-  
CLATURE  
VOLTAGE  
OPTIONS  
08  
800 mV  
(divider  
bypass)  
70  
7.0 V  
A0  
10.4 V  
D0  
20.5 V  
F0  
31.0 V  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
2.7 V  
2.8 V  
2.9 V  
3.0 V  
3.1 V  
3.2 V  
3.3 V  
3.4 V  
3.5 V  
3.6 V  
3.7 V  
3.8 V  
3.9 V  
4.0 V  
4.1 V  
4.2 V  
4.3 V  
4.4 V  
4.5 V  
4.6 V  
4.7 V  
4.8 V  
4.9 V  
5.0 V  
5.1 V  
5.2 V  
5.3 V  
5.4 V  
5.5 V  
5.6 V  
5.7 V  
5.8 V  
5.9 V  
6.0 V  
6.1 V  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
00  
7.1 V  
7.2 V  
7.3 V  
7.4 V  
7.5 V  
7.6 V  
7.7 V  
7.8 V  
7.9 V  
8.0 V  
8.1 V  
8.2 V  
8.3 V  
8.4 V  
8.5 V  
8.6 V  
8.7 V  
8.8 V  
8.9 V  
9.0 V  
9.1 V  
9.2 V  
9.3 V  
9.4 V  
9.5 V  
9.6 V  
9.7 V  
9.8 V  
9.9 V  
10.0 V  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
C0  
C1  
C2  
C3  
C4  
10.8 V  
11.2 V  
11.6 V  
12.0 V  
12.4 V  
12.8 V  
13.2 V  
13.6 V  
14.0 V  
14.4 V  
14.8 V  
15.2 V  
15.6 V  
16.0 V  
16.4 V  
16.8 V  
17.2 V  
17.6 V  
18.0 V  
18.4 V  
18.8 V  
19.2 V  
19.6 V  
20.0 V  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
E0  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
21.0 V  
21.5 V  
22.0 V  
22.5 V  
23.0 V  
23.5 V  
24.0 V  
24.5 V  
25.0 V  
25.5 V  
26.0 V  
26.5 V  
27.0 V  
27.5 V  
28.0 V  
28.5 V  
29.0 V  
29.5 V  
30.0 V  
F1  
F2  
F3  
F4  
F5  
32.0 V  
33.0 V  
34.0 V  
35.0 V  
36.0 V  
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表12-1. Voltage Options (continued)  
100 mV STEPS  
400 mV STEPS  
500 mV STEPS  
1 V STEPS  
NOMEN-  
CLATURE  
VOLTAGE  
OPTIONS  
NOMEN-  
CLATURE  
VOLTAGE  
OPTIONS  
NOMEN-  
CLATURE  
VOLTAGE  
OPTIONS  
NOMEN-  
CLATURE  
VOLTAGE  
OPTIONS  
NOMEN-  
CLATURE  
VOLTAGE  
OPTIONS  
62  
63  
64  
65  
66  
67  
68  
69  
6.2 V  
6.3 V  
6.4 V  
6.5 V  
6.6 V  
6.7 V  
6.8 V  
6.9 V  
12.2 接收文档更新通知  
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更  
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。  
12.3 支持资源  
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解  
答或提出自己的问题可获得所需的快速设计帮助。  
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅  
TI 的《使用条款》。  
12.4 Trademarks  
TI E2E™ is a trademark of Texas Instruments.  
所有商标均为其各自所有者的财产。  
12.5 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
12.6 术语表  
TI 术语表  
本术语表列出并解释了术语、首字母缩略词和定义。  
13 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TPS3760A012DYYRQ1  
TPS3760E012DYYRQ1  
ACTIVE SOT-23-THIN  
ACTIVE SOT-23-THIN  
DYY  
DYY  
14  
14  
3000 RoHS & Green  
3000 RoHS & Green  
NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 125  
-40 to 125  
A012Q  
E012Q  
Samples  
Samples  
NIPDAU  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
29-Jul-2022  
OTHER QUALIFIED VERSIONS OF TPS3760-Q1 :  
Catalog : TPS3760  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Addendum-Page 2  
PACKAGE OUTLINE  
SOT-23-THIN - 1.1 mm max height  
PLASTIC SMALL OUTLINE  
DYY0014A  
C
3.36  
3.16  
SEATING PLANE  
PIN 1 INDEX  
AREA  
A
0.1 C  
12X 0.5  
14  
1
4.3  
4.1  
NOTE 3  
2X  
3
7
8
0.31  
0.11  
14X  
0.1  
C A  
B
1.1 MAX  
2.1  
1.9  
B
0.2  
0.08  
TYP  
SEE DETAIL A  
0.25  
GAUGE PLANE  
0°- 8°  
0.1  
0.0  
0.63  
0.33  
DETAIL A  
TYP  
4224643/B 07/2021  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed  
0.15 per side.  
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.  
5. Reference JEDEC Registration MO-345, Variation AB  
www.ti.com  
EXAMPLE BOARD LAYOUT  
SOT-23-THIN - 1.1 mm max height  
PLASTIC SMALL OUTLINE  
DYY0014A  
SYMM  
14X (1.05)  
1
14  
14X (0.3)  
SYMM  
12X (0.5)  
8
7
(R0.05) TYP  
(3)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE: 20X  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
SOLDER MASK  
OPENING  
METAL  
NON- SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
4224643/B 07/2021  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
SOT-23-THIN - 1.1 mm max height  
PLASTIC SMALL OUTLINE  
DYY0014A  
SYMM  
14X (1.05)  
1
14  
14X (0.3)  
SYMM  
12X (0.5)  
8
7
(R0.05) TYP  
(3)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE: 20X  
4224643/B 07/2021  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
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