TPS37A010122DSKR [TI]
TPS37 Wide VIN 65 V Dual Channel Overvoltage & Undervoltage (OV & UV) Detector with Programmable Sense and Reset Delay Function;
| 型号： | TPS37A010122DSKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS37 Wide VIN 65 V Dual Channel Overvoltage & Undervoltage (OV & UV) Detector with Programmable Sense and Reset Delay Function |
| 文件： | 总48页 (文件大小：5436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS37
SNVSBJ1D – OCTOBER 2020 – REVISED DECEMBER 2021
TPS37 Wide VIN 65 V Dual Channel Overvoltage & Undervoltage (OV & UV) Detector
with Programmable Sense and Reset Delay Function
1 Features
3 Description
•
•
•
•
Wide supply voltage range: 2.7 V to 65 V
SENSE and RESET pins are 65 V graded
Low quiescent current: 1 µA (typical)
Flexible and wide voltage threshold options
Table 13-1
– 2.7 V to 36 V (1.5% maximum accuracy)
– 800 mV option (1% maximum accuracy)
Built-in hysteresis (VHYS)
– Percentage options: 2% to 13% (1% steps)
– Fixed options: VTH < 8 V = 0.5 V, 1 V, 1.5 V,
2 V, 2.5 V
Programmable reset time delay
– 10 nF = 12.8 ms, 10 μF = 12.8 s
Programmable sense time delay
– 10 nF = 1.28 ms, 10 μF = 1.28 s
Manual Reset (MR) feature
The TPS37 is a family of wide input range and
low quiescent current window supervisors for fast
detection of overvoltage (OV) and undervoltage
(UV) conditions. Each device includes a precision
internal reference, two independent and configurable
voltage comparators and integrated resistor dividers.
The TPS37 can be connected directly to and
monitor 12 V / 24 V supply rails in a variety of
industrial applications including factory automation,
motor drives, building automation and others. Built-in
hysteresis on the SENSE pins prevents false reset
signals when monitoring a supply voltage rail.
•
•
•
The separate VDD and SENSE pins allow
redundancy sought by high-reliability systems.
SENSE is decoupled from VDD and can monitor
higher and lower voltages than VDD. Optional use
of external resistors are supported by the high
impedance input of the SENSE pins. CTSx and CTRx
pins allow delay adjustability on the rising and falling
edges of the RESET signals. Also, CTSx functions
as a debouncer by ignoring voltage glitches on the
monitored voltage rails; CTRx operates as a manual
reset (MR) that can be used to force a system reset.
•
•
•
Output reset latching feature
Output topology: Open-Drain or Push-Pull
2 Applications
•
•
•
•
•
•
Analog input module
CPU (PLC controller)
Servo drive control module
Servo drive power stage module
Servo drive functional safety module
HVAC valve and actuator control
TPS37 is available in a WSON or SOT-23 package.
The central pad is non-conductive to increase the
creepage between VDD and GND per guidelines in
IEC60664. TPS37 operates over –40°C to +125°C TA.
Device Information
PART NUMBER
TPS37
PACKAGE (1)
WSON (10) (DSK)
SOT-23 (14) (DYY) (2)
BODY SIZE (NOM)
2.5 mm × 2.5 mm
4.1 mm × 1.9 mm
TPS37
(1) For package details, see the mechanical drawing addendum
at the end of the data sheet.
(2) Product Preview
0.95
0.90
0.85
0.80
0.75
0.70
0.65
Power Switch
or
DC/DC
EN
24V
VDD
VDD
SENSE1
SENSE2
RESET1
RESET2
MCU
TPS37
LDO
0.60
-40oC
25oC
0.55
0.50
125oC
SENSE1 = Overvoltage monitor
SENSE2 = Undervoltage monitor
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
Typical IDD vs VDD
Typical Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS37
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SNVSBJ1D – OCTOBER 2020 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements..................................................9
7.7 Timing Diagrams ......................................................10
7.8 Typical Characteristics..............................................12
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................16
9 Device Functional Modes............................................. 24
10 Application and Implementation................................25
10.1 Adjustable Voltage Thresholds............................... 25
10.2 Application Information........................................... 26
11 Power Supply Recommendations..............................29
11.1 Power Dissipation and Device Operation................29
12 Layout...........................................................................30
12.1 Layout Guidelines................................................... 30
12.2 Layout Example...................................................... 30
12.3 Creepage Distance................................................. 31
13 Device and Documentation Support..........................32
13.1 Device Nomenclature..............................................32
13.2 Support Resources................................................. 33
13.3 Trademarks.............................................................33
13.4 Electrostatic Discharge Caution..............................33
13.5 Glossary..................................................................33
14 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2021) to Revision D (December 2021)
Page
•
Advanced Information to Production Data release............................................................................................. 1
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5 Device Comparison
Contact TI sales representatives or consult TI's E2E forum for details and availability; minimum order quantities
may apply.
Voltage Threshold
Hysteresis
CH 2
CH 1
CH 1
CH 2
XX XX X
X XXX R
TPS37 X
DYY
Large
1. Sense logic: OV = overvoltage; UV = undervoltage
2. Reset topology: PP = Push-Pull; OD = Open-Drain
3. Reset logic: L = Active-Low; H = Active-High
4. A to I hysteresis options are only available for 2.7 V to 8 V threshold options
5. Product Preview (DYY) package
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6 Pin Configuration and Functions
GND
VDD
SENSE1
SENSE2
1
2
3
4
5
10
9
CTR2/MR
8
CTS2
7
CTS1
*
CTR1/MR
6
**
* Pin 4 Options
** Pin 5 Options
1.RESET1_OV##
2.RESET1_OV##
1.RESET2_UVOD
2.RESET2_UVOD
## OD (Open-Drain) or PP (Push-Pull)
Figure 6-1. DSK Package,
10-Pin WSON,
TPS37 (Top View)
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
VDD
GND
NC
CTR2/MR
CTS2
SENSE1
SENSE2
CTS1
NC
*
CTR1/MR
GND
8
**
* Pin 6 Options
** Pin 7 Options
1.RESET1_OV##
2.RESET1_OV##
1.RESET2_UVOD
2.RESET2_UVOD
## OD (Open-Drain) or PP (Push-Pull)
Figure 6-2. DYY Package,
14-Pin SOT-23,
TPS37 (Top View)
PRODUCT PREVIEW
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Table 6-1. Pin Functions
WSON SOT23
(DSK)
(DYY)
PIN
NAME
I/O
DESCRIPTION
PIN
PIN
NUM.
NUM.
VDD
1
1
I
Input Supply Voltage: Bypass with a 0.1 µF capacitor to GND.
This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for
the adjustable variant. When the voltage on SENSE1 pin transitions above the upper threshold voltage
of VIT+, RESET1/RESET1 asserts after the sense time delay, set by CTS1. When the voltage on the
SENSE1 pin transitions below the upper threshold voltage of VIT+ - VHYS, RESET1/RESET1 deasserts
after the reset time delay, set by CTR1. For noisy applications, placing a 10 nF to 100 nF ceramic
capacitor close to this pin may be needed for optimum performance.
SENSE1
2
3
I
I
This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for
the adjustable variant. When the voltage on SENSE2 pin transitions below the lower threshold voltage
of VIT-, RESET2/RESET2 asserts after the sense time delay, set by CTS2. When the voltage on the
SENSE2 pin transitions above the lower threshold voltage of VIT- + VHYS, RESET2/RESET2 deasserts
after the reset time delay, set by CTR2. For noisy applications, placing a 10 nF to 100 nF ceramic
capacitor close to this pin may be needed for optimum performance.
SENSE2
3
4
Output Reset Signal For Channel 1: See Section 5 for output topology options. RESET1/RESET1
asserts when SENSE1 rises outside of the upper voltage threshold. RESET1/RESET1 remains
asserted for the reset time delay period after SENSE1 transitions out of an overvoltage (OV) fault
condition. For active low open-drain reset output, an external pullup resistor is required. Do not place
external pullup resistors on push-pull outputs.
RESET1/
RESET1
4
6
O
Reset output signal for: SENSE1
Sensing Topology: Overvoltage (OV)
Output topology: Open Drain or Push Pull, Active Low or Active High
Output Reset Signal For Channel 2: See Section 5 for output topology options. RESET2/RESET2
asserts when SENSE2 falls outside of the lower voltage threshold. RESET2/RESET2 remains
asserted for the reset time delay period after SENSE2 transitions out of an undervoltage (UV) fault
condition. For active low open-drain reset output, an external pullup resistor is required.
Reset output signal for: SENSE2
RESET2/
RESET2
5
7
O
Sensing Topology: Undervoltage (UV)
Output topology: Open Drain, Active Low or Active High
Channel 1 RESET Time Delay: User-programmable reset time delay for RESET1/RESET1. Connect
an external capacitor for adjustable time delay or leave the pin floating for the shortest delay.
Manual Reset: If this pin is driven low, the RESET1/RESET1 output will reset and become asserted.
The pin can be left floating or be connected to a capacitor. This pin should not be driven high.
CTR1/ MR
CTR2/ MR
6
9
9
-
-
Channel 2 RESET Time Delay: User-programmable reset time delay for RESET2/RESET2. Connect
an external capacitor for adjustable time delay or leave the pin floating for the shortest delay.
Manual Reset: If this pin is driven low, the RESET2/RESET2 output will reset and become asserted.
12
The pin can be left floating or be connected to a capacitor. This pin should not be driven high.
GND
NC
10
8, 13
-
-
Ground. All GND pins must be electrically connected to the board ground.
The PAD for the DSK package is not internally connected, the PAD can be connected to GND or be
left floating. For the DYY package, NC stands for “No Connect”. The pins are to be left floating.
PAD
2, 5, 14
Channel 1 SENSE Time Delay: Capacitor programmable sense delay: CTS1 pin offers a user-
adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-
referenced capacitor sets the RESET1/RESET1 delay time to assert.
CTS1
CTS2
7
8
10
11
O
O
Channel 2 SENSE Time Delay: Capacitor programmable sense delay: CTS2 pin offers a user-
adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-
referenced capacitor sets the RESET2/RESET2 delay time to assert.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted (1)
MIN
–0.3
–0.3
MAX
70
UNIT
V
Voltage
VDD, VSENSE1,VSENSE2, VRESET1, VRESET2, VRESET1, VRESET2
Voltage
VCTS1, VCTS2, VCTR1, VCTR2
IRESET1, IRESET2, IRESET1, IRESET2
Operating junction temperature, TJ
Operating Ambient temperature, TA
Storage, Tstg
6
V
Current
10
mA
°C
°C
°C
Temperature (2)
Temperature (2)
Temperature (2)
–40
–40
–65
150
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001 (1)
± 2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101 (2)
± 750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
0
NOM
MAX
65
UNIT
V
Voltage
Voltage
Voltage
Current
TJ
VDD
VSENSE1,VSENSE2, VRESET1, VRESET2, VRESET1, VRESET2
VCTS1, VCTS2, VCTR1, VCTR2
65
V
0
5.5
±5
V
IRESET1, IRESET2, IRESET1, IRESET2
Junction temperature (free air temperature)
0
mA
°C
–40
125
7.4 Thermal Information
TPS37
DSK
10-PIN
87.4
THERMAL METRIC (1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
76.3
54.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.8
ψJB
54.2
RθJC(bot)
34.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At VDD(MIN) ≤ VDD ≤ VDD (MAX), CTR1/MR = CTR2/MR = CTS1 = CTS2 = open, output reset pull-up resistor RPU = 10 kΩ,
voltage VPU = 5.5 V, and load CLOAD = 10 pF. The operating free-air temperature range TA = – 40°C to 125°C, unless
otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to VITN or VITP).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
VDD
Supply Voltage
2.7
65
V
V
UVLO (1)
Under Voltage Lockout
VDD Falling below VDD (MIN)
2.7
Power on Reset Voltage (2)
RESET, Active Low
(Open-Drain, Push-Pull )
VOL(MAX) = 300 mV
IOUT (Sink) = 15 µA
VPOR
1.4
1.4
V
V
Power on Reset Voltage (2)
RESET, Active High
(Push-Pull )
VOH(MIN) = 0.8 x VDD
IOUT (Source) = 15 µA
VPOR
VIT = 800 mV
VDD (MIN) ≤ VDD ≤ VDD
1
1
2.6
2
µA
µA
(MAX)
IDD
Supply current into VDD pin
VIT = 2.7 V to 36 V
VDD (MIN) ≤ VDD ≤ VDD
(MAX)
SENSE (Input)
Input current
(SENSE1, SENSE2)
ISENSE
VIT = 800 mV
VIT < 10 V
100
0.8
1.2
2
nA
µA
µA
µA
Input current
(SENSE1, SENSE2)
ISENSE
ISENSE
ISENSE
Input current
(SENSE1, SENSE2)
10 V < VIT < 26 V
VIT > 26 V
Input current
(SENSE1, SENSE2)
VIT = 2.7 V to 36 V
VIT = 800 mV (3)
-1.5
0.792
-1.5
1.5
0.808
1.5
%
V
Input Threshold Negative
(Undervoltage)
VITN
0.800
0.800
Input Threshold Positive
(Overvoltage)
VIT = 2.7 V to 36 V
%
VITP
VIT = 800 mV (3)
0.792
0.808
V
VIT = 0.8 V and 2.7 V to 36 V
VHYS Range = 2% to 13%
(1% step)
-1.5
1.5
%
VHYS
Hysteresis Accuracy (4)
VIT = 2.7 V to 8 V
VHYS = 0.5 V, 1 V, 1.5 V, 2 V,
2.5 V
-1.5
1.5
%
VIT-VHYS ≥ 2.4 V
RESET (Output)
VRESET = 5.5 V
VITN < VSENSE < VITP
300
300
300
nA
nA
Open-Drain leakage
(RESET1, RESET2)
Ilkg(OD)
VRESET = 65 V
VITN < VSENSE < VITP
2.7 V ≤ VDD ≤ 65 V
IRESET = 5 mA
(5)
VOL
Low level output voltage
mV
High level output voltage
dropout
2.7 V ≤ VDD ≤ 65 V
IRESET = 500 uA
VOH_DO
(VDD - VOH = VOH_DO
(Push-Pull only)
)
100
mV
V
High level output voltage
(Push-Pull only)
2.7 V ≤ VDD ≤ 65 V
IRESET = 5 mA
(5)
VOH
0.8VDD
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7.5 Electrical Characteristics (continued)
At VDD(MIN) ≤ VDD ≤ VDD (MAX), CTR1/MR = CTR2/MR = CTS1 = CTS2 = open, output reset pull-up resistor RPU = 10 kΩ,
voltage VPU = 5.5 V, and load CLOAD = 10 pF. The operating free-air temperature range TA = – 40°C to 125°C, unless
otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to VITN or VITP).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Capacitor Timing (CTS, CTR)
Internal resistance
RCTR
877
88
1000
100
1147
122
Kohms
Kohms
(CTR1 / MR , CTR2 / MR )
Internal resistance
(CTS1, CTS2
RCTS
)
Manual Reset (MR)
CTR1 / MR and
CTR2 / MR pin
logic high input
VMR_IH
VMR_IH
VMR_IL
VMR_IL
VDD = 2.7 V
2200
2500
mV
mV
mV
mV
CTR1 / MR and
CTR2 / MR pin
logic high input
VDD = 65 V
VDD = 2.7 V
VDD = 65 V
CTR1 / MR and
CTR2 / MR pin
logic low input
1300
1300
CTR1 / MR and
CTR2 / MR pin
logic low input
(1) When VDD voltage falls below UVLO, reset is asserted for Output 1 and Output 2. VDD slew rate ≤ 100 mV / µs
(2) VPOR is the minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined. VDD dv/dt ≤ 100mV/µs
(3) For adjustable voltage guidelines and resistor selection refer to Adjustable Voltage Thresholds in Application and Implementation
section
(4) Hysteresis is with respect to VITP and VITN voltage threshold. VITP has negative hysteresis and VITN has positive hysteresis.
(5) For VOH and VOL relation to output variants refer to Timing Figures after the Timing Requirement Table
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7.6 Timing Requirements
At VDD(MIN) ≤ VDD ≤ VDD (MAX), CTR1/MR = CTR2/MR = CTS1 = CTS2 = open (1), output reset pull-up resistor RPU = 10 kΩ,
voltage VPU = 5.5V, and CLOAD = 10 pF. VDD and SENSE slew rate = 1V / µs. The operating free-air temperature range TA =
– 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to
either VITN or VITP).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Common timing parameters
VIT = 2.7 V to 36 V
CCTR1 = CCTR2 = Open
20% Overdrive from Hysteresis
100
40
µs
µs
µs
Reset release time delay
tCTR
(CTR1/MR, CTR2/MR) (2)
VIT = 800 mV
CCTR1 = CCTR2 = Open
20% Overdrive from Hysteresis
VIT = 2.7 V to 36 V
CCTS1 = CCTS2 = Open
20% Overdrive from VIT
34
8
90
Sense detect time delay
(CTS1, CTS2) (3)
tCTS
VIT = 800 mV
CCTS1 = CCTS2 = Open
20% Overdrive from VIT
17
2
µs
CCTR1/MR = CCTR2/MR = Open
tSD
Startup Delay (4)
ms
(1) CCTR1 = Reset delay channel 1, CCTR2 = Reset delay channel 2,
CCTS1 = Sense delay channel 1, CCTS2 = Sense delay channel 2
(2) CTR Reset detect time delay:
Overvoltage active-LOW output is measure from VITP - HYS to VOH
Undervoltage active-LOW output is measure from VITN + HYS to VOH
Overvoltage active-HIGH output is measure from VITP - HYS to VOL
Undervoltage active-HIGH output is measure from VITN + HYS to VOL
(3) CTS Sense detect time delay:
Active-low output is measure from VIT to VOL (or VPullup
Active-high output is measured from VIT to VOH
VIT refers to either VITN or VITP
)
(4) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD before the output is in the correct state based on
VSENSE
tSD time includes the propagation delay (CCTR1 = CCTR2 = Open). Capaicitor in CCTR1 or CCTR2 will add time to tSD.
.
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7.7 Timing Diagrams
VDD(MIN)
VDD
UVLO(MIN)
VPOR
SENSEx
VSENSEx
VITN (UV) + VHYS
VITN (UV)
Hysteresis
*See
Note C
t < tCTSx
RESETx_UVxx
tSD + tCTRx
tCTSx
tCTRx
*See
Note C
RESETx_UVxx
tSD + tCTRx
tCTSx
tCTRx
A. For open-drain output option, the timing diagram assumes the RESETx_UVOD / RESETx_UVOD pin is connected via an external pull-up resistor to VDD.
B. Be advised that this diagram shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTRx) time.
C. RESETx_UVxx / RESETx_UVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTRx, is reached.
Figure 7-1. SENSEx Undervoltage (UV) Timing Diagram
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VDD(MIN)
VDD
UVLO(MIN)
VPOR
VITP (OV)
SENSEx
Hysteresis
VITP (OV) - VHYS
VSENSEx
*See
Note C
t < tCTSx
RESETx_OVxx
tSD + tCTRx
tCTSx
tCTRx
*See
Note C
RESETx_OVxx
tSD + tCTRx
tCTSx
tCTRx
A. For open-drain output option, the timing diagram assumes the RESETx_OVOD / RESETx_OVOD pin is connected via an external pull-up resistor to VDD.
B. Be advised that this diagram shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTRx) time.
C. RESETx_OVxx / RESETx_OVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTRx, is reached.
Figure 7-2. SENSEx Overvoltage (OV) Timing Diagram
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7.8 Typical Characteristics
Typical characteristics show the typical performance of the TPS37 device. Test conditions are TA = 25°C, RPU = 100 kΩ,
CLoad = 50 pF, unless otherwise noted.
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
-40oC
25oC
-40oC
25oC
125oC
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
RESET = High, VIT = 2.7 V
RESET = Low, VIT = 2.7 V
Figure 7-3. VDD vs IDD (RESET = High, VIT = 2.7 V)
Figure 7-4. VDD vs IDD (RESET = Low, VIT = 2.7 V)
1.30
1.40
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
-40oC
25oC
-40C
25oC
125C
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
RESET = High, VIT = 0.8 V
RESET = Low, VIT = 0.8 V
Figure 7-5. VDD vs IDD (RESET = High, VIT = 0.8 V)
Figure 7-6. VDD vs IDD (RESET = Low, VIT = 0.8 V)
1600
1600
1400
1200
1000
800
600
400
200
0
1400
1200
1000
800
600
400
200
0
-40oC
25oC
-40oC
25oC
125oC
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Sense Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Sense Voltage (V)
VDD = 2.7 V
VDD = 65 V
Figure 7-7. VSENSE vs ISENSE
Figure 7-8. VSENSE vs ISENSE
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS37 device. Test conditions are TA = 25°C, RPU = 100 kΩ,
CLoad = 50 pF, unless otherwise noted.
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0.00
-40oC
25oC
-40oC
25oC
125oC
125oC
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
VDD = 2.7 V
VDD = 65 V
Figure 7-9. Open-Drain Active Low VOL vs IRESET
Figure 7-10. Open-Drain Active Low VOL vs IRESET
0.21
0.21
-40oC
25oC
-40oC
25oC
0.18
0.15
0.12
0.09
0.06
0.03
0
0.18
0.15
0.12
0.09
0.06
0.03
0
125oC
125oC
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
VDD = 2.7 V
VDD = 65 V
Figure 7-11. Open-Drain Active High VOL vs IRESET
Figure 7-12. Open-Drain Active High VOL vs IRESET
0.21
0.21
-40oC
25oC
-40oC
25oC
0.18
0.15
0.12
0.09
0.06
0.03
0
0.18
0.15
0.12
0.09
0.06
0.03
0
125oC
125oC
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IRESET (mA)
VDD = 2.7 V
VDD = 65 V
Figure 7-13. Push-Pull Active High VOL vs IRESET
Figure 7-14. Push-Pull Active High VOL vs IRESET
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TPS37 device. Test conditions are TA = 25°C, RPU = 100 kΩ,
CLoad = 50 pF, unless otherwise noted.
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
-40oC
25oC
-40oC
25oC
125oC
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
Figure 7-15. Open-Drain Active Low VOL vs VDD
Figure 7-16. Open-Drain Active High VOL vs VDD
0.21
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
0.18
0.15
0.12
0.09
0.06
0.03
0
-40oC
25oC
-40oC
25oC
125oC
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
Figure 7-17. Push-Pull Active Low VOL vs VDD
Figure 7-18. Push-Pull Active High VOL vs VDD
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
-40oC
-40oC
25oC
25oC
125oC
125oC
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
Figure 7-19. Push-Pull Active Low VOH vs VDD
Figure 7-20. Push-Pull Active High VOH vs VDD
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8 Detailed Description
8.1 Overview
The TPS37 is a family of high voltage and low quiescent current reset IC with fixed threshold voltage. Voltage
divider is integrated to eliminate the need for external resistors and eliminate leakage current that comes with
resistor dividers. However, it can also support external resistor if required by application, the lowest threshold
800 mV (bypass internal resistor ladder) is recommenced for external resistors use case to take advantage of
faster detection time and lower ISENSE current.
VDD, SENSE and RESET pins can support 65 V continuous operation; both VDD and SENSE voltage levels can
be independent of each other, meaning VDD pin can be connected at 2.7 V while SENSE pins are connected
to a higher voltage. One thing of note, the TPS37 does not have clamps within the device so external circuits or
devices must be added to limit the voltages to the absolute max limit.
Additional features include programmable sense time delay (CTS1, CTS2) and reset delay time and manual
reset (CTR1 / MR, CTR2 / MR).
8.2 Functional Block Diagram
VDD
CTS1
CTR1 / MR
*Device Op ons
Boxes shaded in blue
See Device Nomenclature
IQ
SubReg
POR
VDD
Voltage
Divider
SENSE1
-
Output
Logic select
(High/Low)
OV or UV
Select
Sense
Delay
Manual
Reset
Reset
Delay
RESET1
V
Ref Divider1
+
REFERENCE
RESET2
V
Ref Divider2
+
-
Output
Logic select
(High/Low)
OV or UV
Select
Sense
Delay
Manual
Reset
Reset
Delay
Voltage
Divider
SENSE2
GND
CTR2 / MR
CTS2
Figure 8-1. Functional Block Diagram 1
1
Refer to Section 5 for complete list of topologies and output logic combination
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8.3 Feature Description
8.3.1 Input Voltage (VDD)
VDD operating voltage ranges from 2.7 V to 65 V. An input supply capacitor is not required for this device;
however, if the input supply is noisy good analog practice is to place a 0.1 µF capacitor between the VDD and
GND.
VDD needs to be at or above VDD(MIN) for at least the start-up time delay (tSD) for the device to be fully functional.
VDD voltage is independent of VSENSE and VRESET, meaning that VDD can be higher or lower than the other
pins.
8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
When the voltage on VDD is less than the UVLO voltage, but greater than the power-on reset voltage (VPOR),
the output pins will be in reset, regardless of the voltage at SENSE pins.
8.3.1.2 Power-On Reset (VDD < VPOR
)
When the voltage on VDD is lower than the power on reset voltage (VPOR), the output signal is undefined and is
not to be relied upon for proper device function.
SENSE VOLTAGE OUTSIDE OF THRESHOLD
VSENSEx
VITN > VSENSEx > VITP
VDD(MIN)
VDD
UVLO(MIN)
VPOR
RESETx
Active Low
Output stays low since VSENSEx
is outside of threshold
VOL
RESETx
Active High
VOL
Undefined
Undefined
tSD+ CTRx
t
Figure 8-2. Power Cycle (SENSE Outside of Nominal voltage) 2
2
Figure assumes an external pull-up resistor is connected to the reset pin via VDD
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SENSE VOLTAGE WITH IN THRESHOLD
VITN < VSENSEx < VITP
VSENSEx
VDD(MIN)
VDD
UVLO(MIN)
VPOR
RESETx
Active Low
VOL
RESETx
Active High
VOL
Undefined
Undefined
tSD+ CTRx
t
Figure 8-3. Power Cycle (SENSE Within Nominal voltage) 3
3
Figure assumes an external pull-up resistor is connected to the reset pin via VDD
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8.3.2 SENSE
The TPS37 high voltage family integrates two voltage comparators, a precision reference voltage and trimmed
resistor divider. This configuration optimizes device accuracy because all resistor tolerances are accounted for
in the accuracy and performance specifications. Device also has built-in hysteresis that provides noise immunity
and ensures stable operation.
Channels are independent of each other, meaning that SENSE1 and SENSE2 and respective outputs can be
connected to different voltage rails.
Although not required in most cases, for noisy applications good analog design practice is to place a 10 nF to
100 nF bypass capacitor at the SENSEx inputs in order to reduce sensitivity to transient voltages on the
monitored signal. SENSE1 and SENSE2 pins can be connected directly to VDD pin.
8.3.2.1 SENSE Hysteresis
Built-in hysteresis to avoid erroneous output reset release. The hysteresis is opposite to the threshold voltage;
for overvoltage options the hysteresis is subtracted from the positive threshold (VITP), for undervoltage options
hysteresis is added to the negative threshold (VITN).
VRESETx
VRESETx
VSENSEx
VSENSEx
VITP - VHYS
VITP
VITP - VHYS
VITP
Figure 8-4. Hysteresis (Overvoltage Active-Low)
Figure 8-5. Hysteresis (Overvoltage Active-High)
VRESETx
VRESETx
VSENSEx
VSENSEx
VITN
VITN
VITN+VHYS
VITN+VHYS
Figure 8-6. Hysteresis (Undervoltage Active-High) Figure 8-7. Hysteresis (Undervoltage Active-Low)
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Table 8-1. Common Hysteresis Lookup Table
TARGET
DEVICE ACTUAL HYSTERESIS OPTION
DETECT THRESHOLD
TOPOLOGY
Overvoltage
Overvoltage
Overvoltage
Overvoltage
Overvoltage
Undervoltage
Undervoltage
Undervoltage
Undervoltage
RELEASE VOLTAGE (V)
18.0 V
18.0 V
17.0 V
16.0 V
15.0 V
6.0 V
5.5 V
8 V
17.5 V
16.0 V
16.5 V
15.0 V
14.0 V
6.5 V
6 V
-3%
-11%
-3%
-6%
-7%
0.5 V
0.5 V
1 V
9 V
5 V
7.5 V
2.5 V
Table 8-1 shows a sample of hysteresis and voltage options for the TPS37. For threshold voltages ranging from
2.7 V to 8 V, one option is to select a fixed hysteresis value ranging from 0.5 V to 2.5 V in increments of
0.5 V. Additionally, a second option can be selected where the hysteresis value is a percentage of the threshold
voltage. The percentage of voltage hysteresis ranges from 2% to 13%.
Knowing the amount of hysteresis voltage, the release voltage for the undervoltage (UV) channel is
(VITN(UV) + VHYS) and for the overvoltage (OV) channel is (VITP(OV) - VHYS). For a visual understanding of the
UV and OV release voltage, see SENSEx Undervoltage (UV) Timing Diagram and SENSEx Overvoltage (OV)
Timing Diagram. The accuracy of the release voltage, or stated in the Section 7.5 as Hysteresis Accuracy is
±1.5%. Expanding what is shown in Table 8-1, below are a few voltage hysteresis examples that include the
hysteresis accuracy:
Undervoltage (UV) Channel
VITN = 0.8 V
Voltage Hysteresis (VHYS) = 5% = 40 mV
Hysteresis Accuracy = ±1.5% = 39.4 mV or 40.6 mV
Release Voltage = VITN + VHYS = 839.4 mV to 840.6 mV
Overvoltage (OV) Channel
VITP = 8 V
Voltage Hysteresis (VHYS) = 2 V
Hysteresis Accuracy = ±1.5% = 1.97 V or 2.03 V
Release Voltage = VITP - VHYS = 5.97 V to 6.03 V
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8.3.3 Output Logic Configurations
TPS37 has two channels with separate sense pins and reset pins that can be configured independently of each
other. Channel 1 is available as Open-Drain and Push-Pull while channel 2 is only available as Open-Drain
topology.
The available output logic configuration combinations are shown in Table 8-2.
Table 8-2. TPS37 Output Logic
DESCRIPTION
GPN
NOMENCLATURE
TPS37 (+ topology)
TPS37A
VALUE
CHANNEL 1
OV OD L
OV PP H
OV OD L
OV PP H
OV OD H
OV PP H
OV OD L
OV OD H
CHANNEL 2
UV OD L
UV OD L
UV OD H
UV OD H
UV OD H
UV OD L
UV OD H
UV OD L
Topology (OV and UV only)
both channels are either OV or
UV
TPS37B
TPS37C
•
•
•
•
•
•
UV = Undervoltage
OV = Overvoltage
PP = Push-Pull
OD = Open-Drain
L = Active low
TPS37D
TPS37E
TPS37F
TPS37G
H = Active high
TPS37H
8.3.3.1 Open-Drain
Open-drain output requires an external pull-up resistor to hold the voltage high to the required voltage logic.
Connect the pull-up resistor to the proper voltage rail to enable the output to be connected to other devices at
the correct interface voltage levels.
To select the right pull-up resistor consider system VOH and the (Ilkg) current provided in the electrical
characteristics, high resistors values will have a higher voltage drop affecting the output voltage high. The
open-drain output can be connected as a wired-AND logic with other open-drain signals such as another TPS37
open-drain output pin.
8.3.3.2 Push-Pull
Push-Pull output does not require an external resistor since is the output is internally pulled-up to VDD during
VOH condition and output will be connected to GND during VOH condition.
8.3.3.3 Active-High (RESET)
RESET (active-high), denoted with no bar above the pin label. RESET remains low (VOL, deasserted) as long as
sense voltage is in normal operation within the threshold boundaries and VDD voltage is above UVLO. To assert
a reset sense pins needs to meet the condition below:
•
•
For undervoltage variant the SENSE voltage need to cross the lower boundary (VITN).
For overvoltage variant the SENSE voltage needs to cross the upper boundary (VITP).
8.3.3.4 Active-Low (RESET)
RESET (active low) denoted with a bar above the pin label. RESET remains high voltage (VOH, deasserted)
(open-drain variant VOH is measured against the pullup voltage) as long as sense voltage is in normal operation
within the threshold boundaries and VDD voltage is above UVLO. To assert a reset sense pins needs to meet
the condition below:
•
•
For undervoltage variant the SENSE voltage need to cross the lower boundary (VITN).
For overvoltage variant the SENSE voltage needs to cross the upper boundary (VITP).
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8.3.4 User-Programmable Reset Time Delay
TPS37 has adjustable reset release time delay with external capacitors. Channel timing are independent of each
other.
•
•
•
A capacitor in CTR1 / MR program the reset time delay of Output 1.
A capacitor in CTR2 / MR program the reset time delay of Output 2.
No capacitor on these pins gives the fastest reset delay time indicated in the Section 7.6.
8.3.4.1 Reset Time Delay Configuration
The time delay (tCTR) can be programmed by connecting a capacitor between CTR1 pin and GND, CTR2 for
channel 2. In this section CTRx represent either channel 1 or channel 2.
The relationship between external capacitor CCTRx_EXT (typ) and the time delay tCTRx (typ) is given by Equation 1.
tCTRx (typ) = -ln (0.28) x RCTRx (typ) x CCTRx_EXT (typ) + tCTRx (no cap)
(1)
RCTRx (typ) = is in kilo ohms (kOhms)
CCTRx_EXT (typ) = is given in microfarads (μF)
tCTRx (typ) = is the reset time delay (ms)
The reset delay varies according to three variables: the external capacitor (CCTRx_EXT), CTR pin internal
resistance (RCTRx) provided in Section 7.5, and a constant. The minimum and maximum variance due to the
constant is show in Equation 2 and Equation 3:
tCTRx (min) = -ln (0.31) x RCTRx (min) x CCTRx_EXT (min) + tCTRx (no cap (min))
tCTRx (max) = -ln (0.25) x RCTRx (max) x CCTRx_EXT (max) + tCTRx (no cap (max))
(2)
(3)
The recommended maximum reset delay capacitor for the TPS37 is limited to 10 μF as this ensures enough
time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value
can cause very slow charge up (rise times) and system noise can cause the the internal circuit to trip earlier or
later near the threshold. This leads to variation in time delay where it can make the delay accuracy worse in the
presence of system noise.
When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage
returns from the fault condition before the delay capacitor discharges completely, the delay will be shorter than
expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected
time delay. A larger delay capacitor can be used so long as the capacitor has enough time to fully discharge
during the duration of the voltage fault. To ensure the capacitor is fully discharged, the time period or duration of
the voltage fault needs to be greater than 5% of the programmed reset time delay.
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8.3.5 User-Programmable Sense Delay
TPS37 has adjustable sense release time delay with external capacitors. Channel timing are independent of
each other. Sense delay is used as a de-glitcher or ignoring known transients.
•
•
•
A capacitor in CTS1 program the excursion detection on SENSE1.
A capacitor in CTS2 program the excursion detection on SENSE2.
No capacitor on these pins gives the fastest detection time indicated in the Section 7.6.
8.3.5.1 Sense Time Delay Configuration
The time delay (tCTS) can be programmed by connecting a capacitor between CTS1 pin and GND, CTS2 for
channel 2. In this section CTSx represent either channel 1 or channel 2.R
The relationship between external capacitor CCTSx_EXT (typ) and the time delay tCTSx (typ) is given by Equation 4.
tCTSx (typ) = -In (0.28) x RCTSx (typ) x CCTSx_EXT (typ) + tCTSx (no cap)
(4)
RCTSx = is in kilo ohms (kOhms)
CCTSX_EXT = is given in microfarads (μF)
tCTSx = is the sense time delay (ms)
The sense delay varies according to three variables: the external capacitor (CCTSx_EXT), CTS pin internal
resistance (RCTSx) provided in Section 7.5, and a constant. The minimum and maximum variance due to the
constant is show in Equation 5 and Equation 6:
tCTSx (min) = -ln (0.31) x RCTSx (min) x CCTSx_EXT (min) + tCTSx (no cap (min))
tCTRx (max) = -ln (0.25) x RCTSx (max) x CCTSx_EXT (max) + tCTSx (no cap (max))
(5)
(6)
The recommended maximum sense delay capacitor for the TPS37 is limited to 10 μF as this ensures enough
time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value
can cause very slow charge up (rise times) and system noise can cause the the internal circuit to trip earlier or
later near the threshold. This leads to variation in time delay where it can make the delay accuracy worse in the
presence of system noise.
When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage
returns from the fault condition before the delay capacitor discharges completely, the delay will be shorter than
expected. The capacitor will begin charging from a voltage above zero and resulting in shorter than expected
time delay. A larger delay capacitor can be used so long as the capacitor has enough time between fault events
to fully discharge during the duration of the voltage fault. To ensure the capacitor is fully discharged, the time
period or time duration between fault events needs to be greater than 10% of the programmed sense time delay.
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8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input
The manual reset input allows a processor or other logic circuits to initiate a reset. In this section MR is a generic
reference to (CTR1 / MR) and (CTR2 / MR). A logic low on MR causes RESET1 to assert on reset output.
After MR is left floating, RESET1 will release the reset if the voltage at SENSE1 pin is at nominal voltage. MR
should not be driven high, this pin should be left floating or connected to a capacitor to GND, this pin can be left
unconnected if is not used.
If the logic driving the MR cannot tri-state (floating and GND) then a logic-level FET should be used as illustrated
in Figure 8-8.
Low Voltage
High Voltage
VDD
MCU
CTRx
Active low
Logic
Reset
Delay
GPIO
Low or Floating
Figure 8-8. Manual Reset Implementation
SENSE VOLTAGE WITH IN THRESHOLD
VITN < VSENSEx < VITP
VSENSEx
CTRx/MR
< VMR
MR floating or
connected to capacitor
MR floating or
connected to capacitor
RESETx
Active-High
RESETx
Active-Low
Figure 8-9. Manual Reset Timing Diagram
Table 8-3. MR Functional Table
MR
SENSE ON NOMINAL VOLTAGE
RESET STATUS
Low
Yes
Yes
Reset asserted
Fast reset release when SENSE
voltage goes back to nominal
voltage
Floating
Capacitor
High
Yes
Yes
Programmable reset time delay
NOT Recommended
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9 Device Functional Modes
Table 9-1. Undervoltage Detect Functional Mode Truth Table
SENSE
OUTPUT (2)
(RESET PIN)
DESCRIPTION
CTR (1) / MR PIN
VDD PIN
PREVIOUS
CONDITION
CURRENT CONDITION
Open or capacitor
connected
Normal Operation
SENSE > VITN(UV)
SENSE > VITN(UV)
SENSE < VITN(UV)
SENSE > VITN(UV)
SENSE < VITN(UV)
SENSE > VITN(UV)
VDD > VDD(MIN)
VDD > VDD(MIN)
VDD > VDD(MIN)
High
Low
Low
Undervoltage
Detection
Open or capacitor
connected
Undervoltage
Detection
Open or capacitor
connected
Open or capacitor
connected
Normal Operation
Manual Reset
SENSE < VITN(UV) SENSE > VITN(UV) + HYS
VDD > VDD(MIN)
VDD > VDD(MIN)
High
Low
Low
SENSE > VITN(UV)
SENSE > VITN(UV)
SENSE > VITN(UV)
SENSE > VITN(UV)
Low
Open or capacitor
connected
UVLO Engaged
VPOR < VDD < VDD(MIN)
Below VPOR
Undefined Output
,
Open or capacitor
connected
SENSE > VITN(UV)
SENSE > VITN(UV)
VDD < VPOR
Undefined
(1) Reset time delay is ignored in the truth table.
(2) Open-drain active low output requires an external pull-up resistor to a pull-up voltage.
Table 9-2. Overvoltage Detect Functional Mode Truth Table
SENSE
OUTPUT (2)
(RESET PIN)
DESCRIPTION
CTR (1) / MR PIN
VDD PIN
PREVIOUS
CONDITION
CURRENT CONDITION
SENSE < VITN(OV)
SENSE > VITN(OV)
SENSE < VITN(OV)
Open or capacitor
connected
Normal Operation
SENSE < VITN(OV)
SENSE < VITN(OV)
SENSE > VITN(OV)
VDD > VDD(MIN)
VDD > VDD(MIN)
VDD > VDD(MIN)
High
Low
Low
Overvoltage
Detection
Open or capacitor
connected
Overvoltage
Detection
Open or capacitor
connected
Open or capacitor
connected
Normal Operation
Manual Reset
SENSE > VITN(OV)
SENSE < VITN(OV)
SENSE < VITN(OV)
SENSE < VITN(OV) - HYS
SENSE < VITN(OV)
VDD > VDD(MIN)
VDD > VDD(MIN)
High
Low
Low
Low
Open or capacitor
connected
UVLO Engaged
SENSE < VITN(OV)
VPOR < VDD < UVLO
Below VPOR
Undefined Output
,
Open or capacitor
connected
SENSE < VITN(OV)
SENSE < VITN(OV)
VDD < VPOR
Undefined
(1) Reset time delay is ignored in the truth table.
(2) Open-drain active low output requires an external pull-up resistor to a pull-up voltage.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Adjustable Voltage Thresholds
Equation 7 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The
resistors can be calculated depending on the desired voltage threshold and device part number. TI recommends
using the 0.8 V voltage threshold device when using an adjustable voltage variant. This variant bypasses the
internal resistor ladder.
For example, consider a 12 V rail being monitored VMON for undervoltage (UV) using channel 2 of the
TPS37A010122DSKR variant. Using Equation 7 and shown in Figure 10-1, R1 is the top resistor of the resistor
divider that is between VMON and VSENSE2, R2 is the bottom resistor that is between VSENSE2 and GND, VMON is
the voltage rail that is being monitored and VSENSE2 is the input threshold voltage. The monitored UV threshold,
denoted as VMON-, where the device will assert a reset signal occurs when VSENSE2 = VIT-(UV) or, for this
example, VMON- = 10.8V which is 90% from 12 V. Using Equation 7 and assuming R2 = 10kΩ, R1 can be
calculated shown in Equation 8 where IR1 is represented in Equation 9:
VSENSE2 = VMON- × (R2 ÷ (R1 + R2))
R1 = (VMON- - VSENSE2) ÷ IR1
IR1 = IR2 = VSENSE2 ÷ R2
(7)
(8)
(9)
Substituting Equation 9 into Equation 8 and solving for R1 in Equation 7, R1 = 125kΩ. The TPS37A010122DSKR
is typically meant to monitor a 0.8 V rail with ±2% voltage threshold hysteresis. For the reset signal to become
deasserted, VMON would need to go above VIT- + VHYS. For this example, VMON = 11.016 V when the reset signal
becomes deasserted.
There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the
tolerance of the resistor divider, there is an internal resistance of the SENSE pin that may affect the accuracy
of the resistor divider. Although expected to be very high impedance, users are recommended to calculate the
values for the design specifications. The internal SENSE resistance RSENSE can be calculated by the SENSE
voltage VSENSE divided by the SENSE current ISENSE as shown in Equation 11. VSENSE can be calculated using
Equation 7 depending on the resistor divider and monitored voltage. ISENSE can be calculated using Equation 10.
ISENSE = [(VMON - VSENSE) ÷ R1] - (VSENSE ÷ R2)
(10)
(11)
RSENSE = VSENSE ÷ ISENSE
VMON
VMON
VDD
10 k
VDD
VDD
VDD
R3
R1
10 k
VSENSE1
SENSE1
SENSE2
CTS1
RESET1
RESET2
CTR1
VSENSE2
TPS37A
R2
R4
CTS2
CTR2
GND
Figure 10-1. Adjustable Voltage Threshold with External Resistor Dividers
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10.1.1 Application Curves
V_SENSE
RESET_B
Figure 10-2. Undervoltage Reset Waveform
V_SENSE
RESET_B
Figure 10-3. Undervoltage Recovery Waveform
10.2 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
10.2.1 Typical Application
10.2.1.1 Design 1: High Voltage – Fast AC Signal Monitoring For Power Fault Detection
In many industrial and factory automation applications, there are multiple power rails that power various
subsystems within the application. Some of these power rails include 24 / 48 VAC AC sources with a known
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operating frequency that requires a full-bridge rectifier and capacitors to convert its signal to a DC voltage where
it can be monitored by a voltage supervisor. One drawback with the described conversion is the response time of
the DC voltage when the AC power rail experiences a change of operating frequency or voltage amplitude. Due
to the output filter of the full-bridge rectifier, the detection in the change of voltage or operating frequency may
require several AC cycles before the voltage supervisor outputs a fault condition. The direct monitoring of the
AC source by using a “Resistive-Drop” supply topology circuit provides the user a fast transient fault detection.
In this design example, the TPS37A is being highlighted with the ability to offer a unique “window operating”
solution by monitoring the output of the AC source for over or undervoltage operation.
DC Supply
(Rec ed)
VPull-Up
2.7V to 65V
VDD
OV SENSE1
"Resis ve-Drop"
supply topology circuit
RPull-Up
DC Fault Flag
RESET1
TPS37A
UV SENSE2
R1
R2
RPull-Up
RESET2
CTS2
AC Early Fault Flag
24 VAC
CTS1
GND
D1
R3
C1
* The circuit solu on is not isolated and one must take into account when planning to use in high power systems.
Figure 10-4. Sensing an AC Signal for Power Fault Detection
10.2.1.1.1 Design Requirements
This design requires voltage supervision on an AC, with a known operating frequency, power supply rail. The
overvoltage fault sensing is achieved by monitoring the DC output of a full bridge rectifier while the undervoltage
fault is detected by inputting a half wave signal and its voltage frequency and magnitude are being monitored.
The target output of this TPS37A application is for 5 V reset logic.
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Monitor 24 VAC 800 Hz power supply for
undervoltage and overvoltage conditions. Trigger
undervoltage fault at 5 V and overvoltage fault at
24 V.
TPS37A provides voltage monitoring with 1.5%
max accuracy with adjustable/non-adjustable
variations.
Power Rail Voltage Supervision
Maximum Input Voltage
Output logic voltage
Operate with power supply input up to 34 V.
Open-Drain Output Topology
The TPS37A can support a VDD of up to 65 V.
An open-drain output is recommended to provide
the a 5 V reset signal.
SENSE Delay when a fault is
detected
RESET delay of at least 0.625 ms which is the time
between half wave cycles
CCTS2 = 5.6 nF sets 717 µs delay
The TPS37A has 1.5% maximum voltage monitor
accuracy.
Voltage Monitor Accuracy
Maximum voltage monitor accuracy of 1.5%.
10.2.1.1.2 Detailed Design Procedure
The main advantage of this unique application is being able to monitor a single AC source with a known
operating frequency AC source rail. Because the TPS37A is an over and undervoltage detector with delay
function, detecting faults either from a change of operating frequency range or voltage amplitude of the AC
source is achievable.
Figure 10-4 illustrates an example of how the TPS37A is monitoring an AC source. Input to SENSE1 of TPS37A
is monitoring a full wave rectifier DC signal. The DC signal is the result from the rectification of the 24 VAC
source and monitors the AC source for overvoltage events due to a change of voltage amplitude or an increase
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to operating frequency. Input to SENSE2 of TPS37A will monitor the AC source by using a "resistive-drop"
supply topology circuit. The unique circuit resistively divides the AC voltage signal and provides only the positive
half wave Figure 10-5 into SENSE2 input. The half wave signal does not go through any output filter and hence
any change to the AC voltage or operating frequency can be rapidly detected. Knowing the operating frequency
of the AC source and converting to the time domain, the TPS37A SENSE2 delay can be programmed, by the
capacitor on CTS2 pin, to equal or be greater than one-half of the operating period (the frequency of the half
wave rectification signal) or the half cycle shown in Figure 10-5. When the half wave voltage amplitude falls
below the SENSE2 threshold voltage, the SENSE2 time delay counter begins to increment. If the next half wave
voltage amplitude exceeds the SENSE2 threshold voltage, the SENSE2 time delay counter will reset and the
TPS37A RESET2 pin will indicate no fault was detected. Conversely, if the voltage amplitude of the half wave
does not reach the SENSE2 threshold voltage within the programmed time delay of tCTS, a fault will occur.
Also, a fault can occur if the operating frequency from the AC source decreases, resulting in lower AC voltage
amplitude at the programmed time delay tCTS
.
Full Cycle
tFC = 1.25 ms
Half Cycle
t
HC = 0.625 ms
Half Wave (SENSE2)
AC Early Fault Flag (RESET2)
tCTS
t
CTS ≤ tHC
Figure 10-5. Design 2 Timing Diagram
The TPS37A, with its ability of having a wide VDD range from 2.7 V to 65 V and under and overvoltage
detection, offers a unique “window operating” AC power rail monitoring solution. Combining SENSE delay
feature with the "resistive-drop" supply circuitry, detecting an undervoltage event on the half cycle of the AC
power rail provides a fast power fault response. Likewise, the TPS37A provides an overvoltage monitoring and
SENSE delay fault detection for the same AC power rail. With under and overvoltage supervision of the AC
power rail, applications needing a specific operating DC range to protect its subsystems is achieve through
TPS37A. Good design practice recommends using a 0.1-µF capacitor on the VDD pin and this capacitance may
need to increase if using an adjustable version with a resistor divider.
Note that this design solution is not isolated and one must take into account when planning to use in high power
systems.
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11 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.4 V (VPOR) to 65 V
(max operation). Good analog design practice recommends placing a minimum 0.1 µF ceramic capacitor as near
as possible to the VDD pin.
11.1 Power Dissipation and Device Operation
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power
dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces
between the die junction and ambient air.
The maximum continuous allowable power dissipation for the device in a given package can be calculated using
Equation 12:
PD-MAX = ((TJ-MAX – TA) / RθJA
)
(12)
The actual power being dissipated in the device can be represented by Equation 13:
PD = VDD × IDD + pRESET
(13)
pRESET is calculated by Equation 14 or Equation 15
pRESET (PUSHPULL) = VDD - VRESET x IRESET
pRESET (OPEN-DRAIN) = VRESET x IRESET
(14)
(15)
Equation 12 and Equation 13 establish the relationship between the maximum power dissipation allowed due to
thermal consideration, the voltage drop across the device, and the continuous current capability of the device.
These two equations should be used to determine the optimum operating conditions for the device in the
application.
In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is
present, the maximum ambient temperature (TA-MAX) may be increased.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum
ambient temperature (TA-MAX) may have to be de-rated. TA-MAX is dependent on the maximum operating junction
temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the
application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA),
as given by Equation 16:
TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX))
(16)
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12 Layout
12.1 Layout Guidelines
•
•
•
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
greater than 0.1 µF ceramic capacitor as near as possible to the VDD pin.
To further improve the noise immunity on the SENSEx pins, placing a 10 nF to 100 nF capacitor between the
SENSEx pins and GND can reduce the sensitivity to transient voltages on the monitored signal.
If a capacitor is used on CTS1, CTS2, CTR1, or CTR2, place these components as close as possible to the
respective pins. If the capacitor adjustable pins are left unconnected, make sure to minimize the amount of
parasitic capacitance on the pins to less than 5 pF.
•
•
For open-drain variants, place the pull-up resistors on RESET1 and RESET2 pins as close to the pins as
possible.
When laying out metal traces, separate high voltage traces from low voltage traces as much as possible. If
high and low voltage traces need to run close by, spacing between traces should be greater than 20 mils
(0.5 mm).
•
Do not have high voltage metal pads or traces closer than 20 mils (0.5 mm) to the low voltage metal pads or
traces.
12.2 Layout Example
The DSK layout example in Figure 12-1 shows how the TPS37 is laid out on a printed circuit board (PCB) with
user-defined delays.
CVDD
VDD
1
2
3
10
9
GND
Monitored Voltage
Monitored Voltage
CSENSE1
TPS37
8
CSENSE2
DSK Package
GND
4
5
7
6
Overvoltage Flag
Undervoltage Flag
RPU1
RPU2
VPULL-UP
VPULL-UP
Vias used to connect pins for application-specific connections
Figure 12-1. TPS37 DSK Package Recommended Layout
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The DYY layout example in Figure 12-2 shows how the TPS37 is laid out on a printed circuit board (PCB) with
user-defined delays.
CVDD
VDD
1
2
3
14
13
12
NC
NC
NC
GND
TPS37
Monitored Voltage
Monitored Voltage
DYY Package
4
5
6
7
11
10
9
CSENSE1
CSENSE2
GND
Overvoltage Flag
Undervoltage Flag
8
GND
RPU1
RPU2
VPULL-UP
VPULL-UP
Vias used to connect pins for application-specific connections
Figure 12-2. TPS37 DYY Package Recommended Layout
12.3 Creepage Distance
Per IEC 60664 Creepage is the shortest distance between two conductive parts or as shown in Figure 12-3 the
distance between high voltage conductive parts and grounded parts, the floating conductive part is ignored and
subtracted from the total distance.
a
b
A
C
B
Figure 12-3. Creepage Distance
Figure 12-3 details:
•
•
•
•
A = Left pins (high voltage)
B = Central pad (not internally connected, can be left floating or connected to GND)
C = Right pins (low voltage)
Creepage distance = a + b
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13 Device and Documentation Support
13.1 Device Nomenclature
Section 5 shows how to decode the function of the device based on its part number
Table 13-1 shows TPS37 possible voltage options per channel. Contact TI sales representatives or on TI's E2E
forum for details and availability of other options; minimum order quantities apply.
Table 13-1. Voltage Options
100 mV STEPS
400 mV STEPS
500 mV STEPS
1 V STEPS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
08
800 mV
(divider
bypass)
70
7.0 V
A0
10.4 V
D0
20.5 V
F0
31.0 V
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
2.7 V
2.8 V
2.9 V
3.0 V
3.1 V
3.2 V
3.3 V
3.4 V
3.5 V
3.6 V
3.7 V
3.8 V
3.9 V
4.0 V
4.1 V
4.2 V
4.3 V
4.4 V
4.5 V
4.6 V
4.7 V
4.8 V
4.9 V
5.0 V
5.1 V
5.2 V
5.3 V
5.4 V
5.5 V
5.6 V
5.7 V
5.8 V
5.9 V
6.0 V
6.1 V
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
00
7.1 V
7.2 V
7.3 V
7.4 V
7.5 V
7.6 V
7.7 V
7.8 V
7.9 V
8.0 V
8.1 V
8.2 V
8.3 V
8.4 V
8.5 V
8.6 V
8.7 V
8.8 V
8.9 V
9.0 V
9.1 V
9.2 V
9.3 V
9.4 V
9.5 V
9.6 V
9.7 V
9.8 V
9.9 V
10.0 V
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
C0
C1
C2
C3
C4
10.8 V
11.2 V
11.6 V
12.0 V
12.4 V
12.8 V
13.2 V
13.6 V
14.0 V
14.4 V
14.8 V
15.2 V
15.6 V
16.0 V
16.4 V
16.8 V
17.2 V
17.6 V
18.0 V
18.4 V
18.8 V
19.2 V
19.6 V
20.0 V
D1
D2
D3
D4
D5
D6
D7
D8
D9
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
21.0 V
21.5 V
22.0 V
22.5 V
23.0 V
23.5 V
24.0 V
24.5 V
25.0 V
25.5 V
26.0 V
26.5 V
27.0 V
27.5 V
28.0 V
28.5 V
29.0 V
29.5 V
30.0 V
F1
F2
F3
F4
F5
32.0 V
33.0 V
34.0 V
35.0 V
36.0 V
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Table 13-1. Voltage Options (continued)
100 mV STEPS
400 mV STEPS
500 mV STEPS
1 V STEPS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
NOMEN-
CLATURE
VOLTAGE
OPTIONS
62
63
64
65
66
67
68
69
6.2 V
6.3 V
6.4 V
6.5 V
6.6 V
6.7 V
6.8 V
6.9 V
13.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS37A010122DSKR
ACTIVE
SON
DSK
10
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2KAL
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS37 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2021
Automotive : TPS37-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS37A010122DSKR
SON
DSK
10
3000
180.0
8.4
2.8
2.8
1.0
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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24-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DSK 10
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TPS37A010122DSKR
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSK 10
2.5 x 2.5 mm, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225304/A
PACKAGE OUTLINE
DSK0010A
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
2.6
2.4
A
B
PIN 1 INDEX AREA
2.6
2.4
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
(0.2) TYP
EXPOSED
THERMAL PAD
1.2 0.1
6
5
1
2X
2
11
2
0.1
10
8X 0.5
0.3
10X
0.45
0.35
0.2
0.1
0.05
10X
PIN 1 ID
(OPTIONAL)
C A B
C
4218903/B 10/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSK0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.6)
(1.2)
10
1
10X (0.25)
SYMM
(2)
11
8X (0.5)
(0.75)
(R0.05) TYP
5
6
(0.35)
(
0.2) VIA
TYP
SYMM
(2.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218903/B 10/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
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EXAMPLE STENCIL DESIGN
DSK0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.6)
SYMM
1
10
METAL
TYP
10X (0.25)
SYMM
11
8X (0.5)
(0.89)
6
(R0.05) TYP
5
(1.13)
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4218903/B 10/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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