TPS3808-Q1 [TI]
汽车类低静态电流可编程延迟监控器;
| 型号： | TPS3808-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类低静态电流可编程延迟监控器 监控 电源管理电路 电源电路 |
| 文件： | 总20页 (文件大小：785K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS3808-Q1
www.ti.com
SBVS085H –JANUARY 2007–REVISED JUNE 2012
LOW-QUIESCENT-CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT
Check for Samples: TPS3808-Q1
1
FEATURES
DESCRIPTION
•
•
Qualified for Automotive Applications
The TPS3808 microprocessor supervisory circuits
monitor system voltages from 0.4 V to 5 V, asserting
an open-drain RESET signal when the SENSE
voltage drops below a preset threshold or when the
manual reset (MR) pin drops to a logic low. The
RESET output remains low for the user-adjustable
delay time after the SENSE voltage and MR return
above their thresholds.
Power-On Reset Generator With Adjustable
Delay Time: 1.25 ms to 10 s
•
•
•
Very Low Quiescent Current: 2.4 μA Typ
High Threshold Accuracy: 0.5% Typ
Fixed Threshold Voltages for Standard Voltage
Rails From 1.2 V to 5 V and Adjustable Voltage
Down to 0.4 V Are Available
The TPS3808 uses a precision reference to achieve
0.5% threshold accuracy for VIT ≤ 3.3 V. The reset
delay time can be set to 20 ms by disconnecting the
CT pin, 300 ms by connecting the CT pin to VDD using
a resistor, or can be user adjusted between 1.25 ms
and 10 s by connecting the CT pin to an external
capacitor. The TPS3808 has a very low typical
quiescent current of 2.4 μA, so it is well suited to
battery-powered applications. It is available in a small
SOT-23 package and is fully specified over a
temperature range of –40°C to 125°C (TJ).
•
•
•
•
Manual Reset (MR) Input
Open-Drain RESET Output
Temperature Range: –40°C to 125°C
Small SOT-23 Package
APPLICATIONS
•
•
•
•
•
DSP or Microcontroller Applications
Notebook/Desktop Computers
PDAs/Hand-Held Products
<br/>
<br/>
<br/>
Portable/Battery-Powered Products
FPGA/ASIC Applications
DBV (SOT-23) PACKAGE
(TOP VIEW)
1.2 V
3.3 V
6
5
4
1
2
3
RESET
GND
MR
VDD
SENSE
CT
VI/O VCORE
SENSE VDD
SENSE VDD
TPS3808G12
TPS3808G33
DSP
RESET
MR
RESET
GPIO
GND
DRV PACKAGE
(TOP VIEW)
CT
CT
GND
GND
VDD
1
2
3
6
5
4
RESET
SENSE
CT
GND
MR
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2012, Texas Instruments Incorporated
TPS3808-Q1
SBVS085H –JANUARY 2007–REVISED JUNE 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
NOMINAL
SUPPLY
VOLTAGE
THRESHOLD
VOLTAGE
(VIT)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TJ
PACKAGE(2)
SON – DRV Reel of 3000
TPS3808G01QDRVRQ1 PSJQ
TPS3808G01QDBVRQ1 BAZ
TPS3808G125QDBVRQ1 QWZ
TPS3808G12QDBVRQ1 CEM
TPS3808G15QDBVRQ1 OFR
TPS3808G18QDBVRQ1 OBZ
TPS3808G30QDBVRQ1 AVP
TPS3808G33QDBVRQ1 AVQ
TPS3808G50QDBVRQ1 CEL
Adjustable
0.405 V
SOT-23 – DBV Reel of 3000
SOT-23 – DBV Reel of 3000
1.25 V
1.2 V
1.5 V
1.8 V
3 V
1.16 V
1.12 V
1.4 V
–40°C to 125°C
1.67 V
2.79 V
3.07 V
4.65 V
3.3 V
5 V
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range (unless otherwise noted)(1)
VDD
VCT
VMR
Input voltage range
CT voltage range
–0.3 V to 7 V
–0.3 V to (VDD + 0.3) V
,
VRESET
,
MR, RESET, SENSE voltage ranges
–0.3 V to 7 V
VSENSE
IRESET
TJ
RESET pin current
Operating junction temperature range(2)
5 mA
–40°C to 150°C
–65°C to 150°C
2 kV
Tstg
Storage temperature range
Human-Body Model (HBM)
TPS3808GXX
500 V
Charged-Device Model (CDM)
ESD
Electrostatic discharge rating
TPS3808G125QDBVRQ1
1000 V
Machine Model (MM),
TPS3808G01QDRVRQ1,TPS3808G125QDBVRQ1
50 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electric Characteristics is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Due to the low dissipated power in this device, it is assumed that TJ = TA.
2
Copyright © 2007–2012, Texas Instruments Incorporated
TPS3808-Q1
www.ti.com
SBVS085H –JANUARY 2007–REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS
1.8 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C) (unless
otherwise noted), typical values at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDD
IDD
Input supply range
1.8
6.5
5
V
VDD = 3.3 V, RESET not asserted, MR, RESET, CT open
VDD = 6.5 V, RESET not asserted, MR, RESET, CT open
1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA
2.4
2.7
Supply current (into VDD pin)
μA
6
0.3
0.4
0.8
+2
VOL
Low-level output voltage
Power-up reset voltage(1)
V
V
1.8 V ≤ VDD ≤ 6.5 V, IOL = 1 mA
VOL (max) = 0.2 V, I RESET = 15 μA
TPS3808G01
–2
–1.5
–2
±1
±0.5
±1
V
IT ≤ 3.3 V
3.3 V < VIT ≤ 5 V
IT ≤ 3.3 V
+1.5
+2
Negative-going input
threshold accuracy
VIT
%
V
–1.25
–1.5
±0.5
±0.5
1.5
1
+1.25
+1.5
3
–40°C < TJ < 85°C
3.3 V < VIT ≤ 5 V
TPS3808G01
VHYS
Hysteresis on VIT pin
–40°C < TJ < 85°C
2
%VIT
1
2.5
RMR
MR internal pullup resistance
VSENSE = VIT
TPS3808G01
VSENSE = 6.5 V
70
90
kΩ
nA
μA
nA
–25
25
ISENSE Input current at SENSE pin
1.7
IOH
CIN
RESET leakage current
V RESET = 6.5 V, RESET not asserted
300
CT pin
VIN = 0 V to VDD
VIN = 0 V to 6.5 V
5
5
Input capacitance, any pin
pF
Other pins
VIL
VIH
MR logic low input
MR logic high input
0
0.3 VDD
VDD
V
V
0.7 VDD
SENSE
VIH = 1.05 VIT, VIL = 0.95 VIT
VIH = 0.7 VDD, VIL = 0.3 VDD
20
0.001
20
tw
Maximum transient duration
μs
MR
CT = Open
CT = VDD
CT = 100 pF
CT = 180 nF
MR to RESET
12
180
0.75
0.7
28
420
1.75
1.7
300
1.25
1.2
ms
td
RESET delay time
Propagation delay
See timing diagram
s
VIH = 0.7 VDD, VIL = 0.3 VDD
VIH = 1.05 VIT, VIL = 0.95 VIT
150
ns
tpHL
High-level to low-level
RESET delay
SENSE to RESET
20
μs
Thermal resistance,
junction to ambient
θJA
290
°C/W
(1) Power-up reset voltage is the lowest supply voltage (VDD) at which RESET becomes active (trise(VDD) ≥ 15 μs/V).
Copyright © 2007–2012, Texas Instruments Incorporated
3
TPS3808-Q1
SBVS085H –JANUARY 2007–REVISED JUNE 2012
www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
Adjustable-Voltage Version
Fixed-Voltage Versions
VDD
VDD
VDD
VDD
90k
90k
RESET
RESET
MR
MR
Reset
Logic
Timer
SENSE
Reset
Logic
Timer
R1
−
−
SENSE
CT
CT
+
+
R2
0.4 V
VREF
0.4 V
VREF
R1 + R2 = 4 MW
GND
GND
PIN ASSIGNMENTS
DBV (SOT-23) PACKAGE
(TOP VIEW)
DRV PACKAGE
(TOP VIEW)
VDD
SENSE
CT
1
2
3
6
5
4
RESET
GND
MR
6
5
4
1
2
3
RESET
GND
MR
VDD
SENSE
CT
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
Reset. This is an open-drain output that is driven to a low impedance state when RESET is asserted (either
the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET remains
low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pullup
resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to attain voltages higher than
RESET
1
VDD
.
GND
MR
2
3
Ground
Manual reset. Driving this pin low asserts RESET. MR is internally tied to VDD by a 90-kΩ pullup resistor.
Reset period programming. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or leaving it open
results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced
capacitor ≥ 100 pF gives a user-programmable delay time.
CT
4
Voltage sense. This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below
the threshold voltage (VIT), RESET is asserted.
SENSE
VDD
5
6
Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor close to this pin.
4
Copyright © 2007–2012, Texas Instruments Incorporated
TPS3808-Q1
www.ti.com
SBVS085H –JANUARY 2007–REVISED JUNE 2012
VDD
0.8V
0.0V
RESET
SENSE
tD = Reset Delay
= Undefined State
tD
tD
tD
VIT + VHYS
VIT
MR
0.7VDD
0.3VDD
Time
Figure 1. MR and SENSE Reset Timing Diagram
TRUTH TABLE
MR
L
SENSE > VIT
RESET
0
1
0
1
L
L
L
H
L
H
H
Copyright © 2007–2012, Texas Instruments Incorporated
5
TPS3808-Q1
SBVS085H –JANUARY 2007–REVISED JUNE 2012
www.ti.com
TYPICAL CHARACTERISTICS
At TJ = 25°C, VDD = 3.3 V, RLRESET = 100 kΩ, and CLRESET = 50 pF (unless otherwise noted)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
RESET TIMEOUT PERIOD
vs
CT
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100
10
_
125 C
_
85 C
−40°C, 25°C, 125°C
1
_
25 C
0.1
0.01
0.001
_
−40 C
0
1
2
3
4
5
6
7
0.0001
0.001
0.01
0.1
1
10
V
DD
(V)
µ
CT ( F)
Figure 2.
Figure 3.
NORMALIZED RESET TIMEOUT PERIOD
vs
MAXIMUM TRANSIENT DURATION AT SENSE
TEMPERATURE
vs
(CT = OPEN, CT = VDD, CT = Any)
SENSE THRESHOLD OVERDRIVE VOLTAGE
100
10
1
10
8
6
4
RESET OCCURS
ABOVE THE CURVE
2
0
−2
−4
−6
−8
−10
0
5
10
15
20
25 30
35
45
40
50
10
30
50
70
90 110 130
−50 −30 −10
Overdrive (%VIT
)
Temperature (°C)
Figure 4.
Figure 5.
6
Copyright © 2007–2012, Texas Instruments Incorporated
TPS3808-Q1
www.ti.com
SBVS085H –JANUARY 2007–REVISED JUNE 2012
TYPICAL CHARACTERISTICS (continued)
At TJ = 25°C, VDD = 3.3 V, RLRESET = 100 kΩ, and CLRESET = 50 pF (unless otherwise noted)
NORMALIZED SENSE THRESHOLD VOLTAGE (VIT)
LOW-LEVEL RESET VOLTAGE
vs
vs
TEMPERATURE
RESET CURRENT
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
VDD = 1.8V
−0.8
−1.0
10
30
50
70
90 110 130
−50 −30 −10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
RESET Current (mA)
Temperature (°C)
Figure 6.
Figure 7.
LOW-LEVEL RESET VOLTAGE
vs
RESET CURRENT
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VDD = 3.3V
VDD = 6.5 V
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
RESET Current (mA)
Figure 8.
Copyright © 2007–2012, Texas Instruments Incorporated
7
TPS3808-Q1
SBVS085H –JANUARY 2007–REVISED JUNE 2012
www.ti.com
DEVICE OPERATION
The TPS3808 microprocessor supervisory product family is designed to assert a RESET signal when either the
SENSE pin voltage drops below VIT or the manual reset (MR) is driven low. The RESET output remains asserted
for a user-adjustable time after both the manual reset (MR) and SENSE voltages return above the respective
thresholds. A broad range of voltage threshold and reset delay time adjustments are available, allowing these
devices to be used in a wide array of applications. Reset threshold voltages can be factory-set from 0.82 V to
3.3 V or from 4.4 V to 5.0 V, while the TPS3808G01 can be set to any voltage above 0.405 V using an external
resistor divider. Two preset delay times are also user-selectable: connecting the CT pin to VDD results in a 300-
ms reset delay, while leaving the CT pin open yields a 20-ms reset delay. In addition, connecting a capacitor
between CT and GND allows the designer to select any reset delay period from 1.25 ms to 10 s.
SENSE Input
The SENSE input provides a terminal at which any system voltage can be monitored. If the voltage on this pin
drops below VIT, RESET is asserted. The comparator has a built-in hysteresis to ensure smooth RESET
assertions and deassertions. It is good analog design practice to put a 1-nF to 10-nF bypass capacitor on the
SENSE input to reduce sensitivity to transients and layout parasitics.
The TPS3808G01 can be used to monitor any voltage rail down to 0.405 V using the circuit shown in Figure 9.
VIN
VOUT
VDD
R1
R2
VIT
′
= (1 +
)0.405
R1
TPS3808G01
SENSE
RESET
GND
R2
1nF
Figure 9. Using the TPS3808G01 to Monitor a User-Defined Threshold Voltage
Manual Reset (MR) Input
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 VDD) on
MR causes RESET to assert. After MR returns to a logic high and SENSE is above its reset threshold, RESET is
deasserted after the user-defined reset delay expires. Note that MR is internally tied to VDD using a 90-kΩ
resistor, so this pin can be left unconnected if MR is not used.
Refer to Figure 10 for how MR can be used to monitor multiple system voltages. Note that if the logic signal
driving MR does not go fully to VDD, there will be some additional current draw into VDD as a result of the internal
pullup resistor on MR. To minimize current draw, a logic-level FET can be used as shown in Figure 11.
1.2V
3.3V
V
V
CORE
SENSE
V
SENSE V
DD
I/O
DD
TPS3808G12
TPS3808G33
DSP
RESET
MR
RESET
GPIO
GND
CT
CT
GND
GND
Figure 10. Using MR to Monitor Multiple System Voltages
8
Copyright © 2007–2012, Texas Instruments Incorporated
TPS3808-Q1
www.ti.com
SBVS085H –JANUARY 2007–REVISED JUNE 2012
3.3V
V
SENSE
DD
Ω
90k
CT
TPS3808xxx
GND
Figure 11. Using an External MOSFET to Minimize IDD When MR Signal Does Not Go to VDD
Selecting the Reset Delay Time
The TPS3808 has three options for setting the RESET delay time as shown in Figure 12. Figure 12a shows the
configuration for a fixed 300-ms typical delay time by tying CT to VDD; a resistor from 40 kΩ to 200 kΩ must be
used. Supply current is not affected by the choice of resistor. Figure 12b shows a fixed 20-ms delay time by
leaving the CT pin open. Figure 12c shows a ground referenced capacitor connected to CT for a user-defined
program time between 1.25 ms and 10 s.
The capacitor CT should be ≥100 pF nominal value in order for the TPS3808 to recognize that the capacitor is
present. The capacitor value for a given delay time can be calculated using the following equation:
*3
ƪ
ƫ
CT (nF) + tD (s)*0.5 10 (s) 175
(1)
The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the
external capacitor to 1.23 V. When a RESET is asserted, the capacitor is discharged. When the RESET
conditions are cleared, the internal current source is enabled and begins to charge the external capacitor. When
the voltage on this capacitor reaches 1.23 V, RESET is deasserted. Note that a low-leakage type capacitor such
as a ceramic should be used and that stray capacitance around this pin may cause errors in the reset delay time.
Immunity to SENSE Pin Voltage Transients
The TPS3808 is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients is
dependent on threshold overdrive, as shown in the Maximum Transient Duration at Sense vs Sense Threshold
Overdrive Voltage graph (Figure 5) in the Typical Characteristics section.
3.3V
3.3V
3.3V
SENSE VDD
SENSE VDD
SENSE VDD
Ω
50k
TPS3808G33
TPS3808G33
TPS3808G33
RESET
CT RESET
CT RESET
CT
CT
−3
Delay (s) = C (nF) + 0.5 x 10 (s)
T
300ms Delay
20ms Delay
175
(b)
(a)
(c)
Figure 12. Configuration Used to Set the RESET Delay Time
Copyright © 2007–2012, Texas Instruments Incorporated
9
TPS3808-Q1
SBVS085H –JANUARY 2007–REVISED JUNE 2012
www.ti.com
REVISION HISTORY
Changes from Revision G (November, 2010) to Revision H
Page
•
Changed ISENSE from µA to nA .............................................................................................................................................. 3
10
Copyright © 2007–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS3808G01QDBVRQ1
TPS3808G01QDRVRQ1
TPS3808G125QDBVRQ1
TPS3808G12QDBVRQ1
TPS3808G18QDBVRQ1
TPS3808G30QDBVRQ1
TPS3808G33QDBVRQ1
TPS3808G50QDBVRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SON
DBV
DRV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
6
6
6
3000
3000
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2012
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-
Q1 :
Catalog: TPS3808G01, TPS3808G12, TPS3808G125, TPS3808G18, TPS3808G30, TPS3808G33, TPS3808G50
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jun-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3808G01QDRVRQ1
SON
DRV
DBV
6
6
3000
3000
180.0
179.0
8.4
8.4
2.3
3.2
2.3
3.2
1.15
1.4
4.0
4.0
8.0
8.0
Q2
Q3
TPS3808G125QDBVRQ1 SOT-23
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jun-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3808G01QDRVRQ1
TPS3808G125QDBVRQ1
SON
DRV
DBV
6
6
3000
3000
210.0
203.0
185.0
203.0
35.0
35.0
SOT-23
Pack Materials-Page 2
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