TPS3840PL43DBVR [TI]

具有手动复位和可编程复位时间延迟功能的毫微功耗高输入电压监控器 | DBV | 5 | -40 to 125;


型号：	TPS3840PL43DBVR
厂家：	TEXAS INSTRUMENTS
描述：	具有手动复位和可编程复位时间延迟功能的毫微功耗高输入电压监控器 \| DBV \| 5 \| -40 to 125 监控
文件：	总44页 (文件大小：1545K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS3840

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

具有 MR 和可编程延迟的 TPS3840 毫微功耗高输入电压监控器

1 特性

3 说明

•

宽工作电压范围：1.5V 至 10V

宽输入电压范围允许在不使用外部组件的情况下监控

9V 电压轨或电池，在使用外部电阻器的情况下监控

24V 电压轨。毫微级 Iq 可以在低功耗应用中延长电池

寿命，并在使用外部电阻器时最大限度降低电流消

耗。快速启动延迟允许在系统的其余部分上电之前检测

电压故障，因此可以在危险的启动故障状况下实现最高

的安全性。低上电复位电压 (V_POR) 可防止错误复位、

过早启用或开启下一个器件，并能够在上电和断电期间

正确控制晶体管。

毫微电源电流：300nA（典型值）、700nA（最大

值）

•

固定阈值电压 (V_IT-)

–

阈值范围为 1.6V 至 4.9V（阶跃为 0.1V）

高精度：1%（典型值）、1.5%（最大值）

内置的迟滞 (V_IT+

)

–

1.6V < V_IT-≤ 3.0V = 100mV（典型值）

3.1V ≤ V_IT-< 4.9V = 200mV（典型值）

•

快速启动延迟 (t_STRT)：220µs（典型值）、350µs

（最大值）

当 V_DD上的电压降至负电压阈值 (V_IT-) 以下或手动复位

(MR) 被拉至低逻辑 (V_{MR_L}) 时，会将复位输出信号置

位。当 V_DD升至 V_IT-加迟滞 (V_IT+) 以上以及手动复位

悬空或高于 V_{MR_H}且复位延时时间 (t_D) 已过期时，会

将复位信号清除。可以通过在 CT 引脚和地之间连接一

个电容器对复位延时时间进行编程。对于快速复位，可

以将 CT 引脚悬空。

可编程复位延时时间 (t_D)：

–

50µs（无电容器）至 6.2s (10µF)

•

低电平有效手动复位 (MR)

三种输出拓扑：

–

TPS3840DL：漏极开路，低电平有效

(RESET)，需要上拉电阻器

其他特性：用于 MR 和 V_DD的内置毛刺抑制保护以及

内置迟滞、低漏极开路输出漏电流 (I_LKG(OD))。

–

TPS3840PL：推挽，低电平有效 (RESET)

TPS3840PH：推挽，高电平有效 (RESET)

•

宽温度范围：-40°C 至 +125°C

封装：SOT23-5 (DBV)

器件信息⁽¹⁾

器件型号

TPS3840

封装

封装尺寸（标称值）

SOT-23 (5) (DBV)

2.90mm × 1.60mm

2 应用

(1) 有关封装详细信息，请参阅数据表末尾的机械制图附录。

•

电网基础设施：断路器、智能仪表、其他监控和保

护设备

•

工厂自动化：现场发送器、PLC。

楼宇自动化：防火安全、烟雾探测器和 HVAC

电子销售点

便携式电池供电型系统

典型应用电路

TPS3840 典型电源电流

0.5

DL49

PL49

PH49

1 µF

0.4

Vin

Vout

DC/DC

VDD

0.3

0.2

0.1

RESET

TPS3840DL49

GND

5 6

VDD (V)

IDDv

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSB03

TPS3840

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

www.ti.com.cn

8.3 Feature Description................................................. 16

8.4 Device Functional Modes........................................ 19

Application and Implementation ........................ 20

9.1 Application Information............................................ 20

9.2 Typical Application ................................................. 20

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements................................................ 7

7.7 Typical Characteristics.............................................. 9

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Functional Block Diagram ....................................... 16

10 Power Supply Recommendations ..................... 28

11 Layout................................................................... 28

11.1 Layout Guidelines ................................................. 28

11.2 Layout Example .................................................... 28

12 器件和文档支持 ..................................................... 29

12.1 器件命名规则......................................................... 29

12.2 社区资源................................................................ 30

12.3 商标....................................................................... 30

12.4 静电放电警告......................................................... 30

12.5 Glossary................................................................ 30

13 机械、封装和可订购信息....................................... 30

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (July 2019) to Revision C

Page

•

Changed Device Comparison Table ...................................................................................................................................... 3

Changes from Revision A (May 2019) to Revision B

Page

•

Updated Device Comparison Table ....................................................................................................................................... 3

Updated Functional Block Diagram ..................................................................................................................................... 16

已更改 equation 5 and 6....................................................................................................................................................... 17

Updated Application Design #2 ............................................................................................................................................ 22

Changes from Original (December 2018) to Revision A

Page

•

已更改将数据表从“预告信息”更改为“生产数据”...................................................................................................................... 1

TPS3840

www.ti.com.cn

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

5 Device Comparison Table

Device Comparison Table shows the available (Active) device variants and variants releasing soon (Preview).

Other voltages from 表 3 at the end of datasheet can be sample upon request, please contact TI sales

representative for details.

PART NUMBER

TPS3840DL18

OUTPUT TOPOLOGY

Open-Drain, Active-Low

Push-Pull, Active-Low

Open-Drain, Active-Low

Push-Pull, Active-Low

Open-Drain, Active-Low

Push-Pull, Active-Low

Open-Drain, Active-Low

Push-Pull, Active-Low

Open-Drain, Active-Low

Push-Pull, Active-Low

Push-Pull, Active-High

Push-Pull, Active-Low

Open-Drain, Active-Low

Push-Pull, Active-Low

THRESHOLD (V_it-) (V)

HYSTERESIS (mV)

Status

Active

1.8

2.0

2.2

2.5

2.7

2.8

2.9

3.0

4.3

4.5

100

200

TPS3840DL20

TPS3840PL20

TPS3840DL22

TPS3840PL25

TPS3840DL27

TPS3840PL27

TPS3840DL28

TPS3840PL28

TPS3840DL29

TPS3840DL30

TPS3840PL30

TPS3840PH30

TPS3840PL43

TPS3840DL45

TPS3840PL45

TPS3840

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

www.ti.com.cn

6 Pin Configuration and Functions

DBV Package

5-Pin SOT-23

TPS3840PL, TPS3840DL Top View

DBV Package

5-Pin SOT-23

TPS3840PH Top View

RESET

VDD

RESET

VDD

/ NC

GND

MR / NC

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

TPS3840PL,

TPS3840DL

TPS3840PH

RESET

N/A

Active-High Output Reset Signal: This pin is driven high when either the MR

pin is driven to a logic low or VDD voltage falls below the negative voltage

threshold (V_IT-). RESET remains high (asserted) for the delay time period (t_D)

after both MR is floating or above V_{MR_L}and VDD voltage rise above V_IT+.

RESET

N/A

Active-Low Output Reset Signal: This pin is driven logic when either the MR

pin is driven to a logic low or VDD voltage falls below the negative voltage

threshold (V_IT-). RESET remains low (asserted) for the delay time period (t_D)

after both MR is floating or above V_{MR_L}and VDD voltage rise above V_IT+.

VDD

Input Supply Voltage. TPS3840 monitors VDD voltage

GND

Ground

MR / NC

Manual Reset. Pull this pin to a logic low (V_{MR_L}) to assert a reset signal in the

output pin. After the MR pin is left floating or pull to V_{MR_H}the output goes to the

nominal state after the reset delay time(t_D) expires. MR can be left floating

when not in use. NC stands for "No Connection" or floating.

Capacitor Time Delay Pin. The CT pin offers a user-programmable delay time.

Connect an external capacitor on this pin to adjust time delay. When not in use

leave pin floating for the smallest fixed time delay.

TPS3840

www.ti.com.cn

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted⁽¹⁾

MIN

–0.3

MAX

UNIT

VDD

RESET (TPS3840PL)

V_DD+ 0.3

RESET (TPS3840PH)

Voltage

RESET (TPS3840DL)

MR⁽²⁾

5.5

Current

RESET pin and RESET pin

Operating junction temperature, T_J

Storage, T_stg

±70

°C

–40

–65

150

Temperature⁽³⁾

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If the logic signal driving MR is less than V_DD, then additional current flows into V_DDand out of MR. V_MRshould not be higher than V_DD.

(3) As a result of the low dissipated power in this device, it is assumed that T_J= T_A.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-

001⁽¹⁾

± 2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101⁽²⁾

± 750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.5

NOM

MAX

UNIT

V_DD

Input supply voltage

V_RESET, V_RESET

I_RESET, I_RESET

T_J

RESET pin and RESET pin voltage

RESET pin and RESET pin current

Junction temperature (free air temperature)

Manual reset pin voltage

±5

°C

–40

125

V_DD

(1)

V_MR

(1) If the logic signal driving MR is less than V_DD, then additional current flows into V_DDand out of MR. V_MRshould not be higher than V_DD.

7.4 Thermal Information

TPS3840

THERMAL METRIC⁽¹⁾

DBV (SOT23-5)

5 PINS

187.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

109.2

92.8

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

35.4

ψ_JB

92.5

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

TPS3840

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

www.ti.com.cn

7.5 Electrical Characteristics

At 1.5 V ≤ V_DD≤ 10 V, CT = MR = Open, RESET pull-up resistor (R_pull-up) = 100 kΩ to VDD, output reset load (C_LOAD) = 10 pF

and over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at T_J= 25°C.

PARAMETER

COMMON PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_DD

Input supply voltage

Negative-going input threshold accuracy⁽¹⁾

1.5

–1.5

175

1.5

V_IT-

-40°C to 125°C

200

100

V_HYS

Hysteresis on V_IT-pin

V_IT-= 3.1 V to 4.9 V

225

125

Hysteresis on V_IT-pin

V_IT-= 1.6 V to 3.0 V

VDD = 1.5 V < V_DD< 10 V

(2)

I_DD

Supply current into VDD pin

VDD > V_IT+

300

700

600

T_A= -40°C to 125°C

V_{MR_L}

V_{MR_H}

R_MR

Manual reset logic low input⁽³⁾

Manual reset logic high input⁽³⁾

Manual reset internal pull-up resistance

CT pin internal resistance

0.7V_DD

350

100

500

kΩ

R_CT

650

TPS3840PL (Push-Pull Active-Low)

V_OL(max)= 200 mV

I_OUT(Sink)= 200 nA

V_POR

Power on Reset Voltage⁽⁴⁾

300

200

1.5 V < V_DD< 5 V

V_DD< V_IT-

Low level output voltage

V_OL

I_OUT(Sink)= 2 mA

1.5 V < V_DD₍₂₎< 5 V

V_DD> V_IT+

I_OUT(Source) = 2 mA

0.8V_DD

High level output voltage

V_OH

5 V < V_DD< 10 V

(2)

V_DD> V_IT+

I_OUT(Source)= 5 mA

TPS3840PH (Push-Pull Active-High)

V_POR

Power on Reset Voltage⁽⁴⁾

V_OH, I_OUT(Source)= 500 nA

950

200

1.5 V < V_DD₍₂₎< 5 V

V_DD> V_IT+

I_OUT(Sink)= 2 mA

Low level output voltage

V_OL

1.5 V < V_DD₍₂₎< 5 V

V_DD> V_IT+

200

I_OUT(Sink)= 5 mA

High level output voltage

1.5 V < V_DD< 5 V, V_DD< V_IT-

I_OUT(Source)= 2 mA

V_OH

0.8V_DD

TPS3840DL(Open-Drain)

Power on Reset Voltage⁽⁴⁾

V_OL(max)= 0.2 V

I_{OUT (Sink)}= 5.6 uA

V_POR

950

200

1.5 V < V_DD< 5 V

V_DD< V_IT-

Low level output voltage

V_OL

I_OUT(Sink)= 2 mA

RESET pin in High Impedance,

V_DD= V_RESET= 5.5 V

V_IT+< V_DD

I_lkg(OD)Open-Drain output leakage current

(1) V_IT-threshold voltage range from 1.6 V to 4.9 V in 100 mV steps, for released versions see Device Voltage Thresholds table.

(2) V_IT+= V_HYS+ V_IT-

(3) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR

(4) V_PORis the minimum V_DDvoltage level for a controlled output state. V_DDslew rate ≤ 100mV/µs

TPS3840

www.ti.com.cn

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

7.6 Timing Requirements

At 1.5 V ≤ V_DD≤ 10 V, CT = MR = Open, RESET pull-up resistor (R_pull-up) = 100 kΩ to VDD, output reset load (C_LOAD) = 10 pF

and over the operating free-air temperature range – 40°C to 125°C, VDD slew rate < 100mV / us, unless otherwise noted.

Typical values are at T_J= 25°C.

PARAMETER

Startup Delay⁽¹⁾

TEST CONDITIONS

CT pin open

MIN

TYP

MAX

UNIT

t_STRT

t_{P_HL}

100

220

350

µs

Propagation detect delay for VDD falling

below V_IT-

V_DD= V_IT+to (V_IT-) - 10%⁽²⁾

CT pin = open

µs

t_D

Reset time delay

CT pin = 10 nF

CT pin = 1 µF

5% V_IT-overdrive⁽³⁾

6.2

619

µs

t_{GI_VIT-}

t_{MR_PW}

t_{MR_RES}

Glitch immunity V_IT-

MR pin pulse duration to initiate reset

Propagation delay from MR low to reset

300

700

V_DD= 4.5 V, MR < V_{MR_L}

V_DD= 4.5 V,

MR = V_{MR_L}to V_{MR_H}

t_{MR_tD}

Delay from release MR to deasert reset

t_D

(1) When VDD starts from less than the specified minimum V_DDand then exceeds V_IT+, reset is release after the startup delay (t_STRT), a

capacitor at CT pin will add t_Ddelay to t_STRTtime

(2) t_{P_HL}measured from threhold trip point (V_IT-) to V_OLfor active low variants and V_OHfor active high variants.

(3) Overdrive % = [(V_DD/ V_IT-) - 1] × 100%

V_IT+

V_IT-

VDD

V_DD(MIN)

V_POR

t_{STRT +}t_D

t_{P_HL}

t_D

t_{P_HL}

t_{STRT +}t_D

V_OH

RESET

V_OL

(1) t_{D (no cap)}is included in t_STRTtime delay. If t_Ddelay is programmed by an external capacitor connected to CT pin then

t_Dprogrammed time will be added to the startup time, VDD slew rate = 100 mV / µs.

(2) Open-Drain timing diagram assumes pull-up resistor is connected to RESET

(3) RESET output is undefined when VDD is < V_POR

图 3. Timing Diagram TPS3840DL (Open-Drain Active-Low)

TPS3840

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

www.ti.com.cn

V_IT+

V_IT-

V_DD(MIN)

VDD

V_POR

t_{P_HL}

t_{STRT +}t_D

t_D

t_{P_HL}

t_{STRT +}t_D

V_OH

RESET

V_OL

(4) t_{D (no cap)}is included in t_STRTtime delay. If t_Ddelay is programmed by an external capacitor connected to CT pin, then

t_Dprogrammed time will be added to the startup time. VDD slew rate = 100 mV / µs.

(5) RESET output is undefined when VDD < V_PORand limited to V_OLfor VDD slew rate = 100 mV / µs

图 4. Timing Diagram TPS3840PL (Push-Pull Active-Low)

V_IT+

V_IT-

V_DD(MIN)

VDD

V_POR

t_{STRT +}t_D

t_{P_HL}

t_D

t_{P_HL}

t_{STRT +}t_D

V_OH

RESET

V_OL

(6) t_{D (no cap)}is included in t_STRTtime delay. If t_Ddelay is programmed by an external capacitor connected to CT pin, then

t_Dprogrammed time will be added to the total startup time. VDD slew rate = 100 mV / µs.

图 5. Timing Diagram TPS3840PH (Push-Pull Active-High)

TPS3840

www.ti.com.cn

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

7.7 Typical Characteristics

Typical characteristics show the typical performance of the TPS3840 device. Test conditions are T_J= 25°C, V_DD= 3.3 V, R_pull-

_up= 100 kΩ, C_Load= 50 pF, unless otherwise noted.

0.6

0.55

0.5

0.6

0.55

0.5

25°C

-40°C

125°C

25°C

-40°C

125°C

0.45

0.4

0.45

0.4

0.35

0.3

0.35

0.3

0.25

0.2

0.25

0.2

0.15

0.1

0.15

0.1

0.05

VDD (V)

IDDv

图 6. Supply Current vs Supply Voltage for TPS3840DL49

图 7. Supply Current vs Supply Voltage for TPS3840PL49

0.6

25°C

0.55

DL16

DL29

DL49

0.5

-40°C

125°C

0.4

0.3

0.2

0.1

0.5

0.45

0.4

0.35

0.3

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

0.25

0.2

0.15

0.1

0.05

-40

-20

40 60

Temperature (°C)

100 120 140

5 6

VDD (V)

VIT_

IDDv

图 8. Supply Current vs Supply Voltage for TPS3840PH49

图 9. Negative-going Input Threshold Accuracy over

Temperature for TPS3840DLXX

0.6

0.5

0.4

0.3

0.2

0.1

PL16

PL28

PL49

PH16

PH30

PH49

0.5

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

VIT_

图 10. Negative-going Input Threshold Accuracy over

图 11. Negative-going Input Threshold Accuracy over

Temperature for TPS3840PLXX

Temperature for TPS3840PHXX

TPS3840

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

www.ti.com.cn

Typical Characteristics (接下页)

Typical characteristics show the typical performance of the TPS3840 device. Test conditions are T_J= 25°C, V_DD= 3.3 V, R_pull-

_up= 100 kΩ, C_Load= 50 pF, unless otherwise noted.

DL16

DL29

DL49

PL16

PL28

PL49

-5

-10

-15

-20

-10

-15

-20

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

Vhys

图 12. Input Threshold V_IT-Hysteresis Accuracy for

图 13. Input Threshold V_IT-Hysteresis Accuracy for

TPS3840DLXX

TPS3840PLXX

PH16

PH30

PH49

25°C

-40°C

125°C

-5

-10

-15

-20

-1

-40

-20

40 60

Temperature (°C)

100 120 140

V_DD(V)

Vhys

VRES

图 14. Input Threshold V_IT-Hysteresis Accuracy for

图 15. Output Voltage vs Input Voltage for TPS3840DL49

TPS3840PHXX

5.5

25°C

-40°C

125°C

25°C

-40°C

125°C

4.5

3.5

2.5

1.5

0.5

-1

V_DD(V)

VRES

图 16. Output Voltage vs Input Voltage for TPS3840PL49

图 17. Output Voltage vs Input Voltage for TPS3840PH49

TPS3840

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ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

Typical Characteristics (接下页)

Typical characteristics show the typical performance of the TPS3840 device. Test conditions are T_J= 25°C, V_DD= 3.3 V, R_pull-

_up= 100 kΩ, C_Load= 50 pF, unless otherwise noted.

0.055

0.05

140

120

100

25°C

-40°C

125°C

25°C

-40°C

125°C

0.045

0.04

0.035

0.03

0.025

0.02

0.015

1.5

2.5

3.5

4.5

0.5

1.5

2.5

I_RESET(mA)

3.5

4.5

VDD (V)

VOLv

VOL_

图 19. Low Level Output Voltage vs V_DDfor TPS3840DL49

图 18. Low Level Output Voltage vs I_RESETfor TPS3840DL49

0.055

140

25°C

-40°C

125°C

25°C

-40°C

125°C

0.05

0.045

0.04

120

100

0.035

0.03

0.025

0.02

0.015

-20

1.5

2.5

3.5

4.5

0.5

1.5

2.5

I_RESET(mA)

3.5

4.5

VDD (V)

VOLv

VOL_

图 21. Low Level Output Voltage vs VDD for TPS3840PL49

图 20. Low Level Output Voltage vs I_RESETfor TPS3840PL49

0.09

0.085

0.08

25°C

-40°C

125°C

0.075

0.07

0.065

0.06

0.055

0.05

0.045

0.04

0.035

0.03

25°C

-40°C

125°C

0.025

0.02

0.015

0.5

1.5

2.5

I_RESET(mA)

3.5

4.5

5.5

6.5

7.5 8

VDD (V)

8.5

9.5 10 10.5

VOL_

VOLv

图 23. Low Level Output Voltage vs VDD for TPS3840PH49

图 22. Low Level Output Voltage vs I_RESETfor TPS3840PH49

TPS3840

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Typical Characteristics (接下页)

Typical characteristics show the typical performance of the TPS3840 device. Test conditions are T_J= 25°C, V_DD= 3.3 V, R_pull-

_up= 100 kΩ, C_Load= 50 pF, unless otherwise noted.

4.5

9.975

9.95

25°C

-40°C

125°C

25°C

-40°C

125°C

9.925

9.9

3.5

9.875

9.85

2.5

9.825

9.8

1.5

9.775

9.75

1.5

2.5

3.5

4.5

0.5

1.5

2.5

I_RESET(mA)

3.5

4.5

VDD (V)

VOHv

VOH_

图 25. High Level Output Voltage over Temperature for

图 24. High Level Output Voltage vs I_RESETfor TPS3840PL49

TPS3840PL49

1.6

25°C

-40°C

125°C

25°C

-40°C

125°C

4.5

1.55

1.5

3.5

1.45

1.4

2.5

1.35

1.3

1.5

1.25

1.5

2.5

3.5

4.5

0.5

1.5

2.5

I_RESET(mA)

3.5

4.5

VDD (V)

VOHv

VOH_

图 27. High Level Output Voltage over Temperature for

图 26. High Level Output Voltage vs I_RESETfor TPS3840PH49

TPS3840PH49

2.75

DL16

DL29

DL49

PL16

PL28

PL49

2.5

2.25

2.5

2.25

1.75

1.5

1.25

1.75

1.5

1.25

0.75

0.5

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

MR_L

图 28. Manual Reset Logic Low Voltage Threshold over

图 29. Manual Reset Logic Low Voltage Threshold over

Temperature for TPS3840DLXX

Temperature for TPS3840PLXX

TPS3840

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Typical Characteristics (接下页)

Typical characteristics show the typical performance of the TPS3840 device. Test conditions are T_J= 25°C, V_DD= 3.3 V, R_pull-

_up= 100 kΩ, C_Load= 50 pF, unless otherwise noted.

2.75

2.5

2.25

2.75

2.5

2.25

DL16

DL29

DL49

PH16

PH230

PH49

1.75

1.5

1.25

1.75

1.5

1.25

0.75

0.5

0.75

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

MR_L

MR_H

图 30. Manual Reset Logic Low Voltage Threshold over

图 31. Manual Reset Logic High Voltage Threshold over

Temperature for TPS3840PHXX

Temperature for TPS3840DLXX

2.75

PL16

PL28

PL49

PH16

PH30

PH49

2.5

2.25

2.5

2.25

1.75

1.5

1.25

1.75

1.5

1.25

0.75

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

MR_H

图 32. Manual Reset Logic High Voltage Threshold over

图 33. Manual Reset Logic High Voltage Threshold over

Temperature for TPS3840PLXX

Temperature for TPS3840PHXX

478

25°C

-40°C

125°C

DL49

PL49

PH49

476

474

472

470

468

466

464

462

460

458

25 30

Overdrive (%)

-40

-20

40 60

Temperature (°C)

100 120 140

Glit

RCTv

图 34. Glitch Immunity on V_IT-vs Overdrive (Data Taken with

图 35. CT Pin Internal Resistance over Temperature

TPS3840PL28)

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Typical Characteristics (接下页)

Typical characteristics show the typical performance of the TPS3840 device. Test conditions are T_J= 25°C, V_DD= 3.3 V, R_pull-

_up= 100 kΩ, C_Load= 50 pF, unless otherwise noted.

215

210

205

200

195

190

185

180

175

170

DL49

PL49

PH49

DL49

PL49

PH49

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

Star

Dela

图 36. Startup Delay over Temperature

图 37. Reset Time Delay with No Capacitor over

Temperature

600

500

400

300

200

100

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

25°C

-40°C

125°C

25°C

-40°C

125°C

0.01 0.02

0.05 0.1 0.2 0.3 0.5

Capacitor (µF)

3 4 567 10

0.01

0.02 0.03 0.050.07 0.1

0.2 0.3

Capacitor Value (µF)

0.5 0.7

Dela

图 38. Reset Time Delay vs Capacitor Value (Data Taken

图 39. Reset Time Delay vs Small Capacitor Values (Data

with TPS3840PL16)

Taken with TPS3840PL16)

17.25

25°C

-40°C

125°C

DL49

PL49

PH49

16.75

16.5

16.25

4.5

3.5

2.5

15.75

15.5

15.25

1.5

0.5

14.75

Capacitor Value (µF)

9 10

-40

-20

40 60

Temperature (°C)

100 120 140

Dela

TPHL

图 40. Reset Time Delay vs Large Capacitor Values (Data

图 41. Propagation Detect Time Delay for VDD Falling Below

Taken with TPS3840PL16)

V_IT-(High-to-Low) over Temperature

TPS3840

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Typical Characteristics (接下页)

Typical characteristics show the typical performance of the TPS3840 device. Test conditions are T_J= 25°C, V_DD= 3.3 V, R_pull-

_up= 100 kΩ, C_Load= 50 pF, unless otherwise noted.

465

460

455

450

445

440

435

430

425

420

415

3.55

3.5

DL49

PL49

PH49

DL49

PL49

PH49

3.45

3.4

3.35

3.3

3.25

3.2

3.15

3.1

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

MR_r

MRde

图 42. Propagation Time Delay from MR Asserted to Reset

图 43. Propagation Time Delay from MR Release to

over Temperature

Deasserted Reset over Temperature

TPS3840

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

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8 Detailed Description

8.1 Overview

The TPS3840 is a family of wide VDD and nano-quiescent current voltage detectors with fixed threshold voltage.

TPS3840 features include programable reset time delay using external capacitor, active-low manual reset, 1%

typical monitor threshold accuracy with hysteresis and glitch immunity.

Fixed negative threshold voltages (V_IT-) can be factory set from 1.6 V to 4.9 V (see the Device Comparison Table

for available options). TPS3840 is available in SOT-23 5 pin industry standard package.

8.2 Functional Block Diagram

VDD

Push-pull variants

R_MR

VDD

MR / NC

RESET

(PPH)

R_CT

RESET

(PPL, DL)

Voltage

Divider

VDD

V_REF

GND

CT / NC

8.3 Feature Description

8.3.1 Input Voltage (VDD)

VDD pin is monitored by the internal comparator to indicate when VDD falls below the fixed threshold voltage.

VDD also functions as the supply for the internal bandgap, internal regulator, state machine, buffers and other

control logic blocks. Good design practice involve placing a 0.1 uF to 1 uF bypass capacitor at VDD input for

noisy applications to ensure enough charge is available for the device to power up correctly.

TPS3840

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Feature Description (接下页)

8.3.1.1 VDD Hysteresis

The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD

pin falls below V_IT-the output reset is asserted. When the voltage at the VDD pin goes above V_IT-plus hysteresis

(V_HYS) the output reset is deasserted after t_Ddelay.

Hystersis Width

RESET

V_IT-

V_IT+

VDD

图 44. Hysteresis Diagram

8.3.1.2 VDD Transient Immunity

The TPS3840 is immune to quick voltage transients or excursion on VDD. Sensitivity to transients depends on

both pulse duration and overdrive. Overdrive is defined by how much VDD deviates from the specified threshold.

Threshold overdrive is calculated as a percent of the threshold in question, as shown in 公式 1.

Overdrive = | (V_DD/ V_IT-– 1) × 100% |

(1)

VDD

V_IT+

V_IT-

Overdrive

Pulse

Duration

图 45. Overdrive vs Pulse Duration

8.3.2 User-Programmable Reset Time Delay

The reset time delay can be set to a minimum value of 50 µs by leaving the CT pin floating, or a maximum value

of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (t_D) can be programmed

by connecting a capacitor no larger than 10 µF between CT pin and GND.

The relationship between external capacitor (C_{CT_EXT}) in µF at CT pin and the time delay (t_D) in seconds is given

by 公式 2.

t_D= -ln (0.29) x R_CTx C_{CT_EXT}+ t_D(no cap)

(2)

(3)

(4)

公式 2 is simplified to 公式 3 by plugging R_CTand t_{D(no cap)}given in Electrical Characteristics section:

t_D= 618937 x C_{CT_EXT}+ 50 µs

公式 4 solves for external capacitor value (C_{CT_EXT}) in units of µF where t_Dis in units of seconds

C_{CT_EXT}= (t_D- 50 µs) ÷ 618937

The reset delay varies according to three variables: the external capacitor variance (C_CT), CT pin internal

resistance (R_CT) provided in the Electrical Characteristics table, and a constant. The minimum and maximum

variance due to the constant is shown in Equation 5 and Equation 6.

t_{D (minimum)}= -ln (0.36) x R_{CT (min)}x C_{CT (min)}+ t_{D (no cap, min)}

t_{D (maximum)}= -ln (0.26) x R_{CT (max)}x C_{CT (max)}+ t_{D (no cap, max)}

(5)

(6)

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Feature Description (接下页)

The recommended maximum delay capacitor for the TPS3840 is limited to 10 µF as this ensures there is enough

time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the

previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before

the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above zero and

the reset delay will be shorter than expected. Larger delay capacitors can be used so long as the capacitor has

enough time to fully discharge during the duration of the voltage fault.

8.3.3 Manual Reset (MR) Input

The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR

with pulse duration longer than t_{MR_RES}will causes reset output to assert. After MR returns to a logic high (V_{MR_H}

)

and VDD is above V_IT+, reset is deasserted after the user programmed reset time delay (t_D) expires.

If MR is not controlled externally, then MR can be left disconnected. If the logic signal controlling MR is less than

VDD, then additional current flows from VDD into MR internally. For minimum current consumption, drive MR to

either VDD or GND. V_MRshould not be higher than VDD voltage.

VDD

V_IT+

V_HYS

V_IT-

V_IT+

V_HYS

V_IT-

RESET

t_{P_HL}

t_D

t_{MR_tD}

t_{MR_RES}

V_{MR_H}

V_{MR_L}

Reset not asserted

t_{MR_PW}

Pulse width less than t_{MR_PW}

图 46. Timing Diagram MR and RESET (TPS3840DL)

8.3.4 Output Logic

8.3.4.1 RESET Output, Active-Low

RESET (Active-Low) applies to TPS3840DL (Open-Drain) and TPS3840PL (Push-Pull) hence the "L" in the

device name. RESET remains high (deasserted) as long as VDD is above the negative threshold (V_IT-) and the

MR pin is floating or above V_{MR_H}. If VDD falls below the negative threshold (V_IT-) or if MR is driven low, then

RESET is asserted.

When MR is again logic high or floating and VDD rise above V_IT+, the delay circuit will hold RESET low for the

specified reset time delay (t_D). When the reset time delay has elapsed, the RESET pin goes back to logic high

voltage (V_OH).

The TPS3840DL (Open-Drain) version, denoted with "D" in the device name, requires a pull-up resistor to hold

RESET pin high. Connect the pull-up resistor to the desired pull-up voltage source and RESET can be pulled up

to any voltage up to 10 V independent of the VDD voltage. To ensure proper voltage levels, give some

consideration when choosing the pull-up resistor values. The pull-up resistor value determines the actual V_OL, the

output capacitive loading, and the output leakage current (I_LKG(OD)).

The Push-Pull variants (TPS3840PL and TPS3840PH), denoted with "P" in the device name, does not require a

pull-up resistor

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Feature Description (接下页)

8.3.4.2 RESET Output, Active-High

RESET (active-high), denoted with no bar above the pin label, applies only to TPS3840PH push-pull active-high

version. RESET remains low (deasserted) as long as VDD is above the threshold (V_IT-) and the manual reset

signal (MR) is logic high or floating. If VDD falls below the negative threshold (V_IT-) or if MR is driven low, then

RESET is asserted driving the RESET pin to high voltage (V_OH).

When MR is again logic high and VDD is above V_IT+the delay circuit will hold RESET high for the specified reset

time delay (t_D). When the reset time delay has elapsed, the RESET pin goes back to low voltage (V_OL

)

8.4 Device Functional Modes

表 1 summarizes the various functional modes of the device. Logic high is represented by "H" and logic low is

represented by "L".

表 1. Truth Table

VDD

VDD < V_POR

V_POR< V_DD< V_IT-

VDD ≥ V_IT-

Ignored

RESET

Undefined

(1)

VDD ≥ V_IT-

Floating

(1) When V_DDfalls below V_DD(MIN), undervoltage-lockout (UVLO) takes effect and output reset is held asserted until V_DDfalls below V_POR

8.4.1 Normal Operation (V_DD> V_DD(min)

)

When VDD is greater than V_DD(min), the reset signal is determined by the voltage on the VDD pin with respect to

the trip point (V_IT-) and the logic state of MR.

•

MR high: the reset signal corresponds to VDD with respect to the threshold voltage.

MR low: in this mode, the reset is asserted regardless of the threshold voltage.

8.4.2 VDD Between VPOR and V_DD(min)

When the voltage on VDD is less than the V_DD(min)voltage, and greater than the power-on-reset voltage (V_POR),

the reset signal is asserted.

8.4.3 Below Power-On-Reset (V_DD< V_POR

)

When the voltage on VDD is lower than V_POR, the device does not have enough bias voltage to internally pull the

asserted output low or high and reset voltage level is undefined.

TPS3840

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The following sections describe in detail how to properly use this device, depending on the requirements of the

final application.

9.2 Typical Application

9.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing

A typical application for the TPS3840 is voltage rail monitoring and power-up sequencing as shown in 图 47. The

TPS3840 can be used to monitor any rail above 1.6 V. In this design application, two TPS3840 devices monitor

two separate voltage rails and sequences the rails upon power-up. The TPS3840PL30 is used to monitor the 3.3-

V main power rail and the TPS3840DL16 is used to monitor the 1.8-V rail provided by the LDO for other system

peripherals. The RESET output of the TPS3840PL30 is connected to the ENABLE input of the LDO. A reset

event is initiated on either voltage supervisor when the VDD voltage is less than V_IT-or when MR is driven low by

an external source.

LDO

VDD

1.8 V

3.3V

1 µF

VI/O

V_CORE

10kΩ

Microcontroller

VDD

RESET

TPS3840PL30

CT GND

TPS3840DL16

GND

0.047µF

图 47. TPS3840 Voltage Rail Monitor and Power-Up Sequencer Design Block Diagram

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Typical Application (接下页)

9.2.1.1 Design Requirements

This design requires voltage supervision on two separate rails: 3.3-V and 1.8-V rails. The voltage rail needs to

sequence upon power up with the 3.3-V rail coming up first followed by the 1.8-V rail at least 25 ms after.

PARAMETER

DESIGN REQUIREMENT

Monitor 3.3-V and 1.8-V rails

DESIGN RESULT

Two TPS3840 devices provide voltage monitoring

with 1% accuracy with device options available in

0.1 V variations

Two Rail Voltage Supervision

Power up the 3.3-V rail first followed by 1.8-V rail

25 ms after

The CT capacitor on TPS38240PL28 is set to

0.047 µF for a reset time delay of 29 ms typical

Voltage Rail Sequencing

Output logic voltage

3.3-V Open-Drain

Maximum device current

consumption

1 µA

Each TPS3840 requires 350 nA typical

9.2.1.2 Detailed Design Procedure

The primary constraint for this application is choosing the correct device to monitor the supply voltage of the

microprocessor. The TPS3840 can monitor any voltage between 1.6 V and 10 V and is available in 0.1 V

increments. Depending on how far away from the nominal voltage rail the user wants the voltage supervisor to

trigger determines the correct voltage supervisor variant to choose. In this example, the first TPS3840 triggers

when the 3.3-V rail falls to 3.0 V. The second TPS3840 triggers a reset when the 1.8-V rail falls to 1.6 V. The

secondary constraint for this application is the reset time delay that must be at least 25 ms to allow the

microprocessor, and all other devices using the 3.3-V rail, enough time to startup correctly before the 1.8-V rail is

enabled via the LDO. Because a minimum time is required, the user must account for capacitor tolerance. For

applications with ambient temperatures ranging from –40°C to +125°C, C_CTcan be calculated using R_CTand

solving for C_CTin 公式 2. Solving 公式 2 for 25 ms gives a minimum capacitor value of 0.04 µF which is rounded

up to a standard value 0.047 µF to account for capacitor tolerance.

A 1-µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor

is only required for the Open-Drain device variants and is calculated to maintain the RESET current within the ±5

mA limit found in the Recommended Operating Conditions: R_Pull-up= V_Pull-up÷ 5 mA. For this design, a standard

10-kΩ pull-up resistor is selected to minimize current draw when RESET is asserted. Keep in mind the lower the

pull-up resistor, the higher V_OL. The MR pin can be connected to an external signal if desired or left floating if not

used due to the internal pull-up resistor to VDD.

9.2.1.3 Application Curves

VDD

30ms delay from VDD (3.3V) to LDO Enable set by 0.047µF on CT of TPS3840PL30

RESET

(LDO Enable)

V_OUT(LDO)

Negligible delay from LDO Enable to 1.8V V_OUT

图 48. Startup Sequence Highlighting the Delay Between 3.3V and 1.8V Rails

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www.ti.com.cn

9.2.2 Design 2: Battery Voltage and Temperature Monitor

A typical application for the TPS3840 is battery voltage and temperature monitoring. The TPS3840 is offered in

active-low or active-high output topologies and can operate above or below the voltage threshold meaning the

device can be used as an undervoltage monitor as shown in 图 49 or overvoltage monitor as shown in 图 50.

The TPS3840 can be used to monitor any rail above 1.6 V. In this design application, one TPS3840DL30

monitors the 3.3-V battery voltage rail and triggers an active-low reset fault condition if the battery voltage falls

below the 3-V threshold. For overvoltage monitoring, another TPS3840DL30 monitors a 2.8-V battery and

triggers a logic high at the 3-V threshold plus 100 mV hysteresis so at 3.1 V. Both applications monitor the

battery temperature using TMP303, a push-pull, active-high temperature switch. A temperature fault is triggered if

the battery temperature falls outside of a defined window temperature range set by the TMP303 variant chosen.

3.3V

1MΩ

V_CORE

Microcontroller

VDD

TMP303

RESET

FAULT

SOH

TPS3840DL30

HYST_SET0

HYST_SET1

OUT

GND

10µF

图 49. Low Battery Voltage and Window Temperature Monitoring Solution

2.8V

100kꢀ

Battery Charger

VDD

V_S

OFF

TMP303

RESET

SOH

TPS3840DL30

HYST_SET0

HYST_SET1

OUT

GND

10µF

图 50. Overvoltage and Window Temperature Monitoring Solution

9.2.2.1 Design Requirements

This design requires voltage and temperature supervision on a battery voltage rail and the requirements may

differ depending on if undervoltage or overvoltage monitoring is required. For this design, both requirements are

considered to show the flexibility of the TPS3840 device. The first application example shown in 图 49 uses

TPS3840DL30, an open-drain active-low voltage supervisor to monitoring undervoltage and TMP303, a push-pull

active-high window temperature switch to monitor under and over temperature. For the undervoltage application,

the TPS3840DL30 is operating in the inactive logic high region so an overvoltage fault occurs when the battery

voltage falls below V_IT-= 3.0 V or when the battery temperature is outside the range from 0°C to 60°C. The

second application example uses TPS3840DL30 operating in the active-low region to monitor overvoltage and

TMP303 to monitor under and over temperature. For the overvoltage requirement, the fault occurs when the

battery voltage rises above 3.1 V or when the battery temperature is outside the range from 0°C to 60°C.

TPS3840

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ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

Monitor 3.3-V battery for undervoltage condition

TPS3840 provides voltage monitoring with 1%

accuracy with device options available in 0.1 V

variations. TPS3840DL30 triggers a reset when

VDD falls below 3 V. TPS3840PH30 triggers a

reset when VDD rises above 3 V plus hysteresis

setting the overvoltage threshold to 3.1 V.

Battery Voltage Supervision

Monitor 2.8-V battery for overvoltage condition

TMP303A monitors temperature within 0°C to 60°C

with 1°C resolution. Note this is a push-pull, active-

high output device.

Monitor battery temperature between 0°C and 60°C

with 1°C resolution for undervoltage design

Battery Temperature Supervision

Output Topology

Undervoltage: Active-Low, Open-Drain

Overvoltage: Active-High, Push-Pull

TPS3840 is offered in Active-Low Open-drain,

Active-Low Push-Pull, and Active-High Push-Pull

topologies

Maximum device current

consumption

TPS3840 requires 350 nA (typical) and TMP303

requires 3.5 µA (typical)

10 µA

Delay when returning from fault

condition

Delay of at least 6 seconds when returning from

the fault to prevent operation in fault conditions

C_CT= 10 µF sets 6.18 second delay

9.2.2.2 Detailed Design Procedure

The primary constraint for this application is choosing the correct device to monitor the battery supply voltage.

The TPS3840 can monitor any voltage between 1.6 V and 10 V and is available in 0.1 V increments. Depending

on how far away from the nominal voltage rail the user wants the voltage supervisor to trigger determines the

correct voltage supervisor variant to choose. In this design example, the TPS3840DL30 is chosen for both the

undervoltage and overvoltage monitoring. For undervoltage monitoring, the undervoltage fault occurs when the

3.3-V rail falls to 3 V and for the overvoltage monitoring, the overvoltage fault occurs when the 2.8-V rail rises

above the 3-V threshold (V_IT-) plus 100mV hysteresis (V_HYS). It's important to note that in the undervoltage

application, the TPS3840 RESET output is logic high during normal conditions whereas in the overvoltage

application, the TPS3840 RESET output is logic low during normal conditions which is the reason a single device

can be used for either type of monitoring depending on the logic required at the output. The opposite RESET

output logic is offered in the push-pull, active-high device TPS3840PH noted with the RESET output. The

secondary constraint for this application is the battery temperature monitoring accomplished by the TMP303A.

Typical Lithium Ion battery discharge temperature range is 0°C to 60°C which is accomplished by the 'A' variante

of TMP303A. The TMP303A triggers a fault to the MR pin of the TPS3840 or directly to the battery charger

whenever the temperature is outside of the temperature range. The TMP303A offers 1°C resolution to meet the

high resolution requirement. Because the undervoltage monitor design uses TMP303A, a push-pull active-high

output device, an additional inverter is required before the MR pin because during normal operation, the TMP303

output is low but the MR pin must be logic high during normal operation. If using two TPS3840 devices for both

undervoltage and overvoltage monitoring on the same battery, only one single temperature monitoring device is

required. The last constraint is the RESET/RESET time delay set by C_CT. For applications with ambient

temperatures ranging from –40°C to +125°C, C_CTcan be calculated using R_CTand solving for C_CTin 公式 2. By

choosing a standard 10% capacitor value of 10 µF ensures the RESET/RESET time delay will be at least 6

seconds. Note: active-low devices use the output label RESET and active-high devices use the output label

RESET.

A 0.1-µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up

resistor is only required for the Open-Drain device variants and is calculated to maintain the RESET current

within the ±5 mA limit found in the Recommended Operating Conditions: R_Pull-up= V_Pull-up÷ 5 mA. For this design,

a 1-MΩ pull-up resistor is selected to minimize current draw when RESET is asserted and to prevent the battery

from unnecessary discharge. Keep in mind the lowering the pull-up resistor, increases V_OLand I_OUT. The MR pin

is used for a second fault condition provided by the temperature switch.

TPS3840

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

www.ti.com.cn

9.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input

A typical application for the TPS3840 is a fast startup undervoltage supervisor that operates with an input power

supply higher than the recommended maximum of 10 V through the use of a resistor divider at the input as

shown in 图 51. The TPS3840 can be used to monitor any rail above 1.6 V and only requires maximum 350 µs

upon startup before the device can begin monitoring a voltage. In this design application, a TPS3840 monitors a

12-V rail and triggers a reset fault condition if the voltage rail voltage drops below 10 V using a TPS3840 device

with V_IT-of 4.9 V. This design also accounts for a wide input range in the case the 12-V rail rises higher, the

resistor divider is set so that the voltage at the VDD pin never exceeds 10 V. The resistor values must not be so

large that the external resistor divider affects the accuracy or operation of the device. TPS3840 is available in

both active-low and active-high topologies providing the flexibility to monitor undervoltage or overvoltage with

either output logic. This design uses the active-low, open-drain TPS3840DL49 variant so that when the

undervoltage condition occurs, that is when the voltage at VDD pin falls below the voltage threshold set by the

external resistor divider, the output transitions to logic-low and can be used to flag an undervoltage condition or

used to connect to the ENABLE of the next device to shut it off as a logic low on an ENABLE pin typically

disables the device. In this design, the output of the TPS3840 simply connects to a MCU to flag an undervoltage

condition.

3.3V

12V

10.5kΩ

125kΩ

V_CORE

10kΩ

VDD

Microcontroller

RESET

TPS3840DL49

GND

0.33µF

图 51. Fast Start Undervoltage Supervisor with Level-shifted Input

9.2.3.1 Design Requirements

This design requires voltage supervision on a 12-V power supply voltage rail with possibility of the 12-V rail rising

up as high as 18 V. The undervoltage fault occurs when the power supply voltage drops below 10 V.

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

TPS3840 provides voltage monitoring with 1%

accuracy with device options available in 0.1 V

variations. The TPS3840 monitors voltages above

1.6 V.

Monitor 12-V power supply for undervoltage

condition, trigger a undervoltage fault at 10 V.

Power Rail Voltage Supervision

The TPS3840 limits VDD to 10 V but can monitor

voltages higher than the maximum VDD voltage

with the use of an external resistor divider.

Maximum Input Power

Output logic voltage

Operate with power supply input up to 18 V.

3.3-V Open-Drain

TPS3840 requires 350 nA (typical) and the external

resistor divider will also consume current. There is

a tradeoff between current consumption and

voltage monitor accuracy but generally set the

resistor divider to consume 100 times current into

VDD.

Maximum device current

consumption

35 µA when power supply is at 18 V maximum

The TPS3840 has 1% typical voltage monitor

accuracy. By decreasing the ratio of resistor

values, the resistor divider will consume more

current but the accuracy will increase. The resistor

tolerance also needs to be accounted for.

Typical voltage monitor accuracy of 2.5%. This

allows the voltage threshold to range between

11.75 V and 10.25 V.

Voltage Monitor Accuracy

Delay when returning from fault

condition

RESET delay of at least 200 ms when returning

from a undervoltage fault.

C_CT= 0.33 µF sets 204 ms delay

TPS3840

www.ti.com.cn

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

9.2.3.2 Detailed Design Procedure

The primary constraint for this application is monitoring a 12-V rail while preventing the VDD pin on TPS3840

from exceeding the recommended maximum of 10 V. This is accomplished by sizing the resistor divider so that

when the 12-V rail drops to 10 V, the VDD pin for TPS3840 will be at 4.9 V which is the V_IT-threshold for

triggering a undervoltage condition for TPS3840DL49 as shown in 公式 7.

V_{rail_trigger}= V_IT-x (R_bottom÷ (R_top+ R_bottom))

(7)

where V_{rail_trigger}is the trigger voltage of the rail being monitored, V_IT-is the falling threshold on the VDD pin of

TPS3840, and R_topand R_bottomare the top and bottom resistors of the external resistor divider. V_IT-is fixed per

device variant and is 4.9 V for TPS3840DL49. Substituting in the values from 图 51, the undervoltage trigger

threshold for the rail is set to 10.045 V.

Since the undervoltage trigger of 10 V on the rail corresponds to 4.9 V undervoltage threshold trigger of the

TPS3840 device, there is plenty of room for the rail to rise up while maintaining less than 10 V on the VDD pin of

the TPS3840. 公式 8 shows the maximum rail voltage that still meets the 10 V maximum at the VDD pin for

TPS3840.

V_{rail_max}= 10 x (10,000 ÷ (10,500 + 10,000)) = 20.5 V

(8)

This means the monitored voltage rail can go as high as 20.5 V and still not violate the recommended maximum

for the VDD pin on TPS3840. This is useful when monitoring a voltage rail that has a wide range that may go

much higher than the nominal rail voltage such as in this case with the specification that the 12-V rail can go as

high as 18 V. Notice that the resistor values chosen are less than 100kΩ to preserve the accuracy set by the

internal resistor divider. Good design practice recommends using a 0.1-µF capacitor on the VDD pin and this

capacitance may need to increase when using an external resistor divider.

TPS3840

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

www.ti.com.cn

9.2.4 Design 4: Voltage Monitor with Back-up Battery Switchover

A typical application for the TPS3840 is to monitor a voltage rail and switch the power to a back-up battery if the

main supply is in undervoltage condition. Because systems that utilize a back-up battery tend to require low

quiescent current, TPS3840 serves as the perfect solution as this device only requires 350 nA typically. The

TPS3840 monitors the main power rail via the VDD pin and when the main power rail falls, the RESET output

asserts causing a switch to close on the back-up battery rail. The diodes provide an ORing logic function to

prevent reverse leakage and to allow either rail to connect to the output depending on the status of the main

voltage rail.

System

Output

3.3V

Vbat

VDD

RESET

TPS3840PL30

GND

图 52. Voltage Monitor with Back-up Battery Switchover Solution

9.2.4.1 Design Requirements

This design requires voltage supervision on a 5-V main supply voltage rail and when the main rail fails, switch to

a back-up battery supply to prevent complete power loss in the system. The System Output must remain above

1.8 V even when the main supply completely fails. The design requires less than 500 nA of total current

consumption and must prevent battery leakage when the battery is not being used. When the system is using the

back-up battery and the main supply voltage rail comes back up, the system must switch back to the main power

supply in less than 100 µs to save battery power.

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

TPS3840 provides voltage monitoring with 1%

accuracy with device options available in 0.1 V

variations. This design uses TPS3840PL30 to set

the undervoltage trigger at 3 V.

Monitor 5-V main supply for undervoltage

Main Supply Voltage Supervision condition. When main supply drops below 3 V,

switch to back-up battery.

When undervoltage occurs on the main supply rail,

the PMOS switch closes allowing the back-up

battery to connect to the system output. The diodes

prevent reverse leakage and allow either power

supply to connect to the system output.

When undervoltage occurs on the main supply

Batck-up Battery Switchover

voltage rail, switch to the back-up batter.

No more than 50 µs to switch to the back-up

Main Power Supply to Back-up

TPS3840 provides a propagation delay for VDD

falling below the undervoltage threshold (t_{P_HL}) of

50 µs maximum to meet the requirement.

battery when the main power supply falls to

Battery Switch Response Time

undervoltage condition.

Back-up Battery to Main Power

Supply Switch Back Response

Time

Less than 100 µs when switching from back-up

battery back to main power supply when

undervoltage condition is removed.

By leaving MR disconnected, the RESET delay is

set to a maximum of 50 µs to meet the

requirement.

Device Current Consumption

500 nA

TPS3840 requires 350 nA (typical)

When the main 5-V rail is connected, the System

Output will be the rail voltage minus a diode

voltage drop so at least 3 V - 0.7 V ~ 2.3 V. When

the voltage rail drops below 3 V, the back-up

battery switches into the system and the System

Output becomes the battery voltage minus a diode

voltage drop so 3.3 V - 0.7 V ~ 2.6 V. The

threshold at which the battery switches into the

system directly depends on the TPS3840 variant

chosen.

System Output must remain above 1.8 V in all

cases

System Output Voltage

TPS3840

www.ti.com.cn

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

9.2.4.2 Detailed Design Procedure

The primary constraints for this application are choosing the correct device variant for the monitored voltage and

deciding the preferred solution to switch the back-up battery in and out of the system. For this design, the

TPS3840PL30 provides an active-low, push-pull output topology that turns on the PFET when the 5-V rail

monitored by VDD drops to 3.0 V. The diodes logically OR the power supply with the back-up battery and

prevents reverse current leakage. Using this solution, the System Output remains above 1.8 V in all

circumstances unless both the 5-V rail and back-up battery fail. The System Output voltage will follow the 5-V rail

minus a diode drop until the 5-V rail drops to 3 V then the back-up battery switches into the system providing 3.3

V minus a diode drop to the System Output. When the 5-V rail comes back above 3.1 V accounting for

hysteresis, the PFET turns off to disconnect the back-up battery from the system. Since this design disconnects

the battery when not being used, this solution maximizes battery life.

9.2.5 Application Curve: TPS3840EVM

These application curves are taken with the TPS3840EVM. Please see the TPS3840EVM User Guide for more

information.

VDD

Reset Delay (t_D) = 5.8 ms

Reset Delay (t_D) = 22 µs

RESET

图 53. TPS3840EVM RESET Time Delay (t_D) with No

图 54. TPS3840EVM RESET Time Delay (t_D) with

Capacitor

0.01-µF Capacitor

VDD

Reset Delay (t_D)= 654 ms

RESET

图 55. TPS3840EVM RESET Time Delay (t_D) with 1-µF Capacitor

TPS3840

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

www.ti.com.cn

10 Power Supply Recommendations

These devices are designed to operate from an input supply with a voltage range between 1.5 V and 10 V. TI

recommends an input supply capacitor between the VDD pin and GND pin. This device has a 12-V absolute

maximum rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage

transient that can exceed 12 V, additional precautions must be taken.

11 Layout

11.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends

placing a minimum 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected

to the CT pin, then minimize parasitic capacitance on this pin so the rest time delay is not adversely affected.

•

Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a

>0.1-µF ceramic capacitor as near as possible to the VDD pin.

If a C_CTcapacitor is used, place these components as close as possible to the CT pin. If the CT pin is left

unconnected, make sure to minimize the amount of parasitic capacitance on the pin to <5 pF.

Place the pull-up resistors on RESET pin as close to the pin as possible.

11.2 Layout Example

The layout example in shows how the TPS3840 is laid out on a printed circuit board (PCB) with a user-defined

delay.

Pull-up resistor required for Open-Drain

(TPS3840DLXX) only

RESET

C_CT

R_pull-up

VDD

GND

C_IN

VDD

GND

Vias used to connect pins for application-specific connections

图 56. TPS3840 Recommended Layout

TPS3840

www.ti.com.cn

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

12 器件和文档支持

12.1 器件命名规则

表 2 显示了如何根据器件型号来解译器件的功能

表 2. 器件命名约定

说明

命名规则

值

器件型号

TPS3840

型号代码（输出拓扑）

漏极开路，低电平有效

推挽，高电平有效

推挽，低电平有效

示例：16 表示 1.6V 阈值

SOT23-5

检测电压选项

封装

##（两个字符）

DBV

卷带

大卷带

表 3 显示了 TPS3840 的可能型号。有关所显示的其他选项的详细信息和供货情况，请联系德州仪器 (TI)；最低订

购量适用。

表 3. 器件阈值

产品

电压阈值 (V_IT-

典型值 (V)

1.6

)

迟滞 (V_HYST

典型值 (V)

0.100

0.200

)

漏极开路，低电平有效

TPS3840DL16

推挽，低电平有效

推挽，高电平有效

TPS3840PH16

TPS3840PL16

TPS3840DL17

TPS3840DL18

TPS3840DL19

TPS3840DL20

TPS3840DL21

TPS3840DL22

TPS3840DL23

TPS3840DL24

TPS3840DL25

TPS3840DL26

TPS3840DL27

TPS3840DL28

TPS3840DL29

TPS3840DL30

TPS3840DL31

TPS3840DL32

TPS3840DL33

TPS3840DL34

TPS3840DL35

TPS3840DL36

TPS3840DL37

TPS3840DL38

TPS3840DL39

TPS3840DL40

TPS3840DL41

TPS3840DL42

TPS3840DL43

TPS3840DL44

TPS3840PL17

TPS3840PL18

TPS3840PL19

TPS3840PL20

TPS3840PL21

TPS3840PL22

TPS3840PL23

TPS3840PL24

TPS3840PL25

TPS3840PL26

TPS3840PL27

TPS3840PL28

TPS3840PL29

TPS3840PL30

TPS3840PL31

TPS3840PL32

TPS3840PL33

TPS3840PL34

TPS3840PL35

TPS3840PL36

TPS3840PL37

TPS3840PL38

TPS3840PL39

TPS3840PL40

TPS3840PL41

TPS3840PL42

TPS3840PL43

TPS3840PL44

TPS3840PH17

TPS3840PH18

TPS3840PH19

TPS3840PH20

TPS3840PH21

TPS3840PH22

TPS3840PH23

TPS3840PH24

TPS3840PH25

TPS3840PH26

TPS3840PH27

TPS3840PH28

TPS3840PH29

TPS3840PH30

TPS3840PH31

TPS3840PH32

TPS3840PH33

TPS3840PH34

TPS3840PH35

TPS3840PH36

TPS3840PH37

TPS3840PH38

TPS3840PH39

TPS3840PH40

TPS3840PH41

TPS3840PH42

TPS3840PH43

TPS3840PH44

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.0

4.1

4.2

4.3

4.4

TPS3840

ZHCSJ38C –DECEMBER 2018–REVISED AUGUST 2019

www.ti.com.cn

表 3. 器件阈值 (接下页)

产品

推挽，低电平有效

电压阈值 (V_IT-

)

迟滞 (V_HYST

典型值 (V)

0.200

)

漏极开路，低电平有效

TPS3840DL45

推挽，高电平有效

典型值 (V)

4.5

TPS3840PL45

TPS3840PL46

TPS3840PL47

TPS3840PL48

TPS3840PL49

TPS3840PH45

TPS3840PH46

TPS3840PH47

TPS3840PH48

TPS3840PH49

TPS3840DL46

TPS3840DL47

TPS3840DL48

TPS3840DL49

4.6

0.200

4.7

0.200

4.8

0.200

4.9

0.200

12.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

16-Apr-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS3840DL16DBVR

TPS3840DL17DBVR

TPS3840DL18DBVR

TPS3840DL19DBVR

TPS3840DL20DBVR

TPS3840DL22DBVR

TPS3840DL24DBVR

TPS3840DL25DBVR

TPS3840DL27DBVR

TPS3840DL28DBVR

TPS3840DL29DBVR

TPS3840DL30DBVR

TPS3840DL31DBVR

TPS3840DL35DBVR

TPS3840DL40DBVR

TPS3840DL42DBVR

TPS3840DL44DBVR

TPS3840DL45DBVR

TPS3840DL46DBVR

TPS3840DL49DBVR

ACTIVE

SOT-23

DBV

3000 RoHS & Green

NIPDAU | SN

Level-1-260C-UNLIM

-40 to 125

DL16

DL17

DL18

DL19

DL20

DL22

DL24

DL25

DL27

DL28

DL29

DL30

DL31

DL35

DL40

DL42

DL44

DL45

DL46

DL49

Samples

NIPDAU | SN

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

16-Apr-2023

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS3840PH18DBVR

TPS3840PH19DBVR

TPS3840PH27DBVR

TPS3840PH30DBVR

TPS3840PH40DBVR

TPS3840PH45DBVR

TPS3840PH49DBVR

TPS3840PL16DBVR

TPS3840PL18DBVR

TPS3840PL20DBVR

TPS3840PL25DBVR

TPS3840PL26DBVR

TPS3840PL27DBVR

TPS3840PL28DBVR

TPS3840PL29DBVR

TPS3840PL30DBVR

TPS3840PL31DBVR

TPS3840PL33DBVR

TPS3840PL34DBVR

TPS3840PL40DBVR

TPS3840PL41DBVR

ACTIVE

SOT-23

DBV

3000 RoHS & Green

NIPDAU | SN

Level-1-260C-UNLIM

-40 to 125

PH18

PH19

PH27

PH30

PH40

PH45

PH49

PL16

PL18

PL20

PL25

PL26

PL27

PL28

PL29

PL30

PL31

PL33

PL34

PL40

PL41

Samples

NIPDAU | SN

NIPDAU

NIPDAU | SN

NIPDAU

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

16-Apr-2023

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS3840PL42DBVR

TPS3840PL43DBVR

TPS3840PL45DBVR

TPS3840PL48DBVR

ACTIVE

SOT-23

DBV

3000 RoHS & Green

NIPDAU | SN

Level-1-260C-UNLIM

-40 to 125

PL42

PL43

PL45

PL48

Samples

NIPDAU | SN

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

16-Apr-2023

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS3840 :

Automotive : TPS3840-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS3840DL16DBVR

TPS3840DL17DBVR

TPS3840DL18DBVR

TPS3840DL19DBVR

TPS3840DL20DBVR

TPS3840DL22DBVR

TPS3840DL24DBVR

TPS3840DL25DBVR

TPS3840DL27DBVR

TPS3840DL28DBVR

TPS3840DL29DBVR

TPS3840DL30DBVR

TPS3840DL31DBVR

SOT-23

DBV

3000

180.0

8.4

3.2

1.4

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jun-2023

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS3840DL35DBVR

TPS3840DL40DBVR

TPS3840DL42DBVR

TPS3840DL44DBVR

TPS3840DL45DBVR

TPS3840DL46DBVR

TPS3840DL49DBVR

TPS3840PH18DBVR

TPS3840PH19DBVR

TPS3840PH27DBVR

TPS3840PH30DBVR

TPS3840PH40DBVR

TPS3840PH45DBVR

TPS3840PH49DBVR

TPS3840PL16DBVR

TPS3840PL18DBVR

TPS3840PL20DBVR

TPS3840PL25DBVR

TPS3840PL26DBVR

TPS3840PL27DBVR

TPS3840PL28DBVR

TPS3840PL29DBVR

TPS3840PL30DBVR

TPS3840PL31DBVR

TPS3840PL34DBVR

TPS3840PL40DBVR

SOT-23

DBV

3000

180.0

8.4

3.2

1.4

4.0

8.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jun-2023

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS3840PL41DBVR

TPS3840PL42DBVR

TPS3840PL43DBVR

TPS3840PL45DBVR

TPS3840PL48DBVR

SOT-23

DBV

3000

180.0

8.4

3.2

1.4

4.0

8.0

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS3840DL16DBVR

TPS3840DL17DBVR

TPS3840DL18DBVR

TPS3840DL19DBVR

TPS3840DL20DBVR

TPS3840DL22DBVR

TPS3840DL24DBVR

TPS3840DL25DBVR

TPS3840DL27DBVR

TPS3840DL28DBVR

TPS3840DL29DBVR

TPS3840DL30DBVR

TPS3840DL31DBVR

TPS3840DL35DBVR

SOT-23

DBV

3000

210.0

185.0

35.0

Pack Materials-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jun-2023

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS3840DL40DBVR

TPS3840DL42DBVR

TPS3840DL44DBVR

TPS3840DL45DBVR

TPS3840DL46DBVR

TPS3840DL49DBVR

TPS3840PH18DBVR

TPS3840PH19DBVR

TPS3840PH27DBVR

TPS3840PH30DBVR

TPS3840PH40DBVR

TPS3840PH45DBVR

TPS3840PH49DBVR

TPS3840PL16DBVR

TPS3840PL18DBVR

TPS3840PL20DBVR

TPS3840PL25DBVR

TPS3840PL26DBVR

TPS3840PL27DBVR

TPS3840PL28DBVR

TPS3840PL29DBVR

TPS3840PL30DBVR

TPS3840PL31DBVR

TPS3840PL34DBVR

TPS3840PL40DBVR

TPS3840PL41DBVR

TPS3840PL42DBVR

TPS3840PL43DBVR

SOT-23

DBV

3000

210.0

185.0

35.0

Pack Materials-Page 5

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jun-2023

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS3840PL43DBVR

TPS3840PL45DBVR

TPS3840PL48DBVR

SOT-23

DBV

3000

210.0

185.0

35.0

Pack Materials-Page 6

PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

3.0

2.6

0.1 C

1.75

1.45

0.90

PIN 1

INDEX AREA

(0.1)

2X 0.95

1.9

3.05

2.75

1.9

(0.15)

0.5

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

NOTE 5

0.25

GAGE PLANE

0.22

0.08

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/G 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

5. Support pin may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X (0.95)

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/G 03/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X(0.95)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/G 03/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TPS3840PL43DBVR [TI]

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