TPS3870J4330DSERQ1 [TI]
具有延时时间和手动复位功能的汽车类高精度过压复位 IC | DSE | 6 | -40 to 125;
| 型号： | TPS3870J4330DSERQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有延时时间和手动复位功能的汽车类高精度过压复位 IC | DSE | 6 | -40 to 125 |
| 文件： | 总29页 (文件大小：1073K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS3870-Q1
ZHCSK23A –JULY 2019–REVISED SEPTEMBER 2019
具有延时时间和手动复位功能的 TPS3870-Q1 过压复位 IC
1 特性
3 说明
1
•
符合汽车类 应用要求
具有符合 AEC-Q100 标准的下列特性：
TPS3870-Q1 器件是一款集成式过压 (OV) 监控器或复
位 IC，采用业界较小的 6 引脚 DSE 封装。这款高精
度的电压监控器非常适合采用低电压电源轨的系统，并
具有非常小的电源容差裕度。低阈值迟滞可防止在受监
控的电压处于正常工作范围内时发出虚假复位信号。并
且内置有毛刺抑制功能和噪声滤波器，进一步消除了错
误信号所导致的错误复位。
•
–
器件温度等级 1：–40°C 至 +125°C 的环境工作
温度范围
–
–
器件 HBM ESD 分类等级 2
器件 CDM ESD 分类等级 C7B
•
•
•
•
输入电压范围：1.7V 至 5.5V
欠压锁定 (UVLO)：1.7V
低静态电流：7µA（最大值）
高阈值精度：
TPS3870-Q1 不需要使用任何外部电阻器来设置过压
复位阈值，因此进一步优化了整体精度、成本、解决方
案大小并提高了安全系统的可靠性。电容器时间 (CT)
引脚用于在每个器件的两个可用复位延时时间之间进行
选择，还可以连接一个电容器以调整复位延时时间。单
独的 SENSE 输入引脚和 VDD 引脚可实现高可靠性系
统所需的冗余。
–
–
±0.25%（典型值）
±0.7%（-40°C 至 +125°C）
•
固定阈值电平
–
–
50mV 阶跃（500mV 至 1.3V）
1.5V、1.8V、2.5V、2.8V、2.9V、3.3V、5V
此器件的低典型静态电流规格为 4.5µA（典型值）。
TPS3870-Q1 适用于汽车 应用 ，符合 AEC-Q100 1
级标准。
•
•
•
•
用户可调的电压阈值电平
内部毛刺抑制和迟滞
阶跃为 1% 时，公差介于 3% 至 7% 之间
器件信息(1)
固定延时时间选项：50µs、1ms、5ms、10ms、
20ms、100ms、200ms
器件型号
封装
WSON (6)
封装尺寸（标称值）
•
•
•
使用单个外部电容器的可编程延时时间选项
开漏低电平有效 OV 监控器
TPS3870-Q1
1.50mm × 1.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
RESET 电压锁存输出模式
2 应用
•
•
•
•
•
高级驾驶员辅助系统 (ADAS)
摄像头
传感器融合
HEV/EV
基于 FPGA、ASIC 和 DSP 的系统
集成过压检测
典型过压精度分布
OV Threshold
35
Monitor Voltage
VCORE
30
25
20
15
10
5
TPS3870Q1
1
SENSE
6
5
MR
Processor
Up to
5.5V
VDD
CT
GND
2
3
10k ꢀ
RESET
4
RESET
Optional
0
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
VIT+(OV) Accuracy (%)
D004
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBI5
TPS3870-Q1
ZHCSK23A –JULY 2019–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 20
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD ratings............................................................... 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements................................................ 6
7.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
9
10 Power Supply Recommendations ..................... 22
10.1 Power Supply Guidelines...................................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
12 器件和文档支持 ..................................................... 23
12.1 器件命名规则......................................................... 23
12.2 文档支持................................................................ 24
12.3 接收文档更新通知 ................................................. 24
12.4 支持资源................................................................ 24
12.5 商标....................................................................... 24
12.6 静电放电警告......................................................... 24
12.7 Glossary................................................................ 24
13 机械、封装和可订购信息....................................... 24
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (July 2019) to Revision A
Page
•
将“预告信息”更改为“生产数据发布”......................................................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
TPS3870-Q1
www.ti.com.cn
ZHCSK23A –JULY 2019–REVISED SEPTEMBER 2019
5 Device Comparison Table
Table 1 shows the released versions of the TPS3870-Q1, including the nominal overvoltage thresholds. For all
possible voltages, threshold tolerance, time delays, and threshold options, see 表 6. Contact TI sales
representatives or on TI's E2E forum for details and availability of other options; minimum order quantities apply.
Table 1. Device Comparison Table
TIME DELAY (ms)
THRESHOLD
PART NUMBER
VMON
CT Pin =
Capacitor
CT Pin =
Open
TOLERANCE
CT Pin = VDD
TPS3870J4080DSERQ1
TPS3870J4330DSERQ1
0.80 V
3.30 V
Programmable
Programmable
10 ms
10 ms
200 ms
200 ms
4%
4%
Copyright © 2019, Texas Instruments Incorporated
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TPS3870-Q1
ZHCSK23A –JULY 2019–REVISED SEPTEMBER 2019
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6 Pin Configuration and Functions
DSE Package
6-Pin WSON
Top View
SENSE
MR
VDD
CT
GND
RESET
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
Input for the monitored supply voltage rail. When the SENSE voltage goes above the overvoltage
threshold, the RESET pin is driven low. Connect to VDD pin if monitoring VDD supply voltage.
1
SENSE
VDD
I
I
Supply voltage input pin. Good analog design practice is to place a 0.1-μF ceramic capacitor close to
this pin.
2
3
Capacitor time delay pin. The CT pin offers two fixed time delays by connecting CT pin to VDD or
leaving it floating. Delay time can be programmed by connecting an external capacitor reference to
ground.
CT
I
Active-low, open-drain output. This pin goes low when the SENSE voltage rises above the internally
overvoltage threshold (VIT+). See the timing diagram in 图 19 for more details. Connect this pin to a pull-
up resistor terminated to the desired pull-up voltage.
4
5
6
RESET
GND
MR
O
—
I
Ground
Manual reset (MR), pull this pin to a logic low (VMR_L) to assert a reset signal . After the MR pin is
deasserted the output goes high after the reset delay time(tD) expires. MR can be left floating when not
in use.
4
Copyright © 2019, Texas Instruments Incorporated
TPS3870-Q1
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ZHCSK23A –JULY 2019–REVISED SEPTEMBER 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX UNIT
Voltage
Voltage
Voltage
Voltage
Voltage
Current
VDD
6
6
V
V
VRESET
VCT
6
V
VSENSE
6
V
VMR
6
V
IRESET
±40
mA
Continuous total power dissipation
Operating junction temperature, TJ
Operating free-air temperature, TA
Storage temperature, Tstg
See the Thermal Information
-40
-40
-65
150
150
150
°C
°C
°C
(2)
Temperature
(1) Stresses beyond values listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD ratings
VALUE
±2000
±500
UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Electrostatic
discharge
V(ESD)
All pins
Corner pins
V
Charged-device model (CDM), per AEC
Q100-011
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
7.3 Recommended Operating Conditions
MIN
1.7
0
NOM
MAX
5.5
UNIT
V
VDD
Supply pin voltage
Input pin voltage
VSENSE
VCT
VRESET
VMR
IRESET
TJ
5.5
V
(1) (2)
CT pin voltage
VDD
5.5
V
Output pin voltage
0
0
V
(3)
MR pin Voltage
5.5
V
Output pin current
0.3
-40
10
mA
℃
Junction temperature (free-air temperature)
125
(1) CT pin connected to VDD pin requires a pullup resistor; 10 kΩ is recommended.
(2) The maximum rating is VDD or 5.5 V, whichever is smaller.
(3) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
Copyright © 2019, Texas Instruments Incorporated
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7.4 Thermal Information
TPS3870-Q1
DSE (WSON)
PINS
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
184.2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
30.6
86.4
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
13.4
ΨJB
86.1
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩ to VDD, RESET load = 10 pF, and over the
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical
conditions at VDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
1.7
TYP
MAX
5.5
1.7
1
UNIT
V
VDD
Supply Voltage
UVLO
VPOR
VIT+(OV)
VHYS
IDD
Under Voltage Lockout(1)
Power on reset voltage(2)
Positive- going threshold accuracy
Hysteresis Voltage(3)
VDD falling below 1.7 V
VOL(max) = 0.25 V, IOUT = 15 µA
1.2
V
V
-0.7
0.3
±0.25
0.55
4.5
0.7
0.8
7
%
%
Supply current
V
DD ≤ 5.5 V
µA
µA
mV
mV
mV
nA
V
ISENSE
Input current, SENSE pin
VSENSE = 5 V
1
1.5
250
250
250
300
0.3
VDD = 1.7 V, IOUT = 0.4 mA
VDD = 2 V, IOUT = 3 mA
VDD = 5 V, IOUT = 5 mA
VDD = VRESET = 5.5 V
VOL
Low level output voltage
ILKG
Open drain output leakage current
MR logic low input
VMR_L
VMR_H
VCT_H
RMR
MR logic high input
1.4
1.4
V
High level CT pin voltage
V
Manual reset Internal pullup resistance
CT pin charge current
CT pin comparator threshold voltage(4)
100
375
KΩ
nA
V
ICT
337
413
VCT
1.133
1.15
1.167
(1) RESET pin is driven low when VDD falls below UVLO.
(2) VPOR is the minimum VDD voltage level for a controlled output state.
(3) Hysteresis is with respect of the trip point (VIT+(OV)
)
(4) VCT voltage refers to the comparator threshold voltage that measures the voltage level of the external capacitor at CT pin.
7.6 Timing Requirements
At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩ to VDD, RESET load = 10 pF, and over the
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical
conditions at VDD = 3.3 V.
MIN
7
NOM
10
MAX
13
UNIT
ms
tD
tD
tD
tD
tD
tD
Reset time delay, TPS3870J
Reset time delay, TPS3870J
Reset time delay, TPS3870K
Reset time delay, TPS3870K
Reset time delay, TPS3870L
Reset time delay, TPS3870L
CT = Open
CT = 10 kΩ to VDD
CT = Open
140
0.7
14
200
1
260
1.3
26
ms
ms
CT = 10 kΩ to VDD
CT = Open
20
ms
3.5
70
5
6.5
130
ms
CT = 10 kΩ to VDD
100
ms
6
Copyright © 2019, Texas Instruments Incorporated
TPS3870-Q1
www.ti.com.cn
ZHCSK23A –JULY 2019–REVISED SEPTEMBER 2019
Timing Requirements (continued)
At 1.7 V ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET Voltage (VRESET) = 10 kΩ to VDD, RESET load = 10 pF, and over the
operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical
conditions at VDD = 3.3 V.
MIN
NOM
MAX
UNIT
CT = 10 kΩ to VDD
CT = Open
tD
Reset time delay, TPS3870M
50
µs
tPD
Propagation detect delay(1)(2)
Output rise time(1)(3)
Output fall time(1)(3)
Startup delay(4)
Glitch Immunity overvoltage VIT+(OV), 5% Overdrive(1)
15
2.2
0.2
300
3.5
30
µs
µs
µs
µs
µs
ns
ns
µs
ms
tR
tF
tSD
tGI (VIT+)
tGI (MR)
tPD (MR)
tMR_W
tD (MR)
Glitch Immunity MR pin
25
Propagation delay from MR low to assert RESET
MR pin pulse width duration to assert RESET
MR reset time delay
500
tD
1
(1) 5% Overdrive from threshold. Overdrive % = [VSENSE - VIT+(OV)] / VIT+(OV)
(2) tPD measured from threshold trip point VIT+(OV) to RESET VOL voltage
(3) Output transitions from VOL to 90% for rise times and 90% to VOL for fall times.
(4) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD + tD before the output is in the correct state.
Overdrive[2.5%] above VIT+(OV)
[0.7%]
Accuracy across (-40ºC to 125ºC)
[ 0.4% = 0.7%-0.3%) ]
[0.25%]
[ 0.15% = 0.7%-0.55%) ]
0.5%
[ -0.1% = 0.7%-0.8%) ]
Accuracy at 25ºC
VIT+(OV)
[-0.25%]
[-0.7%]
[-0.3%]
VIT+(OV) - VHYS
[-0.55%]
Hys band for VIT+(OV)
[-0.8%]
[ -1.0% = -0.7%-0.3%) ]
[ -1.25% = -0.7%-0.55%) ]
[ -1.5% = -0.7%-0.8%) ]
0.5%
Nominal monitored voltage
All percentages are calculated with respect to typical VIT
图 1. Voltage Threshold and Hysteresis Accuracy
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TPS3870-Q1
ZHCSK23A –JULY 2019–REVISED SEPTEMBER 2019
www.ti.com.cn
VDD(MIN)
UVLO
VDD
VPOR
VIT+(OV)
Hysteresis
VIT+(OV) - VHYS
SENSE
RESET
tD
tPD
tD
tSD
(1) VDD = 2 V, RPU = 10 kΩ to VDD
(2) Variant M (time delay bypass) has a ~40 µs pulse at RESET pin during power up window, this is present only when
the power cycle off time is longer than 10 seconds, this behavior will not occur if SENSE pin is within window of
operation during VDD power up.
图 2. SENSE Timing Diagram
8
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TPS3870-Q1
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ZHCSK23A –JULY 2019–REVISED SEPTEMBER 2019
7.7 Typical Characteristics
At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
35
30
25
20
15
10
5
0.2
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-50
-25
0
25
50
75
100
125
Temperature (èC)
VIT+(OV) Accuracy (%)
D002
D004
Tested across multiple voltage options
图 3. Overvoltage Accuracy vs Temperature
图 4. Overvoltage Accuracy Distribution
0.6
0.58
0.56
0.54
0.52
0.5
7
6
5
4
3
2
0.8 V
1.2 V
1.8 V
3.3 V
5.0 V
VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D006
D007
Tested across multiple voltage options
Output (RESET Pin) = High
图 6. Supply Current vs Temperature
图 5. Overvoltage Hysteresis Voltage Accuracy vs
Temperature
16
15
14
13
12
11
10
9
6
5
4
3
2
-40èC
25èC
125èC
VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V
-50
-25
0
25
50
75
100
125
0
5
10 15 20 25 30 35 40 45 50 55
Overdrive (%)
Temperature (èC)
D008
D010
Output (RESET Pin) = Low
图 7. Supply Current vs Temperature
VDD = 1.7 V
图 8. SENSE Glitch Immunity (VIT+) vs Overdrive
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Typical Characteristics (接下页)
At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
9
0.3
0.25
0.2
-40èC
25èC
125èC
8
7
6
5
4
3
0.15
0.1
-40èC
25èC
125èC
0.05
0
0
5
10 15 20 25 30 35 40 45 50 55
Overdrive (%)
0
1
2
3
4
5
IRESET (mA)
D012
D013
VDD = 5.5 V
VDD = 1.7 V
图 9. SENSE Glitch Immunity (VIT+) vs Overdrive
图 10. Low-Level Output Voltage vs RESET current
0.6
0.5
0.4
0.3
0.25
0.2
VMR_H
VMR_L
0.15
0.1
-40èC
25èC
125èC
0.05
0
0
1
2
3
4
5
-50
-25
0
25
50
75
100
125
IRESET (mA)
Temperature (èC)
D014
D015
VDD = 5.5 V
VDD = 1.7 V
图 11. Low-Level Output Voltage vs RESET current
图 12. SET Threshold vs Temperature
390
385
380
375
370
365
1.16
1.14
1.12
1.1
VMR_H
VMR_L
1.08
1.06
1.04
1.7 V
5.5 V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D016
D017
VDD = 5.5 V
图 13. SET Threshold vs Temperature
图 14. CT Current vs CT value
10
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ZHCSK23A –JULY 2019–REVISED SEPTEMBER 2019
Typical Characteristics (接下页)
At TJ = 25°C, VDD = 3.3 V, and RPU = 10 kΩ, unless otherwise noted.
500
5
1
100
10
1
-40èC
25èC
125èC
-40èC
25èC
125èC
0.1
0.1
0.1
1
10
CT (nF)
100
1000
0.1
1
CT (nF)
10
D018
D019
图 15. RESET Timeout vs CT Capacitor
图 16. Timeout vs CT Capacitor (0.1 to 10 nF)
12
10
8
6
4
VDD = 1.7 V
VDD = 3.3 V
VDD = 5.5 V
2
0
-50
-25
0
25
50
75
100
125
Temperature (èC)
D020
图 17. Detect Propagation Delay vs Temperature
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TPS3870-Q1
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8 Detailed Description
8.1 Overview
The TPS3870-Q1 family of devices uses a voltage comparator and a precision voltage reference for overvoltage
detection. The TPS3870-Q1 features a highly accurate threshold voltage (±0.7% over temperature) and a variety
of voltage threshold variants.
The TPS3870-Q1 includes the resistors used to set the overvoltage threshold internal to the device. These
internal resistors allow for lower component counts and greatly simplifies the design because no additional
margins are needed to account for the accuracy of external resistors.
TPS3870-Q1 versions J, K and L have three time delay settings, two fixed by connecting CT pin to VDD through
a resistor and leaving CT floating and a programmable time delay setting that only requires a single capacitor
connected from CT pin to ground.
Manual Reset (MR) allows for sequencing or hard reset by driving the MR pin below VMR_L
.
The TPS3870-Q1 is designed to assert active low output signals when the monitored voltage is outside the safe
window. The relationship between the monitored voltage and the states of the outputs is shown in 表 2.
8.2 Functional Block Diagram
VDD
CT
VCT
50mV
ICT
Cap
Control
SENSE
OV Comparator
Time Delay
Logic
RESET
Vref
VDD
RMR
GND
MR
*For all possible voltages, threshold tolerance, time delays, and threshold options, see 表 6.
8.3 Feature Description
8.3.1 VDD
The TPS3870-Q1 is designed to operate from an input voltage supply range between 1.7 V to 5.5 V. An input
supply capacitor is not required for this device; however, if the input supply is noisy good analog practice is to
place a 1-µF capacitor between the VDD pin and the GND pin.
VDD needs to be at or above VDD(MIN) for at least the start-up delay (tSD+ tD) for the device to be fully functional.
8.3.2 SENSE
The TPS3870-Q1 uses a comparator with a precision reference voltage and a trimmed resistor divider. This
configuration optimizes device accuracy because all resistor tolerances are accounted for in the accuracy and
performance specifications. The comparator also includes built-in hysteresis that provides noise immunity and
ensures stable operation.
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Feature Description (接下页)
Although not required in most cases, for noisy applications good analog design practice is to place a 1-nF to 10-
nF bypass capacitor at the SENSE input in order to reduce sensitivity to transient voltages on the monitored
signal.
When monitoring VDD supply voltage, the SENSE pin can be connected directly to VDD. The output (RESET) is
high impedance when voltage at the SENSE pin is lower than the upper boundary of the threshold.
8.3.3 RESET
In a typical TPS3870-Q1 application, the RESET output is connected to a reset or enable input of a processor
[such as a digital signal processor (DSP), application-specific integrated circuit (ASIC), or other processor type]
or the enable input of a voltage regulator [such as a DC-DC converter or low-dropout regulator (LDO)].
The TPS3870-Q1 has an open drain active low output that requires a pull-up resistor to hold these lines high to
the required voltage logic. Connect the pull-up resistor to the proper voltage rail to enable the output to be
connected to other devices at the correct interface voltage levels. To ensure proper voltage levels, give some
consideration when choosing the pull-up resistor values. The pull-up resistor value is determined by VOL, output
capacitive loading, and output leakage current. These values are specified in Specifications. The open drain
output can be connected as a wired-OR logic with other open drain signals such as another TPS3870-Q1
RESET pin.
表 2 describes the scenarios when the output (RESET) is either asserted low or high impedance.
VIT+(OV)
OV Limit
VIT+(OV) - VHYS
VSENSE
RESET
tPD
tD
图 18. RESET output
8.3.4 Capacitor Time (CT)
The CT pin provides the user the functionality of both high-precision, factory-programmed, reset delay timing
options and user-programmable, reset delay timing. The CT pin can be pulled up to VDD through a resistor, have
an external capacitor to ground, or can be left unconnected. The configuration of the CT pin is re-evaluated by
the device every time the voltage on the SENSE line enters the valid window (VSENSE < VIT+(OV)). The pin
evaluation is controlled by an internal state machine that determines which option is connected to the CT pin.
The sequence of events takes 450 μs to determine if the CT pin is left unconnected, pulled up through a resistor,
or connected to a capacitor. If the CT pin is being pulled up to VDD, then a pull-up resistor is required, 10 kΩ is
recommended.
8.3.5 Manual Reset (MR)
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR
causes RESET to assert. After MR returns to a logic high and the SENSE pin voltage is within a valid condition
(VSENSE < VIT+(OV)) , RESET is deasserted after the reset delay time (tD). If MR is not controlled externally, then
MR can either be connected to VDD or left floating because the MR pin is internally pulled up to VDD. Figure 图 19
shows the relation between MR and RESET.
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Feature Description (接下页)
VIT+(OV)
Hysteresis
VIT+(OV) - VHYS
SENSE
Pulse < VMR_L
Pulse < tGI (MR)
MR
VMR_H
VMR_L
tMR_W
RESET
tD(MR)
tPD (MR)
(1) RESET pulls up to VDD with 10 kΩ.
(2) To initiate and continue time reset counter both conditions must be met MR pin above VMR_H or floating and VSENSE
below VIT+(OV) - VHYS
(3) MR is ignored during output RESET low event
图 19. Manual Reset Timing Diagram
8.4 Device Functional Modes
表 2. Functional Mode Truth Table
DESCRIPTION
CONDITION
SENSE < VIT+(OV)
MR PIN
VDD PIN
VDD > VDD(MIN)
OUTPUT (RESET PIN)
Normal Operation
Open or above VMR_H
High
Over Voltage
detection
SENSE > VIT+(OV)
Open or above VMR_H
VDD > VDD(MIN)
Low
Manual reset
SENSE < VIT+(OV)
SENSE < VIT+(OV)
Below VMR_L
VDD > VDD(MIN)
Low
Low
UVLO engaged
Open or above VMR_H
VPOR < VDD < UVLO
8.4.1 Normal Operation (VDD > VDD(MIN)
)
When the voltage on VDD is greater than VDD(MIN) for approximately (tSD+ tD), the RESET output state will
correspond to the SENSE pin voltage with respect to the threshold limits, when SENSE voltage is outside of
threshold limits the RESET voltage will be low (VOL).
8.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage but greater than the power-on reset voltage
(VPOR), the RESET pin will be held low , regardless of the voltage on SENSE pin.
8.4.3 Power-On Reset (VDD < VPOR
)
When the voltage on VDD is lower than the required voltage (VPOR) to internally pull the asserted output to GND,
RESET signal is undefined and is not to be relied upon for proper device function.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Voltage Threshold Accuracy
Voltage monitoring requirements vary depending on the voltage supply tolerance of the device being powered.
Due to the high precision of the TPS3870-Q1 (±0.7% Max), the device allows for a wider supply voltage margins
and threshold headroom for tight tolerance applications.
For example, take a DC/DC regulator providing power to a core voltage rail of an MCU. The MCU has a
tolerance of ±5% of the nominal output voltage of the DC/DC. The user sets an ideal voltage threshold of 4%
which allows for ±1% of threshold accuracy. Since the TPS3870-Q1 threshold accuracy is higher than ±1%, the
user has more supply voltage margin which can allow for a relaxed power supply design. This gives flexibility to
the DC/DC to use a smaller output capacitor or inductor because of a larger voltage window for voltage ripple
and transients. There is also headroom between the minimum system voltage and voltage tolerance of the MCU
to ensure that the voltage supply will never be in the region of potential failure of malfunction without the
TPS3870-Q1 asserting a reset signal.
图 20 illustrates the supply overvoltage margin and accuracy of the TPS3870-Q1 for the example explained
above. Using a low accuracy supervisor will eat into the available budget for the power supply ripple and
transient response. This gives less flexibility to the user and a more stringent DC/DC converter design.
DC/DC nominal output
0%
Supply
Regulator output voltage accuracy
Voltage
Margin
Margin for ripple and transients
Voltage
Threshold
Accuracy
0.7% Allowed threshold tolerance
+
4%
5%
- 0.7% Minimum system voltage
Potential Failure or Malfunction
图 20. TPS3870-Q1 Voltage Threshold Accuracy
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Application Information (接下页)
9.1.2 CT Reset Time Delay
The TPS3870-Q1 features three options for setting the reset delay (tD): connecting a capacitor to the CT pin,
connecting a pull-up resistor to VDD, and leaving the CT pin unconnected. 图 21 shows a schematic drawing of
all three options. To determine which option is connected to the CT pin, an internal state machine controls the
internal pulldown device and measures the pin voltage. This sequence of events takes 450 μs to determine
which timing option is used. Every time the voltage on the SENSE line enters the valid window (VSENSE < VIT+(OV)
-VHYS, the state machine determines the CT option.
VDD
VDD
VDD
VDD
VDD
VDD
CT
ICT
ICT
ICT
CT
CT
Cap
Control
Cap
Control
Cap
Control
User Programmable
Capacitor to GND
CT Unconnected
10 kΩ Resistor to VDD
图 21. CT Charging Circuit
9.1.2.1 Factory-Programmed Reset Delay Timing
To use the factory-programmed timing options, the CT pin must either be left unconnected or pulled up to VDD
through a 10 kΩ pull-up resistor. Using these options enables a high-precision reset delay timing, as shown in 表
3.
表 3. Reset Delay Time for Factory-Programmed Reset Delay Timing
RESET DELAY TIME (tD)
VARIANT
VALUE
CT = Capacitor to GND
Programmable tD
Programmable tD
Programmable tD
N/A
CT = Floating
CT = 10 kΩ to VDD
TPS3870J
TPS3870K
TPS3870L
TPS3870M
10
1
200
20
ms
ms
ms
µs
5
100
50
50
9.1.2.2 Programmable Reset Delay-Timing
The TPS3870 reset time delay is based on internal current source (ICT) to charge external capacitor (CCT) and
read capacitor voltage with the internal comparator. The minimum value capacitor is 250 pF. There is no
limitation on maximum capacitor the only constrain is imposed by the initial voltage of the capacitor, if CT cap is
zero or near to zero then ideally there is no other constraint on the max capacitor. The typical ideal capacitor
value needed for a given delay time can be calculated using 公式 1, where CCT is in nanofarads (nF) and tD is in
ms:
tD = 3.066 × CCT + 0.5 ms
(1)
To calculate the minimum and maximum-reset delay time use 公式 2 and 公式 3, respectively.
tD(min) = 2.7427 × CCT + 0.3 ms
(2)
(3)
tD(max) = 3.4636 × CCT + 0.7 ms
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The slope of the equation is determined by the time the CT charging current (ICT) takes to charge the external
capacitor up to the CT comparator threshold voltage (VCT). When RESET is asserted, the capacitor is discharged
through the internal CT pulldown resistor. When the RESET conditions are cleared, the internal precision current
source is enabled and begins to charge the external capacitor; when VCT = 1.15 V, RESET is unasserted. Note
that in order to minimize the difference between the calculated RESET delay time and the actual RESET delay
time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board
capacitance around this pin. 表 4 lists the reset delay time ideal capacitor values for CCT
.
表 4. Reset Delay Time for Ideal Capacitor Values
CCT
250 pF
1 nF
RESET DELAY TIME (tD), TYPICAL
1.27 ms
3.57 ms
3.26 nF
32.6 nF
65.2 nF
1uF
10.5 ms
100.45 ms
200.40 ms
3066.50 ms
9.1.3 RESET Latch Mode
The TPS3870-Q1 features a voltage latch mode on the RESET pin when connecting the CT pin to common
ground . A pull-down resistor is recommended to limit current consumption of the system. In latch mode, if the
RESET pin is low or triggers low, the pin will stay low regardless if VSENSE is within the acceptable voltage
boundaries (VSENSE < VIT+(OV)). To unlatch the device provide a voltage to the CT pin that is greater than the CT
pin comparator threshold voltage, VCT. The RESET pin will trigger high instantaneously without any reset delay.
A voltage greater than 1.2 V to recommended to ensure a proper unlatch. Use a series resistance to limit current
when an unlatch voltage is applied. For more information, Design 1: RESET Latch Mode gives an example of a
typical latch application.
注
At power up, the TPS3870-Q1 will be latched when CT is connected to GND. To ensure
correct power up when using RESET latch mode, send a pulse to the CT pin greater than
1.2 V after tSD and SENSE is within the correct window of operation.
VDD
VDD
ICT
10 kꢀ
CT
V > VCT
Voltage at CT
to Unlatch
Cap
Control
10 kꢀ Resistor to
GND to Latch
图 22. RESET Latch Circuit
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9.1.4 Adjustable Voltage Thresholds
The TPS3870-Q1 0.7% maximum accuracy allows for adjustable voltage thresholds using external resistors
without adding major inaccuracies to the device. In case that the desired monitored voltage is not available,
external resistor dividers can be used to set the desired voltage thresholds. 图 23 illustrates an example of how
to adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the
desired voltage threshold and device part number. TI recommends using the 0.8V voltage threshold device such
as the TPS3870J4080 because of the bypass mode of internal resistor ladder.
For example, consider a 2.0 V rail being monitored (VMON) using the TPS3870J4080 variant. Using 公式 4, R1 =
15 kΩ given that R2 = 10 kΩ, VMON = 2 V , and VSENSE = 0.8 V. This device is typically meant to monitor a 0.8 V
rail with a +4% voltage threshold. This means that the device overvoltage threshold (VIT+(OV)) is 0.832 V. Using 公
式 4, the monitored overvoltage threshold (VMON+) = 2.08 V when VSENSE = VIT+(OV). If a wider tolerance threshold
is desired, use a device variant shown on 表 6 to determine what device part number matches your application.
VSENSE = VMON × (R2 ÷ (R1 + R2))
(4)
There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the
tolerance of the resistor divider, there is an internal resistance of the SENSE pin that may affect the accuracy of
the resistor divider. Although expected to be very high impedance, users are recommended to calculate the
values for design specifications. The internal sense resistance (RSENSE) can be calculated by the sense voltage
(VSENSE) divided by the sense current (ISENSE) as shown in 公式 6. VSENSE can be calculated using 公式 4
depending on the resistor divider and monitored voltage. ISENSE can be calculated using 公式 5.
ISENSE = (VMON – VSENSE) ÷ R1 – (VSENSE ÷ R2)
RSENSE = VSENSE ÷ ISENSE
(5)
(6)
VMON
VDD
R1
10 lQ
TPS3870-Q1
Vsense
SENSE
RESET
VDD
VDD
CT
MR
R2
GND
图 23. Adjustable Voltage Threshold with External Resistor Dividers
Although 公式 4 solves for VSENSE, inaccuracies for leakage need to be taken into consideration when
understanding the overall threshold accuracy of the device. To calculate the threshold with this inaccuracy taken
into account, use 公式 7
VIT_Actual = VSENSE + R1 × ((VSENSE ÷ R2) + ISENSE
)
(7)
To calculate the worst case values through the resistor divider, ISENSE should be taken from the Electrical
Characteristics table. While these equations provide a summary of what you need to correctly account for factors
that go into determining your resistor divider with inaccuracy, you should use the Application Report Optimizing
Resistor Dividers at a Comparator Input to further understand this and to design your implementation. This report
explains how to optimize the resistor divider at the SENSE input for an adjustable voltage threshold version of
the device. You should follow this Application Report using 0.8 V as the VREF value for the TPS3870-Q1.
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9.1.5 Immunity to SENSE Pin Voltage Transients
The TPS3870-Q1 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends
on both transient duration and overdrive (amplitude) of the transient.
Overdrive is defined by how much the VSENSE exceeds the specified threshold, and is important to know because
the smaller the overdrive, the slower the response of the outputs (RESET). Threshold overdrive is calculated as
a percent of the threshold in question, as shown in 公式 8:
Overdrive % = | (VSENSE - (VIT+(OV))) / VIT (Nominal) × 100% |
where:
•
•
•
VSENSE is the voltage at the SENSE pin
VIT (Nominal) is the nominal threshold voltage
VIT+(OV) represents the actual overvoltage tripping voltage
(8)
9.1.5.1 Hysteresis
The overvoltage comparator includes built-in hysteresis that provides noise immunity and ensures stable
operation. For example if the voltage on the SENSE pin goes above VIT+(OV) and RESET is asserted (driven low),
then when the voltage on the SENSE pin is below the positive threshold voltage, RESET deasserts after the
user-defined RESET delay time. Figure 图 24 shows the relation between VIT+(OV) and hysteresis voltage (VHYS).
VRESET
VSENSE
VIT+(OV) - VHYS
VIT+(OV)
图 24. SENSE Pin Hysteresis
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9.2 Typical Application
9.2.1 Design 1: RESET Latch Mode
Another typical application for the TPS3870-Q1 is shown in 图 25. The TPS3870-Q1 is used in a RESET latch
output mode. In latch mode, once RESET driven logic low, it will stay low regardless of the sense voltage. If the
RESET pin is low on start up, it will also stay low regardless of sense voltage.
VCORE
VCORE
VDD
Microcontroller
10 lQ
TPS3870-Q1
VGPIO
SENSE
VDD
CT
RESET
MR
VDD
Microcontroller
10 lQ
VGPIO
GND
10 lQ
图 25. Window Voltage Monitoring with RESET Latch
9.2.1.1 Design Requirements
表 5. Design Parameters
PARAMETER
Monitored Rail
DESIGN REQUIREMENT
DESIGN RESULT
1.2-VCORE nominal, with alerts if outside of 5% of
1.2 V (including device accuracy), Latch when
RESET is low, until voltage is applied on CT pin.
Worst case VIT+(OV) = 1.256 V (4.7%),
Output logic voltage
5-V CMOS
5-V CMOS
Maximum device current
consumption
15 µA
4.5 µA (Typ), 7 µA (Max)
9.2.1.2 Detailed Design Procedure
The RESET pin can be latched when the CT pin is connected to a common ground with a pull-down resistor. A
10 kΩ resistors is recommended to limit current consumption. To unlatch the device provide a voltage to the CT
pin that is greater than the CT pin comparator threshold voltage, VCT. A voltage greater than 1.15 V to
recommended to ensure a proper unlatch. Use a series resistance to limit current when an unlatch voltage is
applied. To go back into latch operation, disconnect the voltage on the CT pin. The RESET pin will trigger high
instantaneously without any reset delay.
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9.2.1.3 Application Curves
VSENSE ramp from 0 V to 1.4V, VDD = 3.3 V, VCT = 0 V
VRESET = VDD = 3.3 V
VCT biased at least to 1.15 V , VSENSE = 1.2 V
VRESET = VDD = 3.3 V
图 26. TPS3870-Q1 SENSE Ramp Latch Function
图 27. TPS3870-Q1 CT Bias Unlatch Function
VDD ramp up from 0 V to 3.3 V , VSENSE = 1.2 V, CT = 0 V
VRESET = VDD = 3.3 V
图 28. TPS3870-Q1 VDD Ramp Latch Function
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10 Power Supply Recommendations
10.1 Power Supply Guidelines
This device is designed to operate from an input supply with a voltage range between 1.7 V to 5.5 V. It has a 6-V
absolute maximum rating on the VDD pin. It is good analog practice to place a 0.1-µF to 1-µF capacitor between
the VDD pin and the GND pin depending on the input voltage supply noise. If the voltage supply providing power
to VDD is susceptible to any large voltage transient that exceed maximum specifications, additional precautions
must be taken. See SNVA849 for more information.
11 Layout
11.1 Layout Guidelines
•
Place the external components as close to the device as possible. This configuration prevents parasitic errors
from occurring.
•
Avoid using long traces for the VDD supply node. The VDD capacitor, along with parasitic inductance from
the supply to the capacitor, can form an LC circuit and create ringing with peak voltages above the maximum
VDD voltage.
•
•
Avoid using long traces of voltage to the sense pin. Long traces increase parasitic inductance and cause
inaccurate monitoring and diagnostics.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
11.2 Layout Example
Pull-Up Voltage
V_Sense
VDD
MR
GND
Sense
VDD
CT
10 kΩ
RESET
1 …F
GND
图 29. Recommended Layout
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12 器件和文档支持
12.1 器件命名规则
表 6 显示了如何根据器件型号来解译器件的功能。
表 6. 器件命名约定
说明
命名规则
值
TPS3870
TPS3870
CT 引脚断开 = 10ms，CT 引脚连接到 VDD = 200ms
可使用外部电容器对 CT 进行编程
J
K
L
CT 引脚断开 = 1ms，CT 引脚连接到 VDD = 20ms
可使用外部电容器对 CT 进行编程
延时时间选项：每个器件都有两个
固定延时时间，而且可以通过外部
电容器器件型号来调节延迟选项
仅 OV
CT 引脚断开 = 5ms，CT 引脚连接到 VDD = 100ms
可使用外部电容器对 CT 进行编程
CT 引脚断开 = 50µs，CT 引脚连接到 VDD = 50µs
无法对 CT 进行编程
M
3
来自标称值的过压阈值 = OV：3%
4
来自标称值的过压阈值 = OV：4%
容差选项：触发电压或以上述阈值电压百分比
形式表示的阈值电压
5
来自标称值的过压阈值 = OV：5%
6
来自标称值的过压阈值 = OV：6%
7
来自标称值的过压阈值 = OV：7%
标称监控器阈值电压选项
050
055
060
065
070
075
080
085
090
095
100
105
110
115
120
125
130
150
180
250
280
290
330
500
DSE
R
0.50V
0.55V
0.60V
0.65V
0.70V
0.75V
0.80V
0.85V
0.90V
0.95V
1.00V
1.05V
1.10V
1.15V
1.20V
1.25V
1.30V
1.50V
1.80V
2.50V
2.80V
2.90V
3.30V
5.00V
WSON - 6 引脚 (1.5mm × 1.5mm)
大卷带
封装
卷带
汽车版本
Q1
Q100 AEC
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12.2 文档支持
12.2.1 评估模块
评估模块 (EVM) 可与 TPS3870-Q1 配套使用，帮助评估初始电路性能。适用于 TPS3703-Q1 的 EVM 可用于对
TPS3870-Q1 仅进行过压评估。TPS3703-Q1 评估模块（以及相关的用户指南）可在德州仪器 (TI) 网站上的产品
文件夹中获取，也可直接从 TI 网上商店购买。
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
24
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重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3870J4080DSERQ1
TPS3870J4330DSERQ1
ACTIVE
ACTIVE
WSON
WSON
DSE
DSE
6
6
3000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
H5
H4
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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