TPS40042DRCT [TI]
LOW PIN COUNT, LOW VIN (3.0 V TO 5.5 V) SYNCHRONOUS BUCK DC-TO-DC CONTROLLER WITH EXTERNAL REFERENCE INPUT; 低引脚数，低VIN （ 3.0 V至5.5 V ）与外部基准输入同步降压型DC - DC控制器
| 型号： | TPS40042DRCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW PIN COUNT, LOW VIN (3.0 V TO 5.5 V) SYNCHRONOUS BUCK DC-TO-DC CONTROLLER WITH EXTERNAL REFERENCE INPUT |
| 文件： | 总35页 (文件大小：834K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
LOW PIN COUNT, LOW V (3.0 V TO 5.5 V) SYNCHRONOUS BUCK DC-TO-DC
IN
CONTROLLER WITH EXTERNAL REFERENCE INPUT
1
FEATURES
CONTENTS
2
•
3.0-V to 5.5-V Input
•
•
•
•
•
•
External Reference required: 0.5 V to 1.5 V
Output Voltage from REFIN to 90% of VIN
High-Side Drive for N-Channel FET
Supports Pre-Biased Outputs
Device Ratings
2
4
Electrical Characteristics
Device Information
Application Information
Design Examples
8
10
18
28
Adaptive Anti-Cross Conduction Gate Drive
Fixed switching frequency (600 kHz) Voltage
Mode Control
Additional References
•
Three Selectable Short Circuit Protection
Levels
DESCRIPTION
•
•
•
•
Hiccup Restart from Faults
Active Low Enable
The TPS40042 DC/DC controller is designed to
operate with an input source between a 3.0 V and 5.5
V. To reduce the number of external components, a
number of operating parameters are fixed internally.
The operating frequency for example, is internally set
at 600 kHz. (Continued)
Thermal Shutdown Protection at 145°C
10-Pin, 3-mm x 3-mm SON (DRC)
APPLICATIONS
•
•
•
•
DDR Memory
Point of Load
Telecommunications
DC to DC Modules
V
IN
TPS40042
HDRV 10
Reference Input
1
2
3
4
5
REFIN
EN
SW
BOOT
LDRV
GND
9
8
7
6
V
OUT
Enable
FB
COMP
VDD
UDG-07141
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Predictive Gate Drive is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
DESCRIPTION (CONT.)
One of three short circuit threshold levels may be selected by the addition of an external resistor from the COMP
pin to circuit ground (no resistor is the default setting). During power on, and before the internal soft start
commands the output voltage to rise, the TPS40042 enters a calibration cycle, measures the current out of the
COMP pin, and selects an internal SCP threshold voltage. At the end of the 1.5-ms calibration time, the output
voltage is allowed to enter soft-start. During operation, the selected SCP threshold voltage is compared to the
upper MOSFET’s voltage drop during its ON time to determine whether there is an overload condition. If the
voltage across the MOSFET exceeds the threshold voltage, the TPS40042 counts seven continuous pulses
before shutting completely OFF for seven soft start charge/discharge cycles, after which, the TPS40042 attempts
to restart the output.
During startup, both the high-side MOSFET switch and the synchronous rectifier are held in the OFF state until
the internal soft start commands an output voltage higher than the voltage currently at the output. This may
happen when the output is pre-biased at some voltage greater than zero and less than the desired regulation
voltage. When the internal soft start first commands the output to rise, the pulse width of the synchronous
rectifier is slowly increased from zero to the full 1-D conduction time by a number of discrete steps. In this way,
inductor current is not allowed to reverse quickly, and ensures a monotonic startup of the output whether the
output starts from zero or from a pre-bias level. If power is applied to the device while the EN (enable low) pin is
allowed to float high, the TPS40042 remains OFF. Only when the EN pin is pulled down towards ground is the
controller allowed to start.
ORDERING INFORMATION
OPERATING FREQUENCY
600 kHz
PACKAGE
TAPE AND REEL QTY.
PART NUMBER
TPS40042DRCT
TPS40042DRCR
Plastic 10-pin SON (DRC)
Plastic 10-pin SON (DRC)
250
600 kHz
3000
DEVICE RATINGS
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted, all voltages are with respect to GND.)
PARAMETER
VALUE
6.5
UNIT
VDD
SW
-3 to 10.5
-5
SW
transient (< 50 ns)
BOOT
HDRV
SW+6.5
SW to SW+6.5
V
EN, FB, LDRV
,REFIN
-0.3 to 6.5
COMP
-0.3 to 3
-40 to 150
-55 to 150
Operating junction temperature
Storage junction temperature
°C
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
3.0
0.5
-40
TYP
MAX
5.5
UNIT
VVDD
VREFIN
TJ
Input voltage to VDD pin
V
V
Voltage applied to REFIN pin during regulation
Junction temperature
1.5
125
°C
2
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
PARAMETER
MIN
TYP
2500
1500
MAX
UNIT
V
Human body model
CDM
V
PACKAGE DISSIPATION RATINGS(1)
THERMAL IMPEDANCE
TA = 25°C POWER RATING
JUNCTION-TO-AMBIENT
TA = 85°C POWER RATING
48°C/W
2W
0.8W
(1) For more information on the DRC package and the test method, refer to TI technical brief, literature number SZZA017.
Copyright © 2007, Texas Instruments Incorporated
3
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
ELECTRICAL CHARACTERISTICS
TJ = -40 °C to 85°C VVDD = 5 V, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VVDD
Input voltage range(1)
3.0
5.5
180
V
IDDsd
IDDq
Shutdown
VEN = VVDD
100
µA
Quiescent
VFB = 0.8 V
1.0
3.0
2.0
mA
IDDs
Switching current
Minimum turn-on voltage
No load at HDRV/LDRV
UVLOON
1.90
80
2.05
130
2.2
V
UVLOHYS Hysteresis
200
mV
OSCILLATOR/ RAMP GENERATOR
fPWM
PWM frequency
3.0 V < VVDD < 5.5 V
VVDD = 5.0 V, 0°C < TJ < 70°C
VPEAK – VVALLEY
500
540
600
600
0.87
0.4
700
660
1.0
kHz
kHz
V
fPWM
PWM frequency
VRAMP
VVALLEY
PWM
Ramp amplitude PP
Ramp valley voltage
0.75
V
MAXDUTY Maximum duty cycle,
MINDUTY Minimum duty cycle
MIN pulse
VFB = 0 V, 3.0 V < VVDD < 5.5 V
88%
95%
90
0%
Minimum width control range before
jumping to zero.
Minimum controllable pulse width
150
ns
(2)
width
ERROR AMPLIFIER
VOS
IFB
FB to REFIN offset voltage
0.5 V < VREFIN < 1.5 V
-5
0
5
mV
nA
FB, REFIN input bias current
-30
-125
IOH = 0.5 mA, VFB = 0 V, VVDD = 5.5
V
VOH
High level output voltage
2.0
2.5
V
VOL
IOH
Low level output voltage
Output source current
Output sink current
Gain bandwidth
IOL = 0.5 mA, VFB = VVDD
VCOMP = 0.7 V, VFB = GND
VCOMP = 0.7 V, VFB = VVDD
80
6
150
mV
1
2
mA
IOL
8
(2)
GBW
AOL
5
10
85
MHz
dB
Open loop gain
55
SHORT CIRCUIT PROTECTION
Resistor COMP to GND = 2.4 kΩ, TJ
= 25°C
Low short circuit threshold voltage
80
140
250
105
175
130
210
370
TH1
Medium short circuit threshold
voltage
Default: No resistor COMP to GND,
TJ = 25°C
VTH2
mV
Resistor COMP to GND = 12 kΩ, TJ
= 25°C
VTH3
High short circuit threshold voltage
Threshold temperature coefficient
310
3100
190
(2)
(2)
VTH(tc)
tON(oc)
ppm
ns
Minimum HDRV pulse time in over
current
tSWOCblank SW leading edge blanking pulse in
100
40
(2)
over current detection
tHICCUP
Hiccup time between restarts
ms
(1) VVDD operation to 2.25 V is possible with some degradation in specifications. Under this condition, the VREFIN range is limited to 0.5 V to
0.7 V.
(2) Ensured by design. Not production tested.
4
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
TJ = -40 °C to 85°C VVDD = 5 V, (unless otherwise noted)
PARAMETER
SOFT START/ENABLE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Calibration time before softstart
begins
(3)
tCAL
1.0
1.6
2.5
FB rise time from 0 V to VREFIN = 1.5
V
ms
(3)
tSS
Soft start time(4)
4.5
5.5
6.0
7.6
7.5
10
tREG
Time to voltage regulation
Enable threshold
Sum of tCAL plus tSS ; VREFIN = 1.5 V
EN voltage w.r.t. VVDD
VEN
-0.8
-1.2
50
-1.6
V
VENHYS
Enable hysteresis
mV
BOOTSTRAP
RBOOT3V3
VBOOT to VVDD, VVDD = 3.3 V
VBOOT to VVDD, VVDD = 5 V
50
30
Bootstrap switch resistances
Ω
Ω
RBOOT5V
OUTPUT DRIVER
VBOOT - VSW = 3.3 V, ISRCE = 100
mA
RHDHI3V3
HDRV pull-up resistance
3.0
5.5
RHDLO3V3
RLDHI3V3
RLDLO3V3
HDRV pull-down resistance
LDRV pull-up resistance
LDRV pull-down resistance
LDRV, HDRV rise time
LDRV, HDRV fall time
VBOOT - VSW = 3.3 V, ISINK = 100 mA
VVDD = 3.3 V, ISOURCE = 100 mA
VVDD = 3.3 V, ISINK = 100 mA
CLOAD = 1 nF
1.5
3.0
1.0
15
3
5.5
2.0
35
(5)
tRISE
(5)
tFALL
CLOAD = 1 nF
10
25
ns
TDEAD HL Adaptive timing HDRV to LDRV
TDEAD LH Adaptive timing LDRV to HDRV
SWITCH NODE
No load
15
5
30
45
No load
15
35
ILEAK
Leakage current
VEN = VVDD
-2
µA
°C
THERMAL SHUTDOWN
(5)
tSD
Shutdown temperature
Hysteresis
145
15
(3) tCAL and tSS track with temperature and input voltage
(4) Soft start time is a function of VREFIN. See Applications section for further detail.
(5) Ensured by design. Not production tested.
Copyright © 2007, Texas Instruments Incorporated
5
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
TYPICAL CHARACTERISTICS
Quiescent Current (Non-Switching)
Shutdown Current
1.100
1.000
0.900
110
105
100
VDD = 2.25 V
VDD = 5.5 V
95
0.800
0.700
0.600
0.500
0.400
90
85
80
VDD = 2.25 V
VDD = 5.5 V
75
70
−40 −20
0
20
40 60
80 100 120
−20
0
20
40 60
80 100 120
−40
Temperature − C
Temperature − C
Figure 1.
Figure 2.
UVLO Threshold
EN Threshold
2.200
2.150
2.100
2.050
−0.8
−0.9
−1.0
−1.1
−1.2
−1.3
Turn ON
Turn OFF
VDD = 5 V
2.000
1.950
1.900
1.850
1.800
−1.4
−1.5
−1.6
−40 −20
0
20
40 60
80 100 120
−40 −20
0
20
40 60
80 100 120
Temperature − C
Temperature − C
Figure 3.
Figure 4.
Oscillator Frequency
Soft Start Time; VREFIN = 1.5 V
700
650
6.6
6.5
6.4
VDD = 2.25V
VDD = 3.9V
VDD = 5.5V
VDD = 5 V
600
550
500
6.3
6.2
6.1
6.0
-40
-20
0
20
40
60
80
100 120
−40 −20
0
20
40 60
80 100 120
T - Temperature - °C
Temperature − C
Figure 5.
Figure 6.
6
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
TYPICAL CHARACTERISTICS (continued)
PWM Gain
ILIM Threshold
6.1
450
400
R
= 2.5 kΩ
R
= 12.5 kΩ
R
=nil
C
C
C
VDD = 5 V
6.0
350
300
250
200
150
100
50
5.9
5.8
5.7
5.6
5.5
−40 −20
0
20
40 60
80
100 120
−40 −20
0
20
40 60
80
100 120
Temperature − C
Temperature − C
Figure 7.
Figure 8.
Bootstrap Switch Resistance
Minimum Controllable Pulse Width
80
100
95
90
85
80
75
70
VDD = 3.3 V
VDD = 5 V
70
60
50
40
30
20
65
60
VDD = 2.25 V
VDD = 5.5 V
−40 −20
0
20
40 60 80 100 120
−40 −20
0
20
40 60
80
100 120
Temperature − C
Temperature − C
Figure 9.
Figure 10.
Maximum Duty Cycle
SW Node Leakage Current
100
0.00
−0.50
−0.10
VDD = 5.5 V
VDD = 2.25 V
VDD = 5.5 V
98
96
−0.15
−0.20
−0.25
−0.30
94
−0.35
−0.40
92
90
−0.45
−0.50
−40 −20
0
20
40 60
80 100 120
−40 −20
0
20
40 60
80
100 120
Temperature − C
Temperature − C
Figure 11.
Figure 12.
Copyright © 2007, Texas Instruments Incorporated
7
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
DEVICE INFORMATION
TERMINAL CONFIGURATION
The package is an 10-pin SON (DRC) package.
1
REFIN
EN
HDRV 10
2
3
4
5
SW
BOOT
LDRV
GND
9
8
7
6
FB
COMP
VDD
Figure 13. DRC Package Terminal Configuration (Top View)
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Input (bootstrapped) supply to the high-side gate driver for PWM enabling the gate of the
high side FET to be driven above the input supply rail. Connect a ceramic capacitor from this
pin to SW. This capacitor is charged from the VDD pin voltage through an internal switch.
The switch is turned ON during the off time of the converter. To slow down the turn on of the
external MOSFET, a small resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap
capacitor. See Applications Section to calculate the appropriate value.
BOOT
8
I
Output of the error amplifier and connection node for loop feedback components. The
voltage at this pin determines the duty cycle for the PWM. Optionally, a resistor from this pin
to ground is used to determine the voltage threshold used for short circuit protection. (See
Application Section)
COMP
4
O
•
•
•
Low threshold R = 2.4 kΩ, ±10%
Mid threshold R = not installed
High threshold R = 12 kΩ, ±10%
Active low enable input allows ON/OFF operation of the controller. If power is applied to the
TPS40042 while the EN pin is allowed to float high, the TPS40042 remains disabled (both
external switches are held OFF). Only when the EN pin is pulled to 1.2 V below VDD is the
TPS40042 allowed to start. An internal 100-kΩ resistor is connected between VDD and EN
to provide pull up. Connect this pin to GND to bypass the enable function.
EN
FB
2
3
I
I
Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is at the
same potential as the REFIN pin. A series resistor divider from the converter output to
ground, with the center connection tied to this pin, determines the value of the regulated
output voltage. This pin is also a connection node for loop feedback components.
GND
6
10
7
Electrical ground connection for the device.
This is the gate drive output for the high side N-channel MOSFET switch for PWM. It is
referenced to SW and is bootstrapped for enhancement of the high-side switch.
HDRV
LDRV
O
O
Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET.
Non-inverting imput to the error amplifier. A precision voltage must be applied to this pin
before the TPS40042 is enabled. Since this input is connected directly to the non-inverting
pin of the error amplifier, the quality of the voltage at this pin has a direct impact on the
quality of the output voltage.
REFIN
1
I
Connection to the switched node of the converter and the power return for the upper gate
driver. There should be a high current return path from the source of the upper MOSFET to
this pin. It is also used by the adaptive gate drive circuits to minimize the dead time between
upper and lower MOSFET conduction.
SW
9
5
O
I
Power input to the device. This pin should be locally bypassed to GND with a low ESR
ceramic capacitor of 1 µF or greater.
VDD
Thermal pad used to conduct heat from the device. This pad should be tied externally to a
ground plane. See Application Section for PC board layout information.
PPAD
8
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
Block Diagram
TPS40042
VDD/2
SW
VDD
EN
5
2
VDD
UVLO
100-ns
Delay
100 kW
SDN
2 V
EN
Fault
Logic
ILIMSET
VDD
Current Limit
Comparator
(VDD- 1.2 V)
LDRV
REFIN
1
SDN
CLK
8
BOOT
PWM
Comparator
HI
+
+
Soft
Start
10 HDRV
PWM
Logic
FB
3
4
Adaptive
Gate
Drive
Ramp
Oscillator
9
7
SW
VDD
COMP
0.6 V
VREF
LO
VDD
LDRV
ILIMSET
(one of three levels)
Calibration
Circuit
Reference
Thermal
Shutdown
Pre-Bias
6
UDG-07139
GND
Figure 14. Functional Block Diagram
Copyright © 2007, Texas Instruments Incorporated
9
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
APPLICATION INFORMATION
Functional Description
The TPS40042 is a fixed frequency voltage mode synchronous buck controller. In operation, the Synchronous
Rectifier (SR) is allowed to conduct current in both directions, allowing a converter to operate in continuous
cnduction (CCM) mode, even under no load conditions, simplifying feedback loop compensation requirements.
During startup, internal circuitry modulates the switching of the synchronous rectifier to prevent discharging of the
output if a pre-biased condition exists.
Voltage Reference Input
An external voltage reference input is required. During operation, the voltage must be between 0.5v and 1.5v.
REFIN may be used in either of two ways:
•
•
As a reference input. In this case, REFIN must be stable before the TPS40042 is enabled. the internal
soft-start controls the rate of rise of the output voltage during startup. The time to reach output voltage
regulation is dependent on the voltage on the REFIN pin.
As a tracking input. If REFIN is held to zero until soft-start has completed (7.6-ms), then REFIN will control
the output voltage during startup and regulation.
Voltage Error Amplifier
The error amplifier has a bandwidth of greater than 5 MHz, and open loop gain of at least 55 dB. The output
voltage swing is limited to just above and below the oscillator ramp levels to improve transient response.
Loop Compensation
Voltage mode buck type converters are typically compensated using Type III networks. Please refer to the
Design Example for detailed methodology in designing feedback loops for voltage mode converters.
When designing the compensation for the feedback loop, remember that a low
impedance compensation network combined with a long network time constant
DESIGN
HINT:
can cause the short circuit threshold setting to not be as expected. The time
constant and impedance of the network connected from COMP to FB should be
as shown in Equation 1 to guarantee no interaction with the short circuit
threshold setting.
æ
ç
è
ö
t
-
÷
FB´CFB ø
0.4 V
R
´ e
< 10mA
R
FB
(1)
where
•
•
t is 1 ms, the sampling time of the short circuit threshold setting circuit
RFB and CFB are the values of the feedback components. e.g. R3 and C4 of the Design Example.
Oscillator
The oscillator frequency is internally fixed. The TPS40042 operating frequencies is nominally 600 kHz.
UVLO
When the input voltage is below the UVLO threshold, the TPS40042 turns off the internal oscillator and holds all
gate drive outputs in the low (OFF) state. When the input rises above the UVLO threshold, and the EN pin is
below the turn ON threshold, the start-up sequence is allowed to begin.
10
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
Enable and Start-Up Sequence
The EN pin of the TPS40042 is internally pulled to VDD. When power is applied to VDD, the EN pin is allowed to
float high, and the TPS40042 remains OFF. Only when the EN pin is externally pulled below the threshold
voltage of (VVDD - 1.2 V) is the TPS40042 allowed to start. When enabled, the TPS40042 enters a calibration
cycle where the short circuit current threshold is determined. The TPS40042 monitors the current out of the
COMP pin and selects a threshold based on the sensed value of the current. See Selecting the Short Circuit
Current Limit Threshold section for for details. When this calibration time is completed, the soft-start cycle is
allowed to begin. See Figure 15 below.
EN
COMP
V
OUT
Configure
Soft Start
ILIM
Threshold
1.6
6
T - Time - ms
Figure 15. Startup with VREFIN =1.5 V
DESIGN
HINT:
If the enable function is not used, the EN pin should be connected to ground
(GND).
DESIGN
HINT:
When designing the feedback loop compensation, ensure the capacitors used
are not so large that they distort the COMP pin calibration waveform.
Soft Start
At the end of a calibration cycle, the TPS40042 slowly increases the voltage to the non-inverting input of the
error amplifier. In this way, the output voltage slowly ramps up until the voltage on the non-inverting input to the
error amplifier reaches the external (VREFIN) reference voltage. At that time, the voltage at the non-inverting input
to the error amplifier remains at the applied reference voltage.
During the soft-start interval, pulse-by-pulse current limiting is active. If seven consecutive current limit pulses are
detected, overcurrent is declared and a timeout period equivalent to seven calibration/soft-start cycles goes into
effect. See Output Short Circuit Protection section for details.
Since the rate of rise of the output voltage is constant with different REFIN voltage levels, the actual soft start
time is directly proportional to the value of the external reference voltage. The rate of rise at the non-inverting
input of the error amplifier is 0.25 V/ms. The rate of rise measured at the output terminals of the DC/DC
converter will be increased by the output voltage-to-reference voltage ratio.
æ V
ö
÷
ø
REFIN
t
=
´ 6.0ms
ç
SS
1.5V
è
(2)
For example, if a 1-V external reference is applied for a 1.5-V output DC/DC converter, the soft-start
time-to-output voltage regulation is 4 ms.
Copyright © 2007, Texas Instruments Incorporated
11
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
Pre-Bias Startup
The TPS40042 supports pre-biased output voltage applications. In cases where the output voltage is held up by
external means while the TPS40042 is off, full synchronous rectification is disabled during the initial phase of soft
starting the output voltage. When the first PWM pulses are detected during soft start, the controller slowly
initiates synshronous rectification by starting the synchronous rectifier with a narrow on time. It then increments
that on time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle
of the converter. This approach prevents the sinking of current from a pre-biased output, and ensures the output
voltage startup and ramp to regulation is smooth and controlled.
NOTE:
If the output is pre-biased, PWM pulses start when the internal soft-start voltage rises
above the error amplifier input (FB pin).
Figure 16 below depicts the waveform of the HDRV and LDRV output signals at the beginning PWM pulses.
When HDRV turns off, diode rectification is enabled. Before the next PWM cycle starts, LDRV is turned on for a
short pulse. With every clock cycle, the leading edge of LDRV is modulated, increasing the on time of the
synchronous rectifier. Eventually, the leading edge of LDRV coincides with the falling edge of HDRV to achieve
full synchronous rectification. During normal operation of the converter, the TPS40042 operates in full two
quadrant source/sink mode.
Figure 17 shows the startup waveform of a 1.2-V output converter under three different pre-biased output
conditions. The lowest trace is when there is no pre-bias on the output. The center and top most traces indicate
converter startup with 0.5-V and 1.0-V pre-bias conditions.
V
V
= 5 V
IN
= 1.2 V
OUT
(200 mV/div)
PREBIAS = 1 V
V
HDRV
PREBIAS = 0.5 V
PREBIAS = 0 V
V
LDRV
t − Time − 2 µs/div
Figure 16. MOSFET Drivers at Beginning of Soft Start
t − Time − 500 µs/div
Figure 17. Startup Waveforms; VREFIN = 0.6 V
The recommended output voltage pre-bias range is less than or equal to 90% of the final regulation voltage. A
pre-biased output voltage of 90% to 100% of final regulation could lead to the sinking of current from the pre-bias
source. If the pre-biased voltage is greater than the designed converter output regulation voltage, then upon the
completion of the soft-start interval, the TPS40042 turns ON the Synchronous Rectifier, therby drawing current
from the output to bring the output voltage into regulation. Note that this may cause some undershoot of the
output voltage before entering regulation.
Output Short Circuit Protection
To minimize circuit losses, the TPS40042 uses the RDS(on) of the upper MOSFET switch as the current sensing
element. The current limit comparator, initially blanked during the first portion of each switching cycle, senses the
voltage across the high-side MOSFET when it is fully ON. This voltage is compared to an internally selected
short circuit current (SCC) limit threshold voltage. If the comparator senses a voltage drop across the high-side
MOSFET greater than the SCC limit threshold, it outputs an OC pulse. This terminates the current PWM pulse
12
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
preventing further current ramp-up, and sets the fault counter to count up one count on the next clock cycle.
Similarly, if no OC pulse is detected, the fault counter decrements by one count. If seven OC pulses are
summed, a fault condition is declared and the upper switch of the PWM output of the chip is immediately
disabled (turned OFF) and remains that way until the fault time-out period has elapsed. Both HDRV and LDRV
drivers are kept OFF during the fault time-out.
The fault time-out period is determined by cycling through seven internal soft-start time periods. At the end of the
fault time-out period, startup is attempted again.
The main purpose is for hard fault protection of the power switches. The internal SCC voltage has a positive
temperature coefficient designed to improve the short circuit threshold tolerance variation with temperature.
However, given the tolerance of the voltage thresholds and the RDS(on) range for a MOSFET, it is possible to
apply a load that thermally damages the external MOSFETs.
Selecting the Short Circuit Current Limit Threshold
The TPS40042 uses one of three user selectable voltage thresholds. During the calibration interval at power on
or enable (Figure 15), the TPS40042 monitors the current out of the COMP pin and selects a threshold based on
the sensed value. If the current is zero; that is, no resistor is connected between COMP and GND, then the
threshold voltage level is 180 mV. If a 2.4-kΩ resistor is connected between COMP and GND, then the threshold
voltage level is 105 mV. If a 12-kΩ resistor is connected between COMP and GND, then the threshold voltage is
310 mV.
Once calibration is complete, the selected SCP threshold level is latched into place and remains constant. In
addition, the sensing circuits on COMP pin during calibration are disconnected from the COMP pin, and soft start
is allowed to begin.
Synchronous Rectification and Gate Drive
In a buck converter, when the upper switch MOSFET turns off, current is flowing in the inductor to the load. This
current cannot be stopped immediately without using infinite voltage. To give this current a path to flow and
maintain voltage levels at a safe level, a rectifier or catch device is used. This device can be either a diode, or it
can be a controlled active device. The TPS40042 provides a signal to drive an N-channel MOSFET as a
synchronous rectifier (SR). This control signal is carefully coordinated with the drive signal for the main switch so
that there is minimum dead time from the time that the SR turns OFF and the upper switch MOSFET turns ON,
and minimum delay from when the upper switch MOSFET turns OFF and the SR turns ON.
NOTE:
The longer the time spent in diode conduction during the rectifier conduction period,
the lower the converter efficiency.
The drivers for the external HDRV and LDRV MOSFETs are capable of driving a gate to source voltage of
approximately 5 V. At VDD = 5 V, the drivers are capable of driving MOSFETs appropriate for a 15-A converter.
The LDRV driver switches between VDD and ground, while HDRV driver is referenced to SW and switches
between BOOT and SW. The drivers have non-overlapping timing that is governed by an adaptive delay circuit
that minimizes body diode conduction in the synchronous rectifier.
Gate Drive Resistors
The TPS40042’s adaptive gate delay circuitry monitors the HDRV-to-SW and LDRV-to-GND voltages to
determine the state of the external MOSFET switches. Any voltage drop across an external series gate drive
resistor is sensed as reduced gate voltage during turn-off and may interfere with the MOSFET timing.
DESIGN
HINT:
A resistor should never be placed in series with the synchronous rectifiers gate
and the gate trace should be kept as short as practical in the layout.
Copyright © 2007, Texas Instruments Incorporated
13
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
Total Gate Charge
The internal voltage sensing of the external MOSFET gate voltages used by the TPS40042 to control the
dead-times between turn-off and turn-on can be sensitive to large MOSFET gate charges, especially when
different gate charges are used for the high-side and low-side MOSFETs. Increased gate charge increases
MOSFET switching times and decreases the dead-time between the MOSFETs switching.
MOSFETs with no more than 40 nC of total gate charge should be selected.
DESIGN
HINT:
The upper switch MOSFET’s gate charge should be no less than 60% of the
synchronous rectifier’s gate charge to minimize the turn-on/turn-off delay
mismatch between the high-side and low-side MOSFET.
Synchronous Rectifier dV/dt Turn-On
As the upper switch MOSFET turns on, the switch node voltage rises from close to ground to VIN in a very short
period of time (typically 10 ns to 30 ns) resulting in very high voltage spikes on the switch node. The construction
of a MOSFET creates parasitic capacitances between its terminals, particularly the gate-to-drain and
gate-to-source, creating a capacitive divider between the drain and source of the MOSFET with the gate at its
mid-point. If the gate-to-drain charge (QGD) is larger than the gate-to-source charge (QGS), the capacitive divider
places proportionally more charge on the gate of the MOSFET as the switch node voltage rises than is shunted
to GND. In extreme cases, this can cause the synchronous rectifier gate voltage to rise above the turn on
threshold voltage of the MOSFET and causes cross-conduction. This is called dV/dt turn-on. It increases power
dissipation in both the high-side and the low-side MOSFET, reducing efficiency.
Select a synchronous rectifier MOSFET with a QGD to QGS ratio of less than
one and provide a wide, low resistance, low inductance loop in the synchronous
rectifier gate drive circuit. (See Layout Consideration)
DESIGN
HINT:
A resistor in series with the boost capacitor slows the turn on of the high-side
MOSFET, and reduces the dV/dt of the switch node. See Boost Capacitor
Series Resistor section.
DESIGN
HINT:
Bootstrap for N-Channel MOSFET Drive
The PWM duty cycle is limited to a maximum of 95%, allowing the bootstrap capacitor to charge during every
cycle. During each PWM OFF period, the voltage on VDD charges the bootstrap capacitor. When the PWM
switch is next commanded to turn ON, the voltage used to drive the MOSFET is derived from the voltage on this
capacitor. Since this is a charge transfer circuit, the value of the bootstrap capacitor must be sized such that the
energy stored in the capacitor on a per cycle basis is greater then the gate charge requirement of the MOSFET
being used. See the Design Example section for details.
Bootstrap Capacitor Series Resistor
Since resistors should not be placed in series with the high-side gate, it may be necessary to place a small 1-Ω
to 3-Ω resistor in series with the bootstrap capacitor to control the turn-on of the main switching MOSFET and
reduce the dV/dt rate of rise of the switch node voltage. A resistor placed between the BOOT pin and the
bootstrap capacitor increases the series resistance during the turn-on of the high-side MOSFET, and has no
effect during the high-side MOSFET’s turn-off period. This prevents the TPS40042 from sensing the upper switch
MOSFET’s turn-off too early and reducing the upper switch MOSFET turn-off to the SR MOSFET turn-on delay
timing too far.
DESIGN
HINT:
To reduce EMI, place a small 1-Ω to 3-Ω resistor in series with the boost
capacitor to control the turn-on of the main switching FET.
External Schottky Diode for Low Input Voltage
The TPS40042 uses an internal P-channel MOSFET switch between VDD and BOOT to charge the bootstrap
capacitor during synchronous rectifier conduction time. At low input voltages, a MOSFET can not be turned on
14
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
hard enough to rapidly replenish the charge required to turn on an (high gate charge) external high-side
MOSFET. For this situation, an external Schottky diode between the VDD and BOOT pins may be added. While
the diode carries very small average current (QG x FSW) it may be required to carry several hundred mA of peak
surge current. The diode should be rated for at least 500 mA of surge current. For higher input voltage
applications, if a resistor is used in series with the boost capacitor, connect the diode to the junction of the
resistor and capacitor to remove the added resistance from the capacitor’s charge path.
For low input voltages, and a high gate charge upper switch MOSFET, a small
Schottky diode should be placed from VDD to BOOT. Do not use a resistor in
series with the boost capacitor.
DESIGN
HINT:
VDD Bypass and Filtering
To prevent switching noise from being injected into the TPS40042 control circuitry, a ceramic capacitor (1 µF
minimum) must be placed as close to the VDD pin and GND pad as possible.
VDD Filter Resistor
To further limit the noise on VDD, a small 1-Ω to 2-Ω resistor may be placed between the input voltage and the
VDD pin to create a small filter to VDD. The resistor should connect near the drain of the upper switch MOSFET
to prevent trace IR drops from increasing the sensed voltage drop. The resistor itself should be placed close to
Pin 5.
The current through the resistor includes the device's no-load switching current of 2 mA plus gate switching
current. The voltage drop induced across this resistor reduces the VDD-to-SW voltage sensed by the over
current protection circuitry within the device. This results with the apparent voltage drop across the upper switch
MOSFET being increased, thereby decreasing the current at which protection will occur. To minimize this effect,
the resistor value should be selected to yield less than a 25-mV drop.
Thermal Shutdown
If the junction temperature of the device reaches the thermal shutdown level, the PWM and the oscillator are
turned off and HDRV and LDRV are driven off. When the junction cools to the required level, the PWM soft starts
as during a normal power-up cycle.
Package Power Dissipation
The power dissipation in a controller is largely dependent on the MOSFET driver currents and the input voltage.
The driver current is proportional to the total gate charge, Qg, of the external MOSFETs, and the operating
frequency of the converter. The total power dissipation is:
P = V ´ Iq + f
´ Q
(
+ Q
)
)
(
T
DD
SW
SW SR
(3)
where
•
•
•
IQ is the quiescent operating current (neglecting drivers)
QgSWis the total gate charges of the upper switch MOSFET
QgSR is the total gate charges of the synchronous rectifier MOSFET
The maximum power capability of the PowerPad™ package is dependent on the layout as well as air flow. The
thermal impedance from junction-to-air assuming 2-oz. copper trace and thermal pad with solder and no air flow
is detailed in Reference [5]
.
Copyright © 2007, Texas Instruments Incorporated
15
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
PCB Layout Guidelines
A synchronous BUCK power stage has two primary current loops, the input current loop that carries high ac
discontinuous current and an output current loop that carries high dc continuous current. The output current loop
carries low ac inductor ripple current.
VIN
VDD Filter
(Optional)
Main
Gate
Drive
TPS40042
Input
Current
Loop
Reference
Input
REFIN
HDRV
SW
VOUT
EN
EN
Enable Bypass
(Optional)
FB
BOOT
LDRV
GND
BOOST Resistor
(Optional)
Output
Current
Loop
COMP
VDD
Bypass
SR Gate
Drive
VDD
PPAD
Current
Limit Set
Resistor
SignalGround
PowerGround LocateComponentsOverPowerGround
UDG-07140
LocateComponents OverSignalGroundIsland
Figure 18. Synchronous BUCK Power Stage
Power Component Routing
As shown in Figure 18, the input current loop contains the input capacitors, the switching MOSFET, the inductor,
the output capacitors, and the ground path back to the input capacitors. To keep this loop as small as possible, it
is good practice to place some ceramic capacitance directly between the drain of the main switching MOSFET
and the source of the synchronous rectifier (SR) through a power ground plane directly under the MOSFETs.
The output current loop includes the filter inductor, the output capacitors, and the ground return between the
output capacitors and the source of the synchronous rectifier MOSFET. As with the input current loop, the ground
return between the output capacitor ground and the source of the SR source should be routed under the inductor
and MOSFETs to minimize the power loop area.
Device to Power Stage Interface
The TPS40042 uses a very fast break-before-make anti-cross conduction circuit to minimize power loss. Adding
external impedance in series with the gates of the switching MOSFETs adversely affects the converter’s
operation and must be avoided. The loop impedance (HDRV-to-gate plus source-to-SW and LDRV-to-SR gate
plus SR source-to-GND) should be kept to less than 20 nH to avoid possible cross-conduction. The HDRV and
LDRV connections should widen to 20 mils as soon as possible out from the device pin.
The return for the main switching MOSFET gate drive is the SW pin of the TPS40042. The SW pin should be
routed to the source of the main switching FET with at least a 20-mils wide trace as close to the HDRV trace as
possible to minimize loop impedance.
The return for the SR MOSFET gate drive is the TPS40042 GND pad. The GND pad should be connected
directly to the source of the SR with at least a 20-mil wide trace directly under the LDRV trace. Use a minimum of
2 parallel vias to connect the GND pad to the source of the SR if multiple layers are used.
16
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
A small, less than 3-Ω resistor may be added in series with the BOOT pin to slow the turn-on of the upper switch
MOSFET, thereby reducing the rising edge slew-rate of the switch node. In turn, this reduces EMI, increases
upper MOSFET OFF to SR ON dead time, and minimizes induced dV/dt turn-on of the SR when the upper switch
MOSFET turns on. It is recommended customers make provisions on their boards for this resistor and not use
resistors in series with MOSFET gate leads.
VDD Filtering
A ceramic capacitor, 1 µF minimum, must be placed as close to the VDD pin and GND pad as possible with a
15-mil wide (or greater) trace. If used, a small series connected resistor (1 Ω to 2 Ω) may be placed less than
100 mils from the TPS40042 between the supply input voltage and the VDD pin to further reduce switching noise
on the VDD pin.
NOTE:
The voltage drop across this resistor affects the level at which the over-current circuit
operates by filtering the sensed VDD voltage.
Device Connections
If a current limit resistor is used (COMP to GND), it must be placed within 100 mils of the COMP pin to limit noise
injection into the PWM comparator. Compensation components (feedback divider, and associated error amplifier
components) should be placed over a signal ground island connected to the power ground at the GND pad
through a 10-mil wide trace. If multiple layers are used, connect to GND through a single via on an internal layer
opposite the connection to the source of the synchronous rectifier.
PowerPAD™ Layout
The PowerPAD™ package provides low thermal impedance for heat removal from the device. The PowerPAD™
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit
board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend
on the size of the PowerPAD™ package. See PCB Layout Guidelines for further information.
Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned
area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is
plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a
diameter equal to the via diameter plus 0.1 mm minimum. This capping prevents the solder from being wicked
through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD™
Thermally Enhanced Package[2] for more information on the PowerPAD™ package.
Copyright © 2007, Texas Instruments Incorporated
17
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
DESIGN EXAMPLES
Example 1. A 5-V to 1.8-V DC-to-DC Converter Using a TPS40042
The following example illustrates the design process and component selection for a 5-V to 0.9-V DDR
termination synchronous buck converter. The design goal parameters are given in the table below. A list of
symbol definitions is found at the end of this section.
Design Goal Parameters
SYMBOL
VIN
PARAMETER
Input voltage
TEST CONDITION
MIN
TYP
MAX
UNIT
V
4.5
5.5
75
VINripple
VOUT
Input ripple
IOUT = 6 A
mV
V
Output voltage
Line regulation
Load regulation
Output ripple
Transient deviation
Output current
Switching frequency
Size
IOUT = 0 A, VIN = 5 V
VIN = 4.5 A to 5.5 V
IOUT = 0 A to 6 A
0.9
0.5%
0.5%
VRIPPLE
VTRANS
IOUT
IOUT = 6 A
36
6
mV
IOUT = -2 A to 2 A, IOUT = 2 A to -2 A
VIN = 4.5 V to 5.5 V
40
-6
A
FSW
600
kHz
In2
1
For this example, the schematic shown in Figure 19 is used.
Figure 19. TPS40042 Sample Schematic
Inductor Selection
The inductor is typically sized for 30% peak-to-peak ripple current (IRIPPLE) Given this target ripple current, the
required inductor size is calculated by:
18
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
V
IN(max) * VOUT
0.3 IOUT
VOUT
1
VIN(max) FSW
L +
(4)
Solving with VIN(max) = 5.5 V, an inductor value of 0.69 µH is obtained. A standard value of 0.8 µH is selected,
resulting in 1.56-A peak-peak ripple. The RMS current through the inductor is approximated by the equation:
2
2
RIPPLEǓ + ǸI
2
2
1
12
1
12
Ǹ
ǒ
I
ǒ
OUTǓ
ǒ
I
RIPPLEǓ
ǒ
L(avg)Ǔ
I
+
I
)
)
L(rms)
(5)
Using Equation 5, the maximum RMS current in the inductor is about 6 A.
Output Capacitor Selection (C8 & C9)
The selection of the output capacitor is typically driven by the output load transient response requirement.
Equation 6 and Equation 7 estimate the output capacitance required for a given output voltage transient
deviation.
2
I
´ L
TRAN(max)
C
=
when V
< 2 ´ V
OUT(min)
IN(min) OUT
V
(
- V
´ V
)
´ 2
IN(min)
OUT
TRAN
(6)
(7)
ITRAN(max)2 ´L
COUT(min)
=
when V
> 2´ VOUT
IN(min)
VOUT ´ VTRAN ´ 2
For this example, Equation 7 is used in calculating the minimum output capacitance.
Based on a 4-A load transient with a maximum 40-mV deviation, a minimum of 177-µF output of capacitance is
required.
The output ripple is divided into two components. The first is the ripple voltage generated by inductor ripple
current flowing through the output capacitor's capacitance, and the second is the voltage generated by the ripple
current flowing in the output capacitor's ESR. The maximum allowable ESR is then determined by the maximum
ripple voltage and is approximated by:
I
* ǒ Ǔ
RIPPLE
V
RIPPLE(total)
C
F
SW
V
* V
RIPPLE(cap)
OUT
RIPPLE(total)
ESR
+
+
MAX
I
I
RIPPLE
RIPPLE
(8)
Based on 177 µF of capacitance, 1.56-A ripple current, 600-kHz switching frequency and a design goal of 36-mV
ripple voltage, we calculate a maximum ESR of 13.6 mΩ. Two 1206, 100-µF, 6.3-V, X5R ceramic capacitors are
selected to provide significantly less than 13.6 mΩ of ESR.
Peak Current Rating of Inductor
With output capacitance known, it is now possible to calculate the charging current during start-up and determine
the minimum saturation current rating for the inductor. The start-up charging current is approximated by:
VOUT COUT
ICHARGE
+
TSS
(9)
Using the TPS40042’s soft-start time of 5-ms, COUT = 200 µF and VOUT = 0.9 V, ICHARGE is found to be 40 mA.
The peak current rating of the inductor is now found by:
1 ǒ
Ǔ
L
L(peak) + IOUT(max)
)
IRIPPLE ) ICHARGE
2
(10)
The inductor requirements are summarized in the table below.
Copyright © 2007, Texas Instruments Incorporated
19
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
Inductor Requirements
PARAMETER
SYMBOL
L
VALUE
0.8
UNITS
µH
Inductance
RMS current (thermal rating)
Peak current (saturation rating)
IL(rms)
IL(peak)
6.0
A
7.08
A PG0083.801, 0.8 µH is selected for its small size, low DCR and high current handling capability.
Input Capacitor Selection (C1 & C2)
The input voltage ripple is divided between capacitance and ESR. For this design, VRIPPLE(CAP) = 50 mV and
VRIPPLE(ESR) = 25 mV. The minimum capacitance and maximum ESR are estimated by:
ILOAD VOUT
VRIPPLE(cap) VIN FSW
CIN(min)
+
(11)
(12)
VRIPPLE(ESR)
ESRMAX
+
1 ǒ
2
Ǔ
ILOAD
)
IRIPPLE
For this design, CIN > 60 µF and ESR < 3.5 mΩ. The RMS current in the input capacitors is estimated by:
2
2
ƫ
VOUT VOUT IOUT
1
12
ǒ
OUTǓ
ǒ
Ǔ
ƪI
I
RMS(cin) + IIN(rms) * IIN(avg)
+
)
IRIPPLE
*
Ǹ
VIN
VIN
(13)
With VIN = VIN(max), the input capacitors must support a ripple current of 1.56 ARMS. Two 1206, 100-µF, X5R
ceramic capacitors with about 2-mΩ ESR and a 2-A RMS current rating are selected. It is important to check the
dc bias voltage derating curves to ensure the capacitors provide sufficient capacitance at the working voltage.
MOSFET Switch Selection (Q1 & Q2)
The switching losses for the upper switch MOSFET are estimated by:
Q
) Q
*V
GS2_Q1
GD_Q1
1
2
ǒ
Ǔ
P
+
V I
T
) T
F
+ V I
F
SW
G1SW
IN
OUT
RISE
FALL
SW
IN
OUT
V
DD
TH
R
DRIVE
(14)
For this design, switching losses are higher at low input voltage due to the lower gate drive current. Designing for
1 W of total losses in both MOSFETS and 20% of the total MOSFET losses in switching losses, we can estimate
our maximum gate-to-drain charge for the design at:
P
V
* V
t
G1SW
DD
1
Q
) Q
t
GS2_Q1
GD_Q1
V
I
R
F
IN
OUT
DRIVE
SW
(15)
For a low-gate threshold MOSFET, and the TPS40042’s 5 Ω and 3 Ω drive resistances, we estimate a maximum
QGS2+QGD of 10.8 nC.
The conduction losses in the upper switch MOSFET are estimated by the RMS current through the MOSFET
times its RDS(on)
:
2
2
V
2
OUT
1
12
ǒ
ƪI
OUTǓ
ǒ
I
Ǔ
ƫ
R
P
+ D
)
+
I
R
L(rms) DS(on_Q1)
CON_Q1
RIPPLE
DS(on)
V
IN
(16)
Estimating about 30% of total MOSFET losses to be high-side conduction losses, the maximum RDS(on) of the
high-side MOSFET can be estimated by:
PCON_Q1
RDS(on_Q1)
+
VOUT
VIN
2
IL(rms)
(17)
For this design, with IL_RMS = 6 ARMS and 4.5 V to 0.9 V, RDS(on_Q1) is < 39 mΩ for the upper switch MOSFET.
20
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
Estimating 50% of total MOSFET losses are in the SR as conduction losses, repeat equation 14. Then calculate
the maximum RDS(on) of the SR by the equation:
PCON_Q2
RDS(on_Q2)
+
VOUT
VIN
2
ǒ1 * Ǔ
IL(rms)
(18)
For this design IL_RMS = 6 A at 5.5 V to 0.9 V RDS(on_Q2) < 15.9 mΩ. The table below summarizes the MOSFET
requirements.
MOSFET Requirements
PARAMETER
SYMBOL
RDS(on_Q1)
QGS2_Q1 +QGD_Q1
RDS(on_Q2)
VALUE
UNITS
mΩ
High-side FET RDS(on)
39
High-side FET turn-on charge
Low-side FET RDS(on)
10.8
15.9
nC
mΩ
IRF7910 has an RDSON(max) of 15 mΩ at 4.5-V gate drive,QGD of 6.2 nC, and QGS2 of 2 nC.
Bootstrap Capacitor (C7)
To ensure proper charging of the upper switch MOSFET gate, limit the ripple voltage on the bootstrap capacitor
to < 5% of the minimum gate drive voltage of 3.0 V.
20 QGS_Q1
CBOOST
+
VIN(min)
(19)
Based on the IRF7910 MOSFET with a maximum total gate charge of 26 nC, calculate a minimum of 116 nF of
capacitance. The next higher standard value of 220 nF is selected.
VDD Bypass Capacitor (C6)
Select a 1.0-µF ceramic bypass capacitor for VDD.
VDD Filter Resistor (R7)
An optional resistor in series with VDD helps filter switching noise from the device. Driving the two IRF7910
MOSFETs, with a typical total QG of 17 nC each, we calculate a maximum IDD current of 22 mA. The result of
equation 19, leads to selecting a 1-Ω resistor, and limits the voltage drop across this resistor to less than 25 mV.
VRVDD(max)
25 mV
R
VDD t
+
IDD
2 mA ) ǒQ
Ǔ
G_Q1 ) QG_Q2 FSW
(20)
Short Circuit Protection (R2)
The TPS40042 use the forward drop across the upper switch MOSFET during the ON time to measure the
inductor current. The voltage drop across the high-side MOSFET is given by:
V
+ I
R
L(peak) DS(on_Q1)
CS
(21)
When VIN = 4.5 V to 5.5 V, IL_PEAK = 7.2A. Using the IRF7910 MOSFET, we calculate the peak voltage drop to
be 108 mV. The TPS40042’s internal 3100-ppm temperature coefficient helps compensate for the MOSFET’s
RDS(on) temperature coefficient. For this design, select the short circuit protection voltage threshold of 180 mV by
selecting R2 = OPEN.
REFIN Divider Resistors
In DDR2 applications, VTT=1/2 VDDQ. A 2:1 resistor divider with R11=R12 =100-kΩ provides VREFIN. If a buffer
is to be used to provide VTT_REF, the output of the buffer should be tied to VREFIN on the TPS40042 to minimize
offset from VTT_REF to VTT.
Copyright © 2007, Texas Instruments Incorporated
21
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
REFIN Bypass Capacitor
A capacitor from VTT_REF to GND removes VDDQ noise from the REFIN input. The capacitor is selected by
Equation 22.
æ
ç
ç
ç
ç
ç
è
ö
÷
÷
÷
÷
÷
ø
æ
ç
è
ö
÷
ø
1
1
æ
ö
æ
ö
+
ç
÷
ç
÷
R11
R12
è
ø
è
ø
C11=
2p´BWREFIN
(22)
For a bandwidth of BWREFIN = 30 kHz, C11 calculates to 106 pF, a 100-pF ceramic capacitor is used.
Feedback Loop Design
To design feedback circuit, a small signal average modeling technique is employed. Further information on this
technique may be found in the references.
Modeling the Power Stage
The peak-to-peak ramp voltage given in the Electrical Specification table allows the modulator gain to be
calculated as:
VIN
VRAMP(p*p)
AMOD
+
(23)
For this design, a modulator gain of 7.3 (17.3 dB) is calculated.
The LC filter applies a double pole at the resonance frequency:
1
F
+
RES
Ǹ
2 p L C
(24)
For this design, the resonance frequency is about 11.3 kHz. Below this frequency, the power stage has the dc
gain of 17.3 dB and above this frequency the power stage gain drops off at -40 dB per decade. The ESR zero is
approximated by:
1
FESR
+
2 p COUT RESR
(25)
For COUT = 2 x 100 µF and RESR = 2.5 mΩ FESR = 318 kHz. This is greater than 1/5th the switching frequency
and outside the scope of the error amplifier design. The gain of the power stage would change to -20 dB per
decade above FESR. The straight line approximation the power stage gain is approximated in Figure 20.
F
RES
A
−40dB/dec
−20dB/dec
MOD
0dB
F
ESR
Frequency (Log Scale)
Figure 20. Power Stage Frequency Response Straight Line Approximation
22
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
Feedback Divider
Select R8 be between 10 kΩ and 100 kΩ. For this design, select 20 kΩ. While no feedback divider is needed for
the VTT tracking output ( VOUT = VREFIN) , R8 is necessary to provide input impedance to the error amplifier.
Error Amplifier Pole-Zero Selection
Place two zeros at about 80% of the resonance frequency to keep the actual resonance frequency above the two
zeros over the L and C tolerance. For FRES = 11.3 kHz, FZ1 = 9.0 kHz and FZ2 = 7 kHz. Selecting the cross-over
frequency (FCO) of the control loop between 3 times the LC filter resonance and 1/5th the switching frequency.
For most applications 1/10th the switching frequency provides a good balance between ease of design and fast
transient response.
If FESR < FCO; FP1 = (1/2) FCO and FP2 = 2x FCO
If FESR > 2x FCO; FP1 = FCO and FP2 = 4x FCO
For this design with FSW = 600 kHz, FRES = 11.3 kHz and FESR = 318 kHz.
FCO = 60 kHz and since FESR > 2x FCO, FP1 = FCO and FP2 = 4x FCO
.
.
.
Since FCO < FESR the power stage gain at the desired cross-over can be approximated by:
FCO
ǒ Ǔ
PS(fcc) + AMOD * 40 LOG
A
FRES
APS(FCO) = -11.7 dB, so the error amplifier gain between the two poles should be 10(11.7/20) = 3.84.
(26)
If the error amplifier gain is greater than 0 dB at FSW, the converter can achieve a stable bi-modal operation with
duty cycles alternating between two stable values, and the output regulated with a output ripple component at
(1/2) FSW. To prevent this effect, check FP2 by the equation:
F
SW
F
+
P2(max)
A
MID(band)
(27)
Since FP2 > FP2(max), it is possible for this control loop to obtain bi-modal operation. To prevent this bi-modal
operation, reduce FCO and re-calculate APC(FCO), FP1, and FP2(max)
.
Now, FCO = 40 kHz, AMID-BAND = 1.48, FP1 = 25 kHz and FP2 = 100 kHz.
The table below summarizes the error amplifier compensation network design criteria.
Error Amplifier Compensation Network
PARAMETER
SYMBOL
FZ1
VALUE
9
UNITS
First zero frequency
Second zero frequency
First pole frequency
Second pole frequency
Mid-band gain
kHz
FZ2
9
FP1
25
FP2
100
1.48
AMID-BAND
V/V
Feedback Components (R3, R6, C3, C4, C5)
Approximate C5 with the formula:
1
C5 +
2 p R8 FZ2
(28)
C5 = 1000 pF (closest standard capacitor value greater than the calculated 884 pF) and approximate R6 with the
formula:
1
R6 +
2 p C5 FP1
(29)
R6 = 6.34 kΩ (closest standard resistor value to calculated 6.37 kΩ) Calculate R3 by the formula:
Copyright © 2007, Texas Instruments Incorporated
23
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
( )
R6 R8
A
MID(band)
R3 +
R6 ) R8
(30)
With AMID_BAND = 1.48, R6 = 6.34 kΩ and R8 = 20 kΩ, R3 = 7.15 kΩ (closest standard resistor value to calculated
7.12 kΩ) Calculate C3 and C4 by the equations:
1
C4 +
2 p R3 FZ1
(31)
1
C3 +
2 p R3 F
P2
(32)
For R3 = 7.15 kΩ, C3 = 220 pF (closest standard value to 222 pF) C4 = 2200 pF (closest standard value to 2473
pF)
Error Amplifier straight line approximation transfer function looks like Figure 21.
F
F
P2
P1
A
mid−Band
0dB
F
F
F
Z2
SW
Z1
Frequency (Log Scale)
Figure 21. Error Amplifier Frequency Response Straight Line Approximation
POWER LOSS
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
90
80
70
60
50
40
30
20
10
0
V
= 4.5 V
VDD
V
= 5.0 V
VDD
V
= 5.5 V
VDD
V
= 5.5 V
VDD
V
= 5.0 V
VDD
V
(V)
V
(V)
VDD
VDD
4.5
4.5
5.0
5.5
5.0
5.5
V
= 4.5 V
VDD
-10
-6
-4
-2
0
2
4
6
-6
-4
-2
0
2
4
6
I
- Load Current - A
I
- Load Current - A
LOAD
LOAD
Figure 22.
Figure 23.
24
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
OUTPUT VOLTAGE
vs
LOAD CURRENT
0.925
0.920
V
OUT(max)
V
= 5.0 V
VDD
0.915
0.910
V
(V)
VDD
4.5
V
= 4.5 V
5.0
5.5
VDD
0.905
0.900
0.895
V
= 5.5 V
VDD
0.890
0.885
V
OUT(min)
0.880
-6
-4
-2
0
2
4
6
I
- Load Current - A
LOAD
Figure 24.
Copyright © 2007, Texas Instruments Incorporated
25
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
List of Materials
REF
C1
QTY
2
DESCRIPTION
MFR
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
Pulse
IR
PART NUMBER
C325X5R0J107M
C1005C01H221M
C1005X7R1H222M
C1005X7R1H102M
C1005X7R0J105M
C1005X7R0J224M
C3225X5R0J107M
C1005X7R0J105M
C1005C01H101M
PG0083.801
IRF7910
Capacitor, ceramic, 6.3 V, X5R, 20%, 100 µF, 1210
Capacitor, ceramic, 50 V, X7R, 20%, 220pF, 0402
Capacitor, ceramic, 50 V, X7R, 20%, 2200 pF, 0402
Capacitor, ceramic, 50 V, X7R, 20%, 1000 pF, 0402
Capacitor, ceramic, 6.3 V, X5R, 20%, 1.0 µF, 0402
Capacitor, ceramic, 6.3 V, X5R, 20%, 0.22 µF, 0402
Capacitor, ceramic, 6.3 V, X5R, 20%, 100 µF, 1210
Capacitor, ceramic, 6.3 V, X5R, 20%, 1.0 µF, 0402
Capacitor, ceramic, 50 V, X7R, 20%, 100pF, 0402
Inductor, SMT, 0.8 µH, 12 A, 6.6 mΩ, ED1514, 0.268 x 0.268
MOSFET, dual N-channel, 20 V, 6.6 A, 29 mΩ, 1.0 µH, SO8
Resistor, chip, 1/16 W, 1%, 7.15 kΩ, 0402
C3
1
C4
1
C5
1
C6
1
C7
1
C8
2
C10
C11
L1
1
1
1
Q2
R3
1
1
Std
Std
R6
1
Resistor, chip, k 1/1 W, 1%, 6.34 kΩ, 0402
Std
Std
R7
1
Resistor, chip, k, 1/16 W, 1%, 1.0 Ω, 0402
Std
Std
R8
1
Resistor, chip, k 1/16 W, 1%, 20 kΩ, 0402
Std
Std
R11
R12
1
Resistor, chip, 100 kΩ, 1/16 W, 1%, 100 kΩ, 0402
Resistor, chip, 100 kΩ, 1/16 W, 1%, 100 kΩ, 0402
Std
Std
1
Std
Std
Device, Low Voltage DC to DC Synchronous Buck Controller,
TPS40042DRC, SON-10P
U1
1
TPS40042DRC
TI
Active High Enable Circuit
R1
Q1
1
1
Resistor, chip, 100 kΩ, 1/16 W, 1%, 100 kΩ, 0402
Std
Std
Mosfet, N-channel, VDS 60 V, RDS 2 Ω, ID 115 mA,
2N7002W, SOT-323 (SC-70)
Diodes Inc
2N7002W-7
26
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
Definition of Symbols
SYMBOL
DESCRIPTION
VIN(max)
Maximum operating input voltage
VIN(min)
VINRIPPLE
VOUT
Minimum operating input voltage
Peak-to-peak ac ripple voltage on VIN
Target output voltage
VOUTRIPPLE
IOUT(max)
IRIPPLE
IL_PEAK
IL_RMS
IRMS_CIN
FSW
Peak-to-peak ac ripple voltage on VOUT
Maximum operating load current
Peak-to-peak ripple current through the output filter inductor
Peak ripple current through the output filter inductor
Root mean squared current through the output filter inductor
Root mean squared current in input capacitor
Switching frequency
FCO
Desired control loop cross-over frequency
AMOD
Low frequency gain of the pulse width modulator
VCONTROL
FRES
PWM control voltage (error amplifier output voltage - VCOMP
L-C filter resonant frequency
)
FESR
Output capacitors’ ESR zero frequency
FP1
First pole frequency in error amplifier compensation
Second pole frequency in error amplifier compensation
First zero frequency in error amplifier compensation
Second pole frequency in error amplifier compensation
Total gate charge of upper switch MOSFET
FP2
FZ1
FZ2
QG1_Q1
QG2_Q2
RDS(on_Q1)
RDS(on_Q2)
PCON_Q1
PSW_Q1
PCON_Q2
QGD_Q1
Total gate charge of synchronous rectifier MOSFET
“ON” drain-to-source resistance of upper switch MOSFET
“ON” drain-to-source resistance of synchronous rectifier MOSEFT
Conduction losses in upper switch MOSFET
Switching losses in upper switch MOSFET
Conduction losses in synchronous rectifier MOSFET
Gate-to-drain charge of upper switch MOSFET
Post threshold gate-to-source charge of the upper switch MOSFET. (Estimate from QG vs. VGS if not provided in
MOSFET data sheet)
QGS2_Q1
VFB
Internal reference voltage as measured on FB pin.
Slope of internal PWM ramp
VRAMP_slope
APS(Fco)
AMID-BAND
BWREFIN
VCOMP to VOUT gain at desired loop cross-over frequency. (dB)
VOUT to VCOMP gain at desired loop cross-over frequency (V/V)
Desired frequency bandwidth of the REFIN input.
Copyright © 2007, Texas Instruments Incorporated
27
Product Folder Link(s): TPS40042
TPS40042
www.ti.com
SLUS777–NOVEMBER 2007
ADDITIONAL REFERENCES
Related Parts
The following parts have characteristics similar to the TPS40042 and may be of interest.
Related Parts
DEVICE
DESCRIPTION
TPS40007/9
TPS40021
TPS40040/1
Low Voltage Synchronous Buck Controller with Predictive Gate Drive®
Full Featured Low Voltage Synchronous Buck Controller with Predictive Gate Drive®
Low Voltage Synchronous Buck Controller
References
These references may be found on the web at www.power.ti.com under Technical Documents. Many design
tools and links to additional references, including design software, may also be found at www.power.ti.com
1. Under The Hood Of Low Voltage DC/DC Converters, SEM1500 Topic 5, 2002 Seminar Series
2. Understanding Buck Power Stages in Switchmode Power Supplies, SLVA057, March 1999
3. Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar
Series
4. Designing Stable Control Loops, SEM 1400, 2001 Seminar Series
5. Additional PowerPADTM information may be found in Applications Briefs SLMA002 and SLMA004
6. QFN/SON PCB Attachment, Texas Instruments Literature Number SLUA271, June 2002
Package Outline and Recommended PCB Footprint
The following pages outline the mechanical dimensions of the DRC package and provide recommendations for
PCB layout footpring.
28
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2007
PACKAGING INFORMATION
Orderable Device
TPS40042DRCR
TPS40042DRCT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SON
DRC
10
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
DRC
10
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Dec-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
12
TPS40042DRCR
TPS40042DRCT
DRC
DRC
10
10
SITE 41
SITE 41
3.3
3.3
3.3
3.3
1.1
1.1
8
8
12
12
Q2
Q2
180
12
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Dec-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TPS40042DRCR
TPS40042DRCT
DRC
DRC
10
10
SITE 41
SITE 41
346.0
190.0
346.0
212.7
29.0
31.75
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties
may be subject to additional restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
相关型号：
TPS40042DRCTG4
LOW PIN COUNT, LOW VIN (3.0 V TO 5.5 V) SYNCHRONOUS BUCK DC-TO-DC CONTROLLER WITH EXTERNAL REFERENCE INPUTWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS40042_16
LOW PIN COUNT, LOW VIN (3.0 V TO 5.5 V) SYNCHRONOUS BUCK DC-TO-DC CONTROLLER WITH EXTERNAL REFERENCE INPUTWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS40050
WIDE-INPUT SYNCHRONOUS BUCK CONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS40050-Q1
WIDE-INPUT SYNCHRONOUS BUCK CONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS40050PWP
WIDE-INPUT SYNCHRONOUS BUCK CONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS40050PWPR
暂无描述Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS40050PWPRG4
Wide Input Voltage Synchronous Buck Controller 16-HTSSOP -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS40050QPWPRQ1
汽车类 8V 至 40V 同步降压控制器 | PWP | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS40051
Based Design Converts 12-V Bus to 1.8 V at 15 A (SLUP195)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS40051-Q1
WIDE-INPUT SYNCHRONOUS BUCK CONTROLLERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明