TPS40077PWPRG4 [TI]
HIGH-EFFICIENCY, MIDRANGE-INPUT, SYNCHRONOUS BUCK CONTROLLER WITH VOLTAGE FEED-FORWARD; 高效率，中端，输入，具有电压前馈同步降压控制器
| 型号： | TPS40077PWPRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-EFFICIENCY, MIDRANGE-INPUT, SYNCHRONOUS BUCK CONTROLLER WITH VOLTAGE FEED-FORWARD |
| 文件： | 总43页 (文件大小：895K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS40077
www.ti.com
SLUS714–JANUARY 2007
HIGH-EFFICIENCY, MIDRANGE-INPUT, SYNCHRONOUS
BUCK CONTROLLER WITH VOLTAGE FEED-FORWARD
FEATURES
CONTENTS
•
Operation Over 4.5-V to 28-V Input Range
Device Ratings. . . . . . . . . . . . . . . . . . . . . . . .
2
4
•
Programmable, Fixed-Frequency, up to 1-MHz,
Voltage-Mode Controller
Electrical Characteristics. . . . . . . . . . . . . . . . .
Terminal Information. . . . . . . . . . . . . . . . . . . .
Application Information. . . . . . . . . . . . . . . . . .
Example Applications. . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . .
•
Predictive Gate Drive™
Anti-Cross-Conduction Circuitry
11
14
23
38
•
•
<1% Internal 700-mV Reference
Internal Gate Drive Outputs for High-Side and
Synchronous N-Channel MOSFETs
•
•
•
•
•
16-Pin PowerPAD™ Package
Thermal Shutdown Protection
Pre-Bias Compatible
DESCRIPTION
The TPS40077 is a midvoltage, wide-input (4.5-V to
28-V), synchronous, step-down controller, offering
design flexibility for a variety of user-programmable
functions, including soft start, UVLO, operating
frequency, voltage feed-forward, and high-side,
FET-sensed, short-circuit protection.
Power-Stage Shutdown Capability
Programmable High-Side Sense Short-Circuit
Protection
APPLICATIONS
•
•
•
•
•
Power Modules
Networking/Telecom
PCI Express
Industrial
Servers
SIMPLIFIED APPLICATION DIAGRAM
TPS40077PWP
VDD
1
2
KFF
RT
ILIM 16
VDD 15
VDD
3
4
5
6
7
8
LVBP
PGD
SGND
SS
BOOST 14
HDRV 13
SW 12
Powergood
VOUT
VOUT
DBP 11
FB
LDRV 10
COMP
PGND
9
S0202-01
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Predictive Gate Drive, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS40077
www.ti.com
SLUS714–JANUARY 2007
DESCRIPTION (CONTINUED)
The TPS40077 drives external N-channel MOSFETs using second-generation, predictive-gate drive to minimize
conduction in the body diode of the low-side FET and maximize efficiency. Pre-biased outputs are supported by
not allowing the low-side FET to turn on until the voltage commanded by the closed-loop soft start is greater
than the pre-bias voltage. Voltage feed-forward provides good response to input transients and provides a
constant PWM gain over a wide input-voltage operating range to ease compensation requirements.
Programmable short-circuit protection provides fault-current limiting and hiccup recovery to minimize power
dissipation with a shorted output. The 16-pin PowerPAD package gives good thermal performance and a
compact footprint.
ORDERING INFORMATION
PACKAGE
ORDERABLE PART NUMBER
TPS40077PWP
Plastic HTSSOP (PWP)
Plastic HTSSOP (PWP)
Tube
Tape and reel
TPS40077PWPR
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS40077
UNIT
VDD, ILIM
30
COMP, FB, KFF, PGD, LVBP
–0.3 to 6
VVDD
Input voltage range
Output voltage range
V
SW
–0.3 to 40
SW, transient < 50 ns
COMP, KFF, RT, SS
VBOOST
DBP
–2.5
–0.3 to 6
50
VOUT
V
10.5
LVBP
6
Output current source
Output current sink
LDRV, HDRV
LDRV, HDRV
KFF
1.5
IOUT
2
A
10
1
RT
Output current
mA
°C
LVBP
1.5
TJ
Operating junction temperature range
Storage temperature
–40 to 125
–55 to 150
260
Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX
28
UNIT
V
VDD
TA
Input voltage
4.5
Operating free-air temperature
–40
85
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
UNIT
Human body model (HBM)
2000
1500
V
V
Charged device model (CDM)
2
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
PACKAGE DISSIPATION RATINGS
Thermal Impedance,
TA = 25°C Power Rating
2.7
TA = 85°C Power Rating
Junction-to-Ambient(1)
37°C/W
Natural convection
150 LFM airflow
250 LFM airflow
500 LFM airflow
W
1.08 W
1.33 W
1.42 W
1.52 W
30°C/W
3.33 W
3.57 W
3.84 W
28°C/W
26°C/W
(1) For more information on the board and the methods used to determine ratings, see the PowerPAD Thermally Enhanced Package
application report (SLMA002).
3
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT SUPPLY
VVDD Input voltage range, VIN
OPERATING CURRENT
4.5
28
3.5
4.5
V
mA
V
IVDD
Quiescent current
Output drivers not switching
2.5
4.2
LVBP
VLVBP
Output voltage
TA = TJ = 25°C
3.9
450
OSCILLATOR/RAMP GENERATOR
fOSC
VRAMP
VRT
Accuracy
PWM ramp voltage(1)
500
2
550 kHz
V
VPEAK – VVAL
RT voltage
2.23
2.4
2.58
150
V
tON
Minimum output pulse time(1)
CHDRV = 0 nF
ns
VFB = 0 V, 100 kHz ≤ fSW ≤ 500 kHz
VFB = 0 V, fSW = 1 MHz
84%
76%
0.35
20
93%
93%
0.45
1100
Maximum duty cycle
VKFF
IKFF
SOFT START
Feed-forward voltage
0.4
V
Feed-forward current operating range(1)
µA
ISS
Charge current
7
12
17
75
µA
µs
tDSCH
Discharge time
CSS = 3.9 nF
25
CSS = 3.9 nF, VSS rising from 0.7 V to
1.6 V
tSS
Soft-start time
210
290
500
µs
Turnon threshold
310
225
35
365
275
420
325
150
VSSSD
Shutdown threshold
mV
VSSSDH
Shutdown threshold hysteresis
DBP
VDD > 10 V
7
4
8
9
VDBP
Output voltage
V
V
VDD = 4.5 V, IOUT = 25 mA
4.3
ERROR AMPLIFIER
TJ = 25°C
0.698
0.69
0.69
0.7 0.704
0.7 0.707
0.7 0.715
1
VFB
Feedback regulation voltage total variation
0°C ≤ TJ ≤ 85°C
–40°C ≤ TJ ≤ 85°C
Offset from VSS to error amplifier
VSS
Soft-start offset from VSS
Gain bandwidth
V
GBW
AVOL
ISRC
ISINK
IBIAS
5
50
10
MHz
dB
Open-loop gain
Output source current
Output sink current
Input bias current
2.5
4.5
6
mA
nA
2.5
VFB = 0.7 V
–250
0
(1) Assured by design. Not production tested.
4
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SHORT-CIRCUIT CURRENT PROTECTION
IILIM
Current sink into current limit
80
105
–50
135
50
125
–30
225
µA
mV
ns
VILIM(ofst)
tHSC
Current limit offset voltage (VSW – VILIM
)
VILIM = 11.5 V, VVDD = 12 V
During short circuit
–75
Minimum HDRV pulse duration
(2)
Propagation delay to output
ns
tBLANK
tOFF
Blanking time(2)
50
ns
Off time during a fault (SS cycle times)
7
Cycles
Switching level to end precondition
VSW
2
V
(2)
(VVDD – VSW
)
tPC
Precondition time(2)
Current limit precondition voltage threshold(2)
100
ns
V
VILIM
6.8
OUTPUT DRIVERS
tHFALL
tHRISE
tHFALL
tHRISE
tLFALL
tLRISE
tLFALL
tLRISE
High-side driver fall time (HDRV – SW)(2)
36
48
ns
ns
ns
ns
ns
ns
ns
ns
CHDRV = 2200 pF
High-side driver rise time (HDRV – SW)(2)
High-side driver fall time (HDRV – SW)(2)
High-side driver rise time (HDRV – SW)(2)
Low-side driver fall time(2)
Low-side driver rise time(2)
Low-side driver fall time(2)
72
CHDRV = 2200 pF, VVDD = 4.5 V,
0.2 V ≤ VSS ≤ 4 V
96
24
CLDRV = 2200 pF
48
48
CLDRV = 2200 pF, VVDD = 4.5 V,
0.2 V ≤ VSS ≤ 4 V
Low-side driver rise time(2)
96
IHDRV = –0.01 A
IHDRV = –0.1 A
IHDRV = 0.01A
IHDRV = 0.1 A
ILDRV= –0.01A
ILDRV = –0.1 A
ILDRV = 0.01 A
ILDRV = 0.1 A
0.7
1
1.3
0.1
1
High-level output voltage, HDRV
VOH
VOL
VOH
VOL
V
V
V
V
(VBOOST – VHDRV
)
0.95
0.06
0.65
0.65
0.875
0.03
0.3
Low-level output voltage, HDRV (VHDRV – VSW
)
1
High-level output voltage, LDRV
(VDBP – VLDRV
)
1.2
0.05
0.5
Low-level output voltage, LDRV
BOOST REGULATOR
VBOOST
UVLO
VUVLO
Output voltage
VDD = 12 V
15.2
17
V
Programmable UVLO threshold voltage
Programmable UVLO hysteresis
Fixed UVLO threshold voltage
Fixed UVLO hysteresis
RKFF = 90.9 kΩ, turn-on, VVDD rising
RKFF = 90.9 kΩ
6.2
1.1
7.2
1.55
4.3
8.2
2
V
Turn-on, VVDD rising
4.15
275
4.45
365
mV
POWER GOOD
VPG
VOH
VOL
Power-good voltage
IPG = 1 mA
370
770
630
500
High-level output voltage, FB
Low-level output voltage, FB
mV
THERMAL SHUTDOWN
Shutdown temperature threshold(2)
165
15
°C
Hysteresis(2)
(2) Assured by design. Not production tested.
5
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
TYPICAL CHARACTERISTICS
LVBP VOLTAGE
vs
JUNCTION TEMPERATURE
DBP VOLTAGE
vs
JUNCTION TEMPERATURE
8.15
8.10
4.30
4.25
4.20
V
DD
= 28 V
V
DD
= 28 V
8.05
8.00
V
DD
= 12 V
4.15
V
DD
= 12 V
7.95
7.90
7.85
4.10
4.05
7.80
4.00
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 1.
Figure 2.
DBP VOLTAGE
vs
JUNCTION TEMPERATURE
BOOTSTRAP DIODE VOLTAGE
vs
JUNCTION TEMPERATURE
4.50
4.49
2.0
1.9
V
= 4.5 V
= 25 mA
DD
I
LOAD
4.48
4.47
1.8
1.7
1.6
1.5
4.46
4.45
4.44
4.43
1.4
1.3
4.42
4.41
4.40
1.2
1.1
1.0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 3.
Figure 4.
6
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
CURRENT LIMIT OFFSET VOLTAGE
CURRENT LIMIT SINK CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
150
145
0
−10
−20
140
135
+3 S
130
125
Average
−30
120
115
−40
−50
VDD
28 V
12 V
4.5 V
−3 S
110
105
100
−60
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T − Junction Temperature − °C
J
T – Junction Temperature – °C
J
Figure 5.
Figure 6.
FEEDBACK REGULATION VOLTAGE
SWITCHING FREQUENCY
vs
vs
JUNCTION TEMPERATURE
INPUT VOLTAGE
704
500
499
R
RT
= 90.1kΩ
VDD
28 V
4.5 V
12 V
703
702
498
497
496
495
701
700
699
698
494
493
492
491
490
697
−50
−25
0
25
50
75
100
125
4
8
12
16
20
24
28
V
VDD
− Input Voltage − V
T − Junction Temperature − °C
J
Figure 7.
Figure 8.
7
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
MAXIMUM DUTY CYCLE
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
vs
JUNCTION TEMPERATURE
93
92
4.35
4.30
91
90
V
4.25
4.20
UVLO(on)
f
SW
= 100 kHZ
89
88
87
86
4.15
4.10
f
SW
= 500 kHZ
4.05
V
UVLO(off)
4.00
3.95
85
84
f
SW
= 1 MHZ
83
−50
3.90
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 9.
Figure 10.
PROGRAMMABLE UVLO THRESHOLD
SOFT-START CHARGING CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.10
1.08
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
V
UVLO(off)
V
1.06
1.04
UVLO(on)
1.02
1.00
0.98
0.96
0.94
0.92
0.90
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 11.
Figure 12.
8
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
ERROR AMPLIFIER INPUT BIAS CURRENT
MINIMUM OUTPUT VOLTAGE
vs
vs
JUNCTION TEMPERATURE
FREQUENCY
0
5.0
V
V
= 28 V
IN
−10
4.5
4.0
3.5
3.0
= 24 V
IN
V
= 18 V
−20
−30
−40
IN
V
IN
= 15 V
V
IN
= 12 V
V
= 10 V
IN
V
= 8 V
IN
−50
−60
2.5
2.0
1.5
V
IN
= 5 V
−70
−80
−90
1.0
0.5
−50
−25
0
25
50
75
100
125
100 200 300 400 500 600 700 800 900 1000
f
− Oscillator Frequency − kHz
OSC
T − Junction Temperature − °C
J
Figure 13.
Figure 14.
SWITCHING FREQUENCY
vs
TIMING RESISTANCE
UNDERVOLTAGE LOCKOUT THRESHOLD
vs
FEED-FORWARD IMPEDANCE
600
20
f
SW
= 300 kHz
UVLOV
ON
18
16
500
400
300
200
100
0
14
12
10
UVLOV
OFF
8
6
4
2
0
200
400
600
800
1000
100
150
200
250
300
350
400
450
R
KFF
− Feedforward Impedance − kΩ
f
SW
− Switching Frequency − kHz
G017
Figure 15.
Figure 16.
9
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
UNDERVOLTAGE LOCKOUT THRESHOLD
UNDERVOLTAGE LOCKOUT THRESHOLD
vs
vs
FEED-FORWARD IMPEDANCE
FEED-FORWARD IMPEDANCE
20
20
f
SW
= 500 kHz
f
SW
= 750 kHz
UVLOV
ON
UVLOV
ON
18
16
18
16
14
14
12
10
12
10
UVLOV
UVLOV
OFF
OFF
8
6
8
6
4
2
4
2
60
90
120
150
180
210
240
270
40
60
80
100
120
140
160
180
R
KFF
− Feedforward Impedance − kΩ
R
KFF
− Feedforward Impedance − kΩ
Figure 17.
Figure 18.
TYPICAL MAXIMUM DUTY CYCLE
DBP VOLTAGE
vs
INPUT VOLTAGE
vs
INPUT VOLTAGE
100
10
9
UVLO
= 15 V
(on)
90
80
70
UVLO
= 8 V
(on)
8
7
UVLO
= 12 V
(on)
60
UVLO
= 4.5 V
(on)
50
6
5
40
30
20
4
0
5
10
15
20
25
4
8
12
16
20
24
28
V
DD
− Input Voltage − V
G024
V
IN
− Input Voltage − V
G023
Figure 19.
Figure 20.
10
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
INPUT VOLTAGE
vs
LOW-VOLTAGE BYPASS VOLTAGE
4.50
4.45
4.40
4.35
4.30
4.25
4.20
4.15
4.10
4.05
4.00
5
10
15
20
25
30
V
DD
− Input Voltage − V
G025
Figure 21.
DEVICE INFORMATION
Terminal Configuration
PWP PACKAGE(1)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
KFF
RT
ILIM
VDD
LVBP
PGD
SGND
SS
BOOST
HDRV
SW
Thermal
Pad
DBP
FB
LDRV
PGND
COMP
P0047-01
(1) For more information on the PWP package, see the PowerPAD Thermally Enhanced Package technical brief
(SLMA002).
11
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
DEVICE INFORMATION (continued)
Table 1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
The peak voltage on BOOST is equal to the SW node voltage plus the voltage present at DBP less the bootstrap
diode drop. This drop can be 1.4 V for the internal bootstrap diode or 300 mV for an external Schottky diode. The
voltage differential between this pin and SW is the available drive voltage for the high-side FET.
BOOST
14
I
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the
FB pin to compensate the overall loop. The COMP pin is internally clamped to 3.4 V.
COMP
DBP
8
11
7
O
O
I
8-V reference used for the gate drive of the N-channel synchronous rectifier. This pin should be bypassed to
ground with a 1-µF ceramic capacitor.
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference
voltage, 0.7 V.
FB
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
(MOSFET off).
HDRV
13
O
Short-circuit-protection programming pin. This pin is used to set the short circuit detection threshold. An internal
current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to
VDD. The voltage on this pin is compared to the voltage drop (VVDD – VSW) across the high side N-channel
MOSFET during conduction. Just prior to the beginning of a switching cycle, this pin is pulled to approximately
VDD/2 and released when SW is within 2 V of VDD or after a timeout (the precondition time), whichever occurs
first. Placing a capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the
switch-on time, effectively programming the ILIM blanking time. See Application Information.
ILIM
16
I
A resistor connected from this pin to VIN programs the amount of feed-forward voltage. The current fed into this
pin is internally divided by 25 and used to control the slope of the PWM ramp and program undervoltage lockout.
Nominal voltage at this pin is maintained at 400 mV.
KFF
1
I
Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to ground
(MOSFET off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less
than 50 nC.
LDRV
10
O
4.2-V reference used for internal device logic only. This pin should be bypassed by a 0.1-µF ceramic capacitor.
External loads that are less than 1 mA and electrically quiet may be applied.
LVBP
PGD
3
4
O
O
This is an open-drain output that pulls to ground when soft start is active, or when the FB pin is outside a ±10%
band around VREF.
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of
the lower MOSFET(s).
PGND
RT
9
2
–
I
A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.
Signal ground reference for the device. Low-level quiet circuitry around the IC should connect to this pin. This pin
should be connected to the thermal pad under the IC, and that thermal pad should connect to the PGND pin. Do
not allow power currents to flow in the thermal pad or in the SGND part of the ground for best results.
SGND
5
–
Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The
capacitor is charged with an internal current source of 12 µA. The resulting voltage ramp on the SS pin is used as
a second noninverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V
less than that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on
the SS pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV. If SS is pulled
below 225 mV, the device goes into a shutdown state where the power FETSs are turned off and the prebias
circuitry is reset. If the programmed UVLO voltage is below 6 V, connect a 330-kΩ resistor in parallel with the SS
capacitor. Also provides timing for fault recovery attempts.
SS
6
I
This pin is connected to the switched node of the converter. It is used for short-circuit sensing and gate-drive
timing information and is the return for the high-side driver. A 1.5-Ω resistor is required in series with this pin for
protection against substrate current issues.
SW
12
15
I
I
VDD
Supply voltage for the device.
12
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
FUNCTIONAL BLOCK DIAGRAM
11 DBP
16 ILIM
VDD
Reference
Regulator
UVLO
UVLO
VDD 15
Controller
LVBP
RT
3
2
Ramp
Generator
Oscillator
SW
Pulse
Control
CLK
9
PGND
RAMP
KFF
1
4
PGD
770 mV
Power
Good
Logic
FB
630 mV
12 SW
SGND
5
SS Active
Short-Circuit
Comparator
and Control
ILIM
CLK
OC
SS Active
LVBP
Soft Start
and
Fault Control
OC
CLK
DBP
14 BOOST
13 HDRV
OC
CLK
Predictive
FB
7
Gate Drive
Control
Logic
PWM
SW
+
+
700 mV
UVLO
10 LDRV
SS
6
8
PGND
FAULT
COMP
B0150-01
13
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
APPLICATION INFORMATION
The TPS40077 allows the user to construct synchronous voltage-mode buck converters with inputs ranging from
4.5 V to 28 V and outputs as low as 700 mV. Predictive Gate Drive circuitry optimizes switching delays for
increased efficiency and improved converter output-power capability. Voltage feed-forward is employed to ease
loop compensation for wide-input-range designs and provide better line transient response.
The TPS40077 incorporates circuitry to allow startup into a preexisting output voltage without sinking current
from the source of the preexisting output voltage. This avoids damaging sensitive loads at start-up. The
controller can be synchronized to an external clock source or can free-run at a user-programmable frequency.
An integrated power-good indicator is available for logic (open-drain) output of the condition of the output of the
converter.
MINIMUM PULSE DURATION
The TPS40077 devices have limitations on the minimum pulse duration that can be used to design a converter.
Reliable operation is assured for nominal pulse durations of 150 ns and above. This places some restrictions on
the conversion ratio that can be achieved at a given switching frequency. Figure 14 shows minimum output
voltage for a given input voltage and frequency.
SLEW RATE LIMIT ON VDD
The regulator that supplies power for the drivers on the TPS40077 requires a limited rising slew rate on VDD for
proper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can overshoot and
damage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than
0.12 V/µs as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of the
device. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor from
the VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor in
normal operation. This places some constraints on the R-C values that can be used. Figure 22 is a schematic
fragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for
R and C that limit the slew rate in the worst-case condition.
TPS40077
R
ILIM 16
15 VDD
VIN
+
HDRV 13
SW 12
C
_
9
PGND
LDRV 10
S0203-01
Figure 22. Limiting the Slew Rate
14
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
APPLICATION INFORMATION (continued)
V
* 8 V
IN
C u
R t
R SR
(1)
(2)
0.2 V
Q
f
) I
DD
SW
g(TOT)
where
•
•
•
•
•
VVIN is the final value of the input voltage ramp
fSW is the switching frequency
Qg(TOT) is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet)
IDD is the TPS40077 input current (3.5 mA maximum)
SR is the maximum allowed slew rate [12 ×104] (V/s)
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
The TPS40077 has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves
as the master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the
switching frequency of the clock oscillator. The clock frequency is related to RT by:
1
R + ǒ
* 23ǓkW
T
*6
f
(kHz) 17.82 10
SW
(3)
PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator
provides voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a
constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line
variations, because the PWM is not required to wait for loop delays before changing the duty cycle. (See
Figure 23).
The PWM ramp must reach approximately 1 V in amplitude during a clock cycle, or the PWM is not allowed to
start. The PWM ramp time is programmed via a single resistor (RKFF) connected from KFF VDD. RKFF, VSTART
,
and RT are related by (approximately):
2
*3
*5
2
T
R
+ 0.131 R V
* 1.61 10 V
) 1.886 V
* 1.363 * 0.02 R * 4.87 10 R
UVLO T
KFF
T
UVLO(on)
UVLO(on)
(4)
where
•
•
RT and RKFF are in kΩ
VUVLO(on) is in V
This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary
up to ±15% from this number. Figure 16 through Figure 18 show the typical relationship of VUVLO(on), VUVLO(off)
and RKFF at three common frequencies.
The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. For
example, if the startup voltage is programmed to be 10 V, the controller starts when VDD reaches 10 V and shuts
down when VDD falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twice
the startup voltage. Below this point, the maximum duty cycle is as specified in the Electrical Characteristics
table. Note that with this scheme, the theoretical maximum output voltage that the converter can produce is
approximately two times the programmed startup voltage. For design, set the programmed startup voltage equal
to or greater than the desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and
below). For example, a 5-V output converter should not have a programmed startup voltage below 5.9 V.
Figure 23 shows the theoretical maximum duty cycle (typical) for various programmed startup voltages.
15
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
APPLICATION INFORMATION (continued)
VIN
VIN
SW
SW
RAMP
V
PEAK
COMP
COMP
RAMP
V
VALLEY
T
1
T
2
t
ON2
t
ON1
tON
T
d +
t
> t
and d > d
ON2 1 2
ON1
VDG−03172
Figure 23. Voltage Feed-Forward and PWM Duty Cycle Waveforms
PROGRAMMING SOFT START
TPS40077 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft start is
programmed by connecting an external capacitor (CSS) from the SS pin to GND. This capacitor is charged by a
fixed current, generating a ramp signal. The voltage on SS is level-shifted down approximately 1 V and fed into
a separate noninverting input to the error amplifier. The loop is closed on the lower of the level-shifted SS
voltage or the 700-mV internal reference voltage. Once the level-shifted SS voltage rises above the internal
reference voltage, output-voltage regulation is based on the internal reference. To ensure a controlled ramp-up
of the output voltage, the soft-start time should be greater than the L-COUT time constant or:
ǸL C
w 2p
t
START
OUT
(5)
Note that there is a direct correlation between tSTART and the input current required during start-up. The lower
tSTART is, the higher the input current required during start-up, because the output capacitance must be charged
faster. For a desired soft-start time, the soft-start capacitance, CSS, can be found from:
I
SS
C
+ t
SS
SS
V
FB
(6)
16
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
APPLICATION INFORMATION (continued)
PROGRAMMING SHORT-CIRCUIT PROTECTION
The TPS40077 uses a two-tier approach for short-circuit protection. The first tier is a pulse-by-pulse protection
scheme. Short-circuit protection is implemented on the high-side MOSFET by sensing the voltage drop across
the MOSFET when its gate is driven high. The MOSFET voltage is compared to the voltage dropped across a
resistor (RILIM) connected from VVDD to the ILIM pin when driven by a constant-current sink. If the voltage drop
across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately
terminated. The MOSFET remains off until the next switching cycle is initiated. This is illustrated in Figure 24.
ILIM
ILIM Threshold
(A)
Overcurrent
VIN − 2V
SW
T2
ILIM
ILIM Threshold
VIN − 2V
T1
(B)
SW
T1
T3
UDG−03173
Figure 24. Switching and Current-Limit Waveforms and Timing Relationship
In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half of
VVDD. The ILIM pin is allowed to return to its nominal value after one of two events occurs. If the SW node rises
to within approximately 2 V of VVDD, the device allows ILIM to go back to its nominal value. This is illustrated in
Figure 24(A). T1 is the delay time from the internal PWM signal being asserted and the rise of SW. This includes
a driver delay of 50 ns, typical. T2 is the reaction time of the sensing circuit that allows ILIM to start to return to
its nominal value, typically 20 ns. The second event that can cause ILIM to return to its nominal value is for an
internal timeout to expire. This is illustrated in Figure 24(B) as T3. Here SW never rises to VVDD – 2 V, for
whatever reason, and the internal timer times out, releasing the ILIM pin.
Prior to ILIM starting back to its nominal value, overcurrent sensing is not enabled. In normal operation, this
ensures that the SW node is at a higher voltage than ILIM when overcurrent sensing starts, avoiding false trips
while allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across RILIM
sets an exponential approach to the normal voltage at the ILIM pin. This exponential decay of the overcurrent
threshold can be used to compensate for ringing on the SW node after its rising edge and to help compensate
for slower-turnon FETs. Choosing the proper capacitance requires care. If the capacitance is too large, the
voltage at ILIM does not approach the desired overcurrent level quickly enough, resulting in an apparent shift in
overcurrent threshold as pulse duration changes. As a general rule, it is best to make the time constant of the
R-C at the ILIM pin 0.2 times or less of the nominal pulse duration of the converter as shown in Equation 11.
Also, the comparator that uses ILIM and SW to determine if an overcurrent condition exists has a clamp on its
SW input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as
much as 2 V at –40°C) below VVDD. When ILIM is more than 1.4 V below VVDD, the overcurrent circuit is
effectively disabled.
17
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
APPLICATION INFORMATION (continued)
The second-tier protection incorporates a fault counter. The fault counter is incremented on each cycle with an
overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches
seven (7), a fault condition is declared by the controller. When this happens, the outputs are placed in a state
defined in Table 2. Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and the
PWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter is
decremented to zero, the PWM is re-enabled and the controller attempts to restart. If the fault has been
removed, the output starts up normally. If the output is still present, the counter counts seven overcurrent pulses
and re-enters the second-tier fault mode. Refer to Figure 25 for typical fault-protection waveforms.
The minimum short-circuit limit setpoint (ISCP(min)) depends on tSTART, COUT, VOUT, ripple current in the inductor
(IRIPPLE), and the load current at turnon (ILOAD).
C
V
OUT
I
OUT
t
RIPPLE
2
u ǒ
Ǔ) I ǒ Ǔ
I
)
SCP(min)
LOAD
START
(7)
(8)
The short-circuit limit programming resistor (RILIM) is calculated from:
I
R
) V
SCP
DS(onMAX) ILIM (offset)
R
+
W
ILIM
I
ILIM
where
•
•
•
IILIM is the current into the ILIM pin (110 µA, typical)
VILIM(offset) is the offset voltage of the ILIM comparator (–50 mV, typical)
ISCP is the short-circuit protection current
To find the range of the overcurrent values, use the following equations:
1.09 I
R
* 0.09 R
I
* 0.045 V ) 75 mV
ILIM(max)
ILIM
VDD
RVDD
I
+
(A)
SCP(max)
R
DS(ON)min
(9)
1.09 I
R
* 0.09 R
I
* 0.045 V ) 30 mV
RVDD
ILIM(min)
ILIM
VDD
I
+
(A)
SCP(min)
R
DS(ON)max
(10)
The TPS40077 provides short-circuit protection only. Therefore, it is recommended that the minimum
short-circuit protection level be placed at least 20% above the maximum output current required from the
converter. The maximum output of the converter should be the steady state maximum output plus any transient
specification that may exist.
The ILIM capacitor maximum value can be found from:
V
0.2
R f
ILIM
OUT
C
+
(Farads)
ILIM(max)
V
IN
SW
(11)
Note that this is a recommended maximum value. If a smaller value can be used, it should be. For most
applications, consider using half the maximum value above.
18
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
APPLICATION INFORMATION (continued)
HDRV
Clock
t
BLANKING
V
ILIM
V
VIN
− V
SW
SS
7 Current-Limit Trips
(HDRV Cycle Terminated by Current-Limit Trip)
7
Soft-Start
Cycles
VDG−03174
Figure 25. Typical Fault Protection Waveforms
LOOP COMPENSATION
Voltage-mode, buck-type converters are typically compensated using Type III networks. Because the TPS40077
uses voltage feed-forward control, the gain of the voltage feed-forward circuit must be included in the PWM gain.
The gain of the voltage feed-forward circuit, combined with the PWM circuit and power stage for the TPS40077
is:
KPWM VUVLO(on)
The remainder of the loop compensation is performed as in a normal buck converter. Note that the voltage
feed-forward circuitry removes the input voltage term from the expression for PWM gain. PWM gain is strictly a
function of the programmed startup voltage.
SHUTDOWN AND SEQUENCING
The TPS40077 can be shut down by pulling the SS pin below 250 mV. In this state, both of the output drivers
are in the low-output state, turning off both of the power FETs. This places the output of the converter in a
high-impedance state. When shutting down the converter, a crisp pulldown of the SS pin is preferred to a slow
pulldown. A slow pulldown could allow the output to be pulled low, possibly sinking current from the load. As a
general rule of thumb, the fall time of SS when shutting down the converter should be no more than 1/10th of
the control loop crossover frequency. An example of a shutdown interface is shown in Figure 26.
19
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
APPLICATION INFORMATION (continued)
TPS40077
6
SS
Shutdown
S0204-01
Figure 26. TPS40077 Shutdown
In a similar manner, power supplies based on the TPS40077 can be sequenced by connecting the PGD pin of
the first supply to come up to the SS pin of the second supply as shown in Figure 27.
TPS40077
TPS40077
To System Power Good
6
SS
PGD
4
6
SS
PGD
4
S0205-01
Figure 27. TPS40077 Sequencing
BOOST AND LVBP BYPASS CAPACITANCE
The BOOST capacitance provides a local, low-impedance flying source for the high-side driver. The BOOST
capacitor should be a good-quality, high-frequency capacitor. A capacitor with a minimum value of 100-nF is
suggested.
The LVBP pin must provide energy for both the synchronous MOSFET and the high-side MOSFET (via the
BOOST capacitor). The suggested value for this capacitor is 1-µF ceramic, minimum.
20
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
APPLICATION INFORMATION (continued)
INTERNAL REGULATORS
The internal regulators are linear regulators that provide controlled voltages from which the drivers and the
internal circuitry operate. The DBP pin is connected to a nominal 8-V regulator that provides power for the driver
circuits. This regulator has two modes of operation. At VDD voltages below 8.5 V, the regulator is in a
low-dropout mode of operation and tries to provide as little impedance as possible from VDD to DBP. Above 10
V at VDD, the regulator regulates DBP to 8 V. Between these two voltages, the regulator remains in the state it
was in when VDD entered this region (see Figure 20). Small amounts of current can be drawn from this pin for
other circuit functions, as long as power dissipation in the controller device remains at acceptable levels and
junction temperature does not exceed 125°C.
The LVBP pin is connected to another internal regulator that provides 4.2 V (nom) for the operation of
low-voltage circuitry in the controller. This pin can be used for other circuit purposes, but extreme care must be
taken to ensure that no extra noise is coupled onto this pin; otherwise, controller performance suffers. Current
draw is not to exceed 1 mA. See Figure 21 for typical output voltage at this pin.
TPS40077 POWER DISSIPATION
The power dissipation in the TPS40077 is largely dependent on the MOSFET driver currents and the input
voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power
(neglecting external gate resistance) can be calculated from:
PD = Qg × VDR × fSW
(Watts/driver)
where VDR is the driver output voltage
The total power dissipation in the TPS40077, assuming the same MOSFET is selected for both the high-side
and synchronous rectifier, is described in Equation 14 or Equation 15.
2 P
D
P + ǒ Ǔ
) I
V
(Watts)
IN
T
Q
V
DR
(14)
(15)
or
P + ǒ2 Q f
Ǔ
) I V (Watts)
g
T
SW
Q
IN
where IQ is the quiescent operating current (neglecting drivers)
The maximum power capability of the TPS40077 PowerPAD package is dependent on the layout as well as air
flow. The thermal impedance from junction to air, assuming 2-oz. copper trace and thermal pad with solder and
no air flow, is 37°C/W. See the application report titled PowerPAD Thermally Enhanced Package (SLMA002) for
detailed information on PowerPAD package mounting and usage.
The maximum allowable package power dissipation is related to ambient temperature by Equation 16. For θJA,
see the Package Dissipation Ratings table.
T * T
J
A
P +
(Watts)
T
q
JA
(16)
Substituting Equation 16 into Equation 15 and solving for fSW yields the maximum operating frequency for the
TPS40077. The result is described in Equation 17.
ǒ
AǓ
DDǓ
V
T *T
J
ƪ ƫ* I
ǒ Ǔ
Q
ǒ
q
JA
f
+
(Hz)
SW
ǒ2 QgǓ
(17)
21
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
APPLICATION INFORMATION (continued)
BOOST DIODE
The TPS40077 series has internal diodes to charge the boost capacitor connected from SW to BOOST. The
drop across these diodes is rather large, 1.4 V nominal, at room temperature. If this drop is too large for a
particular application, an external diode may be connected from DBP (anode) to BOOST (cathode). This
provides significantly improved gate drive for the high-side FET, especially at lower input voltages.
GROUNDING AND BOARD LAYOUT
The TPS40077 provides separate signal ground (SGND) and power ground (PGND) pins. Care should be given
to proper separation of the circuit grounds. Each ground should consist of a plane to minimize its impedance, if
possible. The high-power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling
capacitor (DBP), and the input capacitor should be connected to PGND plane.
Sensitive nodes such as the FB resistor divider and RT should be connected to the SGND plane. The SGND
plane should only make a single-point connection to the PGND plane. It is suggested that the SGND pin be tied
to the copper area for the thermal pad underneath the chip. Tie the PGND to the thermal-pad copper area as
well, and make the connection to the power circuit ground from the PGND pin. Reference the output voltage
divider to the SGND pin.
Component placement should ensure that bypass capacitors (LVPB and DBP) are located as close as possible
to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be
located near high-dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow
careful layout practices results in suboptimal operation. More detailed information can be found in the
TPS40077EVM User's Guide (SLVU192).
SYNCHRONOUS RECTIFIER CONTROL
Table 2 describes the state of the rectifier MOSFET control under various operating conditions.
Table 2. Synchronous Rectifier MOSFET States
SYNCHRONOUS RECTIFIER OPERATION DURING
FAULT
SOFT-START
NORMAL
(FAULT RECOVERY IS SAME
AS SOFT-START)
OVERVOLTAGE
Turns OFF only at start of next
cycle only if the pulse width
modulator duty cycle is greater
than zero. Otherwise, stays ON
Off until first high-side pulse is
detected, then on when high-side cycle. Turns on when the
MOSFET is off high-side MOSFET is turned off
Turns off at the start of a new
OFF
For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50 nC.
22
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
APPLICATION 1: BUCK REGULATOR 8-V TO 16-V INPUT, 1.8-V OUTPUT AT 10 A
Table 3. Specifications
PARAMETER
NOTES AND CONDITIONS
MIN
NOM
MAX
UNITS
INPUT CHARACTERSTICS
VIN
IIN
Input voltage
Input current
No-load input current
Input UVLO
8
12
16
2
V
A
VIN = NOM, IOUT = MAX
1.8
VIN = NOM, IOUT = 0 A
IOUT = MIN to MAX
IOUT = MIN to MAX
62.6
6
3.6
6.6
7.7
mA
V
VIN_UVLO
VIN_ONV
5.4
6.3
Input ONV
7
V
OUTPUT CHARACTERSTICS
VOUT
Output voltage
VIN = NOM, IOUT = NOM
VIN = MIN to MAX, IOUT = NOM
VIN = NOM, IOUT = MIN to MAX
VIN = NOM, IOUT = MAX
VIN = MIN to MAX
1.75
1.8
1.85
0.5%
0.5%
100
V
Line regulation(1)
Load regulation(1)
Output voltage ripple
Output current
VOUT_ripple
IOUT
mVpp
A
0
12.25
NA
5
19.4
NA
10
Output overcurrent
inception point
IOCP
VIN = NOM, VOUT = VOUT – 5%
IOUT = MIN to MAX
34
A
VOVP
Output OVP
NA
Transient response
∆I Load step
IOUT_Max to 0.2 × IOUT _Max
8
10
A
Load slew rate
Overshoot
A/µs
mV
ms
200
1
Settling time
SYSTEM CHARACTERSTICS
fSW
ηpk
η
Switching frequency
Peak efficiency
240
–40
300
90%
90%
360
85
kHz
VIN = NOM, IOUT = MIN to MAX
VIN = NOM, IOUT = MAX
Full-load efficiency
Operating temperature
range
Top
VIN = MIN to MAX, IOUT = MIN to MAX
25
°C
MECHANICAL CHARACTERSTICS
2
5.08
3
Inches
cm
L
Width
Inches
cm
W
h
Length
7.62
0.41
1.04
Inch
cm
Component height
(1) Voltage accuracy is dependent on resistor tolerance and reference accuracy. Line and load regulation are calculated with respect to the
actual set point voltage.
23
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
Schematic and Performance Curves
VIN
+
CIN
RKFF
CDELAY
ELCO
RLIM
RT
U1
TPS40077PWP
QSW
CBP5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VOUT = 1.8 V
KFF
ILIM
VDD
LOUT
IOUT up to 10 A
CBOOST
RT
RPGD
BP5
PGD
SGND
SS
BOOST
HDRV
SW
VOUT
CVDD
C_IN
MLCC
DBP
R4
0 W
CSS
R10
+
C_OUT
MLCC
COUT
FB
LDRV
PGND
ELCO
QSR
COMP
PWP
330 kW
C13
2.2nF
CDBP
RPZ2
CZ2
CP2
0 V
RZ1
RSET
RP1
C11
0.1 mF
CPZ1
S0239-01
Figure 28. Schematic Diagram
100
90
80
70
60
50
40
30
20
10
0
8 V
12 V
16 V
0
1
2
3
4
5
6
7
8
9
10
I
− Load Current − A
OUT
G026
Figure 29. Module Efficiency, 8 V, 12 V, and 16 V In, 0 to 10 A Out
24
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
200
50
45
40
35
30
25
20
15
10
5
180
160
140
120
100
80
Phase
60
Gain
40
20
0
100
0
1M
1k
10k
f − Frequency − Hz
100k
G027
Figure 30. Bode Plot Showing 57° Phase Margin at Crossover Frequency of 54 kHz
Component Selection
Power Train Components
Output Inductor, LOUT
The output inductor is one of the most important components to select. It stores the energy necessary to keep
the output regulated when the switch FET is turned off. The value of the output inductor dictates the peak and
RMS currents in the converter. These currents are important when selecting other components. Equation (1) can
be used to calculate a value for LOUT for this module which operates at a switching frequency (f) of 300 kHz.
V
* V
V
IN(max)
OUT
f I
s
RIPPLE
OUT
LOUT +
V
IN(max)
(18)
IRIPPLE is the allowable ripple in the inductor. Select IRIPPLE to be between 20% and 30% of maximum IOUT. For
this design, IRIPPLE of 2.5 A was selected. Calculated LOUT is 2.13 µH. A standard inductor with value of 2.5 µH
was chosen. This will reduce IRIPPLE by about 17% to 2.07 A.
This IRIPPLE value can be used calculate the rms and peak current flowing in LOUT. Note that this peak current is
also seen by the switching FET and synchronous rectifier.
2
I
2
+ Ǹ
RIPPLE
12
I
I
)
OUT
+ 10.02 A
LOUT_RMS
(19)
The power loss from the selected inductor DCR is 357 mW. The ac core loss for this Coilcraft inductor may be
found from the Coilcraft Web site, where there is a loss calculator. The loss is 179 mW.
I
RIPPLE
2
I
+ I
)
+ 11.03 A
PK
OUT
(20)
The inductor is selected with a saturation current higher than this current plus the current that is developed
charging the output capacitance during the soft-start interval.
25
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
Output Capacitor, COUT, ELCO and MLCC
Several parameters must be considered when selecting the output capacitor. The capacitance value should be
selected based on the output overshoot, VOVER, and undershoot, VUNDER, during a transient load, ISTEP, on the
converter. The equivalent series resistance (ESR) is chosen to allow the converter to meet the output ripple
specification, VRIPPLE. The voltage rating must be greater than the maximum output voltage. Another parameter
to consider is equivalent series inductance, which is important in fast-transient load situations. Also, size and
technology can be factors when choosing the output capacitor. In this design, a large-capacitance electrolytic
type capacitor, COUT ELCO, is used to meet the overshoot and undershoot specifications. Its ESR is chosen to
meet the output ripple specification. Smaller multiple-layer ceramic capacitors, COUT MLCC, are used to filter
high-frequency noise.
The minimum required capacitance and maximum ESR can be calculated using the following equations.
2
LOUT I
STEP
COUT +
2 V
D
(V * V
)
OUT
max
UNDER
IN
(21)
2
LOUT I
STEP
COUT +
2 V
V
OUT
OVER
(22)
(23)
V
ESR +
I
RIPPLE
RIPPLE
From Equation 21, Equation 22, and Equation 23, the capacitance for COUT should be greater than 444 µF, and
its ESR should be less than 12 mΩ. The 470-µF/6.3-V capacitor from Panasonic's FC series was chosen. Its
ESR is 160 mΩ. MLCCs of 47 µF and 22 µF/16 V are also added in parallel to achieve the required ESR and to
reduce high-frequency noise.
Input Capacitor, CIN ELCO and MLCC
The input capacitor is selected to handle the ripple current of the buck stage. Also, a relatively large capacitance
is used to keep the ripple voltage on the supply line low. This is especially important where the supply line has
high impedance. It is recommended however, that the supply-line impedance be kept as low as possible.
The input-capacitor ripple current can be calculated using Equation 24.
2
ǒI
IN(AVG)Ǔ2
I
2
RIPPLE
12
I
+
* I
)
D ) I
(1 * D)
IN(AVG)
ƪ
Ǹ
ƫ
CAP(RMS)
OUT
(24)
IIN(AVG) is the average input current. This is calculated simply by multiplying the output dc current by the duty
cycle. The ripple current in the input capacitor is 3.3 A. An 1812 MLCC using X5R material has a typical
dissipation factor of 5%. For a 22-µF capacitor at 300 kHz, the ESR is approximately 4 mΩ. Two capacitors are
used in parallel, so the power dissipation in each capacitor is less than 11 mW.
A 470-µF/16-V electrolytic is added to maintain the voltage on the input rail.
Switching MOSFET, QSW
The following key parameters must be met by the selected MOSFET.
•
Drain source voltage, Vds, must be able to withstand the input voltage plus spikes that may be on the
switching node. For this design a Vds rating of 30 volts is recommended.
•
Drain current, ID, at 25°C, must be greater than that calculated using Equation 25.
2
V
I
2
OUT
RIPPLE
12
I
+
I
)
ƪ ƫ
Ǹ
QSW(RMS)
OUT(MAX)
V
IN(MIN)
(25)
•
•
With the parameters specified, the calculation of IQSW(RMS) should be greater than 5 A.
Gate source voltage, Vgs, must be able to withstand the gate voltage from the control IC. For the TPS40077,
this is 11 V.
26
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
Once the above boundary parameters are defined, the next step in selecting the switching MOSFET is to select
the key performance parameters. Efficiency is the performance characteristic which drives the other selection
criteria. Target efficiency for this design is 90%. Based on 1.8-V output and 10 A, this equates to a power loss in
the converter of 1.8 W. Based on this figure, a target of 0.6 W dissipated in the switching FET was chosen.
The following equations can be used to calculate the power loss, PQSW, in the switching MOSFET.
P
+ P
) P
) P
QSW
CON
SW GATE
(26)
(27)
2
V
I
2
2
OUT
RIPPLE
12
P
+ R
I
+ R
DS(on)
I
)
ƪ ƫ
out
CON
DS(on)
QSW(RMS)
V
IN
I
ȱ
ȳ
ȧ
RIPPLE
ǒQ
gdǓ
ǒI Ǔ
)
) Q
gs1
OUT
2
Q
) Q
ȧ
OSS(SW)
OSS(SR)
P
+ V f
)
ȧ
ȧ
SW
IN
S
12
I
g
ȧ
ȧ
(28)
(29)
P
+ Q
V f
g
GATE
g(TOT)
SW
where
PCON = conduction losses
PSW = switching losses
PGATE = gate-drive losses
Qgd = drain-source charge or Miller charge
Qgs1 = gate-source post-threshold charge
Ig = gate-drive current
QOSS(SW) = switching MOSFET output charge
QOSS(SR) = synchronous MOSFET output charge
Qg(TOT) = total gate charge from zero volts to the gate voltage
Vg = gate voltage
If the total estimated loss is split evenly between conduction and switching losses, Equation 27 and Equation 28
yield preliminary values for RDS(on) and (Qgs1 + Qgd). Note output losses due to QOSS and gate losses have been
ignored here. Once a MOSFET is selected, these parameters can be added.
The switching MOSFET for this design should have an RDS(on) of less than 8 mΩ. The sum of Qgd and Qgs
should be approximately 4 nC.
It may not always be possible to get a MOSFET which meets both these criteria, so a compromise may be
necessary. Also, by selecting different MOSFETs close to these criteria and calculating power loss, the final
selection can be made. It was found that the Si7860DP MOSFET from Vishay semiconductor gave reasonable
results. This device has an RDS(on) of 8 mΩ and a (Qgs1 + Qgd) of 5 nC. The estimated conduction losses are
0.115 W and the switching losses are 0.276 W. This gives a total estimated power loss of 0.391 W versus 0.6 W
for our initial boundary condition. Note this does not include gate losses of approximately 71 mW and output
losses of 20 mW.
Rectifier MOSFET, QSR
Similar criteria to the foregoing can be used for the rectifier MOSFET. There is one significant difference: due to
the body diode conducting, the rectifier MOSFET switches with zero voltage across its drain and source, so
effectively with zero switching losses. However, there are some losses in the body diode. These are minimized
by reducing the delay time between the transition from the switching MOSFET turnoff to rectifier MOSFET
turnon and vice-versa. The TPS40077 incorporates TI's proprietary Predictive Gate Drive circuitry (PGD), which
helps reduce these delays to around 10 ns.
The equations used to calculate the losses in the rectifier MOSFET are:
P
+ P
) P ) P
QSR
CON BD GATE
(30)
27
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
2
V
I
2
OUT
RIPPLE
12
ǒ
Ǔ
2
ƪ1 *
f ƫ
P
+ R
* t ) t
I
)
ƪ ƫ
out
1
CON
DS(on)
S
V
IN
(31)
(32)
(33)
ǒ Ǔ
t ) t f
1 2
OUT S
P
+ V I
BD
f
P
+ Q
V f
g
g(TOTAL) S
GATE
where
PBD = body diode losses
t1 = body diode conduction prior to turnon of channel = 12 ns for PGD
t2 = body diode conduction after turnoff of channel = 12 ns for PGD
Vf = body diode forward voltage
Estimating the body diode losses based on a forward voltage of 1 V gives 0.072 W. The gate losses are
unknown at this time, so assume 0.1-W gate losses. This leaves 0.428 W for conduction losses. Using this
figure, a target RDS(on) of 5 mΩ was calculated.
The Si7336ADP from Vishay was chosen. Using the parameters from its data sheet, the actual expected power
losses are calculated. Conduction loss is 0.317 W, body diode loss is 0.072 W, and the gate loss is 0.136W.
This totals 0.525 W associated with the rectifier MOSFET.
Two other criteria should be verified before finalizing on the rectifier MOSFET. One is the requirement to ensure
that predictive gate drive functions correctly. The turnoff delay of the Si7336ADP is 97 ns. The minimum turnoff
delay of the Si7860DP is 25 ns. Together these devices meet the 130-ns requirement.
Secondly, the ratio between Cgs and Cgd should be greater than 1. The Si7336ADP easily meets this criterion.
This helps reduce the risk of dv/dt-induced turnon of the rectifier MOSFET. If this is likely to be a problem, a
small resistor may be added in series with the boost capacitor, CBOOST.
Component Selection for TPS40077
Timing Resistor, RT
The timing resistor is calculated using the following equation.
1
R +
* 23
T
*6
f 17.82 10
S
(34)
This gives a resistor value of 165 kΩ. The nominal frequency using this resistor is 300 kHz.
Feed-Forward and UVLO Resistor, RKFF
A resistor connected to the KFF pin of the IC feeds into the ramp generator. This resistor provides current into
the ramp generator proportional to the input voltage. The ramp is then adjusted to compensate for different input
voltages. This provides the voltage feed-forward feature of the TPS40077.
The same resistor also sets the undervoltage lockout point. The input start voltage should be used to calculate a
value for RKFF. For this module, the minimum input voltage is 8 V; however, due to tolerances in the IC, a start
voltage of 10% less than the minimum input voltage is selected. The start voltage for RKFF calculation is 7.2 V.
Using Equation 35, RKFF can be selected.
2
*3
R
+ 0.131 R V
* 1.61 10 V
) 1.886 V
* 1.363 * 0.02 R
UVLO T
T
UVLO(on)
UVLO(on)
KFF
2
*5
* 4.87 10 R
T
(35)
where RKFF and RT are in kΩ.
This equation gives an RKFF value of 156 kΩ. The closest lower standard value of 154 kΩ should be selected.
This gives a minimum start voltage of 7.1 V.
28
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
Soft-Start Capacitor, CSS
It is good practice to limit the rise time of the output voltage. This helps prevent output overshoot and possible
damage to the load. The selection of the soft-start time is arbitrary. It must meet one condition: it should be
greater than the time constant of the output filter, LOUT and COUT. This time is given by
Ǹ
t
w 2p LOUT COUT
START
(36)
The soft-start time must be greater than 0.23 ms. A time of 0.75 ms was chosen. This time also helps limit the
initial input current during start-up so that the peak current plus the capacitor start-up current is less than the
minimum short-circuit current. The value of CSS can be calculated using Equation 37.
I
SS
C
+
t
START
SS
V
FB
(37)
A standard 15-nF MLCC capacitor was chosen. The calculated start time using this capacitor is 0.875 ms.
Short-Circuit Protection, RILIM and CILIM
Short-circuit protection is programmed using the RILIM resistor. Selection of this resistor depends on the RDS(on)
of the switching MOSFET selected and the required short-circuit current trip point, ISCP. The minimum ISCP is
limited by the inductor peak current, the output voltage, the output capacitor, and the soft-start time. Their
relationship is given by Equation 38. A short-circuit current trip point greater than that calculated by this equation
should be used.
COUT V
OUT
I
w
) I
PK
SCP
t
START
(38)
The minimum short-circuit current trip point for this design is 12.25 A. This value is used in Equation 39 to
calculate the minimum RILIM value.
I
R
) V
SCP
+
DS(on)MAX ILIM(Max)
R
ILIM
I
LIM(Min)
(39)
RILIM is calculated to be 1.17 kΩ, and a 1.2-kΩ resistor is used to verify that the short-circuit current
requirements are met. The minimum and maximum short-circuit current can be calculated using Equation 40 and
Equation 41.
I
R
* V
ILIM(MIN)
+
ILIM(MIN) ILIM(MAX)
I
SCP(MIN)
R
DS(on)MAX
(40)
I
R
* V
ILIM(MIN)
ILIM(MAX)
ILIM(MAX)
I
+
SCP(MAX)
R
DS(on)MIN
(41)
where: VILIM(MAX) and VILIM(MIN) are maximum and minimum voltages across the high side FET when it is turned
on, taking into account temperature variations.
The minimum ISCP is 12.25 A, and the maximum is 34 A.
It is also recommended to add a small capacitor, CILIM, across RILIM. The value of this capacitor should be about
half the value calculated in Equation 42.
V
0.2
OUT
C
+
ILIM(Max)
V
R
f
ILIM S
IN
(42)
This equation yields a maximum CILIM as 55 pF. A smaller value of 27 pF is chosen is chosen.
29
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
Boost Voltage, CBOOST and DBOOST (Optional)
To be able to drive an N-channel MOSFET in the switch location of a buck converter, a capacitor charge pump
or boost circuit is required. The TPS40077 contains the elements for this boost circuit. The designer must only
add a capacitor, CBOOST, from the switch node of the buck power stage to the BOOST pin of the IC. Selection
of this capacitor is based on the total gate charge of the switching MOSFET and the allowable ripple on the
boost voltage, ∆VBOOST. A ripple of 0.2 V is assumed for this design. Using these two parameters and
Equation 43, the minimum value for CBOOST can be calculated.
Q
g(TOTAL)
CBOOST u
DV
BOOST
(43)
The total gate charge of the switching MOSFET is 23 nC. A minimum CBOOST of 0.092 µF is required. A 0.1
µF capacitor was chosen. This capacitor must be able to withstand the maximum input voltage plus the
maximum voltage on DBP. This is 13.2 V plus 9.0 V, which is 22.2 V. A 50-V capacitor is used.
To reduce losses in the TPS40077 and to increase the available gate voltage for the switching MOSFET, an
external diode can be added between the DBP pin and the BOOST pin of the IC. A small-signal Schottky diode
should be used here, such as the BAT54.
Closing the Feedback Loop, RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2, and CPZ1
A graphical method is used to select the compensation components. This is a standard feed-forward buck
converter. Its PWM gain is given by Equation 44.
V
UVLO
K
^
PWM
1 V
(44)
The ramp voltage is 1 V at the UVLO voltage. Because of the feed-forward compensation, the programmed
UVLO voltage is the voltage that sets the PWM gain.
The gain of the output LC filter is given by Equation 45.
1 ) s ESR COUT
K
+
LC
LOUT
2
1 ) s
) s LOUT COUT
ROUT
(45)
The PWM and LC gain is
G (s) + K K
V
UVLO
1 ) s ESR COUT
c
PWM
LC
1 V
LOUT
2
1 ) s
) s LOUT COUT
ROUT
(46)
To plot this on a Bode plot, the dc gain must be expressed in dB. The dc gain is equal to KPWM. To express
this in dB, take its logarithm and multiply by 20. For this converter, the dc gain is
V
UVLO
DCGAIN + 20 logƪ ƫ+ 20 log(7) + 16.9 dB
V
RAMP
(47)
Also, the pole and zero frequencies should be calculated. A double pole is associated with the LC and a zero is
associated with the ESR of the output capacitor. The frequencies where these occur can be calculated using
equations,
1
f
+
+ 4.3 kHz
LC_Pole
Ǹ
2p LOUT COUT
(48)
(49)
1
f
+
+ 2.1 kHz
ESR_Zero
2p ESR COUT
These are shown in the Bode plot of Figure 31.
30
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
30
20
Double Pole
ESR Zero
10
0
−10
−20
−30
−40
−50
−60
ESR = 0.16 Ω
Slope = –20 dB/Decade
0.1
1
10
f − Frequency − kHz
100
1k
G028
Figure 31. PWM and LC Filter Gain
The next step is to establish the required compensation gain to achieve the desired overall system response.
The target response is to have the crossover frequency between 1/9 and 1/5 times the switching frequency, in
order to have a phase margin greater than 45° and a gain margin greater than 6 dB.
A type-III compensation network, shown in Figure 32, was used for this design. This network gives the best
overall flexibility for compensating the converter.
CPZ1
TPS40077
RP1
VOUT
6
7
8
SS
RZ1
CZ2
FB
CP2
RPZ2
COMP
RSET
S0240-01
Figure 32. Type-III Compensation With the TPS40077
A typical Bode plot for this type of compensation network is shown in Figure 33.
31
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
40
30
High-Frequency Gain
20
10
0
−10
−20
f
f
f
f
P2
Z1
Z2
P1
0.1
1
10
f − Frequency − kHz
100
1k
G029
Figure 33. Type-III Compensation Typical Bode Plot
The high-frequency gain and the break (pole and zero) frequencies are calculated using the following equations.
R
) R
SET
Z1
VOUT + VREF
R
SET
(50)
R
) R
Z1
Z1
P1
P1
GAIN + R
PZ2
R
R
(51)
(52)
1
f
+
P1
2p R C
P1
PZ1
C
) C
Z2
P2
1
f
f
f
+
+
+
[
P2
Z1
Z2
2p R
C C
2p R
C
PZ2
P2
Z2
PZ2 P2
(53)
(54)
1
2p R C
Z1
PZ1
1
1
[
2p R
C
Z2
2p ǒR
Ǔ
C
) R
PZ2
PZ2
P1
Z2
(55)
Looking at the PWM and LC bode plot, there are a few things which must be done to achieve stability.
1. Place two zeros close to the double pole, e.g., fZ1 = fZ2 = 4.3 kHz
2. Place both poles well above the crossover frequency. The crossover frequency was selected as one sixth
the switching frequency, fco1 = 50 kHz, fP1 = 66 kHz
3. Place the second pole at three times fco1. This ensures that the overall system gain falls off quickly to give
good gain margin, fp2 = 150 kHz
4. The high-frequency gain should be sufficient to ensure 0 dB at the required crossover frequency, GAIN =
–1 × gain of PWM and LC at the crossover frequency, GAIN = 16.9 dB
Using these values and Equation 50 through Equation 55, the Rs and Cs around the compensation network can
be calculated.
1. Set RZ1 = 51 kΩ
2. Calculate RSET using Equation 50, RSET = 32.4 kΩ
3. Using Equation 54 and fz1 = 4.3 kHz, CPZ1 can be calculated to be 726 pF, CPZ1= 680 pF
4. fP1 and Equation 52 yields RP1 to be a standard value of 3.3 kΩ.
32
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
5. The required gain of 16.9 dB and Equation 51 sets the value for RPZ2. RPZ2 = 21.5 kΩ.
6. CZ2 is calculated using Equation 55 and the desired frequency for the second zero, CZ2 = 1.7 nF, or using
standard values, 1.8 nF.
7. Finally, CP2 is calculated using the second pole frequency and Equation 53; CP2 = 47 pF.
Using these values, the simulated results are 57° of phase margin at 54 kHz.
Table 4. Bill of Materials
RefDes
C1
Count
Value
470 µF
Description
Size
Part Number
Mfr
Panasonic
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
1
2
1
1
1
1
1
2
1
3
Capacitor, aluminum, 470-µF, 25-V, 20%
Capacitor, ceramic, 25-V, X7R, 20%
Capacitor, ceramic, 25-V, X7R 20%
Capacitor, ceramic, 25-V, X7R, 20%
Capacitor, ceramic, 25-V, X7R 20%
Capacitor, ceramic, 25-V, X7R 20%
Capacitor, ceramic, 25-V, COG 20%
Capacitor, ceramic, 25-V, X7R, 20%
Capacitor, ceramic, 25-V, X7R, 20%
0.457 x 0.406 EEVFK1E471P
C2, C10
C3
0.1 µF
15 nF
47 pF
1.8 nF
680 pF
51 pF
0.1 µF
1 µF
0603
0603
0603
0603
0603
0603
0603
0805
Std
Std
Std
Std
Std
Std
Std
Std
C4
C5
C6
C7
C8, C11
C9
C12, C14,
C15
22 µF
Capacitor, ceramic, 22-µF, 16-V, X5R, 20% 1812
C4532X5R1C226MT TDK
C13
C16
1
1
2.2 nF
Capacitor, ceramic, 25-V, X7R, 20%
0603
Std
Std
Vishay
Panasonic
470 µF
Capacitor, aluminum, SM, 6.3-V, 300-mΩ
8 mm × 10
(FC series)
mm
C17
D1
1
1
2
1
47 µF
Capacitor, ceramic, 47-uF, 6.3-V, X5R, 20% 1812
C4532X5R0J476MT TDK
BAT54
Diode, Schottky, 200-mA, 30-V
SOT23
BAT54
Vishay
J1, J2
J3
ED1609-ND
PTC36SAAN
Terminal block, 2-pin, 15-A, 5,1-mm
0.40 × 0.35
0.100 × 2
ED1609
OST
Header, 2-pin, 100-mil spacing, (36-pin
strip)
PTC36SAAN
Sullins
L1
1
1
2.5 µH
Inductor, SMT, 2.5 µH, 16.5-A, 3.4- mΩ
MOSFET, N-channel, 30-V, 18-A, 8.0-mΩ
0.515 × 0.516 MLC1550-252ML
Coilcraft
Vishay
Q1
Si7860DP
PWRPAK
S0-8
Si7860DP
Q2
1
Si7336ADP
MOSFET, N-channel, 30-V, 18-A, 40-mΩ
PWRPAK
S0-8
Si7886ADP
Vishay
Q3
1
1
2
1
2
1
1
1
1
1
1
1
1
FDV301N
10 kΩ
165 kΩ
32.4 kΩ
0 Ω
MOSFET, N-channel, 25-V, 220-mA, 5-Ω
Resistor, chip, 1/16-W, 20%
Resistor, Chip, 1/16-W, 20%
Resistor, chip, 1/16-W, 20%
Resistor, chip, 1/16-W, 20%
Resistor, chip, 1/16-W, 20%
Resistor, chip, 1/16-W, 20%
Resistor, chip, 1/16-W, 20%
Resistor, chip, 1/16-W, 20%
Resistor, chip, 1/16-W, 20%
Resistor, chip, 1/16-W, 20%
Resistor, chip, 1/16-W, 20%
SOT23
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
PWP16
FDV301N
Fairchild
Std
Std
Std
Std
Std
Std
Std
Std
Std
Std
Std
TI
R1
Std
R2, R6
R3
Std
Std
R4, R11
R5
Std
21.5 kΩ
51 kΩ
3.3 kΩ
1.8 kΩ
330 kΩ
51 Ω
Std
R7
Std
R8
Std
R9
Std
R10
R12
R13
U1
Std
Std
1 kΩ
Std
TPS40077PWP IC, Texas Instruments
TPS40077PWP
33
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
EXAMPLE APPLICATIONS
+
VDD
12 V
R6
165 kW
–
C7
10 pF
R9
2 kW
TPS40077PWP
1
2
3
4
5
6
7
KFF
RT
ILIM 16
R2
165 kW
C12
22 mF
C14
22 mF
C8
0.1 mF
VDD 15
C10 0.1 mF
C2 0.1 mF
L1
LVBP BOOST 14
Pulse
PG0077.202
2 mH
Q1
Si7840BDP
PGD
SGND
SS
HDRV 13
SW 12
D1
BAT54
+
C3 22 nF
C9 1 mF
Q2
Si7856ADP
DBP 11
LDRV 10
VOUT
+
+
1.8 V
10 A
C13
4.7 nF
C15
47 mF
C16
C17
470 mF 470 mF 0.1 mF
C18
FB
C5
5.6 nF
R5
10 kW
8
COMP PGND
PWP
9
–
C4 470 pF
R7 8.66 kW
C6
4.7 nF
R3
5.49 kW
R8
226 W
S0209-01
Figure 34. 300 kHz, 12 V to 1.8 V
34
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
EXAMPLE APPLICATIONS (continued)
+
VDD
12 V
R6
165 kW
–
C7
10 pF
R9
2 kW
TPS40077PWP
1
2
3
4
5
6
7
KFF
RT
ILIM 16
R2
165 kW
C12
22 mF
C14
22 mF
C8
0.1 mF
VDD 15
C10 0.1 mF
C2 0.1 mF
L1
LVBP BOOST 14
Pulse
PG0077.202
2 mH
Q1
Si7840BDP
PGD
SGND
SS
HDRV 13
SW 12
D1
BAT54
+
C3 22 nF
C9 1 mF
Q2
Si7856ADP
DBP 11
LDRV 10
VOUT
+
+
1.8 V
10 A
C13
4.7 nF
C15
47 mF
C16
C17
470 mF 470 mF 0.1 mF
C18
FB
C5
5.6 nF
R5
10 kW
8
COMP PGND
PWP
9
–
C4 470 pF
R7 8.66 kW
C6
4.7 nF
R3
5.49 kW
R8
226 W
S0210-01
See the Boost Diode section.
Figure 35. 300 kHz, 12 V to 1.8 V With Improved High-Side Gate Drive
35
Submit Documentation Feedback
TPS40077
www.ti.com
SLUS714–JANUARY 2007
EXAMPLE APPLICATIONS (continued)
+
VDD
5 V
R6
47 kW
–
C7
10 pF
R9
2 kW
TPS40077PWP
1
2
3
4
5
6
7
KFF
RT
ILIM 16
R2
90.1 kW
C12
22 mF
C14
22 mF
C8
0.1 mF
VDD 15
C10 0.1 mF
C2 0.1 mF
L1
LVBP BOOST 14
Pulse
PG0077.202
2 mH
Q1
Si7860DP
PGD
SGND
SS
HDRV 13
SW 12
D1
BAT54
+
C3 22 nF
C9 1 mF
Q2
Si7860DP
DBP 11
LDRV 10
VOUT
+
+
R4 330 kW
1.2 V
10 A
C13
4.7 nF
C15
47 mF
C16
C17
470 mF 470 mF 0.1 mF
C18
FB
C5
5.6 nF
R5
10 kW
8
COMP PGND
PWP
9
–
C4 470 pF
R7 8.66 kW
C6
4.7 nF
R3
12.1 kW
R8
226 W
Note: Resistor across soft start capacitor.
S0211-01
See the Boost Diode section.
Figure 36. 500 kHz, 5 V to 1.2 V With Improved High-Side Gate Drive
REFERENCES
Related Parts
The following parts are similar to the TPS40077 and may be of interest:
•
•
TPS40190 Low Pin Count Synchronous Buck Controller (SLUS658)
TPS40100 Midrange Input Synchronous Buck Controller With Advanced Sequencing and Output Margining
(SLUS601)
•
•
TPS40075 Midrange Input Synchronous Buck Controller With Voltage Feed-Forward (SLUS676)
TPS40057 Wide-Input Synchronous Buck Controller (SLUS593)
36
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
PACKAGING INFORMATION
Orderable Device
TPS40077PWP
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
PWP
16
16
16
16
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS40077PWPG4
TPS40077PWPR
TPS40077PWPRG4
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
TPS40077PWPR
PWP
16
TAI
330
12
6.67
5.4
1.6
8
12 PKGORN
T1TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
TAI
Length (mm) Width (mm) Height (mm)
TPS40077PWPR
PWP
16
346.0
346.0
61.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
相关型号：
TPS40077_07
HIGH-EFFICIENCY, MIDRANGE-INPUT, SYNCHRONOUS BUCK CONTROLLER WITH VOLTAGE FEED-FORWARD
TI
©2020 ICPDF网 联系我们和版权申明