TPS40100RGERG4 [TI]
Wide Input Range Synchronous Buck Controller for Sequencing 24-VQFN -40 to 85;
| 型号： | TPS40100RGERG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Wide Input Range Synchronous Buck Controller for Sequencing 24-VQFN -40 to 85 开关 |
| 文件： | 总39页 (文件大小：920K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS40100
www.ti.com
SLUS601–MAY 2005
MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER
WITH ADVANCED SEQUENCING AND OUTPUT MARGINING
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
Servers
•
Operation over 4.5 V to 18 V Input Range
Networking Equipment
Cable Modems and Routers
XDSL Modems and Routers
Set-Top Boxes
Telecommunications Equipment
Power Supply Modules
•
Adjustable Frequency (Between 100 kHz and
600 kHz) Current Feedback Control
•
•
Output Voltage Range From 0.7 V to 5.5 V
Simultaneous, Ratiometric and Sequential
Startup Sequencing
•
•
•
•
•
•
•
•
•
•
•
Adaptive Gate Drive
Remote Sensing (Via Separate GND/PGND)
Internal Gate Drivers for N-channel MOSFETs
Internal 5-V Regulator
24-Pin QFN Package
Thermal Shutdown
Programmable Overcurrent Protection
Power Good Indicator
1%, 690-mV Reference
Output Margining, 3% and 5%
Programmable UVLO (with Programmable
Hysteresis)
DESCRIPTION
The TPS40100 is a mid voltage, wide-input (between
4.5 V and 18 V), synchronous, step-down controller.
The TPS40100 offers programmable closed loop
soft-start, programmable UVLO (with programmable
hysteresis), programmable inductor sensed current
limit and can be synchronized to other timebases.
The TPS40100 incorporates MOSFET gate drivers
for external N-channel high-side and synchronous
rectifier (SR) MOSFET. Gate drive logic incorporates
adaptive anti-cross conduction circuitry for improved
efficiency, reducing both cross conduction and diode
conduction in the rectifier MOSFET. The externally
•
Frequency Synchronization
programmable current limit provides
overcurrent recovery characteristic.
a
hiccup
TYPICAL APPLICATION
V
IN
24
23
22
21
20
19
1
2
3
4
5
6
COMP
FB
18
VDD
SW 17
HDRV 16
BST 15
TRKOUT
TRKIN
UVLO
TPS40100
V
TRKIN
V
IN
5VBP 14
LDRV 13
ILIM
7
8
9
10
11
12
UDG−04137
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TPS40100
www.ti.com
SLUS601–MAY 2005
ORDERING INFORMATION
TA
PACKAGE
PART NUMBER(1)
TPS40100RGER
TPS40100RGET
-40°C to 85°C
QFN
(1) The QFN package (RGE) is available taped and reeled only. Use
large reel device type R (TPS40100RGER) to order quantities of
3,000 per reel. Use small reel device type T (TPS40100RGET) to
order quantities of 250 per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS40100
UNIT
VDD
-0.3 to 20
5VBP, BIAS, FB, ILIM, ISNS, LDRV, MGU, MGD, PG, SS,
SYNC, UVLO, VO
-0.3 to 6
BST to SW, HDRV to SW(2)
-0.3 to 6.0
-1.5 to VVIN
-6 to 30
-0.3 to 20
-0.3 to 0.3
-0.3 to 8.0
0.5
SW
VIN
Input voltage range
V
SW (transient) < 100 ns
TRKIN
GND to PGND
TRKOUT
HDRV, LDRV (RMS)
A
HDRV, LDRV (peak)
2.0
FB, COMP, TRKOUT
10 to -10
20 to -20
20
mA
SS
IIN
Input current range
PG
GM
1
mA
RT
10
V5BP
RT source
50(3)
100
µA
°C
TJ
Operating junction temperature range
Storage temperature
–40 to 125
–55 to 150
Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) BST to SW and HDRV to SW are relative measurements. BST and HDRV can be this amount of voltage above or below the voltage at
SW.
(3) V5BP current includes gate drive current requirements. Observe maximum TJ rating for the device.
2
TPS40100
www.ti.com
SLUS601–MAY 2005
ELECTRICAL CHARACTERISTICS
-40°C ≤ TA = TJ≤ 85°C, VVDD = 12 V, RRT = 182 kΩ, RGM = 232 kΩ, RILIM = 121 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT VOLTAGE
VVDD Operating range
OPERATING CURRENT
4.5
18.0
2.5
V
IDD
Quiescent current
VFB > 0.8 V, 0% duty cycle
VUVLO < 1 V
1.3
1.8
mA
µA
ISD
Shutdown current
500
5VPB
7 V ≤ VVDD≤ 18 V, 0 mA ≤ ILOAD≤ 30 mA
4.5 V ≤ VVDD < 7 V, 0 mA ≤ ILOAD≤ 30 mA
4.7
4.3
5.0
5.0
5.3
5.3
Internal regulator
V
OSCILLATOR/RAMP GENERATOR
fSW
Programmable oscillator frequency
100
250
600
300
kHz
4.5 V ≤ VVDD < 18 V,
-40°C ≤ TA = TJ≤ 125°C
Oscillator frequency accuracy
275
VRAMP
tOFF
Ramp amplitude(1)
0.5
VP-P
ns
Fixed off-time
100
150
0%
175
2.0
DMIN
tMIN
Minimum duty cycle
Minimum controllable pulse width(1)
Valley voltage(1)
CLOAD = 4.7 nF, -40°C ≤ TA = TJ≤ 125°C
ns
V
VVLY
1.0
2
1.6
5.5
FREQUENCY SYNCHRONIZATION
VIH
High-level input voltage
V
VIL
Low-level input voltage
0.8
ISYNC
tSYNC
tSYNC_SH
Input current, SYNC
VSYNC = 2.5 V
4.0
50
10.0
µA
ns
Mimimum pulse width, SYNC
Minimum set-up/hold time, SYNC(2)
100
SOFT-START AND FAULT IDLE
ISS
Soft-start source (charge) current
13
3.4
20
5.0
25
6.6
µA
V
ISS_SINK
VSSC
VSSD
Soft-start sink (discharge) current
Soft-start completed voltage
3.25
0.15
16
3.40
0.20
3.75
0.25
Soft-start discharged voltage
Retry interval time to SS time ratio(1)
VSSOS
Offset from SS to error amplifier
300
500
800
mV
ERROR AMPLIFIER
GBWP
AVOL
IBIAS
IOH
Gain bandwidth product(1)
3.5
60
5.0
80
50
3
MHz
dB
Open loop
Input bias current, FB
High-level output current
Low-level output current
Slew rate(1)
200
nA
2
2
mA
IOL
3
2.1
V/µs
FEEDBACK REFERENCE
TA =25°C
686
683
690
694
697
VFB
Feedback voltage reference
mV
-40°C < TA = TJ≤ 125°C
(1) Ensured by design. Not production tested.
(2) To meet set up time requirements for the synchronization circuit, a negative logic pulse must be greater than 100 ns wide.
3
TPS40100
www.ti.com
SLUS601–MAY 2005
ELECTRICAL CHARACTERISTICS (continued)
-40°C ≤ TA = TJ≤ 85°C, VVDD = 12 V, RRT = 182 kΩ, RGM = 232 kΩ, RILIM = 121 kΩ (unless otherwise noted)
PARAMETER
VOLTAGE MARGINING
TEST CONDITIONS
MIN
TYP
MAX UNIT
Feedback voltage margin 5% up
Feedback voltage margin 3% up
Margin-up bias current
V
MGU ≤ 500 mV
715
700
60
725
711
80
735
mV
720
VFBMGU
IMGUP
2 V ≤ VMGU ≤ 3 V
100
665
680
100
30
µA
mA
µA
ms
Feedback voltage margin 5% down
Feedback voltage margin 3% down
Margin-down bias current
VMGD ≤ 500 mV
645
660
60
655
669
80
VFBMGD
2 V ≤ VMGD ≤ 3 V
IMGDN
tMGDLY
tMGTRAN
Margining delay time(3)
12
Margining transition time
1.5
300
-50
7.0
CURRENT SENSE AMPLIFIER
gmCSA
TCGM
VGMLIN
IISNS
Current sense amplifier gain
TJ =25°C
333
365
µS
ppm/°C
mV
Amplifier gain temperature coefficient
Gm linear range voltage
-2000
TJ =25°C
50
250
6
Bias current at ISNS pin
VVO = VISNS = 3.3 V
nA
0
0
VGMCM
Input voltage common mode
V
4.5 V ≤ VIN ≤ 5.5 V
3.6
CURRENT LIMIT
VILIM
ILIM pin voltage to trip overcurrent
Current limit comparator propagation delay
1.44
1.48
70
1.52
140
V
tILIMDLY
HDRV transition from on to off
ns
DRIVER SPECIFICATIONS
tRHDRV
HIgh-side driver rise time(4)
tFHDRV
HIgh-side driver fall time(4)
IHDRVSRPKS HIgh-side driver peak source current(4)
CLOAD = 4.7 nF
CLOAD = 4.7 nF
57
47
ns
mA
A
800
700
1.3
1.2
2.4
1.0
57
IHDRVSRMIL
IHSDVSNPK
IHDRVSNMIL
RHDRVUP
RHDRVDN
tRLDRV
HIgh-side driver source current at 2.5 V(4)
HIgh-side driver peak sink current(4)
High-side driver sink current at 2.5 V(4)
HIgh-side driver pullup resistance
HIgh-side driver pulldown resistance
Low-side driver rise time(4)
VHDRV - VSW = 2.5 V
VHDRV - VSW = 2.5 V
IHDRV = 300 mA
IHDRV = 300 mA
CLOAD = 4.7 nF
CLOAD = 4.7 nF
4.0
1.8
Ω
ns
mA
A
tFLDRV
Low-side driver fall time(4)
47
ILDRVSRPK
ILDRVSNMIL
ILSDVSNPK
Low-side driver peak source current(4)
Low-side driver source current at 2.5 V(4)
Low-side driver peak sink current(4)
Low-side driver sink current at 2.5 V(4)
Low-side driver pullup resistance
Low-side driver pulldown resistance
Leakage current from SW pin
800
700
1.3
1.2
2.0
0.8
VLDRV = 2.5 V
VLDRV = 2.5 V
ILDRV = 300 mA
ILDRV = 300 mA
RLDRVUP
RLDRVDN
ISWLEAK
4.0
1.5
1
Ω
-1
µA
POWERGOOD
VLPGD Powergood low voltage
tPGD
IPGD= 2 mA
30
25
100
35
mV
µs
Powergood delay time
15
VVDD = OPEN, 10-kΩ pullup to external
5-V supply
VLPGDNP
Powergood low voltage , no device power
1.00
1.25
V
VOV
VUV
Power good overvoltage threshold, VFB
Power good undervoltage threshold, VFB
765
615
mV
(3) Margining delay time is the time delay from an assertion of a margining command until the output voltage begins to transition to the
margined voltage.
(4) Ensured by design. Not production tested.
4
TPS40100
www.ti.com
SLUS601–MAY 2005
ELECTRICAL CHARACTERISTICS (continued)
-40°C ≤ TA = TJ≤ 85°C, VVDD = 12 V, RRT = 182 kΩ, RGM = 232 kΩ, RILIM = 121 kΩ (unless otherwise noted)
PARAMETER
TRACKING AMPLIFIER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VTRKOS = VTRKIN - VO ; VVO≤ 2 V
7
-5
25
25
40
VTRKOS
VTRKCM
VTRK
Tracking amplifier input offset voltage
Input common mode, active range
Tracking amplifier voltage range
mV
40
VTRKOS = VTRKIN - VO ; 2 V < VVO≤ 6 V
0
6
4.5 V ≤ VVDD ≤ 5.5 V
5 V < VVDD ≤ 18 V(5)
0
3.6
0
6
V
V
VDD = 12 V
VDD = 4.5 V
5.0
3.2
0
6.5
3.6
8.0
VHTKROUT
VLTKROUT
High-level output voltage, TRKOUT
Low-level output voltage, TRKOUT
V
0.5
mA
ISRCTRKOUT Source current, TRKOUT
ISNKTRKOUT Sink current, TRKOUT
0.65
1
2.00
2
VTRKDIF
Differential voltage from TRKIN to VO
18
V
GBWPTRK
AVOLTRK
Tracking amplifier gain bandwidth product(6)
Tracking amplifier open loop DC gain(6)
1
MHz
dB
60
PROGRAMMABLE UVLO
VUVLO Undervoltage lockout threshold
IUVLO Hysteresis current
INTERNALLY FIXED UVLO
1.285 1.332 1.378
9.0 10.0 10.8
V
µA
VUVLOFON
VUVLOFOFF
VUVLOHYST
Fixed UVLO turn-on voltage at VDD pin
-40°C ≤ TA < 125°C
3.850 4.150 4.425
V
Fixed UVLO turn-off voltage at VDD pin
UVLO hysteresis at VDD pin
3.75
130
4.06
85
4.35
mV
THERMAL SHUTDOWN
TSD
Thermal shutdown temerature(6)
Hysteresis(6)
165
25
°C
TSDHYST
(5) Amplifier can track to the lesser of 6 V or (VDD × 0.95)
(6) Ensured by design. Not production tested.
DEVICE INFORMATION
RGE PACKAGE
(BOTTOM VIEW)
1
2
3
4
5
6
MGU
MGD
SYNC
PG
24
7
8
9
RT
23
22
21
20
19
BIAS
GND
SS
10
11
12
VO
GM
ISNS
PGND
18 17 16 15 14 13
5
TPS40100
www.ti.com
SLUS601–MAY 2005
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Output of an internal 5-V regulator. A 1-µF bypass capacitor should be connected from this
pin to PGND. Power for external circuitry may be drawn from this pin. The total gate drive
current and external current draw should not cause the device to exceed thermal capabilities
5VBP
14
O
O
I
The bypassed supply for internal device circuitry. Connect a 0.1-µF or greater ceramic
capacitor from this pin to GND.
BIAS
BST
8
15
1
Gate drive voltage for the high-side N-channel MOSFET. An external diode must be
connected from 5VBP (A) to BST(K). A schottky diode is recommended for this purpose. A
capacitor must be connected from this pin to the SW pin.
Output of the error amplifier. A feedback network is connected from this pin to the FB pin for
control loop compensation.
COMP
O
Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to
the internal reference voltage (approximately 690 mV).
FB
2
11
9
I
I
GM
Connect a resistor from this pin to GND to set the gain of the current sense amplifier.
Low power or signal ground for the device. All signal level circuits should be referenced to
this pin unless otherwise noted.
GND
HDRV
-
16
O
Floating gate drive for the high side N-channel MOSFET.
Current limit pin used to set the overcurrent threshold and transient ride out time. An internal
current source that is proportional to the inductor current sets a voltage on a resistor
connected from this pin to GND. When this voltage reaches 1.48 V, an overcurrent condition
is declared by the device. Adding a capacitor in parallel with the resistor to GND sets a time
delay that can be used to help avoid nuisance trips.
ILIM
6
O
Input from the inductor DCR sensing network. This input signal is one of the inputs to the
current sense amplifier for current feedback control and overcurrent protection
ISNS
19
13
I
LDRV
O
Gate drive for the N-channel synchronous rectifier.
Margin down pin used for load stress test. When this pin is pulled to GND through less than
10 kΩ, the output voltage is decreased by 5%. The 3% margin down at the output voltage is
accommodated when this pin is connected to GND through a 30-kΩ resistor.
MGD
MGU
PG
23
24
21
I
I
Margin up pin used for load stress test. When this pin is pulled to GND through less than 10
kΩ, the output voltage is increased by 5%. The 3% margin up at the output voltage is
accommodated when this pin is connected to GND through a 30-kΩ resistor.
Open drain power good output for the device. This pin is pulled low when the voltage at the
FB pin is more than 10% higher or lower than 690 mV, a UVLO condition exists, soft-start is
active, tracking is active, an overcurrent condition exists or the die is over temperature.
O
PGND
RT
12
7
-
I
Power ground for internal drivers
A resistor connected from this pin to GND sets operating frequency.
Soft-start programming pin. A capacitor connected from this pin to ground programs the
soft-start time. This pin is also used as a time out function during an overcurrent event.
SS
10
17
I
I
Connected to the switched node of the converter. This pin is the return line for the flying high
side driver.
SW
Rising edge triggered synchronization input for the device. This pin can be used to
synchronize the oscillator frequency to an external master clock. This pin may be left floating
or grounded if the function is not used.
SYNC
TRKIN
22
4
I
I
Control input allowing simultaneous startup of multiple controllers. The converter output
tracks TRKIN voltage with a small controlled offset (typically 25 mV) when the tracking
amplifier is used. See application secttion for more information.
Output of the tracking amplifier. If the tracking feature is used, this pin should be connected
to FB pin through a resistor in series with a diode. The resistor value can be calculated from
the equivalent impedance at the FB node. The diode should be a low leakage type to
minimize errors due to diode reverse current. For further information on compensation of the
tracking amplifier refer to the application information
TRKOUT
3
O
Provides for programming the undervoltage lockout level and serves as a shutdown input for
the device.
UVLO
VDD
VO
5
I
I
I
18
20
Supply voltage for the device.
Output voltage. This is the reference input to the current sense amplifier for current mode
control and overcurrent protection.
6
TPS40100
www.ti.com
SLUS601–MAY 2005
FUNCTIONAL BLOCK DIAGRAM
RT
7
SYNC
22
UVLO
5
TPS40100
UVLO
15 BST
16 HDRV
17 SW
+
Oscillator
1.33 V
CLK
10 µA
COMP
FB
1
2
PWM
Adaptive
Gate
Drive
and
Prebias
Control
20 kΩ
SS
+
+
OC
FAULT
CLK
0.725 V
14 5VBP
13 LDRV
12 PGND
MGU 24
MGD 23
0.711 V
0.690 V
0.669 V
0.655 V
+
Reference
Select
+
OC
ISNS 19
VO 20
1.48 V
+
Current
Mirror
21 PG
THERMSD
Reference
Voltages
1.5 V
+
OC/SS
Controller
CLK
OC
FAULT
GM 11
TRKOUT
TRKIN
3
4
Housekeeping
18 VDD
+
6
10
8
9
UDG−04142
ILIM
SS
BIAS
GND
7
TPS40100
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SLUS601–MAY 2005
APPLICATION INFORMATION
Introduction
The TPS40100 is a synchronous buck controller targeted at applications that require sequencing and output
voltage margining features. This controller uses a current feedback mechanism to make loop compensation
easier for loads that can have wide capacitance variations. Current sensing (for both current feedback and
overcurrent) is true differential and can be done using the inductor DC resistance (with a R-C filter) or with a
separate sense resistor in series with the inductor. The overcurrent level is programmable independently from
the amount of current feedback providing greater application flexibility. Likewise, the overcurrent function has
user programmable integration to eliminate nuisance tripping and allow the user to tailor the response to
application requirements. The controller provides an integrated method to margin the output voltage to ± 3% and
± 5% of its nominal value by simply grounding one of two pins directly or through a resistance. Powergood and
clock synchronization functions are provided on dedicated pins. Users can program operating frequency and the
closed loop soft-start time by means of a resistor and capacitor to ground respectively. Output se-
quencing/tracking can be accomplished in one of three ways: sequential (one output comes up, then a second
comes up), ratiometric (one or more outputs reach regulation at the same time – the voltages all follow a
constant ration while starting) and simultaneous (one or more outputs track together on startup and reach
regulation in order from lowest to highest).
Programming Operating Frequency
Operating frequency is set by connecting a resistor to GND from the RT pin. The relationship is:
R +ȡ* 3.98 10
4
ȣ
4
5.14 10
) ǒ Ǔ* 8.6 (kW)
ȧ
ȧ
T
2
f
SW
f
Ȣ
Ȥ
SW
(1)
where
•
fSW is the switching frequency in kHz
•
RT is in kΩ
Figure 1 and Figure 2 show the relationship between the switching frequency and the RT resistor as described in
Equation 1. The scaling is different between them to allow the user a more accurate views at both high and low
frequency.
8
TPS40100
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SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
TIMING RESISTOR
vs
SWITCHING FREQUENCY
(250 kHz to 600 kHz)
TIMING RESISTOR
vs
SWITCHING FREQUENCY
(100 kHz to 350 kHz)
225
200
175
150
550
500
450
400
350
300
250
125
100
200
150
100
75
50
250
300
350
400
450
500
550
600
100
150
200
250
300
350
f − Switching Frequency − kHz
f
SW
− Switching Frequency − kHz
Figure 1.
Figure 2.
Selecting an Inductor Value
The inductor value determines the ripple current in the output capacitors and has an effect on the achievable
transient response. A large inductance decreases ripple current and output voltage ripple, but is physically larger
than a smaller inductance at the same current rating and limits output current slew rate more that a smaller
inductance would. A lower inductance increases ripple current and output voltage ripple, but is physically smaller
than a larger inductance at the same current rating. For most applications, a good compromise is selecting an
inductance value that gives a ripple current between 20% and 30% of the full load current of the converter. The
required inductance for a given ripple current can be found from:
ǒV
Ǔ
V
DI
SW
* V
IN
OUT
OUT
L +
(H)
V
f
IN
(2)
where
•
•
•
•
•
L is the inductance value (H)
V
V
IN is the input voltage to the converter (V)
OUT is the output voltage of the converter (V)
fSW is the switching frequency chosen for the converter (Hz)
∆I is the peak-to-peak ripple current in the inductor (A)
Selecting the Output Capacitance
The required value for the output capacitance depends on the output ripple voltage requirements and the ripple
current in the inductor, as well as any load transient specifications that may exist.
The output voltage ripple depends directly on the ripple current and is affected by two parameters from the
output capacitor: total capacitance and the capacitors equivalent series resistance (ESR). The output ripple
voltage (worst case) can be found from:
9
TPS40100
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SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
1
DV + DI ESR )
ǒ
Ǔ
(V)
ƪ
ƫ
8 C
f
SW
OUT
(3)
where
•
•
•
•
•
∆V is the peak to peak output ripple voltage (V)
∆I is the peak-to-peak ripple current in the inductor (A)
fSW is the switching frequency chosen for the converter (Hz)
COUT is the capacitance value of the output capacitor (F)
ESR is the equivalent series resistance of the capacitor, COUT (Ω)
For electrolytic capacitors, the output ripple voltage is almost entirely (90% or more) due to the ESR of the
capacitor. When using ceramic output capacitors, the output ripple contribution from ESR is much smaller and
the capacitance value itself becomes more significant. Paralleling output capacitors to achieve a desired output
capacitance generally lowers the effective ESR more effectively than using a single larger capacitor. This
increases performance at the expense of board area.
If there are load transient requirements that must be met, the overshoot and undershoot of the output voltage
must be considered. If the load suddenly increases, the output voltage momentarily dips until the current in the
inductor can ramp up to match the new load requirement. If the feedback loop is designed aggressively, this
undershoot can be minimized. For a given undershoot specification, the required output capacitance can be
found by:
2
L I
STEP
C
+
(F)
O(under)
ǒV OUTǓ
* V
IN
2 V
D
UNDER
MAX
(4)
where
•
•
•
•
•
•
•
CO(under) is the output capacitance required to meet the undershoot specification (F)
L is the inductor value (H)
I
STEP is the change in load current (A)
UNDER is the maximum allowable output voltage undershoot
MAX is the maximum duty cycle for the converter
VIN is the input voltage
OUT is the output voltage
V
D
V
Similarly, if the load current suddenly goes from a high value to a low value, the output voltage overshoots. The
ouput voltage rises until the current in the inductor drops to the new load current. The required capacitance for a
given amount of overshoot can be found by:
2
L I
STEP
C
+
(F)
O(over)
2 V
V
OVER
OUT
(5)
where
•
•
•
•
•
CO(over) is the output capacitance required to meet the undershoot specification (F)
L in the inductor value (H)
ISTEP is the change in load current (A)
V
V
OVER is the maximum allowable output voltage overshoot
OUT is the output voltage
The required value of output capacitance is the maximum of CO(under) and CO(over)
.
Knowing the inductor ripple current, the switching frequency, the required load step and the allowable output
voltage excursion allows calculation of the required output capacitance from a transient response perspective.
The actual value and type of output capacitance is the one that satisfies both the ripple and transient
specifications.
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APPLICATION INFORMATION (continued)
Calculating the Current Sense Filter Network
The TPS 40100 gets current feedback information by sensing the voltage across the inductor resistance, RLDC. In
order to do this, a filter must be constructed that allows the sensed voltage to be representative of the actual
current in the inductor. This filter is a series R-C network connected across the inductor as shown in Figure 3.
To ISNS pin
V
IN
To VO pin
R
FLT
C
FLT
100 Ω
L
R
LDC
V
O
C
O
UDG−04150
Figure 3. Current Sensing Filter Circuit
If the RFLT-CFLT time constant is matched to the L/RLDC time constant, the voltage across CFLT is equal to the
voltage across RLDC. It is recommended to keep RFLT 10 kΩ or less. CFLT can be arbitrarily chosen to meet this
condition (100 nF is suggested). RFLT can then be calculated.
L
C
R
+
* 100 (W)
FLT
R
LDC
FLT
(6)
where
•
•
•
•
RFLT is the current sense filter resistance (Ω)
FLT is the current sense filter capacitance (F)
L is the output inductance (H)
C
RLDC is the DC resistance of the output inductor (Ω)
When laying out the board, better performance can be accomplished by locating CFLT as close as possible to the
VO and ISNS pins. The closer the two resistors can be brought to the device the better as this reduces the
length of high impedance runs that are susceptible to noise pickup. The 100-Ω resistor from VOUT to the VO pin
of the device is to limit current in the event that the output voltage dips below ground when a short is applied to
the output of the converter.
Compensation for Inductor Resistance Change Over Temperature
The resistance in the inductor that is sensed is the resistance of the copper winding. This value changes over
temperature and has approximately a 4000 ppm/°C temperature coefficient. The gain of current sense amplifier
in the TPS40100 has a built in temperature coefficient of approximately -2000 ppm/°C. If the circuit is physically
arranged so that there is good thermal coupling between the inductor and the device, the thermal shifts tend to
offset. If the thermal coupling is perfect, the net temperature coefficient is 2000 ppm/°C. If the coupling is not
perfect, the net temperature coefficient lies between 2000 ppm/°C and 4000 ppm/°C. For most applications this is
sufficient. If desired, the temperature drifts can be compensated for. The following compensation scheme
assumes that the temperature rise at the device is directly proportional to the temperature rise at the inductor. If
this is not the case, compensation accuracy suffers. Also, there is generally a time lag in the temperature rise at
the device vs. at the inductor that could introduce transient errors beyond those predicted by the compensation.
Also, the 100-Ω resistor in Figure 3 is not shown. However, it is required if the output voltage can dip below
ground during fault conditions. The calculations are not afffected, other than increasing the effective value of RF1
by 100-Ω.
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APPLICATION INFORMATION (continued)
The relative resistance change in the inductor is given by:
+ 1 ) TC ǒT * TBASEǓ
R
(dimensionless)
REL(L)
L
L
(7)
where
•
•
•
•
RREL(L) is the relative resistance of the inductor at TL compared to the resistance at TBASE
TCL is the temperature coefficient of copper, 4000 ppm/°C or 0.004
TL is the inductor copper temperature (°C)
TBASE is the reference temperature, typically lowest ambient (°C)
The relative gain of the current sense amplifier is given by a similar equation:
ǒT
* T
IC
BASEǓ
(dimensionless)
gm
+ 1 ) TC
(REL)
GM
(8)
where
•
•
•
•
gmREL is the relative gain of the amplifier at TIC compared to the gain at TBASE
TCGM is the temperature coefficient of the amplifier gain, -2000 ppm/°C or -0.002
TIC is the device junction temperature (°C)
TBASE is the reference temperature, typically lowest ambient (°C)
The temperature rise of the device can usually be related to the temperature rise of the inductor. The relationship
between the two temperature rises can be approximated as a linear relationship in most cases:
+ ǒT * T
Ǔ
k
T
* T
IC
BASE
L
BASE
THM
(9)
where
•
•
•
•
TIC is the device junction temperature (°C)
BASE is the reference temperature, typically lowest ambient (°C)
TL is the inductor copper temperature (°C)
kTHM is the constant that relates device temperature rise to the inductor temperature rise and must be
determined experimentally for any given design
T
With these assumptions, the effective inductor resistance over temperature is:
ƪ
ǒ
Ǔƫ ƪ
ǒ
Ǔƫ
RREL(eff) + RREL(L) gmREL + 1 ) TCL TL * TBASE 1 ) kTHM TCGM TL * TBASE (dimensionless)
(10)
RREL(eff) is the relative effective resistance that must be compensated for when doing the compensation. The
circuit of Figure 4 shows a method of compensating for thermal shifts in current limit. The NTC thermistor (RNTC
)
must be well coupled to the inductor. CFLT should be located as close to the device as possible.
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APPLICATION INFORMATION (continued)
VO
20
ILIM
6
ISNS
19
+
−2000 ppm/°C
R
ILIM
R
THE
R
F3
R
F2
R
NTC
V
IN
C
FLT
R
F1
L
R
LDG
V
OUT
C
OUT
UDG−04148
Figure 4. Compensation for Temperature Coefficient of the Inductor Resistance
The first step is to determine an attenuation ratio α. This ratio should be near to 1 but not too close. If it is too
close to 1, the circuit requires large impedances and thermistor values too high. If α is too low, the current signal
is attenuated unnecessarily. A suggested value is 0.8.
R
THE
) R
a ^ 0.8
(dimensionless)
R
THE
F1
(11)
RTHE is the equivalent resistance of the RF2-RF3-RNTC network:
R
R
) R
F3
F3
NTC
NTC
R
+ R
)
F2
(W)
THE
R
(12)
The base temperature (TBASE) should be selected to be the lowest temperature of interest for the thermal
matching – the lowest ambient expected. The resistance of the inductor at this base temperature should be used
to calculate effective resistance. The expected current sense amplifier gain at TBASE should be used for
calculating over current components (RILIM).
The next step is to decide at what two temperatures the compensation is matched to the response of the
deviceand inductor copper, T1 and T2. Once these are chosen, an NTC thermistor can be chosen and its value
found from its data sheet at these two temperatures: RNTC(T1) and RNTC(T2). The component values in the network
can be calculated using the following equations:
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APPLICATION INFORMATION (continued)
L
R
+
(W)
F1
R
LDC(Tbase) C
a
FLT
(13)
(14)
(15)
R
R
+ R
R
R
(W)
(W)
LDC(T1)
LDC(T2)
LDC(Tbase)
REL(effT1)
+ R
LDC(Tbase)
REL(effT2)
a R
R
LDC(Tbase)
F1
R
R
+
(W)
(W)
THE(T1)
THE(T2)
R
R
* a R
LDC(T1)
LDC(Tbase)
(16)
(17)
a R
R
LDC(Tbase)
F1
+
* a R
LDC(T2)
LDC(Tbase)
R
* R
NTC(T1)
THE(T1)
) R
NTC(T2)
THE(T2)
(W)
a + 1 *
b + R
(dimensionless)
R
* R
(18)
(19)
NTC(T1)
NTC(T1)
NTC(T2)
NTC(T2)
2
c + R
R
(W )
(20)
(21)
Ǹ
2a
2
* b " b * 4ac
R
R
+
+
(W)
F3
F2
ǒR
NTC(T1)Ǔ * R
) R
R
) R
R
F3 NTC(T1)
THE(T1)
F3
(W)
R
F3
NTC(T1)
(22)
where
•
•
•
•
•
•
•
•
L is the value of the output inductance (H)
FLT is the value of the current sense filter capacitor (F)
α is the attenuation ratio chosen from Equation 11
C
R
R
R
R
R
THE(T1), RTHE(T2) are the equivalent resistances of the RTHE network at temperatures T1 and T2
LDC(Tbase) is the DC resistance of the inductor at temperature TBASE in Ω
LDC(T1), RLDC(T2) are the inductor resistances at temperatures T1 and T2
REL(effT1), RREL(effT2), are the relative resistances of the inductor at T1 and T2 vs. Tbase
NCT(T1), RNTC(T2) are the effective resistance of the NTC thermistor at temperatures T1 and T2
Establishing Current Feedback
The amount of current feedback in a given application is programmable by the user. The amount of current
feedback used is intended to be just enough to reduce the Q of the output filter double pole. This allows design
of a converter control loop that is stable for a very wide range of output capacitance. Setting the current feedback
higher offers little real benefit and can actually degrade load transient response, as well as introduce pulse
skipping in the converter. The current feedback is adjusted by setting the gain of the current sense amplifier. The
amplifier is a transconductance type and its gain is a set by connecting a resistor from the GM pin to GND:
3
R
+
(W)
GM
2
*6
43.443 gm
) 0.01543 gm
) 3.225 10
CSA
CSA
(23)
where
•
RGM is the resistor that sets the gain of the amplifier (Ω)
•
gmCSA is the gain of the current sense amplifier (S)
The value of the sense amplifier gain should be less than 1000 µS, and more than 250 µS, with the resulting
gain setting resistor greater than 50 kΩ. As a suggested starting point, set the gain of the current sense amplifier
to a nominal 280 µS with RGM of 279 kΩ. This value should accommodate most applications adequately.
Figure 5 shows the current sense amplifier gain setting resistance vs. the sense amplifier gain.
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TPS40100
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SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
CURRENT SENSE AMPLIFIER GAIN SETTING RESISTANCE
vs
CURRENT SENSE AMPLIFIER GAIN
325
275
225
175
125
75
25
250
400
550
700
850
1000
gm − Sense Amplifier Transconductance − µS
Figure 5.
Control to Output Gain of the Converter
A model that gives a good first order approximation to the control to output gain of a converter based on the
TPS40100 controller is shown in Figure 6. This model can be used in conjunction with a simulator to generate ac
and transient response plots. The block labeled “X2” is a simple gain of 2. The amplifier gm can be a simple
voltage controlled current source with a gain equal to the selected gm for the current sense amplifier (CSA).
Analytically, the control to output gain of this model ( Figure 6) can be expressed as follows:
V
K
K
(s)
IN
PWM
FILT
K
(s) +
(dimensionless)
CO
1 ) Y(s) K K
V
IN
CS
PWM
(24)
KFILT(s) is the output filter transfer function:
KFILT(s) =
RLOAD
RLDC ) RLOAD
RESR COUT s ) 1
ǒ
Ǔ
L)COUT RLOAD RESR)RLDC RLOAD)RLDC RESR
L COUT)RLOAD
RLDC)RLOAD
s2 )
s ) 1
RLOAD
(25)
(dimensionless)
Usually, RLDC << RLOAD and the following approximation holds:
C s ) 1
R
ESR
OUT
K
(s) +
FILT
ǒ
LDCǓ
)R
ESR
L)R
C
R
LOAD
OUT
2
s ) ƪ
ƫ
L C
s ) 1
OUT
R
LOAD
(26)
Y(s) is the current signal transfer function and assumes that the inductor intrinsic time constant is matched to the
current sense filter network time constant.
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SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
1 * K
(s)
FILT
Y(s) +
(dimensionless)
L
s ) 1
R
LDC
(27)
(28)
KCS is the gain of the current sense amplifier in the current feedback loop:
+ gm 20 kW (dimensionless)
K
CS
CSA
where (for Equation 24 through Equation 28)
•
•
•
•
•
•
•
•
•
VIN is the input voltage (V)
KPWM is the gain of the pulse width modulator and is equal to 2
RLOAD is the equivalent load resistance (Ω)
RLDC is the DC inductor resistance (Ω)
L is the output filter inductance (H)
COUT is the output filter capacitance (F)
RESR is the equivalent series resistance of the output filter capacitor (Ω)
gmCSA is the gain of the current sense amplifier (S)
20 kΩ is the impedance the current sense amplifier works against (from block diagram)
A computer aided math tool is highly recommended for use in evaluating these equations.
L
R
LDC
V
OUT
V
IN
C
FLT
R
FLT
+
C
OUT
X2
R
LOAD
R
ESR
ISNS
gm
CSA
VO
+
C
1
C
2
R
2
R
EA
R
1
FB
V
X
20 kΩ
COMP
+
1 V AC
R
BIAS
+
690 mV
UDG−04149
Figure 6. Averaged Model for a Converter Based on the TPS40100
Compensating the Loop (Type II)
The first step is to select a target loop crossover frequency. Choosing the crossover frequency too high
contributes to making the converter pulse skip. A balance of crossover frequency and amount of current
feedback must be maintained to avoid pulse skipping. A suggested maximum loop crossover frequency is one
fifth-of the switching frequency.
f
SW
5
f
v
(Hz)
C
(29)
where
•
fC is the loop crossover frequency
SW is the switching frequency
•
f
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TPS40100
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SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
Using either the analytical model or the simulated model, determine the control to output gain at the chosen loop
crossover frequency. The gain of the compensator is the reciprocal of this gain:
1
K
(Hz)
+ ŤK (fc)Ť
COMP(co)
CO
(30)
where
•
KCOMP(CO) is the required compensator gain at the crossover frequency
•
KCO(fC) is the value of the control to output transfer function at the crossover frequency
If simulating the response using the model, the control to output gain is VX/VOUT. Sweep the AC voltage source
over the range of interest and plot VX/VOUT
.
Depending on the chosen loop crossover frequency and the characteristics of the output capacitor, either a Type
II or a Type III compensator could be required. If the output capacitance has sufficient ESR, phase shift from the
ESR zero may by used to eliminate the need for a Type III compensator. The model in Figure 6 uses a Type II
compensator. In this case the compensator response looks like Figure 7.
COMPENSATOR GAIN
vs
FREQUENCY
K
COMP(co)
f
C
f
P
f
Z
f − Frequency − kHz
Figure 7.
First select R1. The choice is somewhat arbitrary but affects the rest of the components once chosen. The
suggested value is 10 kΩ.
R2 is found from the gain required from the compensator at the crossover frequency.
R + K R (W)
2
1
LF
(31)
It is generally recommended to place the pole frequency one decade above the crossover frequency and the
zero frequency one decade below the crossover frequency.
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SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
1
f + f 10 +
(Hz)
P
C
2 p R C
2
1
(32)
(33)
f
C
1
2
f +
+
(Hz)
Z
10
2 p R C
2
Compensating the Loop (Type III)
If the output capacitor does not have sufficient ESR to use the phase shift from the ESR zero, a Type III
compensator is required. This is the case for most designs with ceramic output capacitors only. A series R-C
circuit is added in parallel to R1 as shown in Figure 8.
This is the same compensator as in Figure 6 except for the addition of C3 and R3. A typical response of this
circuit is shown in Figure 9.
COMPENSATOR GAIN
vs
FREQUENCY
C
3
C
1
R
3
C
2
R
2
R
1
VX
K
HF
FB
COMP
Error Amplifier
+
K
COMP(co)
R
BIAS
K
LF
UDG−04143
f
Z
f
Z3
f
C
f
P3
f
P
f − Frequency − kHz
Figure 9.
Figure 8. Type III Compensator Schematic
The reason for using the Type III compensator is to take advantage of the phase lead associated with the
upward slope of the gain between fZ3 and fP3. The crossover frequency should be located between these two
frequencies. The amount of phase lead generated is dependent on the separation of the fZ3 and fP3. In general, if
f
Z3 is one half of fC and fP3 is twice fC, the amount of phase lead at fC generated is sufficient for most applications.
Certainly more or less may be used depending on the situation.
As an example of selecting the extra required extra phase lead, suppose that the control to output gain phase
evaluates to -145° at fC. The Type II compensator has approximately 11.5° of phase lag at fC due to the origin
pole, the zero at fC/10 and the pole at 10xfC. This would give only 23.5° of phase margin, which while stable is
not ideal. Placing fZ3 and fP3 at one half and twice the crossover frequency respectively adds approximately 36°
of phase lead at fC for a new phase margin of 59.5°.
To calculate the values for this type of compensator, first select R1. Again the choice is somewhat arbitrary. 10
kΩ is a suggested value.
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TPS40100
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SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
Select the required extra phase lead beyond the Type II compensation to obtain the required phase margin and
calculate the required mulǸtiple for the additional pole and zero:
K + tanǒQLEADǓ ) tanǒQLEADǓ ) 1 (dimensionless)
3
(34)
where
•
ΘLEAD is the required extra phase lead to be generated by the addition of the extra pole and zero
•
K3 is the multiplier applied to fC to get the new pole and zero locations
The locations of fZ3 and fP3 are:
f
C
f
f
+
(Hz)
Z3
P3
K
3
(35)
(36)
+ f K (Hz)
3
C
where
•
•
•
K3 is the multiplier applied to fC to get the new pole and zero locations
Z3 is the zero created by the addition of R3 and C3
fP3 is the pole created by the addition of R3 and C3
f
The required gain, KCOMP(co), from the compensator at fC, is the same as for the Type II compensation, found in
Equation 30. The gain KLF (see Figure 9) is found by:
K
COMP(co)
K
+
(dimensionless)
LF
K
3
(37)
(38)
R2 can then be found:
R + K R (W)
2
1
LF
The high-frequency gain is:
K
+ K
K (dimensionless)
3
HF
COMP(co)
(39)
Now:
R R
1
2
R +
(W)
3
K
R * R
1
2
HF
(40)
(41)
1
C +
(F)
3
2 p R f
3
P3
The remaining pole and zero are located a decade above and below fC as before. Equation 31 and Equation 32
can be used to solve for C1 and C2 as before.
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TPS40100
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SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
Establishing Tracking and Designing a Tracking Control Loop
The tracking startup feature of the TPS40100 is a separate control loop that controls the output voltage to a
reference applied to the TRKIN pin. This reference voltage is typically a ramp generated by an external R-C
circuit. Connecting the junction of R5, C5 and R6 (see Figure 10) of multiple converters together allows the
converters output voltages to track together during start up. A controlled power down is accomplished by pulling
down the common junction in a controlled manner and then removing power to the converters or turning them off
by grounding the UVLO pin.The relevant circuit fragment is shown in Figure 10.
V
OUT
A
R
3
C
1
R
1
V
IN
C
C
R
2
2
3
VO
20
TRKOUT
3
R
D
1
4
+
R
6
FB
TRKIN
4
COMP
1
R
5
2
+
C
4
R
BIAS
C
5
A
To PWM
690 mV
UDG−04145
Figure 10. Tracking Loop Control Schematic
First, select a value for R4. In order for this circuit to work properly, the output of the tracking amplifier must be
able to cause the FB pin to reach at least 690 mV with the output voltage at zero volts. This is so that the output
voltage can be forced to zero by the tracking amplifier. This places a maximum value on R4:
ƪV
FBƫ
* V
* V
DIODE
R R
HTRKOUT(min)
1
BIAS
BIAS
R t
W
4
V
R ) R
1
FB
(42)
where
•
•
•
VHTRKOUT(min) is the minimum output voltage of the tracking amplifier (see Electrical Characteristics table)
DIODE is the forward voltage of the device selected for D1
VFB is the value of the reference voltage (690 mV)
V
R4 should not be chosen much lower than this value since that unnecessarily increases tracking loop gain,
making compensation more difficult and opening the door to potential non-linear control issues. D1 could be a
schottky if the impedance of the R1-RBIAS string is low enough that the leakage current is not a consequence. Be
aware that schottky diode leakage currents rise significantly at elevated temperature. If elevated temperature
operation and increased accuracy are important, use a standard or low leakage junction diode or the
base-emitter junction of a transistor for D1.
Once R4 is selected, the gain of the closed loop power supply looking into “A” is known. That gain is the ratio of
R1 and R4:
dV
R
R
OUT
1
4
+ *
(dimensionless)
dV
TRKOUT
(43)
The tracking loop itself should have a crossover frequency much less that the crossover frequency of the voltage
control loop. Typically, the tracking loop crossover frequency is 1/10th or less of the voltage loop crossover
frequency to avoid loop interactions. Note that the presence of the diode in the circuit gives a non-linear control
mechanism for the tracking loop. The presence of this non-linearity makes designing a control loop more
challenging. The simplest approach is to simply limit the bandwidth of this loop to no more than necessary.
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TPS40100
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APPLICATION INFORMATION (continued)
Knowing the gain of the voltage loop looking into R4 and the desired tracking loop crossover frequency, R5 and
C4 can be found:
R
4
R C +
(s)
5
4
2 p R f
1
cTRK
(44)
where
•
fCTRK is the desired tracking loop crossover frequency
The actual values of R5 and C4 are a balance between impedance level and component size. Any of a range of
values is applicable. In general, R5 should be no more than 20% of R6, and less than 10 kΩ. If this is done, then
R6 can safely be ignored for purposes of tracking loop gain calculations. For general usage, R6 should probably
be between 100 kΩ and 500 kΩ.
If an overshoot bump is present on the output at the beginning a tracking controlled startup, the tracking loop
bandwidth is likely too high. Reducing the bandwidth helps reduce the initial overshoot. See Figure 11 and
Figure 12.
t − Time − 1 ms/div
Figure 11. Excessive Tracking Loop Bandwidth
Figure 12. Limited Tracking Loop Bandwidth
The tracking ramp time is the time required for C5 to charge to the same voltage as the output voltage of the
converter.
V
OUT
+ * R C lnǒ1 * Ǔ
t
(s)
6
5
TRK
V
IN
(45)
where
•
•
•
VOUT is the output voltage of the converter
IN is the voltage applied to the top of R6
tTRK is the desired tracking ramp time
V
With these equations, it is possible to design the tracking loop so that the impedance level of the loop and the
component size are balanced for the particular application. Note that higher impedances make the loop more
susceptible to noise issues while lower impedances require increased capacitor size.
Figure 13 shows the spice model for the voltage loop expanded for use with the tracking loop.
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TPS40100
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SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
L
R
C
LDC
V
OUT
V
IN
+
R
SFLT
SFLT
C
OUT
X2
R
LOAD
gm
CSA
ISNS
R
CESR
+
C
1
R
3
C
3
R
2
C
2
R
EA
R
1
20 kΩ
+
R
BIAS
+
V
X
+
C4
R
5
R
4
+
UDG−04147
Figure 13. AC Behavioral Model for Tracking Control Loop
To use the model, the AC voltage source is swept over the frequency range of interest. The open loop ac
response is VX/VOUT
.
Programming Soft-Start Time
The soft-start time of the TPS40100 is fully user programmable by selecting a single capacitor. The SS pin
sources 20 µA to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the
20 µA to charge the capacitor through a 690 mV range. There is some initial lag due to an offset from the actual
SS pin voltage to the voltage applied to the error amplifier. See Figure 15. The soft-start is done in a closed loop
fashion, meaning that the error amplifier controls the output voltage at all times during the soft start period and
the feedback loop is never open as occurs in duty cycle limit soft-start schemes. The error amplifier has two
non-inverting inputs, one connected to the 690 mV reference voltage, and one connected to the offset SS pin
voltage. The lower of these two voltages is what the error amplifier controls the FB pin to. As the voltage on the
SS pin ramps up past approximately 1.04 V (resulting in 690 mV at the SS “+” input – See Figure 15), the 690
mV reference voltage becomes the dominant input and the converter has reached its final regulation voltage.
The capacitor required for a given soft-start ramp time for the output voltage is given by:
20 mA
C
+ T
SS
F
SS
V
FB
(46)
where
•
•
•
TSS is the desired soft-start ramp time (s)
SS is the required capacitance on the SS pin (F)
FB is the reference voltage feedback loop (690 mV)
C
V
22
TPS40100
www.ti.com
SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
COMP
1
FB
2
350 mV
COMP
Error Amplifier
+
+
690 mV
20 µA
SS
10
CHARGE
From UVLO circuits,
Fault controller
5 µA
C
SS
UDG−04138
Figure 14. Error Amplifier and Soft-Start Functional Diagram
UVLO
(Internal Logic State)
4.8 V
3.5 V
1.04 V
0.35 V
SS
Tss
Tss Delay
VOUT
PDG
Figure 15. Relationship Between UVLO (Internal Logic State), SS, VOUT and PGD at Startup
Interaction Between Soft-Start and Tracking Startup
Since the TPS40100 provides two means of controlling the startup (closed loop soft-start and tracking) care must
be taken to ensure that the two methods do not interfere with each other. The two methods should not be
allowed to try and control the output at the same time. If tracking is to be used, the reference input to the tracking
amplifier (TRKIN) should be held low until soft-start completes, or the voltage at the SS pin is at least above 1.04
V. This ensures that the soft-start circuit is not trying to control the startup at the same time as tracking circuit. If
it is desired to have soft-start control the startup, then there are two options:
23
TPS40100
www.ti.com
SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
•
Disconnect the tracking amplifier output from the FB node (this is the recommended solution. The tracking
amplifier can then be used for other system purposes if desired)
•
Maintain the tracking amplifier output connection to the FB circuit - the reference to the tracking amplifier
should be tied to VDD pin in this case. This places the tracking amplifier output (TRKOUT) in a low state
continuously and therefore removes any influence the tracking circuit has on the converter startup.
Additionally, when tracking is allowed to control the startup, soft-start should not be set to an arbitrarily short
time. This causes the output voltage to bump up when power is applied to the converter as soft-start ramps up
quickly and the tracking loop (which is necessarily low bandwidth) cannot respond fast enough to control the
output to zero voltage. In other words, the soft start ramp rate must be within the capability of the tracking loop to
override.
Overcurrent Protection
Overcurrent characteristics are determined by connecting a parallel R-C network from the ILIM pin to GND. The
ILIM pin sources a current that is proportional to the current sense amplifier transconductance and the voltage
between ISNS and VO. This current produces a voltage on the R-C network at ILIM. If the voltage at the ILIM pin
reaches 1.48 V, an overcurrent condition is declared and the outputs stop switching for a period of time. This
time period is determined by the time is takes to discharge the soft-start capacitor with a controlled current sink.
To set the overcurrent level:
V
ILIM
R
+
W
ILIM
gm
R
I
CSA
LDC OC
(47)
where
•
•
•
•
•
VILIM is the overcurrent comparator threshold (1.48 V typically)
OC is the overcurrent level to be set
gmCSA is the transconductance of the current sensing amplifier
I
RLDC is the equivalent series resistance of the inductor (or the sense resistor value)
RILIM is the value of the resistor from ILIM to GND
The response time of the overcurrent circuit is determined by the R-C time constant at the ILIM pin and the level
of the overcurrent. The response time is given by:
1
lnǒ1 * Ǔ
t
+ * R
C
ILIM
(s)
OC
ILIM
n
(48)
where
•
•
•
tOC is the response time before declaring an overcurrent
ILIM (Ω) and CILIM (F) are the components connected to the ILIM pin
n is the multiplier of the overcurrent. If the overcurrent is 2 times the programmed level, then n is 2.
R
By suitable manipulation of the time constant at ILIM, the overcurrent response can be tailored to ride out short
term transients and still provide protection for overloads and short circuits. The gm of the current sense amplifier
has a temperature coefficient of approximately -2000 ppm/°C. This is to help offset the temperature coefficient of
resistance of the copper in the inductor, about +4000 ppm/°C. The net is a +2000 ppm/°C temperature
coefficient. So, for a 100°C increase in temperature, the overcurrent threshold decreases by 20%, assuming
good thermal coupling between the controller and the inductor. Temperature compensation can be done as
described earlier if desired.
When an overcurrent condition is declared, the controller stops switching and turns off both the high-side
MOSFET and the low-side MOSFET. The soft-start capacitor is then discharged at 25% of the charge rate during
an overcurrent condition and the converter remains idle until the soft start pin reaches 200 mV, at which point the
soft-start circuit starts charging again and the converter attempts to restart. In normal operation, the soft-start
capacitor is charged to approximately 3.5 V when an initial fault is applied to the output. This means that the
minimum time before the first restart attempt is:
24
TPS40100
www.ti.com
SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
3.3 C
SS
t
+
(s)
RESTART
I
SSDIS
(49)
where
•
•
•
tRESTART is the initial restart time (s)
CSS is soft start capacitance (F)
ISSDIS is the soft start discharge current – 5 µA
If the output fault is persistent, and an overcurrent is declared on the restart, both of the MOSFETs are turned off
and the soft-start capacitor continues to charge to 3.5 V and then discharge to 200 mV before another restart is
attempted.
UVLO Programming
The TPS40100 provides the user with programmable UVLO level and programmable hysteresis. The UVLO
detection circuit schematic is described in Figure 16 from a functional perspective.
R
1
UVLO
1.33 V
+
UVLO
5
R
2
10 µA
TPS40100
UDG−04139
Figure 16. UVLO Circuit Functional Diagram
To program this circuit, first select the amount of hysteresis (the difference between the startup voltage and the
shutdown voltage) desired:
V
HYST
R +
W
1
I
UVLO
(50)
Then select the turn-on voltage and solve for R2.
V
R
1
UVLO
R +
W
2
V
* V
* R I
1
UVLO UVLO
ON
(51)
where
•
•
•
VHYST is the desired level of hysteresis in the programmable UVLO circuit
UVLO is the undervoltage lockout circuit hysteresis current (10 µA typ)
UVLO is the UVLO comparator threshold voltage (1.33 V typ)
I
V
25
TPS40100
www.ti.com
SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
Voltage Margining
The TPS40100 allows the user to make the output voltage temporarily be 3% above or below the nominal output,
or 5% above or below the nominal output. This is accomplished by connecting the MGU or MGD pins to GND
directly or through a resistance. See Table 1.
Table 1. Output Voltage Margining States
RESISTANCE TO GND (kΩ)
OUTPUT VOLTAGE
RMGU
OPEN
< 10
RMGD
OPEN
OPEN
< 10
Nominal
+ 5%
-5%
OPEN
25 to 37
OPEN
OPEN
25 to 37
+3%
-3%
There are some important considerations when adjusting the output voltage.
•
•
•
Only one of these pins should be anything other than an open circuit at any given time. States not listed in
the table are invalid states and the behavior of the circuit may be erratic if this is tried.
When changing the output voltage using the margin pins, it is very important to let the margin transition
complete before altering the state of the margin pins again.
Do not use mechanical means (switches, non-wetted relay contacts, etc) to alter the margining state. The
contact bounce causes erratic behavior.
Synchronization
The TPS40100 may be synchronized to an external clock source that is faster than the free running frequency of
the circuit. The SYNC pin is a rising edge sensitive trigger to the oscillator that causes the current cycle to
terminate and starts the next switching cycle. It is recommended that the synchronization frequency be no more
than 120% of the free running frequency. Following this guideline leads to fewer noise and jitter problems with
the pulse width modulator in the device. The circuit can be synchronized to higher multiples of the free running
frequency, but be aware that this results in a proportional decrease in the amplitude of the ramp from the
oscillator applied to the PWM, leading to increased noise sensitivity and increased PWM gain, possibly affecting
control loop stability.
The pulse applied to the SYNC pin can be any duty ratio as long as the pulse either high or low is at least 100 ns
wide. Levels are logic compatible with any voltage under 1 V considered a low and any voltage over 2 V
considered a high.
Power Good Indication
The PGD pin is an open drain output that actively pulls to GND if any of the following conditions are met
(assuming that the input voltage is above 4.5V)
•
•
•
•
•
•
•
Soft-start is active (VSS < 3.5 V)
Tracking is active (VTRKOUT > 0.7 V)
VFB < 0.61 V
VFB > 0.77 V
VUVLO < 1.33 V
Overcurrent condition exists
Die temperature is greater than 165°C
A short filter (20 µs) must be overcome before PGD pulls to GND from a high state to allow for short transient
conditions and noise and not indicate a power NOT good condition.
The PGD pin attempts to pull low in the absence of input power. If the VDD pin is open circuited, the voltage on
PGD typically behaves as shown in Figure 17.
26
TPS40100
www.ti.com
SLUS601–MAY 2005
POWERGOOD VOLTAGE
vs
POWERGOOD CURRENT
2.5
V
VDD
= 0 V
2.0
1.5
1.0
0.5
0
0
1
2
3
4
5
I
− Powergood Current − mA
PGD
Figure 17.
Pre-Bias Operation
Some applications require that the converter not sink current during startup if a pre-existing voltage exists at the
output. Since synchronous buck converters inherently sink current some method of overcoming this characteristic
must be employed. Applications that require this operation are typically power rails for a multiple supply
processor or ASIC. The method used in this controller, is to not allow the low side or rectifier FET to turn on until
there the output voltage commanded by the start up ramp is higher than the pre-existing output voltage. This is
detected by monitoring the internal pulse width modulator (PWM) for its first output pulse. Since this controller
uses a closed loop startup, the first output pulse from the PWM does not occur until the output voltage is
commanded to be higher than the pre-existing voltage. This effectively limits the controller to sourcing current
only during the startup sequence. If the pre-existing voltage is higher that the intended regulation point for the
output of the converter, the converter starts and sinks current when the soft-start time has completed.
Remote Sense
The TPS 40100 is capable of remotely sensing the load voltage to improve load regulation. This is accomplished
by connecting the GND pin of the device and the feedback voltage divider as near to the load as possible.
CAUTION:
Long distance runs for the GND pin will cause erratic controller behavior.
This begins to appear as increased pulse width jitter. As a starting point, the GND pin connection should be no
further than six inches from the PGND connection. The actual distance that starts causing erratic behavior is
application and layout dependent and must be evaluated on an individual basis. If the controller exhibits output
pulse jitter in excess of 25 ns and the GND pin is tied to the load ground, connecting the GND pin closer to the
PGND pin (and thereby sacrificing some load regulation) may improve performance. In either case, connecting
the feedback voltage divider at the point of load should not cause any problems. For layout, the voltage divider
components should be close to the device and a trace can be run from there to the load point.
27
TPS40100
www.ti.com
SLUS601–MAY 2005
Application Schematics
Margin down 3%
Power Good Indication
3.3 V to 5 V logic supply or 5VBP pin
27 kΩ
27 kΩ
Margin up 3%
2N7002
2N7002
47 pF
24
23
22
21
20
19
12 V
V
OUT
14.3 kΩ
300 pF
Connect at load
5.9 kΩ
100 nF
1
2
COMP
FB
VDD 18
SW 17
Si73444DP
12 V
1.0 µH
COEV
DXM1306−1R0
1.7 mΩ (typ)
10 kΩ
30 kΩ
3
TRKOUT
HDRV 16
BST 15
MMBD1501A
TPS40100
100 nF
BAT54
200 kΩ
100 kΩ
47 nF
4
5
6
TRKIN
UVLO
ILIM
4.99 kΩ
V
OUT
5VBP 14
LDRV 13
470 µF
Panasonic
EEF−SEOD471R
1.2 V
15 A
Si7868DP
2
1 µF
13.7 kΩ
7
8
9
10
11
12
40.2 kΩ
1 µF
158 kΩ
100 pF
270 kΩ
1
1
1 µF
150 nF
162 kΩ
Remote
10 nF
(if required)
10 Ω
GND Sense
Connect at
Load
22 µF TDK C4532X7R1C226M
Open switch after input power is stable and SS capacitor had finished charging.
1
BAT54S
(if required)
2
UDG−04140
Figure 18. 300-kHz, 12-V to 1.2-V Converter With Tracking Startup Capability and Remote Sensing
28
TPS40100
www.ti.com
SLUS601–MAY 2005
Margin down 5%
2N7002
Power Good Indication
3.3 V to 5 V logic supply or 5VBP pin
Margin up 5%
2N7002
V
OUT
47 pF
24 23 22 21 20 19
Connect at load
12 V
3.9 nF
6.2 kΩ
3.32 kΩ
12 V
1
2
COMP
VDD 18
5.9 kΩ 100 nF
Si7344DP
100 nF
330 pF
FB
SW 17
HDRV 16
BST 15
10 kΩ
1.0 µH
COEV
DXM1306−1R0
1.7 mΩ (typ)
15 kΩ
3
TRKOUT
V
OUT
3.3 V
15 A
MMBD1501A
TPS40100
47 nF
100 kΩ
200 kΩ
4
5
6
TRKIN
UVLO
ILIM
4.99 kΩ
BAT54
5VBP 14
LDRV 13
2
2
2
Si7868DP
3
1 µF
40.2 kΩ 2.67 kΩ
1 µF
7
8
9
10 11
12
1
1
158 kΩ
100 pF
150 nF
120 kΩ 1 µF
270 kΩ
UDG−04141
1
2
3
22 µF TDK C4532X7R1C226M
100 µF TDK C3225X5ROJ107M
Open switch after input power is stable and SS capacitor had finished charging.
Figure 19. 400-kHz, 12-V to 3.3-V Converter With Tracking Capability and 5% Margining
29
TPS40100
www.ti.com
SLUS601–MAY 2005
12 V
NC NC NC NC
24 23 22 21
47 pF
20
19
10 kΩ
12 V
300 pF
14.3 kΩ
5.9 kΩ
1
2
COMP
FB
VDD 18
SW 17
100 nF
Si73444DP
1 µH
COEV
DXM1306−1R0
1.7 mΩ (typ)
200 kΩ
3
TRKOUT
NC
NC
HDRV 16
BST 15
TPS40100
100 nF
BAT54
4
5
6
TRKIN
UVLO
ILIM
5VBP 14
LDRV 13
470 µF
Panasonic
Si7868DP
EEF−SEOD471R
V
OUT
1.2 V
15 A
13.7 kΩ
40.2 kΩ
7
8
9
10
11
12
1
1
1 µF
158 kΩ
100 pF
270 kΩ
150 nF
187 kΩ 1 µF
1
22 µF TDK C4532X7R1C226M
UDG−05063
Figure 20. Minimal Application for 12-V to 1-V Converter
30
TPS40100
www.ti.com
SLUS601–MAY 2005
NC NC
24 23
10 kΩ
47 pF
22
21
20
19
12 V
300 pF
14.3 kΩ
1
2
COMP
FB
VDD 18
SW 17
100 nF
5.9 kΩ
Si73444DP
1 µH
COEV
DXM1306−1R0
1.7 mΩ (typ)
3
TRKOUT
NC
NC
12 V
HDRV 16
BST 15
TPS40100
100 nF
BAT54
4
5
6
TRKIN
UVLO
ILIM
200 kΩ
5VBP 14
LDRV 13
470 µF
Si7868DP
Panasonic
EEF−SEOD471R
V
1.2 V
15 A
OUT
1 µF
40.2 kΩ
13.7 kΩ
7
8
9
10
11
12
External 5 V
100 pF
158 kΩ
270 kΩ
1
1
10 kΩ
187 kΩ 1 µF
150 nF
Power
Good
External
Clock
50%
NC NC
24 23
Duty
470 pF
22
21
20
19
10 kΩ
12 V
3.32 kΩ
3.9 nF
6.2 kΩ
330 pF
1
2
COMP
FB
VDD 18
SW 17
100 nF
5.9 kΩ
Si7344DP
100 nF
1 µH
COEV
DZM1306−1R
3 mΩ (typ)
12 V
3
TRKOUT
NC
NC
HDRV 16
BST 15
TPS40100
4
5
6
TRKIN
UVLO
ILIM
200 kΩ
BAT54
5VBP 14
LDRV 13
Si7868DP
V
OUT
3.3 V
15 A
2
2
2
40.2 kΩ
2.67 kΩ
7
8
9
10
11
12
1 µF
1
1
100 pF
158 kΩ
120 kΩ
270 kΩ
150 nF
1 µF
UDG−05064
22 µF TDK C4532X7R1C226M
100 µF TDK C3225X5ROJ107M
1
2
Figure 21. Sequenced Supplies, With Oscillators 180 Degrees Out of Phase
31
TPS40100
www.ti.com
SLUS601–MAY 2005
10 kΩ
External
5V
NC NC
10 kΩ
47 pF
24
23 22 21
20 19
12 V
12 V
300 pF
14.3 kΩ
1
2
COMP
FB
VDD 18
100 nF
5.9 kΩ
Si73444DP
SW 17
HDRV 16
BST 15
200 kΩ
30 kΩ
3
TRKOUT
MMBD1501A
TPS40100
100 nF
BAT54
47 nF
4.99 kΩ
4
5
6
TRKIN
UVLO
ILIM
V
OUT
5VBP 14
LDRV 13
1.2
V
15 A
Si7868DP
470 µF
Panasonic
EEF−SEOD471R
470 µF
Panasonic
EEF−SEOD471R
40.2 kΩ
7
8
9
10
11
12
1 µF
158 kΩ
270 kΩ
13.7 kΩ
100 pF
1
1
150 nF
1 µF
187 kΩ
External Clock,
50% duty
Power
Good
NC NC
3.32 kΩ
10 kΩ
470 pF
24 23 22
21 20 19
12 V
3.9 nF
6.2 kΩ
330 pF
5.9 kΩ
1
COMP
FB
VDD 18
100 nF
12 V
Si7344DP
100 nF
2
3
12 V
SW 17
HDRV 16
BST 15
1 µH
COEV
DZM1306−1R
3 mΩ (typ)
15 kΩ
TRKOUT
47 kΩ
MMBD1501A
200 kΩ
TPS40100
47 nF
4.99 kΩ
4
5
6
TRKIN
UVLO
ILIM
BAT54
5VBP 14
LDRV 13
3
Si7868DP
2.2 µF
V
OUT
3.3
V
15 A
2
2
2
100 pF
40.2 kΩ
2.67 kΩ
7
8
9
10 11
12
1 µF
1
1
270 kΩ
158 kΩ
1 µF
150 nF
120 kΩ
UDG−05066
1
2
22 µF TDK C4532X7R1C226M
100 µF TDK C3225X5ROJ107M
Open switch after input power is stable and SS capacitor has finished charging.
3
Figure 22. Tracking Supplies
32
PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2008
PACKAGING INFORMATION
Orderable Device
TPS40100RGER
TPS40100RGERG4
TPS40100RGET
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
VQFN
RGE
24
24
24
24
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VQFN
VQFN
VQFN
RGE
RGE
RGE
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS40100RGETG4
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS40100RGER
TPS40100RGER
TPS40100RGER
TPS40100RGET
TPS40100RGET
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
3000
3000
3000
250
330.0
330.0
330.0
180.0
180.0
12.4
12.4
12.4
12.4
12.4
4.25
4.25
4.3
4.25
4.25
4.3
1.15
1.15
1.1
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
4.25
4.3
4.25
4.3
1.15
1.1
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS40100RGER
TPS40100RGER
TPS40100RGER
TPS40100RGET
TPS40100RGET
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
3000
3000
3000
250
367.0
367.0
370.0
210.0
195.0
367.0
367.0
355.0
185.0
200.0
35.0
35.0
55.0
35.0
45.0
250
Pack Materials-Page 2
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Copyright © 2012, Texas Instruments Incorporated
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