TPS40345 [TI]
适用于成本优化型应用的 3V 至 20V、25A 同步降压控制器;
| 型号： | TPS40345 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于成本优化型应用的 3V 至 20V、25A 同步降压控制器 控制器 |
| 文件： | 总29页 (文件大小：2068K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS40345
ZHCSH69 –DECEMBER 2017
TPS40345 3V 至 20V 输入同步降压控制器
1 特性
3 说明
1
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输入电压范围：3V 至 20V
TPS40345 是一款同步降压控制器，可在 3V 到 20V
的输入电压下工作，可用于成本优化型 应用。此控制
器实现了一种电压模式控制架构，具有输入电压前馈补
偿功能，可对输入电压变化做出即时响应。开关频率设
置为 600kHz。
600kHz 开关频率
高侧和低侧 FET RDS(on) 电流检测
可编程热补偿 OCP 电平
可编程软启动
600mV、1.3% 基准电压
电压前馈补偿
开关频率中添加了扩频频谱 (FSS) 功能，显著降低了
峰值 EMI 噪声，使其更容易符合 EMI 标准。
支持预偏置输出
TPS40345 可提供各种用户可编程功能，其中包括软
启动、过流保护 (OCP) 电平以及环路补偿。
扩频频谱
145°C 的热关断保护限制
10 引脚 3mm × 3mm VSON 封装，散热垫具有接
地连接
OCP 电平可以通过从 LDRV 引脚连接到电路接地的单
个外部电阻器进行编程。在初始上电过程
中，TPS40345 可进入校准环节，测量 LDRV 引脚电
压，并设置内部 OCP 电压级。在工作期间，器件可在
通电时通过将已编程 OCP 电压电平与低侧 FET 上的
压降进行比较来确定是否发生过流情况。之
后，TPS40345 会进入关断和重启周期，直到故障消
除为止。
2 应用
•
•
•
•
负载点 (POL) 模块
打印机
数字电视
电信
器件信息(1)
器件型号
TPS40345
封装
VSON (10)
封装尺寸（标称值）
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化应用示意图
VOUT
VIN
TPS40345
5
4
3
2
1
FB
BOOT
HDRV
SW
6
7
8
9
COMP
VOUT
PGOOD
EN/SS LDRV/OC
VDD
GND
SD
VIN
BP 10
PAD
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSD62
TPS40345
ZHCSH69 –DECEMBER 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ................................................ 13
Power Supply Recommendations...................... 17
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 12
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 19
11 器件和文档支持 ..................................................... 20
11.1 器件支持................................................................ 20
11.2 文档支持................................................................ 20
11.3 接收文档更新通知 ................................................. 20
11.4 社区资源................................................................ 20
11.5 商标....................................................................... 20
11.6 静电放电警告......................................................... 20
11.7 Glossary................................................................ 20
12 机械、封装和可订购信息....................................... 20
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2017 年 12 月
*
初始发行版
2
Copyright © 2017, Texas Instruments Incorporated
TPS40345
www.ti.com.cn
ZHCSH69 –DECEMBER 2017
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
FB COMP PGOOD EN/SS VDD
5
4
3
2
1
Thermal Pad
6
7
8
9
10
LDRV/
OC
BOOT HDRV SW
BP
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Gate drive voltage for the high-side N-channel MOSFET. A 0.1-µF capacitor (typical) must be connected
between this pin and SW. For low input voltage operation, an external Schottky diode from BP to BOOT is
recommended to maximize the gate drive voltage for the high-side.
BOOT
6
I
Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor of 1 µF or greater from
this pin to GND.
BP
10
4
O
O
COMP
Output of the error amplifier and connection node for loop feedback components.
Logic level input which starts or stops the controller via an external user command. Letting this pin float turns
the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A
capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an
internal current source of 10 µA. The resulting voltage ramp of this pin is also used as a second non-inverting
input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is controlled by the
internal level shifted voltage ramp until that voltage reaches the internal reference voltage of 600 mV – the
voltage ramp of this pin reaches 1.4 V (typical). Optionally, a 267-kΩ resistor from this pin to BP enables the
FSS feature.
EN/SS
2
I
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal
reference voltage.
FB
5
I
PGOOD
HDRV
3
7
O
O
Open-drain power good output.
Bootstrapped gate drive output for the high-side N-channel MOSFET.
Gate drive output for the low-side synchronous rectifier N-channel MOSFET. A resistor from this pin to GND
is also used to determine the voltage level for OCP. An internal current source of 10 µA flows through the
resistor during initial calibration and that sets up the voltage trip point used for OCP.
LDRV/OC
9
O
Power input to the controller. Bypass VDD to GND with a low ESR ceramic capacitor of at least 1 µF close to
the device.
VDD
SW
1
8
I
Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high-
side FET driver.
O
Ground connection to the controller. This is also the thermal pad used to conduct heat from the device. This
connection serves a twofold purpose. The first is to provide an electrical ground connection for the device.
The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be
tied externally to a ground plane.
Thermal
Pad
GND
—
Copyright © 2017, Texas Instruments Incorporated
3
TPS40345
ZHCSH69 –DECEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–3
MAX
22
27
–5
UNIT
V
VDD
SW
V
SW (< 100 ns pulse width, 10 µJ)
BOOT
V
–0.3
–5
30
30
7
V
HDRV
V
BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW)
COMP, PGOOD, FB, BP, LDRV, EN/SS
Operating junction temperature, TJ
Storage temperature, Tstg
–0.3
–0.3
–40
–55
V
7
V
145
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
3
NOM
MAX
20
UNIT
V
Input voltage, VDD
Operating junction temperature, TJ
–20
125
°C
6.4 Thermal Information
TPS40345
DRC (VSON)
10 PINS
44.3
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
56.1
19.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
ψJB
19.4
RθJC(bot)
5.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
TPS40345
www.ti.com.cn
ZHCSH69 –DECEMBER 2017
6.5 Electrical Characteristics
TJ = –20°C to 125°C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
VOLTAGE REFERENCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TJ = 25°C, 3 V < VVDD < 20 V
597
592
600
600
603
608
VFB
FB input voltage
mV
–20°C < TJ < 125°C, 3 V < VVDD < 20 V
INPUT SUPPLY
VVDD
Input supply voltage range
Shutdown supply current
Quiescent, nonswitching
3
20
100
3.5
V
IDDSD
VEN/SS < 0.2 V
70
µA
mA
IDDQ
Let EN/SS float, VFB = 1 V
2.5
ENABLE/SOFT-START
High-level input voltage,
EN/SS
VIH
VIL
0.55
0.27
0.7
0.3
1
V
V
Low-level input voltage,
EN/SS
0.33
ISS
Soft-start source current
Soft-start voltage level
8
10
12
µA
V
VSS
0.4
0.8
1.3
BP REGULATOR
VBP
Output voltage
IBP = 10 mA
6.2
6.5
70
6.8
V
Regulator dropout voltage,
VVDD – VBP
VDO
IBP = 25 mA, VVDD = 3 V
110
mV
OSCILLATOR
fSW
PWM frequency
Ramp amplitude
540
600
660
kHz
V
(1)
VRAMP
VVDD/6.6
VVDD/6 VVDD/5.4
Frequency spread-spectrum
frequency deviation
fSWFSS
12%
fSW
fMOD
Modulation frequency
25
kHz
PWM
(1)
DMAX
Maximum duty cycle
VFB = 0 V, 3 V < VVDD < 20 V
90%
Minimum controllable pulse
width
(1)
tON(min)
70
ns
ns
HDRV off to LDRV on
LDRV off to HDRV on
5
5
25
25
35
30
tDEAD
Output driver dead time
ERROR AMPLIFIER
(1)
GBWP
Gain bandwidth product
Open loop gain
10
60
24
MHz
dB
(1)
AOL
Input bias current (current
out of FB pin)
IIB
VFB = 0.6 V
75
nA
IEAOP
Output source current
Output sink current
VFB = 0 V
VFB = 1 V
2
2
mA
IEAOM
PGOOD
Feedback upper voltage limit
for PGOOD
VOV
VUV
655
500
675
525
700
550
Feedback lower voltage limit
for PGOOD
mV
PGOOD hysteresis voltage
at FB
VPGD-HYST
RPGD
25
30
10
40
70
20
PGOOD pulldown resistance VFB = 0 V, IFB = 5 mA
Ω
550 mV < VFB < 655 mV,
PGOOD leakage current
IPGDLK
µA
VPGOOD = 5 V
(1) Ensured by design. Not production tested.
Copyright © 2017, Texas Instruments Incorporated
5
TPS40345
ZHCSH69 –DECEMBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
TJ = –20°C to 125°C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
OUTPUT DRIVERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-side driver pullup
resistance
RHDHI
RHDLO
RLDHI
VBOOT – VSW = 5 V, IHDRV = –100 mA
VBOOT – VSW = 5 V, IHDRV = 100 mA
ILDRV = -100 mA
0.8
0.5
1.5
1
2.5
2.2
2.5
1.2
Ω
Ω
Ω
Ω
High-side driver pulldown
resistance
Low-side driver pullup
resistance
0.8
1.5
0.6
Low-side driver pulldown
resistance
RLDLO
ILDRV = 100 mA
CLOAD = 5 nF
0.35
(1)
tHRISE
High-side driver rise time
High-side driver fall time
Low-side driver rise time
Low-side driver fall time
15
12
15
10
ns
ns
ns
ns
(1)
tHFALL
(1)
tLRISE
(1)
tLFALL
OVERCURRENT PROTECTION
Minimum pulse time during
short circuit
(1)
tPSSC(min)
250
150
ns
ns
Switch leading-edge
blanking pulse time
(1)
tBLNKH
OC threshold for high-side
FET
VOCH
TJ = 25°C
TJ = 25°C
360
9.5
450
10
580
10.5
400
mV
µA
IOCSET
OCSET current source
Maximum clamp voltage at
LDRV
VLD-CLAMP
VOCLOS
260
340
mV
OC comparator offset
voltage for low-side FET
TJ = 25°C
TJ = 25°C
–8
12
8
mV
mV
Programmable OC range for
low-side FET
(1)
VOCLPRO
300
OC threshold temperature
coefficient (both high-side
and low-side)
(1)
VTHTC
3000
4
ppm
OC retry cycles on EN/SS
pin
tOFF
Cycle
BOOT DIODE
VDFWD
Bootstrap diode forward
voltage
IBOOT = 5 mA
0.8
V
THERMAL SHUTDOWN
Junction shutdown
temperature
Hysteresis
(1)
TJSD
145
20
°C
°C
(1)
TJSDH
6
Copyright © 2017, Texas Instruments Incorporated
TPS40345
www.ti.com.cn
ZHCSH69 –DECEMBER 2017
6.6 Typical Characteristics
625
620
615
610
605
600
595
590
585
580
2.24
2.22
2.2
VDD = 3 V
VDD = 12 V
VDD = 20 V
2.18
2.16
2.14
2.12
-20
5
30
55
80
105
125
-20
5
30
55
80
105
125
Temperature (èC)
Temperature (èC)
D001
iddq
Figure 1. Switching Frequency vs Junction Temperature
Figure 2. Quiescent Current vs Junction Temperature
72
14
13
12
11
10
9
70
68
66
64
62
60
58
8
7
6
-20
5
30
55
80
105
125
-20
5
30
55
80
105
125
Temperature (èC)
Temperature (èC)
D003
iocs
Figure 3. Shutdown Current vs Junction Temperature
Figure 4. OCSET Current Source vs Junction Temperature
600.8
740
600.6
600.4
600.2
600
720
700
680
660
640
620
599.8
599.6
599.4
-20
5
30
55
80
105
125
-20
5
30
55
80
105
125
Temperature (èC)
Temperature (èC)
vfb_
D006
Figure 5. Feedback Reference Voltage vs Junction
Temperature
Figure 6. Enable High-Level Threshold Voltage vs Junction
Temperature
Copyright © 2017, Texas Instruments Incorporated
7
TPS40345
ZHCSH69 –DECEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
303
600
550
500
450
400
350
302.5
302
301.5
301
300.5
300
-20
5
30
55
80
105
125
-20
5
30
55
80
105
125
Temperature (èC)
Temperature (èC)
D007
D008
Figure 7. Enable Low-Level Threshold Voltage vs Junction
Temperature
Figure 8. High-Side Overcurrent Threshold vs Junction
Temperature
1000
800
Overvoltage
Undervoltage
975
950
925
900
875
850
825
800
775
750
750
700
650
600
550
500
450
400
-20
5
30
55
80
105
125
-20
5
30
55
80
105
125
Temperature (èC)
Temperature (èC)
D009
D010
Figure 9. Power Good Threshold Voltage vs Junction
Temperature
Figure 10. Soft-Start Voltage vs Junction Temperature
8
Copyright © 2017, Texas Instruments Incorporated
TPS40345
www.ti.com.cn
ZHCSH69 –DECEMBER 2017
7 Detailed Description
7.1 Overview
The TPS40345 is a cost-optimized synchronous buck controller providing high-end features to construct high-
performance DC–DC converters. Prebias capability eliminates concerns about damaging sensitive loads during
start-up. Programmable overcurrent protection levels and hiccup overcurrent fault recovery maximize design
flexibility and minimize power dissipation in the event of a prolonged output short. The frequency spread
spectrum (FSS) feature reduces peak EMI noise by spreading the initial energy of each harmonic along a
frequency band, thus giving a wider spectrum with lower amplitudes.
7.2 Functional Block Diagram
+
10 mA
0.6 VREF + 12.5%
FB
Soft Start
SS
SS
BP
EN/SS
2
+
SD
0.6 VREF –12.5%
Fault
Controller
Clock
6
7
BOOT
HDRV
OC
+
6-V
Regulator
VDD
BP
1
10
4
References
BP
0.6 VREF
SD
8
SW
Calibration
Circuit
Spread
Spectrum
Oscillator
COMP
FB
Clock
BP
Anti-Cross
Conduction
and
PWM
Logic
9
LDRV/OC
Pre-Bias
Circuit
5
3
PWM
+
+
10 mA
0.6 VREF
SS
Thermal
Shutdown
OC
Threshold
Setting
750 kW
PGOOD
Fault Controller
OC
PAD
GND
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Voltage Reference
The 600-mV bandgap cell is internally connected to the noninverting input of the error amplifier. The reference
voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final
regulation voltage. The 1.3% tolerance on the reference voltage allows the user to design a very accurate power
supply.
Copyright © 2017, Texas Instruments Incorporated
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TPS40345
ZHCSH69 –DECEMBER 2017
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Feature Description (continued)
7.3.2 Enable Functionality, Start-Up Sequence and Timing
After input power is applied, an internal current source of 40 µA starts to charge up the soft-start capacitor
connected from EN/SS to GND. When the voltage across that capacitor increases to 0.7 V, it enables the internal
BP regulator followed by a calibration. The total calibration time is about 1.9 ms. See Figure 11. During the
calibration, the device performs in the following way. It disables the LDRV drive and injects an internal 10-µA
current source to the resistor connected from LDRV to GND. The voltage developed across that resistor is then
sampled and latched internally as the OCP trip level until one cycles the input or toggles the EN/SS.
2.0
V
EN/SS
Calibration
Time
1.9 ms
1.6
1.2
0.8
0.4
0
1.3 V
0.7 V
V
SS_INT
t – Time – ms
UDG-09159
Figure 11. Start-Up Sequence and Timing
The voltage at EN/SS is internally clamped to 1.3 V before and/or during calibration to minimize the discharging
time once calibration. The discharging current is from an internal current source of 140 µA and it pulls the voltage
down to 0.4 V. The discharging current then initiates the soft-start by charging up the capacitor using an internal
current source of 10 µA. The resulting voltage ramp on this pin is used as a second noninverting input to the
error amplifier after an 800 mV (typical) downward level-shift; therefore, actual soft-start does not occur until the
voltage at this pin reaches 800 mV.
If EN/SS is left floating, the controller starts automatically. EN/SS must be pulled down to less than 270 mV to
ensure that the chip is in shutdown mode.
7.3.3 Soft-Start Time
The soft-start time of the TPS40345 is user programmable by selecting a single capacitor. The EN/SS pin
sources 10 µA to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the
10 µA to charge the capacitor through a 600-mV range. There is some initial lag due to calibration and an offset
(800 mV) from the actual EN/SS pin voltage to the voltage applied to the error amplifier.
The soft-start is done in a closed-loop fashion, meaning that the error amplifier controls the output voltage at all
times during the soft-start period and the feedback loop is never open as occurs in duty cycle limit soft-start
schemes. The error amplifier has two non-inverting inputs, one connected to the 600-mV reference voltage, and
the other connected to the offset EN/SS pin voltage. The lower of these two voltages is what the error amplifier
controls the FB pin. As the voltage on the EN/SS pin ramps up past approximately 1.4 V (800-mV offset voltage
plus the 600 mV reference voltage), the 600-mV reference voltage becomes the dominant input and the
converter has reached its final regulation voltage.
The capacitor required for a given soft-start ramp time for the output voltage is given by Equation 1.
æ
ç
è
ö
÷
ø
ISS
CSS
=
´ t
SS
VFB
10
Copyright © 2017, Texas Instruments Incorporated
TPS40345
www.ti.com.cn
ZHCSH69 –DECEMBER 2017
Feature Description (continued)
where
•
•
•
•
CSS is the required capacitance on the EN/SS pin. (F)
ISS is the soft-start source current (10 µA).
VFB is the feedback reference voltage (0.6 V).
tSS is the desired soft-start ramp time (s).
(1)
7.3.4 Oscillator and Frequency Spread Spectrum (FSS)
The oscillator frequency is internally fixed. The TPS40345 operating frequency is 600 kHz.
Connecting a resistor with a value of 267 kΩ ±10% from BP to EN/SS enables the FSS feature. When the FSS is
enabled, it spreads the internal oscillator frequency over a minimum 12% window using a 25-kHz modulation
frequency with triangular profile. By modulating the switching frequency, side-bands are created. The emission
power of the fundamental switching frequency and its harmonics is distributed into smaller pieces scattered
around many sideband frequencies. The effect significantly reduces the peak EMI noise and makes it much
easier for the resultant emission spectrum to pass EMI regulations.
7.3.5 Overcurrent Protection
Programmable OCP level at LDRV is from 6 mV to 150 mV at room temperature with 3000 ppm temperature
coefficient to help compensate for changes in the low-side FET channel resistance as temperature increases.
With a scale factor of 2, the actual trip point across the low-side FET is in the range of 12 mV to 300 mV. The
accuracy of the internal current source is ±5%. Overall offset voltage, including the offset voltage of the internal
comparator and the amplifier for scale factor of 2, is limited to ±8 mV.
Maximum clamp voltage at LDRV is 340 mV to avoid turning on the low-side FET during calibration and in a
prebiased condition. The maximum clamp voltage is fixed and it does not change with temperature. If the voltage
drop across ROCSET reaches the 340-mV maximum clamp voltage during calibration (no ROCSET resistor
included), it disables OC protection. Once disabled, there is no low-side or high-side current sensing.
OCP level at HDRV is fixed at 450 mV with 3000-ppm temperature coefficient to help compensate for changes in
the high-side FET channel resistance as temperature increases. OCP at HDRV provides pulse-by-pulse current
limiting.
OCP sensing at LDRV is a true inductor valley current detection, using sample and hold. Equation 2 can be used
to calculate ROCSET
:
æ
ç
ç
ç
ç
ç
è
ö
÷
÷
÷
÷
÷
ø
æ
ç
è
ö
÷
ø
I
æ
ç
è
ö
P-P
I
-
´R
- V
OCLOS
DS on
÷
OUT max
(
)
( )
2
ø
R
=
OCSET
2 ´ I
OCSET
where
•
•
•
•
•
•
IOCSET is the internal current source.
VOCLOS is the overall offset voltage.
IP-P is the peak-to-peak inductor current.
RDS(on) is the drain to source ON-resistance of the low-side FET.
IOUT(max) is the trip point for OCP.
ROCSET is the resistor used for setting the OCP level.
(2)
To avoid overcurrent tripping in normal operating load range, calculate ROCSET using Equation 2 with:
•
•
The maximum RDS(ON) at room temperature
The lower limit of VOCLOS (–8 mV) and the lower limit of IOCSET (9.5 µA) from the Electrical Characteristics
table.
•
The peak-to-peak inductor current IP-P at minimum input voltage
Copyright © 2017, Texas Instruments Incorporated
11
TPS40345
ZHCSH69 –DECEMBER 2017
www.ti.com.cn
Feature Description (continued)
Overcurrent is sensed across both the low-side FET and the high-side FET. If the voltage drop across either FET
exceeds the OC threshold, a count increments one count. If no OC is detected on either FET, the fault counter
decrements by one count. If three OC pulses are summed, a fault condition is declared which cycles the soft-
start function in a hiccup mode. Hiccup mode consists of four dummy soft-start timeouts followed by a real one if
overcurrent condition is encountered during normal operation, or five dummy soft-start timeouts followed by a
real one if overcurrent condition occurs from the beginning during start. This cycle continues indefinitely until the
fault condition is removed.
7.3.6 Drivers
The drivers for the external high-side and low-side MOSFETs can drive a gate-to-source voltage of VBP. The
LDRV driver for the low-side MOSFET switches between BP and GND, while the HDRV driver for the high-side
MOSFET is referenced to SW and switches between BOOT and SW. The drivers have nonoverlapping timing
that is governed by an adaptive delay circuit to minimize body diode conduction in the synchronous rectifier.
7.3.7 Prebias Start-Up
The TPS40345 contains a circuit to prevent current from being pulled from the output during start-up in the
condition the output is prebiased. There are no PWM pulses until the internal soft-start voltage rises above the
error amplifier input (FB pin), if the output is prebiased. Once the soft-start voltage exceeds the error amplifier
input, the controller slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow
on time. The controller then increments that on time on a cycle-by-cycle basis until it coincides with the time
dictated by (1-D), where D is the duty cycle of the converter. This approach prevents the sinking of current from
a prebiased output, and ensures the output voltage start-up and ramp to regulation is smooth and controlled.
7.3.8 Power Good
The TPS40345 provides an indication that output is good for the converter. This is an open-drain signal and pulls
low when any condition exists that would indicate that the output of the supply might be out of regulation. These
conditions include the following:
•
•
•
VFB is more than ±12.5% from nominal.
Soft-start is active.
A short-circuit condition has been detected.
NOTE
When there is no power to the device, PGOOD is not able to pull close to GND if an
auxiliary supply is used for the power good indication. In this case, a built-in resistor
connected from drain to gate on the PGOOD pulldown device makes the PGOOD pin look
approximately like a diode to GND.
7.3.9 Thermal Shutdown
If the junction temperature of the device reaches the thermal shutdown limit of 145°C, the PWM and the oscillator
are turned off and HDRV and LDRV are driven low. When the junction cools to the required level (125°C typical),
the PWM initiates soft-start as during a normal power-up cycle.
7.4 Device Functional Modes
7.4.1 Modes of Operation
7.4.1.1 UVLO
In UVLO, VDD is less than UVLO_ON, the BP6 regulator is off, and the HDRV and LDRV are held low by
internal passive discharge resistors.
7.4.1.2 Disable
Disable is forced by holding SS/EN below 0.4 V. In disable, the BP6 regulator is off, and both HDRV and LDRV
are held low by passive discharge resistors.
12
Copyright © 2017, Texas Instruments Incorporated
TPS40345
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ZHCSH69 –DECEMBER 2017
Device Functional Modes (continued)
7.4.1.3 Calibration
Each enable of the TPS40345 device requires a calibration which lasts approximately 2 ms. During calibration
the TPS40345 device LDRV and HDRV are held off by its pulldown drivers while the device configures as
detailed in Enable Functionality, Start-Up Sequence and Timing.
7.4.1.4 Converting
When calibration completes, the TPS40345 ramps its reference voltage as described in Soft-Start Time, and the
states of the LDRV and HDRV drivers are dictated by the COMP pin to regulate the FB pin equal to the internal
reference.
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS40345 a cost-optimized synchronous buck controllers providing high-end features to construct high-
performance DC-DC converters. Prebias capability eliminates concerns about damaging sensitive loads during
start-up. Programmable overcurrent protection levels and hiccup overcurrent fault recovery maximize design
flexibility and minimize power dissipation in the event of a prolonged output short. frequency spread spectrum
(FSS) feature reduces peak EMI noise by spreading the initial energy of each harmonic along a frequency band,
thus giving a wider spectrum with lower amplitudes.
8.2 Typical Applications
For this 20-A, 12-V to 1.2-V design, the 600-kHz TPS40345 was selected for a balance between small size and
high efficiency.
+
+
1
Copyright © 2017, Texas Instruments Incorporated
Figure 12. TPS40345 Design Example Schematic
Copyright © 2017, Texas Instruments Incorporated
13
TPS40345
ZHCSH69 –DECEMBER 2017
www.ti.com.cn
Typical Applications (continued)
8.2.1 Design Requirements
For this example, follow the design parameters listed in Table 1.
Table 1. Design Example Electrical Characteristics
PARAMETER
Input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
8
14
V
V
V
VINripple
VOUT
Input ripple
IOUT = 20 A
0.5
Output voltage
Line regulation
Load regulation
Output ripple
0 A ≤ IOUT ≤ 20 A
8 V ≤ VIN ≤ 14 V
0 A ≤ IOUT ≤ 20 A
IOUT = 20 A
1.164
1.2 1.236
0.5%
0.5%
36
VRIPPLE
VOVER
VUNDER
IOUT
mV
mV
mV
A
Output overshoot
Output undershoot
Output current
Soft-start time
Short-circuit current trip point
Switching frequency
Size
5 A ≤ IOUT ≤ 15 A
5 A ≤ IOUT ≤ 15 A
8 V ≤ VIN ≤ 14 V
VIN = 12 V
100
100
0
20
tSS
1.5
ms
A
ISCP
26
fSW
600
1.5
kHz
in2
8.2.2 Detailed Design Procedure
8.2.2.1 Selecting the Switching Frequency
To achieve the small size for this design the TPS40345, with fSW = 600 kHz, is selected for minimal external
component size.
8.2.2.2 Inductor Selection (L1)
Synchronous buck power inductors are typically sized for approximately 30% peak-to-peak ripple current
(IRIPPLE).
Given this target ripple current, the required inductor size can be calculated in Equation 3.
V
- VOUT
VOUT
1
14V -1.2V 1.2V
1
IN(max)
L »
´
´
=
´
´
= 305nH
0.3´IOUT
V
FSW
0.3´ 20A 14V 600kHz
IN(max)
(3)
(4)
Selecting a standard 300-nH inductor value, solve for IRIPPLE = 6 A
The RMS current through the inductor is approximated by Equation 4.
2
2
2
2
2
=
202
126
20.07 A
+
1
1
1
=
+
I
Lrms = ILavg
+
12IRIPPLE
=
IOUT
12IRIPPLE
8.2.2.3 Output Capacitor Selection (C12)
The selection of the output capacitor is typically driven by the output transient response. Equation 5 and
Equation 6 overestimate the voltage deviation to account for delays in the loop bandwidth and can be used to
determine the required output capacitance.
2
I
I
I
´L
I
´L
TRAN
TRAN
TRAN
TRAN
V
<
´ DT =
´
=
OVER
C
C
V
V
´C
OUT
OUT
OUT
OUT OUT
(5)
(6)
ITRAN
ITRAN
ITRAN ´L
ITRAN2 ´L
VUNDER
<
´ DT =
´
=
COUT
COUT
VIN - VOUT
VIN - VOUT ´ C
)
(
OUT
If VIN(min) > 2 × VOUT, use overshoot (Equation 5) to calculate minimum output capacitance. If VIN(min) < 2 × VOUT
,
use undershoot (Equation 6) to calculate minimum output capacitance.
14
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TPS40345
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ZHCSH69 –DECEMBER 2017
ITRAN(MAX)2 ´L
102 ´300nH
1.2´100mV
COUT(MIN)
=
=
= 250mF
V
(
´ V
OVER
)
OUT
(7)
With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is
approximated by Equation 8.
æ
ç
è
ö
÷
IRIPPLE
æ
ç
è
6A
8´ 250mF´ 600kHz
6A
ö
÷
ø
VRIPPLE(total)
-
36mV -
VRIPPLE(Total) - VRIPPLE(CAP)
8´ COUT ´FSW ø
ESRmax
=
=
=
= 5.2mW
IRIPPLE
IRIPPLE
(8)
Two 47-µF and one 220-µF capacitors are selected to provide more than 250 µF of minimum capacitance and
5.2 mΩ of ESR.
8.2.2.4 Peak Current Rating of Inductor
With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum
saturation current rating for the inductor. The start-up charging current is approximated by Equation 9.
VOUT
C
×
1.2 V(2 47 mF 220 mF)
×
+
OUT
ICHARGE
0.251A
=
=
=
TSS
1.5 ms
(9)
1
1
+
=
+
IL _PEAK IOUT(max) 2 IRIPPLE
+
×
6 A 0.2512 A 23.25 A
=
+
I
CHARGE = 20 A
2
(10)
Table 2. Inductor Requirements
PARAMETER
VALUE
300
UNIT
nH
A
L
Inductance
IL(rms)
IL(peak)
RMS current (thermal rating)
Peak current (saturation rating)
20.07
23.25
A
8.2.2.5 Input Capacitor Selection (C8)
The input voltage ripple is divided between capacitance and ESR. For this design VRIPPLE(cap) = 150 mV and
VRIPPLE(esr) = 150 mV. The minimum capacitance and maximum ESR are estimated by Equation 11.
I
LOAD ´ VOUT
20´1.2V
CIN(min)
=
=
= 33.3uF
V
RIPPLE(CAP) ´ VIN ´FSW 150mV ´8V ´ 600kHz
(11)
(12)
VRIPPLE(ESR)
150 mV
23A
ESRMAX
=
=
= 6.5 mW
1
ILOAD
+
2IRIPPLE
The RMS current in the input capacitors is estimated by Equation 13.
=
´
´
=
´ ´ - =
0.15 (1 0.15) 7.14 Arms
–
1 D
IRMS _ CIN ILOAD
D
20 A
(
)
(13)
Three 1210, 10-µF, 25-V, X5R ceramic capacitors are selected. Higher voltage capacitors are selected to
minimize capacitance loss at the DC bias voltage to ensure the capacitors allow sufficient capacitance at the
working voltage.
8.2.2.6 MOSFET Switch Selection (Q1 and Q2)
Reviewing available TI NexFET MOSFETs using the TI NexFET MOSFET selection tool, the CSD16410Q5A and
CSD16321Q5 5-mm × 6-mm MOSFETs are selected.
These two FETs have maximum total gate charges of 5 nC and 10 nC, respectively.
8.2.2.7 Bootstrap Capacitor (C6)
To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than
50 mV.
CBoost = 20 ´QG1 = 20´ 5 nC = 100 nF
(14)
Copyright © 2017, Texas Instruments Incorporated
15
TPS40345
ZHCSH69 –DECEMBER 2017
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8.2.2.8 VDD Bypass Capacitor (C7)
Per this TPS40345 data sheet, select a 1-uF X5R or better ceramic bypass capacitor for VDD.
8.2.2.9 BP Bypass Capacitor (C5)
Per the TPS40345 data sheet, a minimum 1-uF ceramic capacitance is required to stabilize the BP regulator. To
limit regulator noise to less than 10 mV, the value of the bypass capacitor is calculated in Equation 15.
CBP = 100´MAX(QG1,QG2
)
(15)
Because Q2 is larger than Q1, and the total gate charge of Q2 is 10 nC, a BP capacitor of 1 µF is calculated. A
standard value of 1 µF is selected to limit noise on the BP regulator.
8.2.2.10 Short-Circuit Protection (R11)
The TPS40345 uses the negative drop across the low-side FET at the end of the OFF-time to measure the
inductor current. Allowing for 30% over maximum load and 20% rise in RDS(on)Q1 for self-heating, the voltage drop
across the low-side FET at current limit is given by Equation 16.
1
2
VOC (1.3 I
= ´
1 Iripple ) 1.2 R
(1.3 20 A
´
6 A) 1.2 4.6 m
´ ´ W =
127 mV
-
´
´
=
-
LOAD
DSONG2
2
(16)
The TPS40345 internal temperature coefficient helps compensate for the MOSFET’s RDS(on) temperature
coefficient, so the current limit programming resistor is selected by Equation 17.
VOC - VOCLOS(min)
127 mV
-
(
–
8 mV)
A
RCS
=
=
= 7.1kW
2
´
IOCSET(min)
2
´
9.5
m
(17)
8.2.2.11 Feedback Divider (R4, R5)
The TPS40345 controller uses a full operational amplifier with an internally fixed 0.6-V reference. R4 is selected
between 10 kΩ and 50 kΩ for a balance of feedback current and noise immunity. With R4 set to 10 kΩ, The
output voltage is programmed with a resistor divider given by Equation 18.
VFB R4
´
0.600 V ´10.0 kW
R7 =
=
= 10 kW
VOUT - VFB
1.2 V - 0.600 V
(18)
8.2.2.12 Compensation: (C2, C3, C4, R3, R6)
Using the TPS40k Loop Stability Tool for 100-kHz bandwidth and 60° phase margin with a R4 value of 10.0 kΩ,
the following values are returned.
•
•
•
•
•
C4 = 680 pF
C5 = 100 pF
C6 = 680 pF
R1 = 10 kΩ
R2 = 1.5 kΩ
16
Copyright © 2017, Texas Instruments Incorporated
TPS40345
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ZHCSH69 –DECEMBER 2017
8.2.3 Application Curves
95
100
80
225
180
135
90
V
= 8 V
IN
90
85
80
75
70
65
Phase
60
V
= 14 V
IN
40
V
= 12 V
IN
20
45
0
0
60
55
50
–20
–40
–60
–45
–90
–135
Gain
0
5
10
15
20
1 k
10 k
100 k
1 M
I
– Load Current – A
LOAD
f – Frequency – Hz
Figure 14. Gain and Phase vs Frequency
Figure 13. Efficiency vs Load Current
Figure 15. Output Ripple 10 mV/div, 2-µs/div, 20-MHz Bandwidth
9 Power Supply Recommendations
The TPS40345 device is designed to operate from an input voltage supply between 3 V and 20 V. This input
supply must remain within the input voltage supply range. This supply must be well regulated.
Copyright © 2017, Texas Instruments Incorporated
17
TPS40345
ZHCSH69 –DECEMBER 2017
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
•
For MOSFET or power block layout, follow the layout recommendations provided for the MOSFET or power
block selected.
•
Connect VDD to VIN as close as possible to the drain connection of the high-side FET to avoid introducing
additional drop, which could trigger short-circuit protection.
•
•
•
•
Place VDD and BP to GND capacitors within 2 mm of the device and connected to the thermal pad (GND).
Connect the FB to GND resistor to the thermal tab (GND) with a minimum 10-mil wide trace.
Place VOUT to FB resistor within 2 mm of the FB pin.
Connect the EN/SS-to-GND capacitor to the thermal tab (GND) with a minimum 10-mil-wide trace. It may
share this trace with FB to GND.
•
•
•
If a BJT or MOSFET is used to disable EN/SS, place it within 5 mm of the device.
If a COMP to GND resistor is used, place it within 5 mm of the device.
All COMP and FB traces should be kept minimum line width and as short as possible to minimize noise
coupling.
•
•
EN/SS should not be routed more than 20 mm from the device.
If multiple layers are used, extend GND under all components connected to FB, COMP and EN/SS to reduce
noise sensitivity.
•
HDRV and LDRV must provide short, low inductance paths of 5 mm or less to the gates of the MOSFETs or
power block.
•
•
Place no more than 1 Ω of resistance between HDRV or LDRV and their MOSFET or power block gate pins.
LDRV / OC to GND current limit programming resistor may be placed on the far side of the MOSFET if
necessary to ensure a short connection from LDRV to the gate of the low-side MOSFET.
•
•
Place the BOOT to SW resistor and capacitor within 4 mm of the device using a minimum of 10-mil-wide
trace. The full width of the component pads are preferred for trace widths if design rules allow.
If via must be used between the HDRV, SW and LDRV pins and their respective MOSFET or power block
connections, use a minimum of two vias to reduce parasitic inductance
•
•
Refer to the land pattern data for the preferred layout of thermal vias within the thermal pad.
TI recommends extending the top-layer copper area of the thermal pad (GND) beyond the package a
minimum 3 mm between pins 1 and 10 and 5 and 6 to improve thermal resistance to ambient of the device.
18
Copyright © 2017, Texas Instruments Incorporated
TPS40345
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ZHCSH69 –DECEMBER 2017
10.2 Layout Example
Figure 16. Top Copper With Components
Figure 17. Top Internal Copper Layout
..
..
..
..
Figure 18. Bottom Internal Copper Layout
Figure 19. Bottom Copper Layer
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19
TPS40345
ZHCSH69 –DECEMBER 2017
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11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 文档支持
11.2.1 相关文档
这些参考资料、设计工具以及附加参考资料的链接（包括设计软件）均可在 http://power.ti.com 网站上找到
1. 更多 PowerPAD™ 信息可在 应用 简介 (SLMA002) 和 (SLMA004) 中找到。
2. 了解开关模式电源中的降压功率级
3. 《低电压直流/直流转换器内部探究》 – SEM1500 主题 5 – 2002 年研讨会系列
4. 《设计稳定控制环路》– SEM 1400 – 2001 年研讨会系列
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS40345DRCR
TPS40345DRCT
ACTIVE
ACTIVE
VSON
VSON
DRC
DRC
10
10
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-20 to 85
-20 to 85
0345
0345
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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Addendum-Page 2
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17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS40345DRCR
TPS40345DRCT
VSON
VSON
DRC
DRC
10
10
3000
250
330.0
180.0
12.4
12.5
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS40345DRCR
TPS40345DRCT
VSON
VSON
DRC
DRC
10
10
3000
250
338.0
205.0
355.0
200.0
50.0
33.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
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PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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