TPS48110AQDGXRQ1 [TI]
具有保护和诊断功能的 3.5V 至 80V 汽车高侧驱动器 | DGX | 19 | -40 to 125;
| 型号： | TPS48110AQDGXRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有保护和诊断功能的 3.5V 至 80V 汽车高侧驱动器 | DGX | 19 | -40 to 125 驱动 驱动器 |
| 文件： | 总38页 (文件大小：3531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS4811-Q1
ZHCSMA7B –JANUARY 2022 –REVISED SEPTEMBER 2022
TPS4811-Q1 具有保护和诊断功能的100V 汽车智能高侧驱动器
1 特性
3 说明
• 具有符合AEC-Q100 标准的下列特性
TPS4811x-Q1 系列是一款具有保护和诊断功能的
100V 智能高侧驱动器。该器件的宽工作电压范围为
3.5V 至80V，适合12V、24V 和48V 系统设计。
– 器件温度等级1：
–40°C 至+125°C 环境工作温度范围
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 功能安全型
它具有强大的4A 灌电流(PD) 和拉电流(PU) 栅极驱动
器，可在大电流系统设计中使用并联 FET 进行电源切
换。将INP 用作栅极驱动器控制输入。
– 可提供用于功能安全系统设计的文档
• 3.5V 至80V 输入范围（绝对最大值100V）
• 具有100µA 容量的集成12V 电荷泵
• 1.7µA 低关断电流（EN/UVLO = 低电平）
• 强上拉和下拉栅极驱动器：4A
• 驱动外部背对背N 沟道MOSFET
• 具有集成预充电开关驱动器(TPS48111-Q1) 以驱动
容性负载的变体
• 具有可调断路器计时器(TMR) 和故障标志输出
(FLT_I) 的两级可调过流保护(IWRN、ISCP)
• 快速短路保护：1.2µs (TPS48111-Q1)、5µs
(TPS48110-Q1)
该器件具有精确的电流检测(< ±2%) 输出(IMON) 支持
系统，可用于能源管理。该器件集成了具有 FLT_I 输
出的两级过流保护，具有完全可调的阈值和响应时间。
可以配置自动重试和锁存故障行为。该器件具有远程过
热保护，具有FLT_T 输出。
TPS48111-Q1 将预充电驱动器 (G) 与控制输入
(INP_G) 集成。此功能支持必须驱动大容性负载的设
计。在关断模式下，控制器在 48V 电源输入下的总 IQ
为1.7µA。
TPS4811x-Q1 采用 19 引脚 VSSOP 封装，在相邻的
高压和低压引脚之间移除了一个引脚，提供0.8 毫米的
间隙。
• 准确的模拟电流监控器(IMON) –
30mV VSNS 下< ±2%
• 可调节欠压锁定(UVLO) 和过压保护(OV)
• 具有故障标志输出(FLT_T) 的远程过热检测
(DIODE)
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS48110-Q1、
TPS48111-Q1
VSSOP (19)
5.1mm × 3.0mm
2 应用
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
• 配电盒
• 车身控制模块
• 直流/直流转换器
• 电池管理系统
Q3
R
Pre-charge
Q2
Supply Input
Q4
Q1
G
Q1
RSNS
VBATT
(48 V)
VOUT
Q2
RSNS
VOUT
VBATT
(48 V)
RSET
RISCP
CBLK
CBST
RSET
RISCP
CBST
VS ISCP CS+ CS-
OV
PU PD DIODE
SRC
BST
R1
R2
VS ISCP CS+ CS-
EN/UVLO
BST
DIODE
PU PD SRC
VCC
R3
OFF
ON
G
G
VCC
TPS48110-Q1
TPS48111-Q1
FLT_I
ON OFF
OFF
INP
VCC
R2
VCC
R4
R1
EN/UVLO
ON OFF
ON
INP_G
FLT_I
FLT_T
INP
FLT_T
IMON
IWRN
RIWRN
TMR
GND
IMON
IWRN
TMR
GND
RIWRN
CTMR
RIMON
RIMON
CTMR
用于直流/直流转换器的断路器
适用于加热器负载的智能高侧驱动器
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEE5
TPS4811-Q1
ZHCSMA7B –JANUARY 2022 –REVISED SEPTEMBER 2022
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Table of Contents
8.4 Device Functional Mode (Shutdown Mode)..............18
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application: Driving HVAC PTC Heater
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Switching Characteristics............................................7
8 Detailed Description........................................................8
8.1 Overview.....................................................................8
8.2 Functional Block Diagram...........................................8
8.3 Feature Description.....................................................9
Load on KL40 Line in Power Distribution Unit.............19
9.3 Tpyical Application: Driving B2B FETs With Pre-
Charging the Output Capacitance...............................26
9.4 Layout....................................................................... 28
10 Device and Documentation Support..........................30
10.1 接收文档更新通知................................................... 30
10.2 支持资源..................................................................30
10.3 Trademarks.............................................................30
10.4 Electrostatic Discharge Caution..............................30
10.5 术语表..................................................................... 30
11 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (June 2022) to Revision B (September 2022)
Page
• 进行了全面更新以包含TPS48110-Q1 可订购产品。..........................................................................................1
Changes from Revision * (January 2022) to Revision A (June 2022)
Page
• 向特性部分添加了功能安全要点........................................................................................................................ 1
• Corrected pin number for TPS48111-Q1 VS pin.................................................................................................3
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5 Device Comparison Table
TPS48110-Q1
TPS48111-Q1
Overvoltage protection
Pre-charge driver
Yes
No
No
Yes
Short-circuit protection
response time
5 µs
1.2 µs
Overtemperature fault
Auto-retry with fixed 512-ms timer
Latch-off
response
6 Pin Configuration and Functions
1
EN/UVLO
1
EN/UVLO
VS
VS
20
20
19
18
17
ISCP
OV
2
3
INP_G
INP
2
3
ISCP
19
18
17
CS+
CS-
INP
CS+
CS-
FLT_T
4
5
4
5
FLT_T
FLT_I
FLT_I
6
6
PU
PD
GND
GND
15
PU
PD
15
7
8
IMON
IMON
7
8
14
13
14
13
IWRN
TMR
IWRN
TMR
SRC
SRC
BST
12
11
9
12
11
9
BST
G
10
N.C
10
DIODE
DIODE
图6-1. VSSOP 19-Pin DGX Top View
表6-1. Pin Functions
PIN
TPS48110-Q1
TPS48111-Q1
TYPE
DESCRIPTION
NAME
DGX-19 (VSSOP)
EN/UVLO input. A voltage on this pin above 1.21 V enables normal
operation. Forcing this pin below 0.3 V shuts down the TPS4811x-
Q1, reducing quiescent current to approximately 1.7 µA (typical).
Optionally connect to the input supply through a resistive divider to
set the undervoltage lockout. When EN/UVLO is left floating an
internal pull down of 100 nA pulls EN/UVLO low and keeps the
device in OFF state.
EN/UVLO
1
1
I
Adjustable overvoltage threshold input. Connect a resistor ladder
from input supply, OV to GND. When the voltage at OVP exceeds
the overvoltage cut-off threshold then the PD is pulled down to
SRC turning OFF the external FET. When the voltage at OV goes
below OV falling threshold then PU gets pulled up to BST, turning
ON the external FET.
OV
2
I
—
OV must be connected to GND when not used. When OV is left
floating an internal pull down of 100 nA pulls OV low and keeps PU
pulled up to BST.
Input Signal. CMOS compatible input reference to GND that sets
the state of G pin. INP_G has an internal pull-down to GND to keep
G pulled to SRC when INP_G is left floating.
INP_G
INP
2
3
I
I
—
Connect INP_G to GND if the G drive functionality is unused.
Input Signal. CMOS compatible input reference to GND that sets
the state of PD and PU pins. INP has an internal pull-down to GND
to keep PD pulled to SRC when INP is left floating
3
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表6-1. Pin Functions (continued)
PIN
TPS48110-Q1
TPS48111-Q1
TYPE
DESCRIPTION
NAME
DGX-19 (VSSOP)
Open Drain Fault Output. This pin asserts low when
overtemperature fault is detected.
FLT_T
4
5
4
O
Open Drain Fault Output. This pin asserts low after the voltage on
the TMR pin has reached the fault threshold of 1.1 V. This pin
indicates the pass transistor is about to turn off due to an
overcurrent condition. The FLT_I pin does not go to a high-
impedance state until the overcurrent condition and the auto-retry
time expire.
FLT_I
5
O
GND
6
7
6
7
G
O
Connect GND to system ground
Analog current monitor output. This pin sources a scaled down
ratio of current through the external current sense resistor RSNS. A
resistor from this pin to GND converts current to proportional
voltage. If unused, connect the pin to GND.
IMON
Overcurrent detection setting. A resistor across IWRN to GND sets
the over current comparator threshold.
Connect IWRN to GND if overcurrent protection feature is not
desired.
IWRN
TMR
8
9
8
9
I
I
Fault Timer Input. A capacitor across TMR pin to GND sets the
times for fault warning, fault turn-off (FLT_I) and retry periods.
Leave it open for fastest setting. Connect TMR to GND to disable
overcurrent protection.
Diode connection for temperature sensing. Connect this pin to
base and collector of an MMBT3904 NPN BJT.
Connect DIODE to GND, if remote overtemperature protection
feature is not desired.
DIODE
G
10
10
11
I
GATE of external pre-charge FET. Connect to the GATE of the
external FET.
Leave the G pin floating if the G drive functionality is unused.
O
—
11
12
13
14
N.C
BST
SRC
PD
No connect
—
12
13
14
—
O
O
O
High Side Bootstrapped Supply. An external capacitor with a
minimum value of > Qg(tot) of the external FET must be connected
between this pin and SRC.
Source connection of the external FET
High Current Gate Driver Pull-Down. This pin pulls down to SRC.
For the fastest turn-off, tie this pin directly to the gate of the
external high side MOSFET.
High Current Gate Driver Pull-Up. This pin pulls up to BST.
Connect this pin to PD for maximum gate drive transition speed. A
resistor can be connected between this pin and the gate of the
external MOSFET to control the in-rush current during turn-on.
PU
15
15
O
CS-
17
18
17
18
I
I
Current sense negative input
Current sense positive input. Connect a 100-Ωresistor across
CS+ to the external current sense resistor.
CS+
Short circuit detection threshold setting. Connect ISCP to CS–if
short-circuit protection is not desired.
ISCP
VS
19
20
19
20
I
Power Supply pin of the controller
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–1
MAX
UNIT
Input Pins
Input Pins
Input Pins
Input Pins
Input Pins
Input Pins
Input Pins
100
VS, CS+, CS–, ISCP to GND
VS, CS+, CS–to SRC
100
–60
–30
–0.3
–0.3
–1
SRC to GND
100
PU, PD, G, BST to SRC
16
V
TMR, IWRN, DIODE to GND
OV, EN/UVLO, INP, INP_G, FLT_I , FLT_T to GND
5.5
20
0.3
CS+ to CS–
–0.3
I(FLT_I), I(FLT_T)
10
Sink current
Source current
Output Pins
mA
I(CS+) to I(CS–) , 1 msec
I(IMON)
100
–100
Internally limited
PU, PD, G, BST to GND
112
7.5
–30
–1
V
IMON to GND
(2)
Operating junction temperature, Tj
Storage temperature, Tstg
150
150
–40
–40
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
7.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
±750
±500
Corner pins (EN/UVLO, DIODE,
V(ESD) Electrostatic discharge
V
Charged device model (CDM), per
AEC Q100-011
G, VS)
Other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
0
NOM
MAX
80
UNIT
VS, CS+, CS- to GND
EN/UVLO, OV to GND
FLT_I, FLT_T to GND
IMON to GND
Input Pins
0
15
V
0
15
Output
Pins
0
5.5
VS, SRC to GND
22
0.1
–40
nF
µF
°C
External
Capacitor
BST to SRC
Tj
Operating Junction temperature(2)
150
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
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UNIT
7.4 Thermal Information
TPS4811-Q1
DGX
THERMAL METRIC(1)
19 PINS
87
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
26.5
43.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.5
43.3
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
TJ = –40 ℃to +125℃. V(VS) = V(CS+) = V(CS-) = 48 V, V(BST –SRC) = 12 V, V(SRC) = 0 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE
VS
Operating input voltage
3.5
80
V
I(Q)
Total System Quiescent current, I(GND) V(VS) = 48 V, V(EN/UVLO) = 2 V
SHDN current, I(GND) V(EN/UVLO) = 0 V, V(SRC) = 0 V
510
1.7
µA
µA
I(SHDN)
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
V(UVLOR)
V(UVLOF)
UVLO threshold voltage, rising
UVLO threshold voltage, falling
1.16
1.11
1.18
1.12
1.2
V
V
1.15
Enable threshold voltage for low Iq
shutdown, falling
V(ENF)
0.3
V
OVER VOLTAGE PROTECTION (OV) INPUT –TPS48110-Q1 Only
V(OVR)
V(OVF)
Overvoltage threshold input, risIng
Overvoltage threshold input, falling
1.16
1.11
1.18
1.12
1.2
V
V
TPS48110-Q1 Only
1.15
CHARGE PUMP (BST–SRC)
I(BST)
Charge Pump Supply current
V(BST –SRC) = 10 V
100
µA
V
Charge Pump Turn ON voltage
Charge Pump Turnoff voltage
11
V(BST –SRC)
13
V
V(BST –SRC) UVLO voltage threshold,
rising
8.2
V
V(BST UVLO)
V(BST –SRC) UVLO voltage threshold,
falling
6
8
V
V
V(BST –SRC)
Charge Pump Voltage at V(VS) = 3.5 V
GATE DRIVER OUTPUTS (PU, PD, G)
I(PU)
I(PD)
Peak Source Current
Peak Sink Current
3.7
4
A
A
Gate charge (sourcing) current, on
state
100
135
µA
I(G)
TPS48111-Q1 Only
Gate discharge (sinking) current, off
state
mA
CURRENT SENSE AND OVER CURRENT PROTECTION (CS+, CS–, IMON, ISCP, IWRN)
RSET = 100 Ω, RIMON = 5 kΩ, 10
Input referred offset (VSNS to VIMON
scaling)
kΩ (corresponds to VSNS = 6 mV to 30
mV) and Gain of 45 and 90
respectively.
V(OS_SET)
350
µV
–350
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7.5 Electrical Characteristics (continued)
TJ = –40 ℃to +125℃. V(VS) = V(CS+) = V(CS-) = 48 V, V(BST –SRC) = 12 V, V(SRC) = 0 V
PARAMETER
TEST CONDITIONS
RSET = 100 Ω, R(IWRN) = 41.2 kΩ
RSET = 100 Ω, R(IWRN) = 123 kΩ
MIN
TYP
30
MAX UNIT
OCP threshold threshold
OCP threshold threshold
SCP Input Bias current
28
32
mV
mV
µA
V(SNS_WRN)
ISCP
10
14.5
40
35
45
mV
mV
R(ISCP) = 2.1 kΩ
R(ISCP) = 750 Ω
V(SNS_SCP)
SCP threshold
20
DELAY TIMER (TMR)
I(TMR_SRC_CB)
I(TMR_SRC_FLT)
I(TMR_SNK)
TMR source current
77
2.5
2.5
µA
µA
µA
TMR source current
TMR sink current
INPUT CONTROLS (INP, INP_G), FAULT FLAG (FLT_I, FLT_T)
V(INP_H) , V(INP_G_H
V(INP_G_H) for TPS48111-Q1 Only
2
V
)
V(INP_L) , V(INP_G_L
V(INP_G_L) for TPS48111-Q1 Only
0.8
V
)
R(FLT_I), R(FLT_T)
FLT_x Pull-down resistance
70
Ω
TEMPERATURE SENSING AND PROTECTION (DIODE)
High level
Low level
160
10
µA
µA
℃
℃
℃
I(DIODE) External diode current source
T(DIODE_TSD_rising) DIODE sense TSD rising threshold
155
Internal TSD rising threshold
T(TSD_INT)
165
150
Internal TSD falling threshold
7.6 Switching Characteristics
TJ = –40 ℃to +125℃. V(VS) = V(CS+) = V(CS-) = 48 V, V(BST –SRC) = 12 V, V(SRC) = 0 V
PARAMETER
TEST CONDITIONS
INP ↑to PU ↑, CL = 47 nF
INP ↓to PD ↓, CL = 47 nF
INP_G ↑to G ↑, CL = 1 nF
INP_G ↓to G ↓, CL = 1 nF
UVLO ↓to PD ↓, CL = 47 nF
MIN
TYP
2
MAX UNIT
tPU(INP_H)
INP Turn ON propogation Delay
INP Turn OFF propogation Delay
INP_G Turn ON propogation Delay
INP_G Turn OFF propogation Delay
UVLO Turn OFF Propogation Delay
µs
µs
µs
µs
µs
tPD(INP_L)
1
tG(INP_G_H)
tG(INP_G_L)
tPD(UVLO_OFF)
25
1
3
UVLO to PU Turn ON Propogation
Delay with CBT pre-biased > VPORF
and INP kept high
EN/UVLO ↑to PU ↑, CL = 47 nF,
INP = 2 V
tPU(UVLO_ON)
tPD(OV_OFF)
3
µs
OV Turn Off progopation Delay
3
5
µs
µs
OV ↑to PD ↓, CL = 47 nF
(VCS+ –VCS–) ↑I(SCP) to PD ↓, CL
= 47 nF, TPS48110–Q1 Only
Short Circuit Protection propogation
Delay
tPD(IFLT_OFF)
(VCS+ –VCS–) ↑ to I(SCP) PD ↓,
CL = 47 nF, TPS48111-Q1 Only
1.2
290
260
512
µs
µs
tFLT_I(IFLT_ASSERT) FLT_I assertion delay
tFLT_I(IFLT_DEASSER
FLT_I de-assertion delay
µs
T)
tFLT_T(AR)
TSD Auto-retry
TPS48110-Q1 Only
msec
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8 Detailed Description
8.1 Overview
The TPS4811x-Q1 family is a 100-V smart high side driver with protection and diagnostics. With wide operating
voltage range of 3.5 V –80 V, the device is suitable for 12-V, 24-V, and 48-V system designs.
The device has a strong 4-A sink (PD) and source (PU) GATE driver that enables power switching using parallel
FETs in high current system designs. Use INP as the gate driver control input. MOSFET slew rate control (ON
and OFF) is possible by placing external R-C components.
The device has accurate current sensing (<±2 % at 30-mV VSNS) output (IMON) enabling systems for energy
management. The device has integrated two-level overcurrent protection with FLT_I output with complete
adjustability of thresholds and response time. Auto-retry and latch-off fault behavior can be configured.
The device features remote overtemperature protection with FLT_T output enabling robust system protection.
TPS48110-Q1 has an accurate overvoltage protection (<±2 %), providing robust load protection.
The TPS48111-Q1 integrates a pre-charge driver (G) with control input (INP_G). This feature enables system
designs that need to drive large capacitive loads by pre-charging first and then turning ON the main power FETs.
TPS4811x-Q1 has an accurate undervoltage protection (±3 %) using EN/UVLO pin. Pull EN/UVLO low (< 0.3 V)
to turn OFF the device and enter into shutdown state. In shutdown mode, the controller draws a total IQ of 1.7
µA at 48-V supply input.
8.2 Functional Block Diagram
Q2
RSNS
Q1
VOUT
VBATT
RISCP
ISCP
RSET
CS+
BST
CS-
DIODE
VS
PU
PD
SRC
4 A
3.7 A
Remote
Temp
sense
+
Internal
Regulators
EN
14.5 µA
EN
3.1 V
2.9 V
EN
R_Temp
VINT
POR
PU/PD_ON/OFF
+
PU/PD_ON/
OFF
CP (12 V)
EN
1V
VS
0.3V
FLT_I
100 µA
+
+
UVLO
EN/UVLO
INP
FLT_I
FLT_T
+
1.18 V
1.11 V
FLT_I
70
70
CS-
Gate Driver
control
logic
EN
Charge
pump
enable
logic
2 V
+
VREF
BST
SRC
0.8 V
+
VINT
FLT_T
OV
1.18 V
1.11 V
79 µA
/ 2.5 µA
FLT_T
4.5 V
6.5 V
R_Temp
TPS48110-Q1
GND
IMON
RIMON
IWRN
RIWRN
TMR
CTMR
图8-1. TPS48110-Q1 Functional Block Diagram
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R
Q3
V_Precharge
Q2
RSNS
Q1
VBATT
VOUT
RISCP
ISCP
RSET
CS+
BST
CS-
DIODE
VS
PU
PD
G
SRC
4 A
3.7 A
0.14 A
Remote
Temp
sense
+
Internal
Regulators
EN
14.5 µA
EN
3.1 V
2.9 V
G_ON/
OFF
EN
VS
R_Temp
VINT
POR
100 µA
PU/PD_ON/OFF
+
PU/PD_ON/
OFF
G_ON/OFF
EN
BST
70
CP (12 V)
1 V
0.3 V
FLT_I
+
+
UVLO
EN/UVLO
INP
FLT_I
100 µA
FLT_T
+
1.18 V
1.11 V
FLT_I
CS-
Gate Driver
control
logic
EN
2 V
+
VREF
Charge
pump
enable
logic
0.8 V
BST
+
FLT_T
VINT
INP_G
SRC
2 V
79 µA
/2.5 µA
FLT_T
70
0.8 V
4.5 V
6.5 V
R_Temp
TPS48111-Q1
IMON
RIMON
GND
IWRN
RIWRN
TMR
CTMR
图8-2. TPS48111-Q1 Functional Block Diagram
8.3 Feature Description
8.3.1 Charge Pump and Gate Driver output (VS, PU, PD, BST, SRC)
图8-3 shows simplified diagram of the charge pump and gate driver circuit implementation. The device houses a
strong 3.7-A source and 4-A sink gate drivers. The strong gate drivers enable paralleling of FETs in high power
system designs ensuring minimum transition time in saturation region. A 12-V, 100-µA charge pump is derived
from VS terminal and charges the external boot-strap capacitor, CBST that is placed across the GATE driver (BST
and SRC).
In switching applications, if the charge pump supply demand is higher than 100 µA, then supply BST externally
using a low leakage diode and 12-V supply as shown in the 图8-3.
VS is the supply pin to the controller. With VS applied and EN/UVLO pulled high, the charge pump turns ON and
charges the CBST capacitor. After the voltage across CBST crosses V(BST_UVLOR), the GATE driver section is
activated. The device has a 1-V (typical) UVLO hysteresis to ensure chattering less performance during initial
GATE turn ON. Choose CBST based on the external FET’s QG and allowed dip during FET turn ON. The
charge pump remains enabled until the BST to SRC voltage reaches 12.3 V, typically, at which point the charge
pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until the BST to
SRC voltage discharges to 11.7 V typically at which point the charge pump is enabled. The voltage between BST
and SRC continue to charge and discharge between 12.3 V and 11.7 V as shown in the 图8-4.
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VS
48 V
CS+
To
current
sensing
RSNS
CS-
Charge
pump (12 V)
12 V
D1*
100 µA
BST
CBST
Q1
PU
PD
INP
Level Shifter
Q2
SRC
TPS4811x-Q1
RLOAD
图8-3. Gate Driver
TON
TDRV_EN
TOFF
VIN
Vs
0V
VEN/UV LO
12.3 V
11.7 V
VBST-SRC
7.5 V
V(BST UVLOR)
GATE DRIVER
ENABLE
图8-4. Charge Pump Operation
Use the following equation to calculate the initial gate driver enable delay.
CBST × V(BST_UVLOR)
TDRV_EN
Where,
=
100 µA
(1)
C(BST) is the charge pump capacitance connected across BST and SRC pins,
V(BST_UVLOR) = 7.5 V (typical).
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If TDRV_EN needs to be reduced then pre-bias BST terminal externally using an external 12-V supply through a
low leakage diode D1 as shown in 图8-3. With this connection TDRV_EN reduces to 350 µs.
8.3.2 Capacitive Load Driving
Certain end equipments like automotive power distribution unit power different loads including other ECUs.
These ECUs can have large input capacitances. If power to the ECUs is switched on in uncontrolled way, large
inrush currents can occur potentially damaging the power FETs.
To limit the inrush current during capacitive load switching, the following system design techniques can be used
with TPS4811x-Q1 devices.
8.3.2.1 FET Gate Slew Rate Control
For limiting inrush current during turn ON of the FET with capacitive loads, use R1, R2, C1 as shown in 图 8-5.
The R1 and C1 components slow down the voltage ramp rate at the gate of the FET. The FET source follows the
gate voltage resulting in a controlled voltage ramp across the output capacitors.
BST
CBST
Q1
R1
PU
PD
INP
Level Shifter
R2
C1
SRC
TPS4811x-Q1
CLOAD
图8-5. Inrush Current limiting
Use the 方程式2 to calculate the inrush current during turn-ON of the FET.
VBATT
IINRUSH
=
CLOAD
×
Tcharge
(2)
(3)
0.63 × V(BST-SRC) × CLOAD
R1 × C1
IINRUSH
=
Where,
CLOAD is the load capacitance, VBATT is the input voltage and Tcharge is the charge time, V(BST-SRC) is the charge
pump voltage (12 V),
Use a damping resistor R2 (~ 10 Ω) in series with C1. 方程式 3 can be used to compute required C1 value for a
target inrush current. A 100 kΩresistor for R1 can be a good starting point for calculations.
Connecting PD pin of TPS4811x-Q1 directly to the gate of the external FET ensures fast turn OFF without any
impact of R1 and C1 components.
C1 results in an additional loading on CBST to charge during turn ON. Use 方程式4 to calculate the required CBST
value.
CBST > Qg(total) + 10 × C1
(4)
Where, Qg(total) is the total gate charge of the FET.
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8.3.2.2 Using Precharge FET - (with TPS48111-Q1 Only)
In high-current applications where several FETs are connected in parallel, the gate slew rate control for the main
FETs is not recommended due to unequal distribution of inrush currents among the FETs. This action makes
FET selection complex and results in over sizing of the FETs.
The TPS48111-Q1 integrates precharge gate driver (G) with a dedicated control input (INP_G). This feature can
be used to drive a separate FET that can be used to precharge the capacitive load. 图 8-6 shows the precharge
FET implementation for capacitive load charging using TPS48111-Q1. An external capacitor Cg reduces the gate
turn-ON slew rate and controls the inrush current.
VBATT
BST
CBST
Q1
PU
PD
INP
Level Shifter
Level Shifter
Q2
SRC
G
INP_G
Q3
Rg
Cg
IG
VOUT
CLOAD
BST
TPS48111-Q1
图8-6. Capacitor Charging Using Gate Slew Rate Control of Precharge FET
During power up with EN/UVLO high and C(BST) voltage above V(BST_UVLOR) threshold, INP and INP_G controls
are active. For the precharge functionality, drive INP low to keep the main FETs OFF and drive INP_G high. G
output gets pulled up to BST with IG. Use 方程式5 to calculate the required Cg value.
IINRUSH
IG = Cg ×
COUT
(5)
Where,
IG is 100 µA (typical),
Use 方程式 2 to calculate the IINRUSH. A series resistor Rg must be used in conjunction with Cg to limit the
discharge current from Cg during turn-off . The recommended value for Rg is between 220 Ω to 470 Ω. After the
output capacitor is charged, turn OFF the precharge FET by driving INP_G low. G gets pulled low to SRC with
an internal 135-mA pulldown switch. The main FETs can be turned ON by driving INP high.
图8-7 shows other system design approaches to charge large output capacitors in high current applications. The
designs involve an additional power resistor in series in series with precharge FET. The back-to-back FET
topology shown is typically used in bi-directional power control applications like battery management systems.
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Q2
R
Q3
R
Q4
Q3
G
Q1
Q2
Q1
RSNS
VOUT
CBLK
RSNS
VOUT
CBLK
VBATT
(48 V)
VBATT
(48 V)
RSET
RISCP
CBST
RSET
RISCP
CS+ CS-
ISCP
PU PD DIODE
G
VS
VS ISCP CS+ CS-
EN/UVLO
SRC
BST
DIODE
PU PD
SRC
BST
CBST
VCC
R1
OFF
ON
ON OFF
OFF
EN/UVLO
INP
OFF
ON
G
G
VCC
TPS48111-Q1
VCC
R2
TPS48111-Q1
ON OFF
INP
VCC
R2
R1
ON
INP_G
FLT_I
OFF
ON
INP_G
FLT_I
FLT_T
IMON
IWRN
RIWRN
TMR
GND
FLT_T
IMON
IWRN
RIWRN
TMR
GND
CTMR
RIMON
CTMR
RIMON
图8-7. TPS48111-Q1 application Circuits for Capacitive Load Driving Using Precharge FET and a Series
Power Resistor
8.3.3 Overcurrent and Short-Circuit Protection
TPS4811x-Q1 has two-level current protection.
• Adjustable overcurrent protection (IOC) threshold and response time (TOC),
• Adjustable short-circuit threshold (ISC) with internally fixed fast response (TSC).
图8-8 shows the I-T characteristics.
Time
TOC
Nominal current
Over current
No Shutdown
Shutdown with
adjustable delay
Short circuit
Immediate
shutdown
TSC
Current
IOC
ISC
图8-8. Overcurrent and Short-Circuit Protection Characteristics
The device senses the voltage across the external current sense resistor through CS+ and CS–. Set the circuit
breaker detection threshold using an external resistor RIWRN across IWRN and GND. Use 方程式 6 to calculate
the required RIWRN value.
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11.9 × RSET
RIWRN (Ω) =
RSNS × IOC
(6)
Where, RSET is the resistor connected across CS+ and VS,RSNS is the current sense resistor, IOC is the
overcurrent level
8.3.3.1 Overcurrent Protection With Auto-Retry
The C(TMR) programs the over current protection delay (TOC) and auto-retry time (TRETRY). Once the voltage
across CS+ and CS– exceeds the set point, the C(TMR) starts charging with 77-µA pullup current. After the
C(TMR) charges up to V(TMR_FLT), FLT_I asserts low providing warning on impending FET turn OFF. After C(TMR)
charges to V(TMR_OC), PD pulls low to SRC turning OFF the FET. Post this event, the auto-retry behavior starts.
The C(TMR) capacitor starts discharging with 2.5-uA pulldown current. After the voltage reaches V(TMR_Low) level,
the capacitor starts charging with 2.5-uA pullup. After 32 charging, discharging cycles of C(TMR) the FET turns
ON back and FLT_I de-asserts after de-assertion delay of 260 µs.
Use 方程式7 to calculate the TOC duration.
1.2 × CTMR
TOC
=
77.5 µ
(7)
(8)
Where, TOC is the delay to turn OFF the FET, CTMR is the capacitance across TMR to GND.
Use 方程式8 to calculate the TFLT duration.
1.1 × CTMR
TFLT
=
77.5 µ
Where, TFLT is the FLT_I assertion delay.
The auto-retry time can be computed as, TRETRY = 22.7 × 106 × CTMR
If the overcurrent pulse duration is below T(OC) then the FET remains ON and C(TMR) gets discharged using
internal pull down switch.
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IOC
TPULSE
0 A
TOC = TCB
VINT
VTMR_OC
VTMR_FLT
VTMR_Low
77 µA
/ 5 µA
TMR
1st
2nd
32nd
2.5 µA
Vcc
0 V
TPS4811x-Q1
TWRN
TFLT = 0.9xTCB
12 V
0 V
图8-9. Overcurrent Protection With Auto-Retry
8.3.3.2 Overcurrent Protection With Latch-Off
Connect an approximately 100-kΩ resistor across C(TMR) as shown in 图 8-10. With this resistor, during the
charging cycle, the voltage across C(TMR) gets clamped to a level below V(TMR_OC) resulting in a latch-off
behavior.
Toggle INP or EN/UVLO (below ENF) or power cycle VS below VSPORF to reset the latch. At low edge, the timer
counter is reset and C(TMR) is discharged. PU pulls up to BST when INP is pulled high.
IOC
TPULSE
0 A
TOC = TCB
VTMR_OC
The resistor across TMR to GND prevents the VTMR to charge to upper threshold
VTMR_FLT
VTMR_Low
and the counter does not see next counts, resulting in FET to stay latch OFF
VINT
77 µA
/ 5 µA
1st
TMR
Vcc
0 V
100 kΩ
2.5 µA
TPS4811x-Q1
TWRN
TFLT = 0.9xTCB
12 V
0 V
When INP is pulled low, the timer counter is reset
and TMR cap is discharged
Starts a fresh
turn ON cycle
图8-10. Overcurrent Protection With Latch-Off
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8.3.4 Short-Circuit Protection
Connect a resistor, RISCP as shown in 图8-11.
Use 方程式9 to calculate the required RISCP value.
ISC × RSNS
600
RISCP (Ω) =
14.5 µ
(9)
Where, RSNS is the current sense resistor, and ISC is the desired short-circuit protection level. After the current
exceeds the ISC threshold then, PD pulls low to SRC within 1.2 µs in TPS48111-Q1 and 5 µs in TPS48110-Q1,
protecting the FET. FLT_I asserts low at the same time. Subsequent to this event, the charge and discharge
cycles of C(TMR) starts similar to the behavior post FET OFF event in the over current protection scheme.
Latch-off can also achieved in the similar way as explained in the overcurrent protection scheme.
8.3.5 Analog Current Monitor Output (IMON)
TPS4811x-Q1 features an accurate analog load current monitor output (IMON) with adjustable gain. The current
source at IMON terminal is configured to be proportional to the current flowing through the RSNS current sense
resistor. This current can be converted to a voltage using a resistor RIMON from IMON terminal to GND terminal.
This voltage, computed using 方程式10 can be used as a means of monitoring current flow through the system.
Use 方程式10 to calculate the VIMON
.
VIMON = (VSNS + VOS_SET) × Gain
(10)
Where VSNS = ILOAD × RSNS and VOS_SET is the input referred offset (± 350 µV) of the current sense amplifier
(VSNS to VIMON scaling). Use the following equation to calculate gain.
0.9 × RIMON
Gain =
RSET
(11)
Where 0.9 is the current mirror factor between the current sense amplifier and the IMON pass FET.
The maximum voltage range for monitoring the current (V(IMONmax)) is limited to minimum([V(VS) –0.5V], 5.5V)
to ensure linear output. This puts limitation on maximum value of RIMON resistor. The IMON pin has an internal
clamp of 6.5 V (typical).
Accuracy of the current mirror factor is < ± 1%. Use the following equation to calculate the overall accuracy of
VIMON
.
VOS_SET
× 100
% VIMON
=
VSNS
(12)
图 8-11 shows external connections and simplified block diagram of current sensing and overcurrent protection
implementation.
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RSNS
VIN
RISCP
ISCP
RSET
50
100
-
CS+
CS-
14.5 µA
+
CS-
To OCP Logic
VREF
+
4.5 V
6.5 V
TPS4811x-Q1
IMON
RIMON
IWRN
RIWRN
图8-11. Current sensing and Overcurrent protection
8.3.6 Overvoltage (OV) and Undervoltage Protection (UVLO)
VIN
R1
R1
EN/UVLO
EN/UVLO
+
+
UVLOb
UVLOb
1.18 V
1.12 V
1.18 V
R2
R2
1.12 V
OV
+
OVP
R3
1.18 V
TPS48111-Q1
1.12 V
TPS48110-Q1
图8-12. Programming Overvoltage and Undervoltage Protection Threshold
8.3.7 Remote Temperature sensing and Protection (DIODE)
The device features an integrated remote temperature sensing, protection and dedicated fault output. With a
companion BJT, MMBT3904 as a remote temperature sense element, the controller gets the temperature
information of the sense point. Connect the DIODE pin of TPS4811x-Q1 to the collector, base of a MMBT3904
BJT. After the sensed temperature reaches approximately 155ºC, the device pulls PD low to SRC, turning off the
external FET and also asserts FLT_T low. After the temperature reduces to 125ºC (minimum), an internally fixed
auto-retry cycle of 512 ms commences. FLT_T de-asserts and the external FET turns ON after the retry duration
of 512 ms is lapsed.
In TPS48111-Q1, after the sensed temperature crosses 155°C, PD and G get pulled low to SRC. After the TSD
hysteresis, PU and G stays latched OFF. Latch gets reset by toggling EN/UVLO below V(ENF) or by power cycling
VS below VSPORF
.
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8.3.8 TPS4811x-Q1 as a Simple Gate Driver
图 8-13 shows application schematics of TPS4811x-Q1 as a simple gate driver in load disconnect switch as well
as back-to-back FETs driving topologies. The protection features like two- level overcurrent protection,
overvoltage protection, and overtemperature protection are disabled.
Q2
Q1
Q1
VOUT
VOUT
VIN
VIN
RSET
100
RSET
100
CBST
CBST
CS+ CS-
CS+ CS-
ISCP
VS
ISCP
VS
PU PD SRC
PU PD SRC
BST
BST
OFF
OFF
OFF
ON
ON
ON
ON
EN/UVLO
INP
EN/UVLO
INP
TPS48110-Q1
TPS48110-Q1
FLT_I
FLT_I
OFF
FLT_T
IMON
FLT_T
IMON
DIODE GND OV
DIODE GND OV
TMR
IWRN
IWRN
TMR
图8-13. Connection Diagram of TPS48110-Q1 for Simple Gate Driver Design
8.4 Device Functional Mode (Shutdown Mode)
The TPS4811x-Q1 enters shutdown mode when the EN/UVLO pin voltage is below the specified input low
threshold, V(ENF). The gate drivers and the charge pump are disabled in shutdown mode. During shutdown
mode, the TPS4811x-Q1 enters low IQ operation with a total input quiescent consumption of 1.7 μA (typical).
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPS4811x-Q1 family is a 100-V smart high side driver with protection and diagnostics. The TPS4811x-Q1
device controls external N-channel MOSFETs and its drive architecture is suitable to drive back-to-back N-
Channel MOSFETs. The strong gate 4-A source and sink capabilities enable switching parallel MOSFETs in high
current applications such as circuit breaker in Powertrain (DC/DC converter), Battery Management System,
Electric Power Steering, and driving PTC heater loads etc. The TPS4811x-Q1 device provides two-level
adjustable overcurrent protection with adjustable circuit breaker timer, fast short-circuit protection, accurate
analog current monitor output, and remote overtemperature protection.
The variant TPS48111-Q1 features a separate pre-charge driver (G) with independent control input (INP_G).
This feature enables system designs that need to pre-charge the large output capacitance before turning ON the
main power path.
The following design procedure can be used to select the supporting component values based on the application
requirement. Additionally, a spreadsheet design tool TPS4811-Q1 Design Calculator is available in the web
product folder.
9.2 Typical Application: Driving HVAC PTC Heater Load on KL40 Line in Power Distribution Unit
Q2
Q1
RSNS
VBATT
(48 V)
VOUT
RSET
RISCP
R1
CBST
VS ISCP CS+ CS-
EN/UVLO
DIODE
RLOAD
PU PD
SRC
BST
VCC
R4
Heater
Element
R2
R3
OV
TPS48110-Q1
FLT_I
VCC
R5
FLT_T
INP
ON OFF
IMON
IWRN
TMR
GND
RIWRN
RIMON
CTMR
图9-1. Typical Application Schematic: Driving HVAC PTC Heater
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9.2.1 Design Requirements
表9-1 shows the design parameters for this application example.
表9-1. Design Parameters
PARAMETER
VALUE
48 V
Typical input voltage, VIN
Undervoltage lockout set point, VINUVLO
OV set point, VINOVP
24 V
58 V
Maximum load current, IOUT
12 A
Overcurrent protection threshold, IOC
15 A
20 A
Short-circuit protection threshold, ISC
Fault timer period (TOC
)
1 ms
Fault response
Auto-retry
4 ± 0.2 Ω
100 Hz
Load resistance, RLOAD
Load switching frequency, FSW
9.2.2 Detailed Design Procedure
Selection of Current Sense Resistor, RSNS
The recommended range of the overcurrent protection threshold voltage, V(SNS_WRN), extends from 10 mV to 30
mV. Values near the low threshold of 10 mV can be affected by the system noise. Values near the upper
threshold of 30 mV can cause high power dissipation in the current sense resistor. To minimize both the
concerns, 25 mV is selected as the overcurrent protection threshold voltage. The current sense resistor, RSNS
can be calculated using 方程式13.
V(SNS-WRN)
25 mV
15 A
1.66 mΩ
=
RSNS
=
=
IOC
(13)
The next smaller available sense resistor 1.5 mΩ, 1% is chosen.
Selection of Scaling Resistor, RSET
RSET is the resistor connected between VS and CS+ pins. This resistor scales the overcurrent protection
threshold voltage and coordinates with RIWRN and RIMON to determine the overcurrent protection threshold and
current monitoring output. The recommended range of RSET is 50 Ω–100 Ω.
RSET is selected as 100 Ω, 1% for this design example.
Programming the Overcurrent Protection Threshold –RIWRN Selection
The RIWRN sets the overcurrent protection (circuit breaker detection) threshold, whose value can be calculated
using 方程式14.
11.9 × RSET
RIWRN (Ω) =
RSNS × IOC
(14)
To set 15 A as overcurrent protection threshold, RIWRN value is calculated to be 52.88 kΩ.
Choose the closest available standard value: 54 kΩ, 1%
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.
Programming the Short-Circuit Protection Threshold –RISCP Selection
The RISCP sets the short-circuit protection threshold, whose value can be calculated using 方程式15.
ISC × RSNS
600
RISCP (Ω) =
14.5 µ
(15)
To set 20 A as overcurrent protection threshold, RISCP value is calculated to be 1.4 kΩ.
Choose the closest available standard value: 1.43 kΩ, 1%.
In case where large di/dt is involved, the system and layout parasitic inductances can generate large differential
signal voltages between ISCP and CS- pins. This action can trigger false short-circuit protection and nuisance
trips in the system. To overcome such scenario, TI recommends to add filter capacitor of 1 nF across ISCP and
CS- pins close to the device. Because nuisance trips are dependent on the system and layout parasitics, TI
recommends to test the design in a real system and tweaked as necessary.
Programming the Fault timer Period –CTMR Selection
For the design example under discussion, overcurrent transients are allowed for 1-ms duration. This blanking
interval, TOC (or circuit breaker interval, TCB) can be set by selecting appropriate capacitor CTMR from TMR pin to
ground. The value of CTMR to set 1 ms for TOC can be calculated using 方程式16.
TOC × 77.5 µA
64.58 nF
CTMR
=
=
1.2
(16)
Choose closest available standard value: 68 nF, 10%.
Selection of MOSFET, Q1
For selecting the MOSFET Q1, important electrical parameters are the maximum continuous drain current ID, the
maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX), and the drain-to-
source ON resistance RDSON
.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current.
The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest voltage seen in
the application. Considering 60 V as the maximum application voltage, MOSFETs with VDS voltage rating of 80 V
is suitable for this application.
The maximum VGS TPS4811-Q1 can drive is 13 V, so a MOSFET with 15-V minimum VGS rating must be
selected.
To reduce the MOSFET conduction losses, lowest possible RDS(ON) is preferred.
Based on the design requirements, IPB160N08S4-03ATMA1 is selected and its ratings are:
• 80-V VDS(MAX) and ±20-V VGS(MAX)
• RDS(ON) is 2.6-mΩtypical at 10-V VGS
• MOSFET Qg(total) is 86 nC
Selection of Bootstrap Capacitor, CBST
The internal charge pump charges the external bootstrap capacitor (connected between BST and SRC pins) with
approximately 100 μA. In case of switching applications, the BST must be powered externally from 12-V supply
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through a low-leakage silicon diode such as CMHD3595 to avoid collapsing the BST-SRC supply. This need is
determined by the value of the switching frequency and MOSFET gate charge.
The maximum possible frequency without external supply is given by 方程式17.
I(BST)
581 Hz
FSW,max
=
=
2 × Qg(total)
(17)
As the present application is switched at 100 Hz, external supply is not required. The minimum value of the
bootstrap capacitor can be calculated using 方程式18.
Qg(total)
86 nF
CBST
=
=
1 V
(18)
Choose closest available standard value: 100 nF, 10 %.
Setting the Undervoltage Lockout and Overvoltage Set Point
The undervoltage lockout (UVLO) and overvoltage set point are adjusted using an external voltage divider
network of R1, R2 and R3 connected between VS, EN/UVLO, OVP and GND pins of the device. The values
required for setting the undervoltage and overvoltage are calculated by solving 方程式19 and 方程式20.
R3
V(OVR)
=
× VINOVP
(R1 + R2 + R3)
(19)
R2 + R3
V(UVLOR)
=
× VINUVLO
(R1 + R2 + R3)
(20)
For minimizing the input current drawn from the power supply, TI recommends to use higher values of resistance
for R1, R2 and R3. However, leakage currents due to external active components connected to the resistor string
can add error to these calculations. So, the resistor string current, I(R123) must be chosen to be 20 times greater
than the leakage current of UVLO and OVP pins.
From the device electrical specifications, V(OVR) = 1.18 V and V(UVLOR) = 1.18 V. From the design requirements,
VINOVP is 58 V and VINUVLO is 24 V. To solve the equation, first choose the value of R1 = 470 kΩ and use 方程式
20 to solve for (R2 + R3) = 24.3 kΩ. Use 方程式19 and value of (R2 + R3) to solve for R3 = 10.1 kΩ and finally R2
= 14.2 kΩ. Choose the closest standard 1 % resistor values: R1 = 470 kΩ, R2 = 14.3 kΩ, and R3 = 10.2 kΩ.
Choosing the Current Monitoring Resistor, RIMON
Voltage at IMON pin VIMON is proportional to the output load current. This can be connected to an ADC of the
downstream system for monitoring the operating condition and health of the system. The RIMON must be
selected based on the maximum load current and the input voltage range of the ADC used. RIMON is set using 方
程式21.
0.9 × RIMON
VIMON = (VSNS + VOS_SET) ×
RSET
(21)
Where VSNS = IOC × RSNS and VOS_SET is the input referred offset (± 350 µV) of the current sense amplifier.
For IOC = 15 A and considering the operating range of ADC to be 0 V to 3.3 V (for example, VIMON = 3.3 V),
RIMON can be calculated as
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VIMON × RSET
16.52 k
RIMON
=
=
(VSNS + VOS_SET) × 0.9
(22)
Selecting RIMON value less than shown in 方程式 22 ensures that ADC limits are not exceeded for maximum
value of load current. Choose the closest available standard value: 16.5 kΩ, 1%.
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9.2.3 Application Curves
EN/UVLO
EN/UVLO
BST
BST
BST – SRC
BST – SRC
VOUT
VOUT
PU
PU
图9-2. Start-Up Profile of Bootstrap Voltage for INP 图9-3. Start-Up Profile of Bootstrap Voltage for INP
= GND = HIGH
INP
INP
PD
PU
VOUT
VOUT
PD – SRC
PU – SRC
图9-4. Turn-ON Response of TPS48110-Q1 for INP 图9-5. Turn-OFF Response of TPS48110-Q1 for INP
-> LOW to HIGH -> HIGH to LOW
INP
VIN
VOUT
VOUT
GATE
GATE
I_LOAD
图9-6. Overvoltage Cut-off Response at 58-V Level 图9-7. Load Switching at 100 Hz With TPS48110-
of TPS48110-Q1
Q1
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VIN
TMR
VOUT
FLT_I/
I_LOAD
PD
I_LOAD
IMON
图9-8. IMON Response During 10-A Load Step
图9-9. Overcurrent Response of TPS48110-Q1 for
a Load Step from 5 A to 18 A With 15-A
Overcurrent Protection Setting
TMR
TMR
FLT_I/
FLT_I/
PD
PD
I_LOAD
I_LOAD
图9-10. Auto-Retry Response of TPS48110-Q1 for 图9-11. Latch-off Response of TPS48110-Q1 for an
an Overcurrent Fault Overcurrent Fault
PD
INP
VOUT
FLT_I/
PD
FLT_I/
I_LOAD
I_LOAD
图9-12. Response During Coming Out of Overload
图9-13. Output Hot-Short Response of the
Fault With INP Reset
TPS48110-Q1 Device
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9.3 Tpyical Application: Driving B2B FETs With Pre-Charging the Output Capacitance
Q3
Rpre-ch
Pre-charge
Supply Input
Q4
G
Q2
Q1
RSNS
VOUT
CBLK
VBATT
(48 V)
RSET
RISCP
CBST
R1
VS ISCP CS+ CS-
EN/UVLO
SRC
BST
DIODE
PU PD
R2
G
G
VCC
TPS48111-Q1
ON OFF
INP
VCC
R2
R1
OFF
ON
INP_G
FLT_I
FLT_T
IWRN
RIWRN
IMON
GND
TMR
CTMR
RIMON
图9-14. Typical Application Schematic: Driving DC-DC Converter Loads in Powertrain
9.3.1 Design Requirements
表9-2 shows the design parameters for this application example.
表9-2. Design Parameters
PARAMETER
VALUE
48 V
Typical input voltage, VIN
Undervoltage lockout set point, VINUVLO
Maximum load current, IOUT
24 V
40 A
Overcurrent protection threshold, IOC
Short-circuit protection threshold, ISC
50 A
60 A
Fault timer period (TOC
)
1 ms
Fault response
Latch-off
400 μF
500 mA
Load capacitance, COUT
Inrush current limit, Iinrush
9.3.2 External Component Selection
By following similar design procedure as outlined in Detailed Design Procedure, the external component values
are calculated as below:
• RSNS = 500 μΩ
• RSET = 100 Ω
• RIWRN = 47 kΩto set 50 A as overcurrent protection threshold
• RISCP = 1.4 kΩto set 60 A as short-circuit protection threshold
• CTMR = 68 nF to set 1 ms circuit breaker time
• R1 and R2 are selected as 470 kΩand 24.9 kΩrespectively to set VIN undervoltage lockout threshold at 24
V
• RIMON = 15 kΩto limit maximum V(IMON) voltage to 3.3 V at full-load current of 50 A
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• To reduce conduction losses, IAUS300N08S5N012 MOSFET is selected. Two FETs are used in parallel for
control and another two FETs are used in parallel for reverse current blocking
– 80-V VDS(MAX) and ±20-V VGS(MAX)
– RDS(ON) is 1-mΩtypical at 10-V VGS
– Qg of each MOSFET is 231 nC
• CBST = (4 × Qg) / 1 V = 1 μF
Selection of Pre-Charge Resistor
The value of pre-charge resistor must be selected to limit the inrush current to Iinrush as per 方程式23.
VIN
96
Rpre-ch
=
=
Iinrush
(23)
The power rating of the pre-charge resistor is decided by the average power dissipation given by 方程式24.
2
Epre-ch
Tpre-ch
0.5 × COUT × VIN
5 × Rpre-ch × COUT
2.4 W
=
Pavg
=
=
(24)
The peak power dissipation in the pre-charge resistor is given by 方程式25.
2
VIN
24 W
Ppeak
=
=
Rpre-ch
(25)
Two 220-Ω, 1.5-W, 5% CRCW2512220RJNEGHP resistors are used in parallel to support both average and
peak power dissipation.
TI suggests the designer to share the entire power dissipation profile of pre-charge resistor with the resistor
manufacturer and get their recommendation.
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9.3.3 Application Curves
INP_G
TMR
FLT_I/
G
PD
VOUT
I_LOAD
I_IN
图9-15. Pre-charge Profile of the Output
Capacitance (VIN = 48 V, COUT = 440 μF, No Load)
图9-16. Overcurrent Response of TPS48111-Q1 for
a Load Step from 24 A to 54 A With 50-A
Overcurrent Protection Setting
VIN
VOUT
I_LOAD
IMON
图9-17. IMON Response During 40-A Load Step
9.4 Layout
9.4.1 Layout Guidelines
• The sense resistor (RSNS) must be placed close to the TPS4811x-Q1 and then connect RSNS using the Kelvin
techniques. Refer to Choosing the Right Sense Resistor Layout for more information on the Kelvin
techniques.
• For all the applications, TI recommends a 0.1 µF or higher value ceramic decoupling capacitor between VS
terminal and GND. Consider adding RC network at the supply pin (VS) of the controller to improve decoupling
against the power line disturbances.
• The high current path from the board’s input to the load, and the return path, must be parallel and close to
each other to minimize loop inductance.
• The external MOSFETs must be placed close to the controller such that the GATE of the MOSFETs are close
to PU/PD pins to form short GATE loop. Consider adding a place holder for a resistor in series with the Gate
of each external MOSFET to damp high frequency oscillations if need arises.
• Place a TVS diode at the input to clamp the voltage transients during hot-plug and fast turn-off events.
• The external boot-strap capacitor must be placed close to BST and SRC pins to form very short loop.
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• The ground connections for the various components around the TPS4811x-Q1 must be connected directly to
each other, and to the TPS4811x-Q1’s GND, and then connected to the system ground at one point. Do not
connect the various component grounds to each other through the high current ground line.
• The DIODE pin sources current to measure the temperature. TI recommends BJT MMBT3904 to use as a
remote temperature sense element. Take care in the PCB layout to keep the parasitic resistance between the
DIODE pin and the MMBT3904 low so as not to degrade the measurement. In addition, TI recommends to
make a Kelvin connection from the emitter of the MMBT3904 to the GND of the part to ensure an accurate
measurement. Additionally, a small 1000 pF bypass capacitor must be placed in parallel with the MMBT3904
to reduce the effects of noise.
9.4.2 Layout Example
图9-18. Typical PCB Layout Example With TPS4811-Q1 With Two Parallel B2B MOSFETs
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10 Device and Documentation Support
10.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS48110AQDGXRQ1
TPS48111LQDGXRQ1
ACTIVE
ACTIVE
VSSOP
VSSOP
DGX
DGX
19
19
5000 RoHS & Green
5000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
2UZS
2XXS
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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14-Mar-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS48110AQDGXRQ1 VSSOP
TPS48111LQDGXRQ1 VSSOP
DGX
DGX
19
19
5000
5000
330.0
330.0
16.4
16.4
5.4
5.4
5.4
5.4
1.45
1.45
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS48110AQDGXRQ1
TPS48111LQDGXRQ1
VSSOP
VSSOP
DGX
DGX
19
19
5000
5000
356.0
356.0
356.0
356.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGX0019A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
PIN 1 INDEX
AREA
C
SEATING
PLANE
5.1
4.7
TYP
0.1 C
A
18X 0.5
20
1
5.2
5.0
2X 4.5
NOTE 3
4X (0 -15 )
10
11
0.275
0.165
20X
3.1
2.9
B
0.1
C A B
SEE DETAIL A
4X (7 -15 )
(0.15) TYP
0.25
GAGE PLANE
1.1 MAX
0.7
0.4
0.15
0.05
0 -8
A
20
DETAIL A
TYPICAL
4226944/A 07/2021
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. No JEDEC registration as of July 2021.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DGX0019A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.45)
20
1
20X (0.3)
(R0.05) TYP
18X (0.5)
SYMM
10
11
(4.4)
LAND PATTERN EXAMPLE
SCALE: 16X
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
EXPOSED METAL
ALL AROUND
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
15.000
SOLDER MASK DETAILS
4226944/A 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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EXAMPLE STENCIL DESIGN
DGX0019A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
20X (1.45)
SYMM
20X (0.3)
1
20
(R0.05) TYP
SYMM
(18X 0.5)
11
10
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 16X
4226944/A 07/2021
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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