TPS5103IDB [TI]
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER; 多模式同步DC / DC控制器
| 型号： | TPS5103IDB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER |
| 文件： | 总37页 (文件大小：1050K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
Step-Down DC-DC Converter
DB PACKAGE
(TOP VIEW)
Three Operation-Mode
– Heavy Load:
– Fixed Frequency PWM
– Hysteretic (User Selctable)
– Light Load:
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SOFTSTART
LH
INV
FB
OUT_u
LL
– Skip Mode
C
R
OUT_d
OUTGND
TRIP
T
4.5 V to 25 V Input Voltage Range
Adjustable Output Voltage Down to 1.2 V
95% Efficiency
T
GND
REF
VCC_SENSE
VCC
COMP
Stand-By Control
PWMSKIP
STBY
VREF5
VREG5V_IN
Over Current Protection
UVLO for Internal 5 V Regulation
Low Standby Current . . . 0.5 mA Typical
T = –40°C to 85°C
A
description
The TPS5103 is a synchronous buck dc/dc controller, designed for notebook PC system power. The controller
has three user-selectable operation modes available; hysteretic mode, fixed frequency PWM control, or SKIP
control.
In high current applications, where fast transient response is advantageous for reducing bulk capacitance, the
hysteretic mode is selected by connecting the Rt pin to Vref5. Selecting the PWM/SKIP modes for less
demanding transient applications is ideal for conserving notebook battery life under light load conditions. The
device includes high-side and low-side MOSFET drivers capable of driving low Rds (on) N–channel MOSFETs.
The user-selectable overcurrent protection (OCP) threshold is set by an external TRIP pin resister in order to
protect the system. The TPS5103 is configured so that a current sense resistor is not required, improving the
operating efficiency.
C4
5 V
R1
U1
TPS5103
D1
R3
Q1
Q2
OUTPUT
C1
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
C3
L1
SOFTSTART
LH
OUTU
INV
+
R2
C5
FB
LL
CT
OUTD
RT
OUTGND
TRIP
R4
GND
REF
C2
VCCSENSE
VCC
COMP
PWM/SKIP
STBY
VREF5
10
VREG5V_IN
Figure 1. Typical Design
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
functional block diagram
SOFT START
Soft Start
_
+
FB
PWM Comp.
_
LH
_
+
INV
OUT_u
LL
+
Error Amp
1.185 V
OUT_d
OUTGND
One Shot ON
PWMSKIP
_
+
TRIP
C
R
T
T
Disable
OSC
_
+
VCC_SENSE
_
+
UVLO
1.185 V
VREF5
Comp
GND
V
CC
VREF
_
+
STBY
1.185 V
VREG5V_IN
REF
AVAILABLE OPTIONS
PACKAGE
T
A
SSOP(DB)
TPS5103IDB
TPS5103IDBR
EVM
TPS5103EVM–136
–40 °C to 85 °C
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
Terminal Functions
TERMINAL
NAME
COMP
I/O
DESCRIPTION
NO.
8
I
Comparator input for voltage monitor
External capacitor from C to GND for adjusting the triangle oscillator and decreasing the current limiting
T
C
4
I/O
O
T
voltage
FB
3
6
Feedback output of error amp
GND
INV
LH
Control GND
2
I
Inverting input of both error amp and hysteretic comparator
20
I/O Bootstrap. Connect 1 µF low-ESR capacitor from LH to LL.
Bootstrap low. High side gate driving return and output current protection. Connect to the junction of the high
side and low side FETs for floating drive configuration.
LL
18
I/O
OUT_d
17
16
19
I/O Gate-drive output for low-side power switching FETs
Ground for FET drivers
OUTGND
OUT_u
O
Gate-drive output for high-side power switching FETs
PWM/SKIP mode select
L:PWM mode
PWMSKIP
9
I
H:SKIP mode
REF
7
O
1.185-V reference voltage output
R
T
5
I/O External resistor connection for adjusting the triangle oscillator.
SOFTSTART
STBY
1
I
I
External capacitor from SOFTSTART to GND for soft start control
Standby control
10
15
13
14
12
11
TRIP
I
External resistor connection for output current control
Supply voltage input
V
CC
I
VCC_SENSE
VREF5
I
Supply voltage sense for current protection
5-V-internal regulator output
O
I
VREG5V_IN
External 5-V input (input voltage range = 4.5 V to 25 V)
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
detailed description
REF
The reference voltage is used for the output voltage setting and the voltage protection(COMP). The tolerance
is 1.5% typically.
VREF5
An internal linear voltage regulator is used for the high-side driver bootstrap voltage. Since the input voltage
range is from 4.5 V to 25 V, this voltage offers a fixed voltage for the bootstrap voltage so that the design for
the bootstrap is much easier. The tolerance is 6%.
hysteretic comparator
The hysteretic comparator is used to regulate the output voltage of the synchronous-buck converter. The
hysteresis is set internally and is typically 9.7 mV. The total delay time from the comparator input to the driver
output is typically 400 ns for going both high and low.
error amplifier
The error amplifier is used to sense the output voltage of the synchronous buck converter. The negative input
of the error amplifier is connected to the Vref voltage(1.185 V) with a resistive divider network. The output of
the error amplifier is brought out to the FB terminal to be used for loop gain compensation.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The maximum drive voltage is 5 V
from VREF5. The current rating of driver is typically 1.2 A at sink current, –1.5 A at source current.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
1.2 A at sink current, –1.7 A at source current. When configured as a floating driver, the bias voltage to the driver
is developed from the VREF5, limiting the maximum drive voltage between OUT_u and LL to 5 V. The maximum
voltage that can be applied between LH and OUTGND is 30 V.
driver deadtime control
The deadtime control prevents shoot-through current from flowing through the main power FETs. During
switching transitions the deadtime control actively controls the turnon time of the MOSFET drivers. The typical
deadtime from the low-side-driver-off to the high-side-driver-on is 90 ns, and 110 ns from high-side-driver-off
to low-side-driver-on.
COMP
COMP is designed for use with a regulation output monitor. COMP also functions as an internal comparator
used for any voltage protection such as the input under voltage protection. If the input voltage is lower than the
setpoint, the comparator turns off and prevents external parts from damage. The investing terminal of the
comparator is internally connected to REF(1.185 V).
current protection
Current protection is achieved by sensing the high-side power MOSFET drain-to-source voltage drop during
on-time through VCC_SENSE and LL terminals. An external resistor between Vin and TRIP terminal with the
internal current source connected to the current comparator negative input adjusts the current limit. The typical
internal current source value is 15 µA in PWM mode, 5 µA in SKIP mode. When the voltage on the positive
terminal is lower than the negative terminal, the current comparator turns on the trigger, and then activates the
oscillator. This oscillator repeatedly reset the trigger until the over current condition is removed. The capacitor
on the C terminal can be open or added to adjust the reset frequency.
T
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
detailed description (continued)
softstart
SOFTSTART sets the sequencing of the output for any possibility. The capacitor value for a start-up time can
be calculated by the following equation: C = 2xT (uF) where C is the external capacitor value, T is the required
start-up time in (ms).
standby
This controller can be switched into standby mode by grounding the STBY terminal. When it is in standby mode,
the quiescent current is less than 1.0 uA.
UVLO
The under-voltage-lock-out (ULVO) threshold is approximately 3.8 V. The typical hysteresis is 55 mV.
5-V Switch
5-V Switch if the internal 5-V switch senses a 5-V input from REG5V terminal, the internal 5-V linear regulator
will be disconnected from the MOSFET drivers. The external 5 V will be used for both the low-side driver and
the high-side bootstrap, thus increasing the efficiency.
PWM/SKIP switch
The PWM/SKIP switch selects the output operating mode. This controller has three operational modes, PWM,
SKIP, and Hysteretic. The PWM and SKIP mode control should be used for slower transient applications.
oscillator
The oscillator gives a triangle wave by connecting an external resistor to the R terminal and an external
T
capacitor to the C terminal. The voltage amplitude is 0.43 V ~ 1.17 V. This wave is connected to the non-
T
inverting input of the PWM comparator.
Comparison Table Between PWM Mode and Hysteretic Mode
MODE
PWM
HYSTERETIC
Not Fixed
Very fast
Frequency
Fixed
Transient Response
Normal
Need
Feed back compensation
Needless
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 27 V
CC
Input voltage, V , INV, C , R , PWM/SKIP, SOFTSTART, COMP . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
I
T
T
Input voltage, VREG5V_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Input voltage, STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Input voltage, TRIP, VCC_SENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 27 V
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
O
Low level output voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 27 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 32 V
OL
OH
High level output voltage, V
Reference voltage, V
Operating free-air temperature range, T
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3 V
ref
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. See Dissipation Rating Table for free-air temperature range above 25°C.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
DB
801 mW
6.408mW/°C
416 mW
recommended operating conditions
MIN NOM
MAX
25
UNIT
V
Supply voltage
Input voltage
4.5
V
CC
I
INV, CT, RT, COMP, PWM_SKIP, SOFTSTART
6
VREG5V_IN
STBY
5.5
12
V
V
TRIP, V _SENCE
CC
25
‡
‡
R
C
f
Timing register
Timing capacitor
Frequency
82
100
200
kΩ
pF
T
T
Oscillator frequency
kHz
°C
T
A
Operating temperature range
–40
85
‡
Not a JEDEC symbol.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, V
(unless otherwise noted)
= 7 V
CC
reference voltage
PARAMETER
TEST CONDITIONS
= 50 µA
MIN
TYP
MAX
UNIT
T
= 25°C,
I
vref
1.167 1.185 1.203
A
V
ref
Reference voltage
V
‡
I
= 50 µA
1.155
1.215
12
vref
†
Regin
Regl
Line regulation
V
= 4.5 V to 25 V,
I = 50 µA
0.2
0.5
mV
mV
CC
†
Load regulation
I = 1 µA to 1 mA
10
†
Not a JEDEC symbol.
oscillator
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kHz
kΩ
f
Frequency
PWM mode
500
R
T
Timing resistor
47
fdv
fdt
V
= 4.5 V to 25 V
0.1%
2%
CC
= –40°C to 85°C
†
Frequency change
T
A
DC includes internal comparator error
1
1.1
1.2
0.6
‡
V
High-level output voltage
Low-level output voltage
V
V
HL
f = 200 kHz, includes internal comparator error
DC includes internal comparator error
1.17
0.5
0.4
‡
V
LL
f = 200 kHz, includes internal comparator error
0.43
†
‡
Not a JEDEC symbol.
The output voltages of oscillator (f = 200 kHz) are ensured by design.
error amp
PARAMETER
Input offset voltage
Open-loop voltage gain
TEST CONDITIONS
MIN
50
TYP
MAX
UNIT
mV
dB
V
T
A
= 25°C
2
10
†
Av
GB
†
Unity-gain bandwidth
0.8
45
MHz
µA
I
Output sink current
VO = 0.4 V
VO = 1 V
30
O
S
I
Output source current
300
µA
†
Not a JEDEC symbol.
§
hysteresis comparator
PARAMETER
Hysteresis window
TEST CONDITIONS
MIN
TYP
9.7
2
MAX
UNIT
mV
mV
pA
V
Hysteretic mode
6
13
hsy
Vp-V
Offset voltage
S
I
Bias current
10
t
t
Propagation delay from INV to OUT_U
TTL input signal
230
400
ns
PHL
10 mV overdrive on hysteresis band signal
ns
PLH
§
The numbers in the table include the driver delay. All numbers are ensured by design.
control
PARAMETER
High-level input voltage
TEST CONDITIONS
STBY
MIN
2.5
2
TYP
MAX
UNIT
V
V
V
IHA
PWM_SKIP
STBY
0.5
0.5
Low-level input voltage
V
ILA
PWM_SKIP
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, V
(unless otherwise noted) (continued)
= 7 V
CC
5-V regulator
PARAMETER
Output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
I = 10 mA
= 5.5 V to 25 V,
4.7
5.3
20
40
O
†
Regin
Regl
Line regulation
V
I = 10 mA
= 5.5 V
mV
mV
mA
CC
I = 1 mA to 10 mA,
†
Load regulation
Short-circuit output current
Not a JEDEC symbol.
V
CC
I
V
ref
= 0 V
70
OS
†
5-V switch
PARAMETER
TEST CONDITIONS
TEST CONDITIONS
TEST CONDITIONS
MIN
4.2
4.1
50
TYP
MAX
4.9
UNIT
V
V
V
V
IT(high)
IT(low)
hsy
†
Threshold voltage
4.8
Hysteresis)
150
250
mV
†
Not a JEDEC symbol.
UVLO
PARAMETER
MIN
3.6
3.5
10
TYP
MAX
4.2
UNIT
V
V
V
V
IT(high)
IT(low)
hys
†
Threshold voltage
4.1
Hysteresis
150
mV
†
Not a JEDEC symbol.
output
PARAMETER
MIN
0.5
–1
0.5
–1
10
3
TYP
1.2
–1.7
1.2
–1.5
15
MAX
UNIT
I
O
I
S
I
O
I
S
OUT_u sink curent
V
O
V
O
V
O
V
O
= 3 V
= 2 V
= 3 V
= 2 V
A
A
A
A
OUT_u source current
OUT_d sink current
OUT_d source current
PWM mode,
SKIP mode,
VTRIP = 7 V
VTRIP = 7 V
20
7
I
TRIP terminal current
µA
5
High side driver is GND referenced.
Input: INV = 0 – 3V
t
r
Rise time
t /t = 10 ns,
r f
Frequency = 200 kHz
ns
C
C
= 2200 pF
= 3300 pF
28
39
L
L
High side driver is GND referenced.
Input: INV = 0 – 3 V
t
f
Fall time
t /t = 10 ns,
r f
Frequency = 200 kHz
ns
C
C
= 2200 pF
= 3300 pF
30
38
L
L
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, V
(unless otherwise noted) (continued)
= 7 V
CC
softstart
PARAMETER
Softstart current
TEST CONDITIONS
MIN
TYP
2.5
3.9
2.6
MAX
UNIT
I
1.9
3
µA
(CTRL)
V
V
IT(high)
IT(low)
V
†
Threshold voltage (SKIP mode)
†
Not a JEDEC symbol.
output voltage monitor
PARAMETER
Threshold voltage
TEST CONDITIONS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
1.08
1.18
1.28
V
IT
driver deadtime section
PARAMETER
Low-side to high-side
High-side to low-side
MIN
MIN
TYP
90
MAX
UNIT
ns
T
T
DRVLH
110
ns
DRVHL
whole device
PARAMETER
Supply current
Shutdown current
TEST CONDITIONS
TYP
0.5
MAX
1.2
UNIT
mA
I
I
CC
STBY = 0 V
0.01
10
µA
LH
OUT_u
SOFTSTART
INV
FB
LL
OUT_d
C
R
T
T
OUTGND
TRIP
GND
VCC_SENSE
REF
0.1 µF
VCC
VREF5
5V_IN
COMP
PWM SKIP
STBY
0.1 µF
7 V
5 V
Figure 2. Test Circuit
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
700
50
650
600
550
500
450
400
45
40
35
30
25
20
15
10
V
= 25 V
CC
V
= 25 V
CC
V
= 7 V
V
CC
= 7 V
CC
V
= 4.5 V
CC
V
= 4.5 V
CC
350
300
5
0
–40
–20
25
85
125
–40
–20
25
85
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 3
Figure 4
DRIVE OUTPUT VOLTAGE
vs
DRIVE OUTPUT VOLTAGE
vs
DRIVE CURRENT
DRIVE CURRENT
5.5
3
V
CC
J
= 7 V,
= 25°C
V
CC
J
= 7 V,
= 25°C
T
T
2.5
2
5
4.5
4
1.5
1
3.5
3
0.5
0
0.1
0.7
1
0.1
0.7
1
I
– Drive Source Current – A
(OUT_source)
I
– Drive Source Current – A
(OUT_sink)
Figure 5
Figure 6
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
DRIVE OUTPUT VOLTAGE
vs
DRIVE OUTPUT VOLTAGE
vs
DRIVE CURRENT
DRIVE CURRENT
4.5
4
6
5
T
J
= 25°C
T
J
= 25°C
3.5
3
4
3
2
2.5
2
1.5
1
1
0
0.5
0
0.1
0.7
1
0.1
(OUT_source)
0.7
1
I
– Drive Source Current – A
I
– Drive Source Current – A
(OUT_sink)
Figure 7
Figure 8
OSCILLATOR OUTPUT VOLTAGE
vs
OSCILLATOR OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
500
1.125
1.115
1.105
1.095
495
490
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 25 V
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 25 V
485
480
1.085
1.075
–40
–20
25
85
125
–40
–20
25
85
125
T – Junction Temperature – °C
J
T
J
– Junction Temperature – °C
Figure 9
Figure 10
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
ERROR AMPLIFIER INPUT OFFSET VOLTAGE
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.5
2
2.5
2
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 25 V
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 25 V
1.5
1
1.5
1
0.5
0
0.5
0
–40
–20
25
85
125
–40
–20
25
85
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 11
Figure 12
HYSTERESIS COMPARATOR HYSTERESIS VOLTAGE
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
10.5
6.2
6
V
CC
= 7 V
10.25
10
5.8
5.6
5.4
5.2
5
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 25 V
9.75
9.5
4.8
9.25
9
4.6
4.4
–40
–20
25
85
125
–40
–20
25
85
125
T – Junction Temperature – °C
J
T
J
– Junction Temperature – °C
Figure 13
Figure 14
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
STANDBY SWITCH THRESHOLD VOLTAGE
VREF5 OUTPUT VOLTAGE
vs
vs
JUNCTION TEMPERATURE
SUPPLY VOLTAGE
2.5
2
5.2
5.1
5
V
CC
V
CC
= 4.5 V,
= 7 V
T
J
= –40°C
V
CC
= 25 V
T
J
= 125°C
4.9
4.8
4.7
4.6
4.5
4.4
T
J
= 25°C
1.5
V
CC
= 25 V
1
0.5
0
V
CC
= 4.5 V
V
CC
= 7 V
135
4.3
4.2
–45
–25
25
95
0
10
20
T
J
– Junction Temperature – °C
V
CC
– Supply Voltage – V
Figure 15
Figure 16
VREF5 OUTPUT VOLTAGE
vs
VREF5 SHORT CURRENT
vs
JUNCTION TEMPERATURE
OUTPUT CURRENT
6
5
4
3
2
–100
T
= 125°C
J
V
= 25 V
CC
–80
–60
–40
T
J
= 25°C
V
CC
= 7 V
V
= 4.5 V
CC
T
= –40°C
J
–20
0
1
0
0
–10
–20 –30
–40 –50 –60
–70
–40
–20
25
85
125
I
O
– Output Current – mA
T
J
– Junction Temperature – °C
Figure 17
Figure 18
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
UVLO HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
UVLO THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
80
70
60
50
40
30
20
4
3.95
3.90
3.85
3.80
3.75
3.70
V
TLH
V
THL
10
0
–40
–20
25
85
125
–40
–20
25
85
125
T – Junction Temperature – °C
J
T
J
– Junction Temperature – °C
Figure 19
Figure 20
5 VSW HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
5 VSW THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
200
4.80
4.75
4.70
4.65
4.60
180
160
140
120
100
80
V
TLH
V
THL
4.55
4.50
4.45
60
40
4.40
4.35
20
0
–45
–25
25
95
135
–45
–25
25
95
135
T – Junction Temperature – °C
J
T
J
– Junction Temperature – °C
Figure 21
Figure 22
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SOFTSTART THRESHOLD VOLTAGE
SOFTSTART CURRENT
vs
JUNCTION TEMPERATURE
vs
JUNCTION TEMPERATURE
4.5
4
–2.45
–2.40
–2.35
–2.30
3.5
3
V
CC
= 4.5 V
V
CC
V
CC
= 7 V,
= 25 V
2.5
2
V
CC
= 4.5 V
V
CC
= 7 V
1.5
1
V
CC
= 25 V
–2.25
–2.20
0.5
0
–40
–20
25
85
125
–40
–20
25
85
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 23
Figure 24
OUTPUT VOLTAGE MONITOR COMPARATOR
THRESHOLD VOLTAGE
vs
SOFTSTART THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
3.5
3
1.195
1.193
1.190
1.188
1.185
1.183
1.180
V
CC
V
CC
= 7 V,
= 25 V
2.5
2
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 25 V
V
CC
= 4.5 V
1.5
1
–40
–20
25
85
125
–40
–20
25
85
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 25
Figure 26
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
OSCILLATOR OUTPUT VOLTAGE
vs
vs
JUNCTION TEMPERATURE
FREQUENCY
600
500
400
1.6
F = 500 kHz
1.4
1.2
1
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 25 V
V
OSCH
V
CC
V
CC
V
CC
= 4.5 V,
= 7 V,
= 25 V
300
200
0.8
0.6
0.4
V
OSCL
F = 200 kHz
100
0
0.2
0
–40
–20
25
85
125
10
100
1000
T
J
– Junction Temperature – °C
F
OSC
– Frequency – kHz
Figure 27
Figure 28
ERROR AMPLIFIER GAIN AND PHASE SHIFT
60
50
40
30
20
10
0
180
140
100
60
R
= 100 Ω,
s
f
R = 10 kΩ
Phase
Gain
20
–20
–60
–10
–20
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
f – Frequency – Hz
Figure 29
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
MAXIMUM DUTY CYCLE
SOFTSTART CAPACITANCE
vs
vs
JUNCTION TEMPERATURE
SOFTSTART TIME
100
99.5
99
4
10
10
10
f = 200 kHz
98.5
98
3
2
97.5
97
96.5
96
95.5
95
100
0.01
–40
–20
25
85
125
0.1
1
10
100
T
J
– Junction Temperature – °C
T
SS
– Soft Start Time – ms
Figure 30
Figure 31
DRIVER DEAD TIME
vs
JUNCTION TEMPERATURE
CURRENT PROTECTION SOURCE CURRENT
vs
INPUT VOLTAGE PWM MODE
140
120
100
14.5
14.25
14
V
CC
= 4.5 V
T
DRVHL
T
A
= 125°C
13.75
13.5
13.25
13
T
80
60
40
DRVLH
T
= 25°C
A
V
= 7 V,
= 25 V
CC
V
= 4.5 V
CC
V
CC
V
= 7 V,
= 25 V
CC
V
CC
T
A
= –40°C
20
0
12.75
12.5
–45
–25
25
95
135
4.5
7
25
T
J
– Junction Temperature – °C
V
TRIP
– Input Voltage – V
Figure 32
Figure 33
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
CURRENT PROTECTION SOURCE CURRENT
vs
INPUT VOLTAGE SKIP MODE
4.6
T
A
= 125°C
4.5
4.4
T
A
= 25°C
4.3
4.2
T
A
= –40°C
4.1
4
4.5
7
25
V
TRIP
– Input Voltage – V
Figure 34
OSCILLATOR FREQUENCY
vs
RESISTOR
700
600
500
400
300
200
C
= 10 pF
T
C
= 15 pF
T
C
= 22 pF
= 33 pF
T
C
T
C
= 470 pF
T
C
= 680 pF
T
100
0
10
100
– Resistor – kΩ
1000
R
T
Figure 35
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
overshoot of output rectangle wave
The drivers in the TPS5103 controller are fast and can produce high transients on V or the junction of Q1 and
CC
Q2(shown below). Care must be taken to insure that these transients do not exceed the absolute maximum
rating for the device or associated external component. A low-ESR capacitor connected directly from Q1 drain
to Q2 source can greatly reduce transient pulses on V . Also, Q1 turn-on-speed can be reduced by adding
CC
a resistor (5 – 15 Ω) in series with OUT_u. Poor layout of the switching node (V1 in figure) can result in the
requirement for additional snubber circuitry require from V1 to ground.
C1
V
CC
Q1
OUT_u
V1
Q2
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
application for general power
The design shown in this data sheet is a reference design for a general power supply application. An evaluation
module (EVM), TPS5103EVM-136 (SLVP136), is available for customer testing and evaluation. The intent is
to allow a customer to fully evaluate the given design using the plug-in EVM supply shown here. For subsequent
customer board revisions, the EVM design can be copied onto the users PCB to shorten design cycle time,
component count, and board cost.
To help the customers to design the power supply using TPS5103, some key design procedures are shown
below.
R2
C4
J1
C15
C5
Vi
TP18
R3
J2
J3
J4
J5
Vi
Q1
C14
C1
+
Input GND
Input GND
Input GND
TP26
R4
C7
R11
R5
C6
L1
D2
TP17
TP16
C2
J6
J7
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
SENSE
Vo
Q2
C10
J8
TP15
TP14
+
Vo
D1
C8
J9
R6B
C3
Vo
J10
J11
J12
VoGND
VoGND
VoGND
R12
TP13
R6A
R7
C12
J13
J14
C9
TP12
TP11
C11
C13
R13
R9
JP1
JP2
R10
Figure 36. EVM Schematic
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
output voltage setpoint calculation
The output voltage is set by the reference voltage and the voltage divider. In TPS5102, the reference voltage
is 1.185 V, and the divider is composed of two resistors in the EVM design that are R4 and R5, or R14 and R15.
The equation for the setpoint is:
R1 Vr
R2
Vo Vr
Where R1 is the top resistor (kΩ) like R4 or R15; R2 is the bottom resistor (kΩ) such as R5 or R14; Vo is the
required output voltage (V); Vr is the reference voltage (1.185 V in TPS5103).
Example: R1 = 1 kΩ; Vr = 1.185 V; Vo = 1.8 V, then R2 = 1.9 kΩ.
For your convenience, some of the most popular output voltage setpoints are calculated in the table below:
Vo
1.3 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
R1 (top) (kΩ)
R2 (bottom) (kΩ)
1
1
1
1
1
1
10
3.7
1.9
0.9
0.56
0.31
If higher precision resistor is used, the output voltage setpoint can be more accurate.
In some applications, the output voltage is required to be lower than the reference voltage. With few extra
components, the lower voltage can be easily achieved. The drawing below shows the method.
V
CC
V
O
R
R
(top)
z1
INV
R
z2
TPS5103
R
Zener
(bottom)
In the schematic, the Rz1, Rz1, and the zener are the extra components. Rz1 is used to give zener enough
current to build up the zener voltage. The zener voltage is added to INV through Rz2. Therefore, the voltage
on INV is still equal to the IC internal voltage (1.185 V) even if the output voltage is regulated at lower setpoint.
The equation for setting up the output voltage is shown below:
(
)
Vz–Vr
Rz2
Vr–Vo
Rtop
Vr
Rbtm
Where Rz2 is the adjusting resistor for low output voltage; Vz is the zener voltage; Vr is the internal reference
voltage; Rtop is the top resistor of voltage sensing network; Rbtm is the bottom resistor of the sensing network;
Vo is the required output voltage setpoint.
Example: Assuming the required output voltage setpoint is Vo = 0.8 V, Vz = 5 V; Rtop = 1 kΩ; Rbottom = 1 kΩ,
then the Rz2 = 2.43 kΩ.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
switching frequency
With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the
hysteresis window, the delay of the hysteresis comparator and the driver, the output inductance, the resistance
in the output inductor, the output capacitance, the ESR and ESL in the output capacitor, the output current, and
the turnon resistance of high side and low side MOSFET. It is a very complex equation if everything is included.
To make it more useful to the designers, a simplified equation only considers the most influential factors. The
tolerance of this equation is about 30%:
7
V
(Vin
V
)
(ESR (10 10
Td) C
out
)
out
out
out
ESL V )
ƒs
7
V
(V
ESR (10 10
Td) 0.0097
L
in
in
in
Where fs is the switching frequency (Hz); Vout is the output voltage (V); Vin is the input voltage (V); Cout is the
output capacitance; ESR is the equivalent series resistance in the output capacitor (Ω); ESL is the equivalent
series inductance in the output capacitor (H); Lout is the output inductance (H); Td is output feedback RC filter
time constant (S).
In the EVM module design, for the 1.8 V output, for example: Vin = 5 V, Vout = 1.8 V, Cout = 680 µF; ESR =
40 mΩ; ESL = 3 nH; Lout = 6 µH; Td = 0.5 µs.
Then, the frequency fs = 122 kHz.
output inductor ripple current
The output inductor current ripple can affect not only the efficiency and the inductor saturation, but also the
output voltage capacitor selection. The equation is exhibited as below:
(
)
Rdson RL
Vin Vout Iout
Lout
Iripple
D
Ts
Where Iripple is the peak-to-peak ripple current (A) through inductor; Vin is the input voltage (V); Vout is
the output voltage (V); Iout is the output current; Rdson is the on-time resistance of MOSFET (Ω); D is the duty
cycle; and Ts is the switching cycle (S). From the equation, it can be seen that the current ripple can be adjusted
by changing the output inductor value.
Example: Vin = 5 V; Vout = 1.8 V; Iout = 5 A; Rdson = 10 mΩ; RL = 5 mΩ; D = 0.36; Ts = 10 µS; Lout = 6 µH
Then, the ripple Iripple = 2 A.
output capacitor RMS current
Assuming the inductor ripple current totally goes through the output capacitor to the ground, the RMS current
in the output capacitor can be calculated as:
I
I (rms)
o
12
Where I(orms) is the maximum RMS current in the output capacitor (A); ∆I is the peak-to-peak inductor ripple
current (A).
Example: ∆I = 2 A, so Io(rms) = 0.58 A
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
input capacitor RMS current
Assuming the input ripple current totally goes into the input capacitor to the power ground, the RMS current in
the input capacitor can be calculated as:
1
12
2
2
I (rms)
I
D
(1 D)
D
Iripple
o
i
Where Ii(rms) is the input RMS current in the input capacitor (A); Io is the output current (A); D is the duty cycle.
From the equation, it can be seen that the highest input RMS current usually occurs at the lowest input voltage,
so it is the worst case design for input capacitor ripple current.
Example: Io = 5 A; D = 0.36
Then, Ii(rms)= 3.36 A
softstart
The softstart timing can be adjusted by selecting the soft-start capacitor value. The equation is
C
2
T
soft
Where C
soft
is the softstart capacitance (µF); T
is the start-up time on softstart terminal (S).
soft
soft
Example: Tsoft = 5 mS, so Csoft = 0.01 µF.
current protection
The current protection in TPS5103 is set using an internal current source and an external resistor to set up the
current limit. The sensed high side MOSFET drain-to-source voltage drop is compared to the set point, if the
voltage drop exceeds the limit, the internal oscillator is activated, and it continuously resets the current limit until
the over-current condition is removed. The equation below should be used for calculating the external resistor
value for current protection:
Rds(on) (Itrip Iind(p-p) 2)
PWM or HYS mode
SKIP mode
Rcl
Rcl
0.000015
Rds(on) (Itrip Iind(p-p) 2)
0.000005
Where Rcl is the external current limit resistor (R10,R11); Rds(on) is the high side MOSFET on-time resistance.
Itrip is the required current limit; Iind(p-p) is the peak-to-peak output inductor current.
Example: PWM mode or HYS mode
Rds(on) = 10 mΩ, Itrip =5 A, Iind = 2 A, so Rcl = 4 kΩ
Example: SKIP mode
Rds(on) = 10 mΩ, Itrip = 2 A, Iind = 1 A, so Rcl = 5 kΩ
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
loop gain compensation
Voltage mode control is used in this controller for the output voltage regulation. To achieve fast, stabilized
control, two parts are discussed in this section: the power stage small signal modeling and the compensation
circuit design.
For the buck converter, the small signal modeling circuit is shown below:
Z
L
V
ap
d
L
D
R
a
c
L
+
–
d
V
O
i
a
i
c
D
1
+
C
R
V
I
I
c
Z
RC
R
C
p
From this equivalent circuit, several control transfer functions can be derived: input-to-output, output
impedance, and control-to-output. Typically the control-to-output transfer function is used for the feedback
control design.
Assuming Rc and RL are much smaller than R, the simplified small signal control-to-output transfer function is:
(
)
1
sCRc
Vod
d
L
R
2
s LC
1
s C
Rc
R
L
Where C is the output capacitance; Rc is the equivalent serial resistance (ESR) in the output capacitor; L is the
output inductor; RL is the equivalent serial resistance (ESR) in the output inductor; R is the load resistance.
To achieve the fast transient response and the better output voltage regulation, a compensation circuit is added
to improve the feedback control. The whole system is shown below:
Power
Stage
PWM
V
ref
Compensation
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
The typical compensation circuit used as an option in the EVM design is a part of the output feedback circuit.
The circuitry is displayed below.
C3
R1
C1
R2
R4
C2
_
To PWM
+
V
ref
R3
This circuit is composed of one integrator, two poles, and two zeros:
Assuming R1 << R2 and C2 << C3, the equation is:
(
)
(
)
sC2R2
)( )
1
sC3R4
(
1
Comp
Therefore,
sC3R2 1 sC2R4 1 sC1R1
1
1
Pole1
Pole2
Zero1
2 C1R1
2 C2R4
1
1
Zero2
2 C3R4
2 C2R2
1
Integrator
2 ƒC3R2
A simplified version used in the EVM design is exhibited below.
Vo
C3
R2
R4
C2
_
+
V
ref
R3
Assuming C2 << C3, the equation is:
(
)
sC3R4
1
Comp
(
)
sC3R2 1 sC2R4
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
there is one pole, one zero and one integrator:
1
1
1
Zero
Pole
Integrator
2 C3R4
2 C2R4
2 ƒC3R2
The loop-gain concept is used to design a stable and fast feedback control. The loop-gain equation is derived
by that the control-to-output transfer function times the compensation:
Loop gain
Vod X Comp
Byusingabodeplot, theamplitudeandthephaseofthisequationcanbedrawnwithsoftwaresuchasMathCad.
In turn, the stability can be easily designed by adjusting the compensation perimeters. The sample bode plot
is shown below to explain the phase margin, gain margin and the crossover frequency.
The gain is drawn as 20 log (loop-gain), and the phase is in degrees. To explain them clearer, 180 degrees is
added to the phase, so that the gain and phase share the same zero.
Where the gain curve touches the zero is the crossover frequency. The higher this frequency is, the faster the
transient response is, since the transient recovery time is 1/(crossover frequency). The phase to the zero is the
phase margin at the crossover frequency. The phase margin should be at least 60 degrees to cover all the
condition changes such as temperature. The gain margin is the gap between gain curve and the zero when the
phase curve touches the zero. This margin should be at least 20 dB to guarantee the stability over all conditions.
180
166
152
Phase
138
124
110
96
82
68
54
40
Phase
Margin
20 Log (Loop-Gain)
180 + Phase
26
12
–2
–16
–30
–44
–58
–72
Gain
Gain
Margin
Crossover
–86
–100
3
10
4
10
5
10
6
10
10
100
f – Frequency – Hz
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
synchronization
Some applications require switching clock synchronization. Two methods are used for synchronization:
Triangle wave synchronization
740 mV
C
R
t
t
TPS5103
740 mV
Square wave synchronization
It can be seen that R and C are removed from the circuit. Therefore, two components are saved. This method
T
T
is good for the synchronization between two controllers. If the controller needs to be synchronized with digital
circuit such as DSP, usually the square-type clock signal is used. The configuration exhibited below is for this
type of application:
C
R
t
t
TPS5103
Anexternalresistorisaddedintothecircuit, butR isstillremoved. C iskepttobeapartofRCcircuitgenerating
T
T
triangle waveform for the controller. Assuming the peak value of the square is known, the resistor and the
capacitor can be adjusted to achieve the correct peak–to–peak value and the offset value.
layout guidelines
Goodpowersupplyresultswillonlyoccurwhencareisgiventoproperdesignandlayout. Layout willaffectnoise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output, then
back to the driver section and, finally, place the low-level components. Below are several specific points to
consider before layout of a TPS5103 design begins.
All sensitive analog components should be referenced to ANAGND. These include components connected
to Vref5, Vref, INV, LH, and COMP .
Analogground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on V , and drive ground will connect to the main ground
O
plane close to the source of the low-side FET.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
The bypass capacitor for V
should be placed close to the TPS5103.
CC
When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should
be as short and as wide as possible.
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to
LL) should be placed close to the TPS5103.
When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND.
The bulk storage capacitors across V should be placed close to the power FETS. High-frequency bypass
IN
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
High-frequency bypass capacitors should be placed across the bulk storage capacitors on V .
O
LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH
and LL should be routed very close to each other to minimize differential-mode noise coupling to these
traces. Ceramic decoupling capacitors should be placed close to where V
connects to V , to reduce
CC
in
high-frequency noise coupling on V
.
CC
The output voltage sensing trace should be isolated by either ground trace or V
trace.
CC
test results
The tests are conducted at T = 25°C, the point voltage is 5 V.
A
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
95
95
90
85
1.8 V Output Efficiency
1.8 V Output Efficiency
90
PWM Mode
85
PWM Mode
80
80
75
75
SKIP Mode
SKIP Mode
70
70
65
60
65
60
0
0.1
0.2
0.3
0.4
0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
I – Output Current – A
O
I
O
– Output Current – A
Figure 37
Figure 38
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
OUTPUT CURRENT
1.790
1.785
1.790
1.790
1.780
1.780
1.770
1.770
1.760
1.8 V Line Regulation
1.8 V Output Load Regulation
1.780
1.775
1.770
0
5
10
15
20
25
0
0.5
1
1.5
2
2.5
3
3.5
4
V – Input Voltage – V
I
I
O
– Output Current – A
Figure 39
Figure 40
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
EFFICIENCY
vs
OUTPUT/VOLTAGE
OUTPUT CURRENT
OUTPUT
VOLTAGE
95
1.8 V Output Diode Type Efficiency
90
85
80
75
70
65
60
0
0.5
1
1.5
2
2.5
3
3.5
4
I
O
– Output Current – A
Figure 41
Figure 42
TRANSIENT RESPONSE (OVERSHOOT)
TRANSIENT RESPONSE (UNDERSHOOT)
Figure 43
Figure 44
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
Table 1. Bill of Materials (see Note 3)
REF
C1opt
PN
DESCRIPTION
Capacitor, POSCAP, 220 µF, 10 V
MFG
Sanyo
SIZE
7.3x4.3mm
10x10mm
1210
10TPB220M
C1
C2
C3
C4
C5
C6
C7
C8
C9
RV-35V221MH10-R
Capacitor, electrolytic, 220 µF, 35 V
Capacitor, ceramic, 10 µF, 35 V
Capacitor, POSCAP, 470 µF, 4 V
Open, capacitor, Ceramic, 2.2 µF, 16 V
Capacitor, ceramic, 1 µF, 16 V
Capacitor, ceramic, 0.01 µF, 16 V
Capacitor, ceramic, 220 pF, 16 V
Capacitor, ceramic, 100 pF, 16 V
Capacitor, ceramic, 1 µF, 16 V
Capacitor, ceramic, 2.2 µF, 35 V
Open
ELNA
GMK325F106ZH
Taiyo Yuden
Sanyo
4TPB470M
7.3x4.3mm
805
†
std
std
805
std
805
std
805
std
805
std
805
C10
GMK316F225ZG
std
Taiyo Yuden
1206
†
C11
C12
C13
C14
805
GMK316F225ZG
GMK325F106ZH
Capacitor, Ceramic, 2.2 µF, 35 V
Capacitor, Ceramic, 10 µF, 35 V
Open
Taiyo Yuden
Taiyo Yuden
1206
1210
†
C14 opt
Open
10x10mm
805
†
C15
D1
std
Open, capacitor, ceramic, 1000 pF, 16 V
Diode, Schottky, 40 V, 3 A
Diode, Schottky, 30 V, 1 A
Diode, Schottky, 40 V, 200 mA, 400 mW
Inductor, 6.8 uH, 4.4 A
MBRS340T3
MBRS130LT3
SD103-AWDICT-ND
DO3316P-682
Motorola
Motorola
Digikey
SMC
D1opt
D2
SMB
3.5x1.5mm
0.5x0.37 in
L1
Coilcraft
J1–J14
JP1
CA26DA-D36W-0FC Edge connector, surface-mount, 0.040” board, 0.090” standoff
NAS Interplex 0.040”
S1132-2-ND
929950-00-ND
S1132-2-ND
Header, straight, 2–pin, 0.1 ctrs, 0.3” pins
Sullins
DigiKey #
S1132-2-ND
JP1 Shunt
JP2
Shunt, jumper, 0.1”
3M
DigiKey
#929950-00-ND
Header, straight, 2–pin, 0.1 ctrs, 0.3” pins
Sullins
DigiKey
#S1132-2-ND
R1
std
Resistor, 5.1 kΩ, 5 %
Open, resistor, 1 kΩ, 5%
Resistor, 910 Ω, 1%
Resistor, 1.74 kΩ, 1%
Resistor, 5.1 kΩ, 5%
Resistor, 82 kΩ, 5%
Open, 0 Ω, 5%
805
†
R2
R3
R4
R5
std
805
std
805
std
805
std
805
R6A
R6B
R7
std
805
†
std
805
std
Resistor, 1 kΩ, 5%
805
R9
std
Resistor, 1 kΩ, 5%
805
R10
R11
R12
std
Resistor, 1 kΩ, 5%
805
std
Resistor, 10 Ω, 5%
805
std
Resistor, 51 kΩ, 5%
Open
805
†
R13
Q1
Q2
U1
std
805
Si4410DY
Si4410DY
TPS5103
Transistor, MOSFET, n-ch, 30-V, 10-A, 13–mΩ
Transistor, MOSFET, n-ch, 30-V, 10-A, 13-mΩ
IC, controller
Siliconix
Siliconix
TI
SO–8
SO–8
SSOP–20
†
Components for optional mode test only.
NOTE 3: This operation mode is PWM mode only.
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
Top Layer
.
Bottom Layer (Top View)
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
Top Assembly
–
Power Supply
Load
0 – 4 A
+
5–V, 5–A Supply
–
+
Test Setup
NOTE: All wire pairs should be twisted.
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
Table 2. Test Specifications
PARAMETER
Input voltage range
CONDITIONS
MIN
TYP
MAX UNITS
5
25
1.9
4
V
V
A
A
Output voltage range
Output current range
Output current limit
Output ripple
Vi = 5 – 25 V Io = 0 – 4 A
1.7
0
1.8
Vi = 5 – 10 V
Vi = 5 V
4.3
Vi =5 V,
Io = 4 A
50 mVp–p
Operating frequency
Efficiency
Io = 4 A
150
250
KHz
%
Vi = 5 V,
Vo = 1.8 V,
Io = 4 A
90
Table 3. EVM Operating Specifications
SKIP MODE
Remove JP1 shunt
HYS MODE
Remove R5, C6 and C7
Remove R6A
Add R6B
Add C15
If it needs the loop-compensation, add R2 and C4
ThisEVMisdesignedtocoverasmanyapplicationsaspossible. Forsomemorespecificapplications, thecircuit
can be simpler. The table below gives some recommendations.
Table 4. EVM Application Recommendations
5-V INPUT VOLTAGE
<3-A OUTPUT CURRENT
DIODE VERSION
Change C1 to low profile capacitor
Sanyo 10TPB220M (220 µF, 10 V)
Or 6TPB330M (330 µF, 6.3 V)
Change Q1 and Q2 to dual pack MOSFET,
IRF7311 to reduce the cost.
Remove Q2 to reduce the cost.
Remove R10
Table 5. Vendor and Source Information
MATERIAL
SOURCE
In EVM design
Second source
PART NUMBER
DISTRIBUTORS
Si4410
MOSFETS (Q1–Q2)
Local distributor
IRF7811 (International Rectifier)
RV–35V221MH10–R (ELNA)
35CV330AX/GX (Sanyo)
UUR1V221MNR1GS (Nichicon)
MBRS340T3 (Motorola)
In EVM design
Second source
Bell Microproducts 972–783–4191
870–633–5030
INPUT CAPACITORS (C1)
Future Electronics (Local Office)
Local distributors
MAIN DIODES (D1)
INDUCTORS (L1)
In EVM design
Second source
In EVM design
U3FWJ44N (Toshiba)
Local distributors
DO3316P–682 (Coilcraft)
972–458–2645
CTDO3316P–682
(Inductor Warehouse)
Second source
800–533–8295
GMK325F106ZH
GMK316F225ZG
(Taiyo Yuden)
CERAMIC CAPACITORS
(C2, C14) (C12, C10)
SMEC
512–331–1877
IN EVM design
Taiyo Yuden representative
e–mail: mike@millsales.com
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
High current applications are described in Table 6. The values are recommendations based on actual test
circuits. Many variations are possible based on the requirements of the user. Performance of the circuit is
dependent upon the layout rather than on the specific components, if the device parameters are not exceeded.
The power stage, having the highest current levels and greatest dv/dt rates, should be given the most attention,
as both the supply and load can be severely affected by the power levels and edge rates.
Table 6. High Current Applications
REFERENCE
DESIGNATIONS
FUNCTION
8-A OUTPUT
12-A OUTPUT
16-A OUTPUT
4x ELNA
2x ELNA
3x ELNA
C1
Input bulk capacitor
RV-35V221MH10-R
RV-35V221MH10-R
RV-35V221MH10-R
220 µF, 35 V
220 µF, 35 V
220 µF, 35 V
2x Taiyo Yuden
GMK325F106ZH
10 µF, 35 V
3x Taiyo Yuden
GMK325F106ZH
10 µF, 35 V
4x Taiyo Yuden
GMK325F106ZH
10 µF, 35 V
C2
L1
C3
Input bypass capacitor
Output filter indicator
Output filter capacitor
Coiltronics UP4B-1R5
1.5 µΗ, 13.4 A
MicorMetals T68-8/90
Core w/7T, #16
1.0 µΗ, 25 A
Coiltronics UP3B-2R2
2.2 µΗ, 9.2 A
3x Sanyo 4TPB470M
470 µF, 4 V
2x Sanyo 4TPB470M
470 µF, 4 V
4x Sanyo 4TPB470M
470 µF, 4 V
2x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
3x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
4x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
Q1
Q2
Power switch
Power switch
2x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
3x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
4x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
R11
R12
Gate drive resistor
Current limit resistor
7 Ω
5 Ω
4 Ω
10 kΩ
200 kHz
15 kΩ
150 kHz
20 kΩ
100 kHz
Switching frequency
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PINS SHOWN
0,38
0,65
28
M
0,15
0,22
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–8°
1,03
0,63
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
DIM
3,30
2,70
6,50
5,90
6,50
5,90
7,50
6,90
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
9,90
12,30
4040065 /C 10/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明