TPS51103DRCRG4 [TI]
Integrated LDO with Switchover Circuit for Notebook Computers 10-SON -40 to 85;
| 型号： | TPS51103DRCRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Integrated LDO with Switchover Circuit for Notebook Computers 10-SON -40 to 85 光电二极管 输出元件 调节器 |
| 文件： | 总17页 (文件大小：631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51103
www.ti.com ...................................................................................................................................................................................................... SLUS808–JUNE 2008
INTEGRATED LDO WITH SWITCHOVER CIRCUIT FOR NOTEBOOK COMPUTERS
1
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
Wide Input Voltage Range: 4.5 V to 28 V
5-V/3.3-V, 100-mA, LDO Output
The TPS51103 integrates three LDOs. The 5-V and
3.3-V LDOs are both rated at 100 mA and also
include a glitch-free switch-over feature allowing for
optimized battery life. An additional 3.3-V LDO is
designed to provide an always on power output for
the real time clock (RTC). The TPS51103 integrates
a clock output to use with an external charge pump.
The TPS51103 offers an innovative solution for
optimizing the complex and multiple power rails
Glitch Free Switch Over Circuit
Always-On 3.3-V, 5-mA LDO Output for RTC
250 kHz Clock Output for Charge Pump
Thermal Shutdown (Non-latch)
10Ld QFN (DRC) Package
APPLICATIONS
•
•
typically found in
TPS51103 is available in the 10-pin QFN package
and is specified from –40°C to 85°C.
a Notebook Computer. The
Notebook Computers
Mobile Digital Consumer Products
TYPICAL APPLICATION CIRCUIT
A2
C2
AC2
C1
V15
C8
1 mF
AC1
A1
5V_IN
C5
0.1 mF
C4
C6
0.1 mF 0.1 mF 0.1 mF
C7
TPS51103DRC
1
2
3
4
5
VCLK
GND
VRTC3
EN5
V5IN 10
5V_IN
VREG5
9
8
7
6
5 V/100 mA
V
IN
(4.5 V to 28 V
3.3 V/5 mA
EN5
VIN
VREG3
V3IN
3.3 V/100 mA
EN3
3.3V_IN
EN3
C2
10 mF
C3
1 mF
C0
10 mF
C1
10 mF
UDG-08017
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS51103
SLUS808–JUNE 2008 ...................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TAPE & REEL
QUANTITY
TA
PACKAGE
PART NUMBER
ECO-PLAN
TPS51103DRCT
TPS51103DRCR
250
Green (RoHS and No
Sb/Br)
–40°C to 85°C
Plastic DRC(1)
3000
(1) For the most current package and ordering information, seet he Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.3 to 30
–0.3 to 6
UNIT
VIN
EN3, EN5, V3IN
Input voltage range(2)
V5IN
–0.3 to 6
V
V5IN , (VVIN< 5.7 V)
VRTC3, VCLK, VREG3, VREG5
–0.3 to VVIN + 0.3
–0.3 to 6
Output voltage range(2)
Junction temperature, TJ
Storage temperature, Tst
150
°C
°C
–55 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
DISSIPATION RATINGS(1)
POWER RATING
BELOW AND AT TA = 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
10-pin DRC
1.256 W
12.6 mW/°C
0.502 W
(1) θJA (junction to air) for high-K board in still air environment is 80°C/W.
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
TYP
MAX
28
UNIT
V
VIN
EN5, EN3, V3IN
–0.1
–0.1
–0.1
–0.1
–40
5.5
5.5
VVIN
5.5
85
Input voltage range
V5IN
V5IN, (VVIN< 5.5 V)
Output voltage range
VCLK, VRTC3, VREG3, VREG5
Operating free-air temperature, TA
°C
2
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ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VVIN=12 V, (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVIN current, TA = 25°C, No Load, VEN3=VEN5=5 V,
VV5IN = VV3IN = 0 V
IVIN
VIN supply current
VIN standby current
35
7
50
20
µA
µA
IVIN current, TA = 25°C, No Load, VEN3=VEN5= 0 V,
VV5IN = VV3IN = 0 V
IVINSTBY
VRTC3 OUTPUT
IVRTC3 = 1 mA, TA = 25°C
3.27
3.17
3.15
5
3.32
3.37
3.43
3.43
15
VVRTC3
VRTC3 output voltage
0 A < IVRTC3 < 5 mA, 5.5 V < VVIN < 28 V
0 A < IVRTC3 < 5 mA, 4.5 V < VVIN ≤ 5.5 V
VVRTC3 = 2 V
V
IVRTC3
VRTC3 output current
10
mA
VREG5 OUTPUT
VV5IN = 0 V, IVREG5 = 1 mA, TA = 25°C
4.95
4.80
4.75
5.05
5.15
5.20
VV5IN = 0 V, 10 µA < IVREG5 < 100 mA,
6.5V < VVIN < 28 V
VVREG5
VREG5 output voltage
V
VV5IN = 0 V, 0 A ≤ IVREG5 < 50 mA, 5.5V < VVIN < 28V
VV5IN = 0 V, IVREG5 = 50 mA, VVREG5 = 4.5 V
VV5IN = 0 V, VVREG5 = 4.5 V
Turns on
5.25
750
250
4.80
75
VVREG5DO VREG5 drop out voltage
400
160
4.65
50
mV
mA
V
IVREG5
VREG5 output current
100
4.45
25
VTH5VSW
Switch ovethreshold
Hysteresis
mV
Ω
R5VSW
Td5
5V SW RDS(on)
VV5IN = 5 V, IVREG5 = 100 mA
Turns on
1
Delay for 5V SW
1
ms
VREG3 OUTPUT
VV3IN =0 V, IVREG3 = 1 mA, TA = 25°C
3.23
3.17
3.33
3.37
3.43
VV3IN =0 V, 10 µA < IVREG3 < 100 mA,
6.5 V < VVIN < 28 V
VVREG3
VREG3 output voltage
V
VV3IN = 0V, 0A < IVREG3 < 50 mA, 5.5 V < VVIN < 28 V
3.14
3.00
100
2.95
20
3.47
3.47
250
3.17
50
VV3IN = 0V, 0A < IVREG3 < 50 mA, 4.5 V < VVIN ≤ 5.5 V
IVREG3
VREG3 output current
Switchover threshold
VV3IN= 0V, VVREG3 = 3 V
Turns on
150
3.07
35
mA
V
VTH3VSW
Hysteresis
mV
Ω
R3VSW
Td3
3V SW RDS(on)
VV3IN = 3.3 V, IVREG5 = 100 mA
Turns on
1.5
1
Delay for 3V SW
ms
LOGIC THRESHOLD
Enable
1.05
0.7
2.0
3.0
VTHEN EN3, EN5 threshold
V
Shutdown
0.3
0.5
IEN3,5
EN3, EN5 pulldown current
VEN3 = 3 V, VEN5 = 3 V
1.5
µA
VCLK OUTPUT
fVCLK
Clock frequency
TA = 25°C
200
1.5
250
6
320
15
kHz
V5IN to VCLK, IVCLK = 10 mA
VCLK to GND, IVCLK = 10 mA
VCLK on
RVCLK
Driver impedance
V5IN threshold
Ω
4
15
2.0
0.3
2.5
VTHV5IN
V
Hysteresis
THERMAL SHUTDOWN
TSDN Thermal SDN threshold
Shutdown temperature(1)
Hysteresis(1)
150
20
°C
(1) Ensured by design. Not production tested.
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DRC PACKAGE
(Top View)
VCLK
GND
1
2
3
4
5
10 V5IN
9
8
7
6
VREG5
Thermal
Pad
VRTC3
EN5
VIN
VREG3
V3IN
EN3
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
5
EN3
EN5
GND
V3IN
I
I
3.3-V LDO enable input.
5-V LDO enable input.
Ground.
4
2
–
I
6
3.3-V switchover power supply input.
Switchover occurs 1 ms after this input voltage reaches the threshold voltage.
V5IN
10
I
5-V switchover power supply input. Switchover occurs 1 ms after this input voltage reaches to threshold
voltage.
VCLK
VIN
1
8
7
9
3
O
I
50% duty 250-kHz clock output for charge pump power supply.
Power supply input for LDOs.
VREG3
VREG5
VRTC3
O
O
O
3.3-V 100 mA LDO output.
5-V 100 mA LDO output.
3.3-V 5 mA always on LDO output for RTC.
4
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FUNCTIONAL BLOCK DIAGRAM
VIN
8
3
+
+
VRTC3
+
+
7
VREG3
GND
VREG5
9
GND
GND
V5IN 10
V3IN
6
1-ms
Delay
1-ms
Delay
+
+
3.07 V/
3.03 V
4.65 V/
4.60 V
5
1
EN3
EN5
4
2
+
2.0 V/1.7 V
250 kHz
GND
VCLK
UDG-08026
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T1 = 1 ms
VIN
VRTC3
EN5
EN3
Switch over (ON)
Switch over (ON)
Switch over (OFF)
VREG5
VREG3
V5IN
Switch over (OFF)
Vt2_V5IN = 4.65 V
Vt1_V5IN = 2.0 V
Vt3_V5IN = 4.6 V
Vt4_V5IN = 1.7 V
Vt1_V3IN = 3.07 V
Vt2_V3IN = 3.03 V
V3IN
Turn on Clock
Turn off clock
VCLK
T0 = 1 ms
UDG-08016
Figure 1. Power Sequencing
DETAILED DESCRIPTION
GENERAL DESCRIPTION
The TPS51103 integrates three LDOs. The VREG5 and VREG3 can each deliver 100 mA of current. The device
includes glitch free switch-over circuits which turn off VREG5 and VREG3 LDOs and switch VREG5 and VREG3
to V5IN and V3IN external power inputs respectively when the external high efficiency 5V and 3.3V power rails
are available. It improves overall system efficiency and therefore extends battery life. An additional 5-mA VRTC3
LDO is designed to provide an always on feature for the real time clock (RTC). A 5-V clock with 50% duty cycle
runs at 250 kHz. It can be used as a simple external charge pump driver to generate a 10-V or 15-V low-current
voltage rail (see Figure 2). In the notebook application, the 10 V or 15 V created by this circuit could be used to
drive an N-channel MOSFET instead of the traditional P-channel MOSFET load switch. The TPS51103 boosts
performance and reduce the cost of load switch.
6
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VREG5
When EN5 is asserted high, VREG5 supplies 5 V through an LDO from VIN. Its maximum sourcing current is
100 mA. If EN5 is high and the V5IN voltage becomes higher than 4.65 V, then the VREG5 output is switched
over to the V5IN input after a 1-ms delay. In the switched over condition, the LDO is turned off and VREG5 is
connected to V5IN through the 1.0-Ω RDS(on) MOSFET switch. When the V5IN voltage becomes lower than 4.6 V,
this MOSFET turns off and 5-V LDO is turned back on immediately. A bypass ceramic capacitor is required to
stabilize LDO. The recommended value is between 10 µF and 22 µF. Place the bypass capacitor close to the
VREG5 pin. When EN5 is asserted low, both the 5-V LDO and switchover circuit are turned off.
VREG3
When EN3 is asserted high, VREG3 supplies 3.3 V through an LDO from VIN. Its maximum sourcing current is
100 mA. If EN3 is high and the V3IN voltage becomes higher than 3.07 V, then the VREG3 output is switched
over to the V3IN input after a 1-ms delay. In the switched over condition, LDO is turned off and VREG3 is
connected to V3IN through the 1.5-Ω RDS(on) MOSFET switch. When the V3IN voltage becomes lower than
3.03 V, this MOSFET turns off and the 3.3-V LDO is turned back on immediately. A bypass ceramic capacitor is
needed to stabilize LDO, recommended value is between 10 µF and 22 µF. Place the bypass capacitor close to
the VREG3 pin. When EN3 is asserted low, both the 3.3-V LDO and the switchover circuit are turned off.
VRTC3
This 3.3-V low-current auxiliary power source is typically used for the system’s RTC bias voltage. It is powered
on after VIN is applied. A ceramic capacitor with a value between 1 µF and 2.2 µF placed close to the VRTC3
pin is needed to stabilize the LDO.
VCLK OUTPUT
When the V5IN voltage becomes higher than 2.0 V, the internal 250-kHz clock turns on and the VCLK pin
outputs a 50% duty-cycle clock signal. The voltage swing of VCLK is equal to the GND to V5IN voltage
THERMAL SHUTDOWN
When the device temperature exceeds the internal threshold value (typically 150C) the TPS51103 shuts off the
VREG3, VREG5 and VCLK outputs. This is a non-latch protection.
THERMAL DESIGN
The thermal performance greatly depends on the printed circuit board (PCB) layout. The TPS51103 is housed in
a thermally-enhanced PowerPAD™ package that has an exposed die pad underneath the body. For improved
thermal performance, this die pad must be attached to ground via thermal land on the PCB. This ground trace
acts as a heatsink and a heat spreader. For further information regarding the PowerPAD™ package and the
recommended board layout, refer to the PowerPAD™ package application note (SLMA002). This document is
available at www.ti.com.
LAYOUT GUIDELINES
Consider the following points before starting the TPS51103 layout design.
•
•
•
The input bypass capacitor for VIN should be placed as close as possible to the pin with short and wide
connection.
The output capacitors for VREG5, VREG3 and VRTC3 should be placed close to the pins with short and wide
connections.
In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly
to the package thermal pad. Wide copper traces connected to the thermal land help to dissipate heat.
Numerous 0.33 mm diameter vias are connected from the thermal land to the internal and/or solder-side
system ground plane(s) can also be used to help dissipation.
•
The GND pin, output capacitors for VREG5, VREG3 and VRTC3 should be connected to the internal and/or
solder-side system ground plane(s) with multiple vias. Use as many vias as possible to reduce the impedance
between them and the system ground plane.
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APPLICATION INFORMATION
A2
C2
AC2
C1
V15
C8
1 mF
AC1
A1
5V_IN
C4
C6
C7
0.1 mF 0.1 mF 0.1 mF
BAV199DW
C5
0.1 mF
TPS51103DRC
VCLK V5IN 10
1
2
3
4
5
5V_IN
GND
VRTC3
EN5
VREG5
9
8
7
6
5 V/100 mA
V
IN
(4.5 V to 28 V
3.3 V/5 mA
EN5
VIN
VREG3
V3IN
3.3 V/100 mA
EN3
3.3V_IN
EN3
C2
10 mF
C3
1 mF
C0
10 mF
C1
10 mF
UDG-08101
Figure 2. Typical Application
8
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TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
INPUT VOLTAGE
VREG3 LDO OUTPUT VOLTAGE
vs
LDO OUTPUT CURRENT
50
40
3.36
3.34
3.32
3.30
3.28
3.26
3.24
V
(V)
IN
5.5 V
6.5 V
12 V
V
= 28 V
IN
28 V
V
= 12 V
IN
V
= V
= 5 V
EN5
EN3
30
20
V
= 5.5 V
IN
V
= V
= 0 V
EN5
EN3
V
= 6.5 V
IN
10
0
0
10 20 30 40 50 60 70 80 90 100
– Output Current – mA
0
5
10
15 20
– Input Voltage – V
25
30
I
V
OUT
IN
Figure 3.
Figure 4.
VREG5 LDO OUTPUT VOLTAGE
vs
CHARGE PUMP OUTPUT VOLTAGE
vs
CHARGE PUMP OUTPUT CURRENT
LDO OUTPUT CURRENT
5.10
5.05
5.00
4.95
4.90
21
19
V
(V)
IN
5.5 V
6.5 V
12 V
V
= 28 V
IN
28 V
V
= 12 V
IN
17
15
13
11
V
= 6.5 V
IN
V
= 5.5 V
IN
9
0
10 20 30 40 50 60 70 80 90 100
I
0
1
2
3
4
5
6
7
– Output Current – mA
8
9
10
– Output Current – mA
I
OUT
OUT
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
ALWAYS ON OUTPUT VOLTAGE
vs
ALWAYS ON OUTPUT CURRENT
VREG5 SWITCHOVER OUTPUT VOLTAGE
vs
VREG5 SWITCHOVER OUTPUT CURRENT
3.34
3.33
5.00
4.99
4.98
T
= 25°C
A
4.97
4.96
4.95
4.94
4.93
4.92
4.91
4.90
4.89
3.32
3.31
T
= 85°C
A
3.30
3.29
3.28
T
= 0°C
A
T
= –40°C
A
4.88
3.27
0
10 20 30 40 50 60 70 80 90 100
– Output Current – mA
0
1
2 3
– Output Current – mA
4
5
I
I
VREG5
VRTC3
Figure 7.
Figure 8.
VREG3 SWITCHOVER OUTPUT VOLTAGE
vs
VREG3 SWITCHOVER OUTPUT VOLTAGE
INPUT CURRENT
vs
JUNCTION TEMPERATURE
3.30
50
45
VIN Standby Current
V
Supply Current
3.28
3.26
IN
40
35
30
3.24
25
20
3.22
3.20
15
10
3.18
3.16
5
0
0
10 20 30 40 50 60 70 80 90 100
– Output Current – mA
–50
0
50
100
– Junction Temperature – °C
150
I
T
VREG3
J
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
VREG5 DROP OUT VOLTAGE
vs
OUTPUT CURRENT
0
V
= 4.5 V
IN
0.2
0.4
T
= –40°C
A
0.6
0.8
1.0
1.2
T
= 25°C
A
T
(°C)
A
85
25
–40
T
= 85°C
A
0
10 20 30 40 50 60 70 80 90 100
– Output Current – mA
I
OUT
Figure 11.
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PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS51103DRCR
TPS51103DRCT
SON
SON
DRC
DRC
10
10
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS51103DRCR
TPS51103DRCT
SON
SON
DRC
DRC
10
10
3000
250
346.0
346.0
346.0
346.0
29.0
29.0
Pack Materials-Page 2
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www.ti.com/space-avionics-defense
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www.ti.com/wireless-apps
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