TPS5110PWRG4 [TI]
1.5A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO24, GREEN, PLASTIC, TSSOP-24;
| 型号： | TPS5110PWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.5A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO24, GREEN, PLASTIC, TSSOP-24 开关 光电二极管 |
| 文件： | 总42页 (文件大小：641K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLVS025B − APRIL 2002 − REVISED JULY 2004
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FEATURES
DESCRIPTION
D
D
Switching Mode Step-Down dc-to-dc
Controller With Fast LDO Controller
The TPS5110 provides one PWM-mode synchronous
buck regulator controller (SBRC) and one low drop-out
(LDO) regulator controller. The TPS5110 supports a
low-voltage/high-current power supply for I/O and other
peripherals in modern digital systems. The SBRC of the
TPS5110 automatically adjusts from PWM mode to
SKIP mode to maintain high efficiency under all load
conditions. The LDO controller drives an external
N-channel power MOSFET that realizes fast response
and ultra-low dropout voltage. A unique overshoot
protection circuit prevents a voltage hump at fast load
decreasing transients. The current protection circuit for
SBRC detects the drain-to-source voltage drop across
the low-side and high-side power MOSFET while it is
conducting. Also, the current protection circuit has a
Input Voltage Range
Switcher: 4.5 V to 28 V
LDO: 1.1 V to 3.6 V
D
Output Voltage Range
Switcher: 0.9 V to 3.5 V
LDO: 0.9 V to 2.5 V
D
D
D
D
D
Synchronous for High Efficiency
Precision V
( 1 %)
REF
PWM Mode Control: Max. 500-kHz Operation
High-Speed Error Amplifier
Overcurrent Protection With Temperature
Compensation Circuit
temperature coefficient to compensate for the R
DS(on)
D
Overvoltage and Undervoltage Protection
Programmable Short-Circuit Protection
variation of the MOSFET. This resistor-less current
protection simplifies the system design and reduces the
external parts count. The LDO controller includes
current-limit protection. Other features, such as
undervoltage lockout, power good, overvoltage,
D
APPLICATIONS
D
D
D
Notebook PCs, PDAs
Consumer Game Systems
DSP Application
undervoltage,
and
programmable
short-circuit
protection promote system reliability.
SIMPLIFIED APPLICATION
LDO Load Transient Response
C
= 47 µF
TPS5110PW
VIN
OUT
1
6
INV
LH 24
OUT_u 23
LL 22
V
= 1.5 V
OUT
(50 mV/ div)
V
O1
OUT_d 21
GND
5 V
INPUT
REG5V_IN 17
LDO_IN 16
LDO_CUR 15
LDO_GATE 14
LDO_OUT 13
12 INV_LDO
I = 0 A to 3 A
OUT
(1 A/ div)
V
O2
UDG-02052
t− time 100 µs/div
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Copyright 2002, Texas Instruments Incorporated
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ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ
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1
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SLVS025B − APRIL 2002 − REVISED JULY 2004
PW PACKAGE
(TOP VIEW)
ORDERING INFORMATION
(1)
PACKAGED DEVICES
T
A
PLASTIC TSSOP (PW)
TPS5110PW (24)
1
24
23
22
21
20
19
18
17
16
15
14
13
INV
FB
LH
OUT_u
LL
OUT_d
OUTGND
TRIP
VIN_SENSE
REG5V_IN
LDO_IN
LDO_CUR
LDO_GATE
LDO_OUT
−40°C to 85°C
2
3
SOFTSTART
PWM_SEL
CT
GND
REF
STBY
STBY_LDO
FLT
(1) The PW package is also available taped and reeled. Add an R
suffix to the device type (i.e. TPS5110PWR)
4
5
6
7
8
9
10
11
12
POWERGOOD
INV_LDO
2
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SLVS025B − APRIL 2002 − REVISED JULY 2004
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
TPS5110
UNIT
VIN_SENSE STBY STBY_LDO TRIP, LL
−0.3 to 30
,
,
,
INV, SOFTSTART, PWM_SEL, CT, FLT,
INV_LDO, LDO_OUT, LDO_CUR, LDO_IN,
REG5V_IN
−0.3 to 7
Input voltage range, V
V
I
LH
−0.3 to 35
−0.3 to 3
−0.3 to 7
−0.3 to 9
−0.3 to 35
REF
V
V
V
V
FB, POWERGOOD, OUT_d
LDO_GATE
Output voltage range, V
O
OUT_u
Continuous total power dissipation
Operating ambient temperature range, T
See dissipation rating table
−40 to 85
A
°C
Storage temperature range, T
stg
−55 to 150
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
4.5
MAX
5.5
3.6
28
UNIT
Supply voltage
Supply voltage
REG5V_IN
LDO_IN
1.1
VIN_SENSE
4.5
INV, INV_LDO, CT, PWM_SEL, SOFTSTART, FLT
POWERGOOD, FB, OUT_d
LDO_CUR, LDO_OUT
STBY, STBY_LDO, LL
OUT_u, LH
−0.1
−0.1
−0.1
−0.1
−0.1
−0.1
−0.1
300
6
5.5
3.5
28
V
Input voltage, V
I
33
TRIP
28
LDO_GATE
8
Oscillator frequency, f
OSC
500
85
kHz
Operating free-air temperature, T
−40
_C
A
DISSIPATION RATINGS (THERMAL RESISTANCE = °C/W)
DERATING FACTOR ABOVE
T
A
≤ 25°C POWER
T
A
= 85°C POWER
RATING
(1)
PACKAGE
T
A
= 25°C
RATING
24-PW
11.24 mW/°C
1404 mW
730 mW
(2) These devices are mounted on a JEDEC high-k board (2 oz. traces on surface, 2-layer 1-oz plane inside).
(Assume the maximum junction temperature is 150°C)
3
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SLVS025B − APRIL 2002 − REVISED JULY 2004
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, V
PARAMETER
= 12 V and V
= 5 V (unless otherwise specified).
VIN_SENSE
REG5V_IN
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT SECTION
REG5V_IN current, T = 25_C,
A
I
Supply current
V
= 3.6 V,
LDO_IN
0.9
1.4
mA
CC
V
CT
= V
INV
= V
INV_LDO
= V = 0 V
PWM_SEL
REG5V_IN current,
I Shutdown current
CC(S)
0.001 10.00
µA
V
V
= 0 V
STBY = STBY_LDO
UNDERVOLTAGE LOCKOUT SECTION
V
V
V
Low-to-high threshold voltage
REG5V_IN voltage
REG5V_IN voltage
REG5V_IN voltage
3.6
3.5
30
4.2
4.1
(TLH)
V
High-to-low threshold voltage
Hysteresis
(TLL)
200
mV
HYS
REFERENCE VOLTAGE SECTION
Reference voltage
V
REF
0.85
1%
V
T
= 25_C,
I
= 50 µA
= 50 µA
= 50 µA
−1%
-1.5%
−2%
A
REF
REF
REF
0_C ≤ T ≤ 85_C,
I
I
1.5%
2%
VREF
(tol)
Reference voltage tolerance
A
−40_C ≤ T ≤ 85_C,
A
I
= 50 µA,
REF
Reg(line)
Reg(load)
Line regulation
Load regulation
0.05
0.15
5
5
mV
mV
4.5 V ≤ V
≤ 5.5 V
(REG5V_IN)
0.1 µA ≤ I
≤ 1 mA
REF
CONTROL SECTION
V
V
High-level input voltage
Low-level input voltage
STBY, STBY_LDO, PWM_SEL
STBY, STBY_LDO, PWM_SEL
2.2
IH
V
V
0.3
IL
OUTPUT VOLTAGE MONITOR SECTION
OVP comparator threshold voltage
SBRC, LDO
SBRC, LDO
0.91
0.51
0.75
0.88
0.95
0.55
0.79
0.91
1.2
0.99
0.59
0.81
0.94
UVP comparator threshold voltage
Powergood comparator 1, 4 threshold voltage
Powergood comparator 2, 3 threshold voltage
POWERGOOD high-to-low
POWERGOOD low-to-high
UVP protection
Powergood propagation delay from INV and
INV_LDO to POWERGOOD
µs
4
−1.5
−2.3
−3.1
Timer latch current source
µA
OVP protection
−80 −125 −180
OSCILLATOR SECTION
PWM mode,
C
= 44 pF
CT
f
Oscillator frequency
300
kHz
V
OSC
T
= 25_C
A
dc
1.0
0.4
1.1
1.17
0.5
1.2
0.6
V
CT high-level output voltage
OH
OL
f
= 300 kHz
OSC
dc
V
CT low-level output voltage
f
= 300 kHz
0.43
OSC
4
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SLVS025B − APRIL 2002 − REVISED JULY 2004
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, V
= 12 V and V
= 5 V (unless otherwise specified).
VIN_SENSE
REG5V_IN
SBRC ERROR AMPLIFIER SECTION
V
Input offset voltage
Open loop voltage gain
Unity gain bandwidth
Output sink current
Output source current
T
= 25_C
2
10
mV
dB
IO
A
50
2.5
0.7
MHz
I
I
V
V
= 1 V
= 1 V
0.2
SNK
FB
mA
−0.2
−0.9
SRC
FB
DUTY CONTROL SECTION
DUTY Maximum duty control
OUTPUT DRIVERS SECTION
OUT_u sink current
f
= 300 kHz,
V
INV
= 0 V
82%
OSC
V
V
V
V
V
V
T
− V = 3 V
1.2
−1.2
1.5
OUT_u
− V
LL
OUT_u source current
= 3 V
LH
OUT_u
A
OUT_d sink current
= 3 V
= 2 V
OUT_d
OUT_d
OUT_d source current
−1.5
1.5
LDO_GATE sink current
LDO_GATE source current
= 2 V
LDO_GATE
mA
= 2 V
−1.4
13.0
LDO_GATE
I
TRIP current
= 25_C
11.5
−1.6
14.5
−2.9
10
µA
TRIP
SOFT-START SECTION
Soft-start current
A
I
−2.3
2
µA
SOFT
LDO ERROR AMPLIFIER SECTION
V
IO
Input offset voltage
T
= 25_C,
V
LDO_IN
= 3.3 V
mV
dB
A
Open loop voltage gain
Unity-gain bandwidth
V
= 3.3 V
50
40
LDO_IN
LDO_IN
V
= 3.3 V,
C
= 2000 pF
1.4
50
MHz
LOAD
LDO CURRENT LIMIT SECTION
Current limit comparator threshold voltage
LDO OVERSHOOT PROTECTION SECTION
LDO_OUT sink current
V
= 3.3 V
60
mV
mA
LDO_IN
V
= V
LDO_GATE
= 1.5 V
25
LDO_OUT
5
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SLVS025B − APRIL 2002 − REVISED JULY 2004
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
5
CT
FB
I/O External capacitor from CT to GND adjusts frequency of the triangle oscillator.
Feedback output of error amplifier
2
O
FLT
10
I/O Fault latch timer pin. An external capacitor is connected between FLT and GND to set the FLT enable time
up.
GND
INV
6
1
−
I
Signal GND
Inverting input of the SBRC error amplifier, skip comparator, OVP/UVP comparators and POWERGOOD
comparator
INV_LDO
12
15
14
13
I
I
Inverting input of the LDO regulator, OVP/UVP comparators and POWERGOOD comparator
Current sense input of the LDO regulator.
LDO_CUR
LDO_GATE
LDO_OUT
O
Gate control output of an external MOSFET for LDO
I/O LDO regulator’s output connection. If output voltage causes an over shoot at output current changes high
to low quickly, it pulls out electrical charge from this pin.
LDO_IN
LH
16
24
22
I
Input of LDO regulator and current sense input of LDO regulator
I/O Bootstrap capacitor connection for high-side gate driver
LL
I/O High side gate driving return. Connect this pin to the junction of the high side and low side MOSFET(s) for
floating drive configuration. This pin also is an input terminal for current comparator.
OUT_d
21
23
20
11
O
O
−
Gate drive output for low-side MOSFET(s)
OUT_u
Gate drive output for high-side MOSFET(s).
OUTGND
POWERGOOD
Ground for FET drivers. It is connected to the current limiting comparator’s negative input.
O
Power good open-drain output. PG comparators monitor both SBRC’s and LDO’s over voltage and under
voltage. The threshold is 7%. When either output is beyond this condition, POWERGOOD output goes
low. When STBY or STBY_LDO goes high, the POWERGOOD pin’s output starts with high. POWER-
GOOD also monitors REG5V_IN’s UVLO output.
PWM_SEL
REF
4
7
I
PWM or auto PWM/SKIP modes select.
H: auto PWM/SKIP
L: PWM fixed
O
I
0.85-V reference voltage output. This 0.85-V reference voltage is used for setting the output voltage and
the voltage protections. This reference voltage is regulated from REG5V_IN power supply.
REG5V_IN
SOFTSTART
STBY
17
3
External 5-V input. This input is a supply voltage for internal circuits.
I/O External capacitor between SOFTSTART and GND sets SBRC soft−start time.
8
I
I
Standby control input for SBRC. SBRC can be switched into standby mode by grounding the STBY pin.
STBY_LDO
9
Standby control input for LDO regulator. LDO regulator can be switched into standby mode by grounding
the STBY_LDO pin.
TRIP
19
18
I
I
External resistor connection for SBRC’s output current protection control.
VIN_SENSE
SBRC supply voltage monitor. Input range is 4.5 V to 28 V. This pin is for reference of current limit.
6
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SLVS025B − APRIL 2002 − REVISED JULY 2004
FUNCTIONAL BLOCK DIAGRAM
LH
SOFTSTART
SOFT START
OUT_u
LL
Skip Comp.
−
Delay
−
+
PWM Comp.
+
OUT_d
Delay
FB
OUTGND
INV
Current Comp.1
−
PWM
SKIP
−
+
control
+
Err. Amp.
+
Current
0.85 V
Protection
Trigger
SOFT
− (VIN_SENSE − TRIP)
VIN_SENSE
TRIP
START
CT
OSC
UVLO
Signal
STBY
−
+
OVP SBRC
−
+
Current Comp.2
PG Comp.1
+
0.85 V +12 %
INV
PWM_SEL
FLT
−
POWERGOOD
0.85 V −7 %
INV
OVP LDO
−
TIMER
+
+
PG Comp.2
UVP SBRC
0.85 V +7 %
INV_LDO
0.85 V −35 %
−
PG Comp.3
−
UVP LDO
+
+
INV_LDO
STBY_LDO
UVLO
Signal
−
0.85 V +7 %
STBY
PG Comp.4
0.85 V −7 %
STBY_LDO
REG5V_IN
VREF
UVLO
Signal
REF
0.85 V
−
VIN
sense
+
−
OVP LDO
Err. Amp.
UVLO Comp.
+
−
LDO_GATE
0.85 V +12 %
+
Clamp
INV_LDO
GND
0.85 V
LDO_IN
+
−
UVP LDO
Current Limit
LDO_CUR
0.85 V −35 %
LDO Overshoot
Protection
LDO_OUT
Figure 1. Block Diagram
7
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SLVS025B − APRIL 2002 − REVISED JULY 2004
DETAILED DESCRIPTION
PWM operation
The SBRC block has a high-speed error amplifier to regulate the output voltage of the synchronous buck
converter. The output voltage of the SBRC is fed back to the inverting input (INV) of the error amplifier. The
noninverting input is internally connected to a 0.85 V precise band gap reference circuit. The unity-gain
bandwidth of the amplifier is 2.5 MHz. This decreases the amplifier delay during fast-load transients and
contributes to a fast response. Loop gain and phase compensation is programmable by an external C, R
network between the FB and INV pins. The output signal of the error amplifier is compared with a triangular wave
to achieve the PWM control signal. The oscillation frequency of this triangular wave sets the switching frequency
of the SBRC and is determined by the capacitor connected between the CT and GND pins. The PWM mode
is used for the entire load range if the PWM_SEL pin is set LOW, or used in high-output current condition if auto
PWM/SKIP mode is selected by setting the same pin to HIGH.
SKIP mode operation
The PWM_SEL pin selects either the auto PWM/SKIP mode or fixed PWM mode. If this pin is lower than 0.3 V,
the SBRC operates in the fixed PWM mode. If 2.5 V (min.) or higher is applied, it operates in auto PWM/SKIP
mode. In the auto PWM/SKIP mode, the operation changes from constant frequency PWM mode to an
energy-saving SKIP mode automatically in accordance with load conditions. Using a MOSFET with ultra-low
R
if the auto SKIP function is implemented is not recommended. The SBRC block has a hysteretic
DS(on)
comparator to regulate the output voltage of the synchronous buck converter during SKIP mode. The delay from
the comparator input to the driver output is typically 1.2 µs. In the SKIP mode, the frequency varies with load
current and input voltage.
high-side driver
The high-side driver is designed to drive high current and low R
N-channel MOSFET(s). The current rating
DS(on)
of the driver is 1.2 A at source and sink. When configured as a floating driver a 5-V bias voltage is delivered from
external REG5V_IN supply. The instantaneous-drive current is supplied by the flying capacitor between the LH
and LL pins since a 5-V power supply does not usually have low impedance. It is recommended to add a 5-Ω
to 10-Ω resistor between the gate of the high-side MOSFET(s) and the OUT_u pin to suppress noise. The
maximum voltage that can be applied between the LH and OUTGND pins is 33 V. When selecting the
high-current rating MOSFET(s), it is important to pay attention to both gate-drive power dissipation and the
rise/fall time against the dead-time between high-side and low-side drivers. The gate-drive power is dissipated
from the controller device and it is proportional to the gate charge at Vgs = 5 V, PWM switching frequency and
the numbers of all MOSFETs used for low-side and high-side switches. This gate drive loss should not exceed
the maximum power dissipation of the device.
low-side driver
The low-side driver is designed to drive high-current and low R
N-channel MOSFET(s). The maximum
DS(on)
drive voltage is 5 V from REG5V_IN pin. The current rating of the driver is typically 1.5 A at source and sink.
Gate resistance is not necessary for the low-side MOSFET for switching noise suppression since it turns on after
the parallel diode is turned on (ZVS). It needs the same dissipation consideration when using high-current rating
MOSFET(s). Another issue that needs precaution is the gate threshold voltage. Even though the OUT_d pin
is shorted to the OUTGND pin with low resistance when the low-side MOSFET(s) is OFF, high dv/dt at the LL
pin during turnon of the high side arm generates voltage peak at the OUT_d pin through the drain to gate
capacitance, Cdg, of the low-side MOSFET(s). To prevent a short period shoot-through during this switching
event, the application designer should select MOSFET(s) with adequate threshold voltage.
8
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SLVS025B − APRIL 2002 − REVISED JULY 2004
DETAILED DESCRIPTION
dead time
The internally defined dead-time prevents shoot-through current flowing through the main power MOSFETs
during switching transitions. Typical value of the dead-time is 100 ns.
standby
The SBRC and the LDO controller can be switched into standby mode separately by grounding the STBY pin
and/or SYBY_LDO pins. The standby-mode current, when both controllers are off, can be as low as 1 nA.
Table 1. Standby Logic (V
> 4 V){
REG5V_IN
STBY
STBY_LDO
SBRC
OFF
OFF
ON
LDO
OFF
ON
POWERGOOD
L
L
L
H
L
OFF
OFF
OFF
ON
H
H
OFF
ON
H
ON
soft start
Soft-start ramp up of the SBRC is controlled by the SOFTSTART pin voltage. After the STBY pin is raised to
a HIGH level, an internal current source charges up an external capacitor connected between the SOFTSTART
and GND pins. The output voltage ramps up as the SOFTSTART pin voltage increases from 0 V to 0.85 V. The
soft-start time is easily calculated by the supply current and the capacitance value (see application information).
The soft-start timing circuit for the LDO is integrated into the device. The soft-start time is fixed and can be as
short as 600 µs. This is observed when the LDO is turned on separately from the SBRC. Simultaneous start
up of the two outputs is also possible. Tie the LDO input to the SBRC’s output and let both STBY_LDO and STBY
voltages rise to the HIGH level simultaneously, then the LDO’s output follows the ramp of the SBRC’s output.
over current protection
Over current protection (OCP) is achieved by comparing the drain-to-source voltage of the high-side and
low-side MOSFET to a set-point voltage, which is defined by both the internal current source, I
, and the
TRIP
external resistor connected between the VIN_SENSE and TRIP pins. I
has a typical value of 13 µA at 25°C.
TRIP
When the drain-to-source voltage exceeds the set-point voltage during low-side conduction, the high-side
current comparator becomes active, and the low-side pulse is extended until this voltage comes back below
the threshold. If the set-point voltage is exceeded during high-side conduction in the following cycle, the
current-limit circuit terminates the high-side driver pulse. Together this action has the effect of decreasing the
output voltage until the under voltage protection circuit is activated to latch both the high-side and low-side
drivers OFF. In the TPS5110, trip current I
compensate for temperature drift of the MOSFET on-resistance.
also has a temperature coefficient of 3400 ppm/°C in order to
TRIP
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SLVS025B − APRIL 2002 − REVISED JULY 2004
DETAILED DESCRIPTION
OCP for the LDO
To achieve the LDO current limit, a sense resistor must be placed in series with the N-channel MOSFET drain,
connected between the LDO_IN and LDO_CUR pins (see reference schematic). If the voltage drop across this
sense resistor exceeds 50 mV, the output voltage is reduced to approximately 22% of the nominal value, thus
activates UVP to start the FLT latch timer. When the time is up, the LDO_GATE pin is pulled LOW to makes the
LDO regulator shutdown. Note that the SBRC is also latched OFF at the same time since the LDO and the SBRC
share the same FLT capacitor.
overvoltage protection
For over voltage protection (OVP), the TPS5110 monitors the INV and INV_LDO pin voltages. When the INV
or INV_LDO pin voltage is higher than 0.95 V (0.85 V +12%), the OVP comparator output goes low and the FLT
timer starts to charge an external capacitor connected to FLT pin. After a set time, the FLT circuit latches the
high-side and low-side MOSFET drivers and the LDO. The latched state of each block is summarized in Table 2.
The timer-source current for the OVP latch is 125 µA(typ.), and the time-up voltage is 1.185 V (typ.). The OVP
timer is designed to be 50 times faster than the undervoltage protection timer described below.
Table 2. Overvoltage Protection Logic
HIGH-SIDE
MOSFET DRIVER
LOW-SIDE
MOSFET DRIVER
OVP OCCURS AT
LDO
SBRC
LDO
OFF
OFF
ON
OFF
OFF
OFF
undervoltage protection
For under voltage protection (UVP), the TPS5110 monitors the INV and INV_LDO pin voltages. When the INV
or INV_LDO pin voltage is lower than 0.55 V (0.85 V − 35 %), the UVP comparator output goes low, and the
FLT timer starts to charge the external capacitor connected to FLT pin. Also, when the current comparator
triggers the OCP, the UVP comparator detects the under-voltage output and starts the FLT capacitor charge,
too. After a set time, the FLT circuit latches all of the MOSFET drivers to the OFF state. The timer-latch source
current for UVP is 2.3 µA (typ.), and the time-up voltage is also 1.185 V (typ.). The UVP function of the LDO
controller is disabled when voltage across the pass transistor is less than 0.23 V (typ.).
FLT
When an OVP or UVP comparator output goes low, the FLT circuit starts to charge the FLT capacitor. If the FLT
pin voltage goes beyond a constant level, the TPS5110 latches the MOSFET drivers. At this time, the state of
MOSFET is different depending on the OVP alert and the UVP alert, see Table 2. The enable time used to latch
the MOSFET drivers is decided by the value of the FLT capacitor. The charging constant current value depends
on whether it is an OVP alert or a UVP alert as shown in the following equation:
FLTsource current (OVP) + FLTsource current (UVP) 50
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SLVS025B − APRIL 2002 − REVISED JULY 2004
DETAILED DESCRIPTION
undervoltage lockout (UVLO)
When the REG5V_IN voltage decreases below about 4 V, the output stages of both the SBRC and the LDO are
turned off. This state is not latched and the operation recovers immediately after the input voltage becomes
higher than the turn-on value again. The typical hysteresis voltage is 100 mV.
UVLO for LDO
The LDO_IN voltage is monitored with a hysteretic comparator. When this voltage is less than 1 V, the UVLO
circuit disables the UVP/OVP comparators that monitor the INV_LDO voltage. In case the SBRC over current
protection is activated prior to that of the LDO’s, this protection function may also be observed.
LDO control
The LDO controller can drive an external N-channel MOSFET. This realizes a fast response as well as an
ultra-low dropout voltage regulator. For example, it is easy to configure both a 1.8-V and a 1.5-V high-current
power supply for core and I/O of modern digital processors, one from the SBRC and the other from the LDO.
The LDO_IN voltage range is from 1.1 V to 3.6 V, and the output voltage is adjustable from 0.9 V to 2.5 V by
an external resistor divider. Gain and phase of the high-speed error amplifier for this LDO control is internally
compensated and is connected to the 0.85-V band-gap reference circuit. The gate driver buffer is supplied by
VIN_SENSE voltage. In the relatively high-output voltage applications, make sure that output voltage plus
threshold voltage of the pass transistor is less than the minimum VIN. More precisely,
V
* 0.7 V w V
) V
VIN_SENSE
where V
THN
LDO_OUT
is the threshold voltage of N-channel MOSFET.
THN
The LDO controller is also equipped with OVP, UVP, over current limit and overshoot protection functions.
overshoot protection − LDO
In the event that load current changes from high to low very quickly, the LDO regulator output voltage may start
to overshoot. In order to resist this phenomenon, the LDO controller has an overshoot protection function. If the
LDO regulator output overshoots, the controller draws electrical charge out from LDO_OUT pin to hold it stable.
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SLVS025B − APRIL 2002 − REVISED JULY 2004
DETAILED DESCRIPTION
powergood
A single powergood circuit monitors the SBRC output voltage, LDO output voltage and REF5V_IN voltage. The
POWERGOOD pin is an open-drain output. When INV or INV_LDO voltage go beyond +/− 7% of 0.85 V or the
REG5V_IN voltage is lower than 4 V, the POWERGOOD pin is pulled down to the LOW level. POWERGOOD
propagation delay is minimal, 1 µs to 4 µs.
Table 3. Powergood Logic{
POWER
GOOD
STBY
STBY_LDO
0.79 V ≤ V
≤ 0.91 V 0.79 V≤ V
≤ 0.91 V
V
> 4 V
INV
INV_LDO
REG5V_IN
L
H
L
L
L
X
X
X
X
X
L
L
L
L
L
L
H
X
X
X
H
H
H
H
H
X
X
H
H
H
H
FALSE
X
X
FALSE
X
X
X
FALSE}
TRUE
TRUE
TRUE
†
‡
X = True OR False
The logic circuit is under normal operation
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT (SHUTDOWN)
vs
JUNCTION TEMPERATURE
2.0
200
150
100
50
V
V
= 3.6 V
LDO_IN
V
V
= 0 V
STBY
STBY_LDO
= 0 V
= V
CT
=
= 0 V
VPWM_SEL
= V
INV
INV_LDO
1.5
1.0
0.5
0.0
0
−50
0
50
100
150
−50
0
50
100
150
T
J
− Junction Temperature −
°C
T
− Junction Temperature −
°C
J
Figure 2
Figure 3
NOTE: V
VIN_SENSE
= 12 V, V
REG5V_IN
= 5 V unless otherwise noted.
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SLVS025B − APRIL 2002 − REVISED JULY 2004
TYPICAL CHARACTERISTICS
FLT (OVP) SOURCE CURRENT
FLT (UVP) SOURCE CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
−160
−140
−120
−100
−80
−60
−40
−20
0
−3.0
−2.5
−2.0
−1.5
−1.0
−0.5
V
= 3.6 V,
LDO_IN
= 0.5 V, V
V
= 0.5 V
= 3.6 V, V
= 1.0 V, V
LDO_IN
0
FLT
100
INV
50
= 0.5 V
V
FLT
INV
0.0
−50
150
−50
0
J
50
100
150
T
J
− Junction Temperature −
T
− Junction Temperature −
°C
°C
Figure 4
Figure 5
TRIP CURRENT
vs
LDO_GATE SINK CURRENT
vs
JUNCTION TEMPERATURE
OUTPUT VOLTAGE
2.0
1.5
1.0
0.5
0.0
25
20
15
10
5
V
= 2.0 V
= V
INV_LDO
V
= 3.3 V
LDO_CUR
LDO_IN
V
TRIP
= V
VIN_SENSE
− 0.1 V
50
0
−50
0
100
150
0
2
4
6
8
Voltage − V
T
J
− Junction Temperature − °C
Figure 6
Figure 7
NOTE: V
VIN_SENSE
= 12 V, V = 5 V unless otherwise noted.
REG5V_IN
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SLVS025B − APRIL 2002 − REVISED JULY 2004
TYPICAL CHARACTERISTICS
LDO_GATE SOURCE CURRENT
OVER VOLTAGE PROTECTION THRESHOLD VOLTAGE
vs
vs
OUTPUT VOLTAGE
JUNCTION TEMPERATURE
−2.0
−1.5
−1.0
−0.5
0.0
960
955
950
945
940
V
V
= 0 V,
INV_LDO
= V
= 3.3 V
LDO_IN
LDO_CUR
0
2
4
6
8
−50
0
50
100
150
Ouput Voltage − V
T
− Junction Temperature −
°C
J
Figure 8
Figure 9
OSCILLATOR FREQUENCY
OUTPUT MAXIMUM DUTY CYCLE
vs
vs
CAPACITANCE
JUNCTION TEMPERATURE
88
1000
100
10
= 44 pF,
C
V
CT
PWM_SEL
87
86
85
84
83
82
81
80
= V
= V
LL
= V
= 0 V
FLT
INV
V
= 4.5 V
REG5V_IN
5.0 V
5.5 V
T = 25 °C
J
−50
0
50
100
150
10
50
100
150
200
250
300
350
Capacitance − pF
T
− Junction Temperature − °C
J
Figure 10
Figure 11
NOTE: V
VIN_SENSE
= 12 V, V
REG5V_IN
= 5 V unless otherwise noted.
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SLVS025B − APRIL 2002 − REVISED JULY 2004
TYPICAL CHARACTERISTICS
FLT DELAY TIME (OVP)
FLT DELAY TIME (UVP)
vs
vs
CAPACITANCE
CAPACITANCE
100000
100000
V
= 0.65 to 0.50 V,
INV
V
= 0.85 to 1.05 V,
INV
T = 25 °C
T = 25
10000
1000
10000
1000
J
°C
J
100
100
10
10
1
1
0.1
0.1
10
100
1000
10000
10
100
1000
10000
Capacitance − pF
Capacitance − pF
Figure 12
Figure 13
SOFT-START TIME
vs
CAPACITANCE
LDO CURRENT LIMIT THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
100000
60
°C
= 25
T
J
50
40
10000
1000
30
100
10
20
10
V
= 3.3 V, V
= 0.5 V
LDO_IN
INV_LDO
50
1
0
1
10
100
Capacitance
1000
10000 100000
−50
0
100
°C
150
−
T
− Junction Temperature −
°C
J
Figure 14
Figure 15
NOTE: V
VIN_SENSE
= 12 V, V = 5 V unless otherwise noted.
REG5V_IN
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SLVS025B − APRIL 2002 − REVISED JULY 2004
TYPICAL CHARACTERISTICS
LDO UVLO THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
1.2
VTLH
VTHL
1.0
0.8
0.6
0.4
0.2
= 0.50 V
V
INV_LDO
0.0
−50
0
J
50
100
150
T
− Junction Temperature − °C
Figure 16
NOTE: V
VIN_SENSE
= 12 V, V
REG5V_IN
= 5 V unless otherwise noted.
APPLICATION INFORMATION
The design shown in this application information is a reference design for a notebook PC application. An
evaluation module (EVM) is available for customer testing and evaluation. This information allows a customer
to fully evaluate the given design using the plug-in EVM shown in Figure17. For subsequent board revisions,
the EVM design can be copied onto the system PCB to shorten the design cycle.
The following key design procedures aid in the design of the notebook PC power supply using TPS5110. An
optional circuit composed of Q04, R16, R22 and R24 can be used to increase temperature coefficient of the
trip current, which is at the top in the page 18.
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
1
C 1
C 1 9
C 0 1 C
C 0 1 B
C 0 1 A
C 0 9
R 1 5 A
R 1 5 B
R 1 5 C
C 2 6
C 2 5
C 1 5
C 1 4 ( D U M M Y )
8
7
6
5
8
7
6
5
1
2
3
1
2
3
8
7
6
5
8
7
6
5
1
2
3
1
2
3
8
7
6
5
1
2
3
Figure 17. EVM Typical Design
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APPLICATION INFORMATION
Table 4. EVM Input and Outputs
VIN{
REG5V_IN
5 V
Vo1 (SBRC)
1.8 V
Io1 (SBRC)
6 A
Vo2 (LDO)
1.5 V
Io2 (LDO)
3 A
8 V to 20 V
†
Recommended operation voltage for the EVM
output voltage setpoint calculation
The reference voltage and the voltage divider set the output voltage. In the TPS5110, the reference voltage is
0.85 V, and the divider is composed of three resistors in the EVM design that are R01A, R01B and R03 for
switching regulator output; R10, R11 and R09 for LDO regulator output.
R1 V
R1 V
O
REF
REF
REF
V
+
) V
or R2 +
O
REF
R2
V
* V
where R1 is the top resistor (kΩ) (R01A + R01B or R10 + R11); R2 is the bottom resistor (kΩ) (R03 or R09);
is the required output voltage (V); V is the reference voltage (0.85 V in TPS5110). The value for R1 is
V
O
REF
set as a part of the compensation circuit and the value of R2 may be calculated to achieve the desired output
voltage. In the EVM design, the value of R1 was determined as R01A = R01B = 10 kΩ for V 1, and R10 = 6.8 kΩ
O
and R11 = 820 Ω for V 2 considering stability. For V 1:
O
O
20 kW 0.85
R03 +
+ 17.89 kW
1.8 * 0.85
Use 18 kΩ.
For V 2:
O
(
)
6.8 kW ) 820 0.85
R09 +
+ 9.96 kW
1.5 * 0.85
Use 10 kΩ.
The values of R01A, R01B, R10 and R11 are chosen so that the calculated values of R03 and R09 are those
of standard value resistor and the V setpoint maintains the highest precision. This can be best accomplished
O
by combining two resistor values. If a standard value resistor can not be applied such as R10 and R11, use a
value for R10 that is just slightly less than the desired total. A small value resistor in the range of tens or hundreds
of ohms for R11 can then be added to generate the desired final value.
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
output inductor selection
The required value for the output-filter inductor can be calculated by using the equation:
ǒVIN * V
Ǔ
V
O
O
1
L
+
OUT
k I
VIN
f
OUT
S
Where L
is output filter inductor value (H), VIN is the input voltage (V), Iout is the maximum output current
OUT
(A), f is the switching frequency (Hz). Constant value k, a ratio of ripple current to output current, is typically
S
in the range 0.2 to 0.3. For V 1, the calculation for the maximum input voltage of 20 V, yields a value for L01
O
of 3.03 µH, and for minimum input voltage of 8 V, 2.58 µH. For the EVM, a value of 2.8 µH is used for L01.
output inductor ripple current
The output-inductor current can affect not only the efficiency, but also the output voltage ripple. The equation
is exhibited below:
ǒRDS(on) ) RIǓ
VIN * V * I
V
O
O
L
O
1
I
+
RIPPLE
VIN
f
OUT
S
where I
is the peak-to-peak ripple current (A) through the inductor; I is the output current; R
is the
RIPPLE
O
DS(on)
on-time resistance of MOSFET (Ω); Rl is the inductor dc resistance (Ω). From the equation, it can be seen that
the current ripple can be adjusted by changing the output inductor value. For the EVM design, the worst-case
output ripple occurs with VIN = 20 V:
Example: VIN = 20 V; V = 1.8 V; I = 6 A; R
= 25 mΩ; R = 10 mΩ; Fs = 300 kHz; L
= 2.8 µH.
O
O
DS(on)
l
OUT
Then, the ripple current I
= 1.93 A
RIPPLE
output capacitor selection (SBRC)
Selection of the output capacitor is basically dependent on the amount of peak-to-peak ripple voltage allowed
on the output and the ability of the capacitor to dissipate the RMS ripple current. Assuming that the ESR of the
output filter sees the entire inductor-ripple current then:
V
+ I
R
PP
RIPPLE
ESR
And a suitable capacitor must be chosen so that the peak-to-peak output ripple is within the limits allowable for
the application.
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APPLICATION INFORMATION
output capacitor RMS current (SBRC)
Assuming the inductor-ripple current totally goes through the output capacitor to ground, the RMS current in
the output capacitor can be calculated as:
I
RIPPLE
I
+
O(rms)
Ǹ
12
where I
current (A).
is maximum RMS current in the output capacitor (A); I
is the peak-to-peak inductor-ripple
O(rms)
RIPPLE
Example: I
= 1.93 A, therefore, I
= 0.56 A
O(rms)
RIPPLE
input capacitor RMS current (SBRC)
Assuming the input current totally goes into the input capacitor to the power ground, the RMS current in the input
capacitor can be calculated as:
2
1
12
+ Ǹ
I
I
D (1 * D) )
D I
i(rms)
where I
O
RIPPLE
is the input RMS current in the input capacitor (A); I is the output current (A); I
peak-to-peak output inductor-ripple current; D is the duty cycle and defined as V /V in this case. From the
is the
i(rms)
O
RIPPLE
O
I
equation, it can be seen that the highest input RMS current usually occurs at the lowest input voltage, so it is
the worst case design for input capacitor ripple current.
Example: I = 6 A; D = 22.5 %; I
= 1.6 A then, I
= 2.5 A
i(rms)
O
RIPPLE
The input capacitors must be chosen so that together they can safely handle the input-ripple current. Depending
on the input filtering and the dc input voltage source, not all the ripple current flows through the input capacitors,
but some may be present on the input leads to the EVM.
soft start
The soft-start timing can be adjusted by selecting the soft-start capacitor value. The equation is;
T
SOFT
0.85
−6
C
+ 2.3 10
SOFT
where C(soft) is the soft-start capacitor (µF) (C04 in EVM design): T
is the start-up time (s).
SOFT
Example: T
= 5 ms, therefore, C
= 0.0135 µF.
SOFT
SOFT
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APPLICATION INFORMATION
current protection (SBRC)
The current limit in TPS5110 is set using an internal current source and an external resistor (R13). The current
limit protection circuit compares the drain-to-source voltage of the high-side and low-side drivers with respect
to the set-point voltage. If the voltage up exceeds the limit during high-side conduction, the current-limit circuit
terminates the high-side driver pulse. If the set point voltage is exceeded during low-side conduction, the
low-side pulse is extended through the next cycle. Together this action has the effect of decreasing the output
voltage until the under voltage protection circuit is activated and the fault latch is set and both the high and
low-side MOSFET drivers are shut off. The equation below should be used for calculating the external resistor
value for current protection set point:
I
RIPPLE
R
ǒ
I
)
Ǔ
DS(on)
TRIP
2
R
+
CL
−6
13 10
where R is the external current limit resistor (R13); R
is the low-side MOSFET(Q02) on-time resistance.
CL
DS(on)
I
is the required current limit.
TRIP
Example: R
= 25 mΩ, I
= 6 A, I
= 1.93 A, therefore, R = 13.4 kΩ.
DS(on)
TRIP
RIPPLE CL
It should be noted that R
operating temperature, the value of R
it is recommended that the high-side MOSFET(s) has same, or slightly higher R
MOSFET(s). If the low-side MOSFET(s) has a higher R
of a FET is highly dependent on temperature, so to insure full output at maximum
DS(on)
in the above equation should be adjusted. For maximum stability,
DS(on)
than the low-side
DS(on)
, in certain low duty cycle applications it may be
DS(on)
possible for the device to regulate at an output current higher than that set by the above equation by increasing
the high side conduction time to compensate for the missed conduction cycle caused by the extension of the
previous low-side pulse.
timer latch
The TPS5110 includes fault latch function with a user adjustable timer to latch the MOSFET drivers in case of
a fault condition. When either the OVP or UVP comparator detect a fault condition, the timer starts to charge
FLT capacitor (C07), which is connected with FLT pin 10. The circuit is designed so that for any value of FLT
capacitor, the under-voltage latch time t
is about 50 times larger than the over-voltage latch time
(uvplatch)
t
. The equations needed to calculate the required value of the FLT capacitor for the desired over and
(ovplatch)
under-voltage latch delay times are:
t
t
(uvplatch)
1.185
(ovplatch)
1.185
*6
*6
C
+ 2.3 10
and
C
+ 125 10
LAT
LAT
where C
OVP detection to latch.
is the external capacitor, t
is the time from UVP detection to latch. t
is the time from
LAT
(uvplatch)
(ovplatch)
For the EVM, t
= 5 ms and t
= 0.1 ms, so C
= 0.01 µF
(uvplatch)
(ovplatch)
LAT
If the voltage on the FLT pin reaches 1.185 V, the fault latch is set, and the MOSFET drivers are set as follows:
under-voltage protection
The under-voltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the
voltage at either pin falls below 65% of the 0.85-V reference, the timer begins to charge the FLT capacitor. If
the fault condition persists beyond the time t
drivers, and LDO regulator drivers are forced OFF.
, the fault latch is set and both the high side and low-side
(uvplatch)
21
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
short circuit protection
The short circuit protection circuitry uses the UVP circuit to latch the MOSFET drivers. When the current-limit
circuit limits the output current, then the output voltage goes below the target-output voltage and UVP
comparator detects a fault condition as described above.
over voltage protection
The over-voltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage
at either pin rises above 112% of the 0.85-V reference, the timer begins to charge the FLT capacitor. If the fault
condition persists beyond the time t
the low-side drivers are forced ON, and LDO regulator drivers are forced OFF.
, the fault latch is set and the high-side drivers are forced OFF, while
(ovplatch)
CAUTION: Do not set the FLT pin to a lower voltage (or GND) while the device is timing out an OVP
or UVP event. If the FLT pin is manually set to a lower voltage during this time, output overshoot
may occur. The TPS5110 must be reset by grounding STBY and STBY_LDO, or dropping down
REG5V_IN.
disablement of the protection function
If it is necessary to inhibit the protection functions of the TPS5110 for troubleshooting or other purposes, the
OCP, OVP and UVP circuits may be disabled.
• OCP(SBRC): Remove the current-limit resistors R13 to disable the current limit function.
• OCP(LDO): Short-circuit R12 to disable the current limit function.
• OVP, UVP: Grounding the FLT pin can disable OVP and UVP.
output capacitor selection for LDO
To keep stable operation of the LDO, capacitance of more than 33 µF and R
recommended for the output capacitor.
of more than 30 mΩ are
ESR
power MOSFET selection for LDO
Also, to keep stable operation of the LDO, lower input capacitance is recommended for the external power
MOSFET. However, too small input capacitance may lead the feedback loop into unstable region. In such a
case, the gate resistor of several hundred ohms keeps the LDO operation in the stable state.
current protection for LDO
If excess output current flows through sense resistor (R12) and the voltage drop exceeds 50 mV, the output
voltage is reduced to approximately 22% of the nominal value, thus activates UVP to start the FLT latch timer.
When the set current is 4 A, the value of R12 is 12.5 mΩ.
22
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
layout guidelines
Good power supply results only occur when care is given to proper design and layout. Layout affects noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milli-amps to tens of amps, good power supply layout is much more difficult than most general
PCB designs. The general design should proceed from the switching node to the output, then back to the driver
section and, finally, parallel the low-level components. Below are specific points to consider before the layout
of a TPS5110 design begins.
• A four-layer PCB design is recommended for design using the TPS5110. For the EVM design, the top
layer contains the interconnection to the TPS5110, plus some additional signal traces. Layer 2 is fully
devoted to the DRVGND plane. Layer 3 mainly has wide VIN and V 1 pattern. The bottom layer is
O
almost devoted to other GND plane including ANAGND, and the rest is to wide signal trace for V 2.
O
• All sensitive analog components such as INV, REF, CT, GND, FLT and SOFTSTART should be
reference to ANAGND.
• Ideally, all of the area directly under the TPS5110 chip should also be ANAGND.
• ANAGND and DRVGND should be isolated as much as possible, with a single point connection
between them.
TPS5110PW
LH
1
2
INV
FB
24
23
22
OUT_u
V
O1
3
4
5
6
7
8
SOFTSTART
PWM_SEL
CT
LL
OUT_d
21
20
OUTGND
ANAGND
GND
DRVGND
REF
TRIP 19
V
OGND
STBY
VIN_SENSE
18
17
16
15
14
13
VIN
9
STBY_LDO
REG5V_IN
LDO_IN
EX5V
10 FLT
LDO_CUR
11 POWERGOOD
LDO_GATE
LDO_OUT
12 INV_LDO
V
O2
UDG−02069
Figure 18. Four-Layer PCB Diagram
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ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢅ
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
low-side MOSFET(s)
• The source of low-side MOSFET(s) should be referenced to DRVGND, otherwise ANAGND is subject
to the noise of the outputs.
• DRVGND should be connected to the main ground plane close to the source of the low-side FET.
• OUTGND should be placed close to the source of low-side MOSFET(s).
• The Schottky diode anode, the returns for the high-frequency bypass capacitor for the MOSFETs, and
the source of the low-side MOSFET(s) traces should be routed as close together as possible.
TPS5110PW
LH
1
2
INV
FB
24
23
22
OUT_u
V
O1
3
4
5
6
7
8
SOFTSTART
PWM_SEL
CT
LL
OUT_d
21
20
OUTGND
DRVGND
ANAGND
GND
REF
TRIP 19
V
OGND
STBY
VIN_SENSE
18
17
16
15
14
13
VIN
9
STBY_LDO
REG5V_IN
LDO_IN
EX5V
10 FLT
LDO_CUR
11 POWERGOOD
LDO_GATE
LDO_OUT
12 INV_LDO
V
O2
UDG−02070
Figure 19. Low-Side MOSFETs Diagram
24
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ꢀꢁ ꢂ ꢃꢄꢄꢅ
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
connections
• Connections from the drivers to the gate of the power MOSFETs should be as short and wide as
possible to reduce stray inductance. This becomes more critical if external gate resistors are not being
used. In addition, as for the current limit noise issue, use of a gate resistor on the high-side MOSFET(s)
considerably reduce the noise at the LL node, improving the performance of the current limit function.
• The connection from LL to the power MOSFETs should be as short and wide as possible.
TPS5110PW
LH
1
2
INV
FB
24
23
22
OUT_u
V
O1
3
4
5
6
7
8
SOFTSTART
PWM_SEL
CT
LL
OUT_d
21
20
OUTGND
DRVGND
ANAGND
GND
REF
TRIP 19
V
OGND
STBY
VIN_SENSE
18
17
16
15
14
13
VIN
9
STBY_LDO
REG5V_IN
LDO_IN
EX5V
10 FLT
LDO_CUR
11 POWERGOOD
LDO_GATE
LDO_OUT
12 INV_LDO
V
O2
UDG−02071
Figure 20. Connections From the Drivers to the Gate Diagram
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
bypass capacitor
• The bypass capacitor for VIN_SENSE should be placed close to the TPS5110.
• The bulk-storage capacitors across VIN should be placed close to the power MOSFETs.
High-frequency bypass capacitors should be placed in parallel with the bulk capacitors and connected
close to the drain of the high-side MOSFET(s) and to the source of the low-side MOSFET(s).
• For aligning phase between the drain of high-side MOSFET(s) and the TRIP pin, and for noise
reduction, a 0.1-µF capacitor should be placed in parallel with the trip resistor.
TPS5110PW
LH
1
2
INV
FB
24
23
22
OUT_u
V
O1
3
4
5
6
7
8
SOFTSTART
PWM_SEL
CT
LL
OUT_d
21
20
OUTGND
DRVGND
ANAGND
GND
REF
TRIP 19
V
OGND
STBY
VIN_SENSE
18
17
16
15
14
13
VIN
9
STBY_LDO
REG5V_IN
LDO_IN
EX5V
10 FLT
LDO_CUR
11 POWERGOOD
LDO_GATE
LDO_OUT
12 INV_LDO
V
O2
UDG−02072
Figure 21. Bypass Capacitor Diagram
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ꢀꢁ ꢂ ꢃꢄꢄꢅ
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
bootstrap capacitor
• The bootstrap capacitor (connected from LH to LL) should be placed close to the TPS5110.
• LH and LL should be routed close to each other to minimize differential-mode noise coupling to these
traces.
• LH and LL should not be routed near the control pin area (ex. INV, FB, REF, etc.).
TPS5110PW
LH
1
2
INV
FB
24
23
22
OUT_u
V
O1
3
4
5
6
7
8
SOFTSTART
PWM_SEL
CT
LL
OUT_d
21
20
OUTGND
DRVGND
ANAGND
GND
REF
TRIP 19
V
OGND
STBY
VIN_SENSE
18
17
16
15
14
13
VIN
9
STBY_LDO
REG5V_IN
LDO_IN
EX5V
10 FLT
LDO_CUR
11 POWERGOOD
LDO_GATE
LDO_OUT
12 INV_LDO
V
O2
UDG−02073
Figure 22. Bootstrap Capacitor Diagram
27
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ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢅ
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
output voltage
• The output voltage sensing trace should be isolated by either ground plane.
• The output voltage sensing trace should not be placed under the inductors on same layer.
• The feedback components should be isolated from output components, such as, MOSFETs, inductors,
and output capacitors. Otherwise the feedback signal line is susceptible to output noise.
• The resistors for set up output voltage should be referenced to ANAGND.
• The INV trace should be as short as possible.
TPS5110PW
LH
1
2
INV
FB
24
23
22
OUT_u
V
O1
3
4
5
6
7
8
SOFTSTART
PWM_SEL
CT
LL
OUT_d
21
20
OUTGND
DRVGND
ANAGND
GND
REF
TRIP 19
V
OGND
STBY
VIN_SENSE
18
17
16
15
14
13
VIN
9
STBY_LDO
REG5V_IN
LDO_IN
EX5V
10 FLT
LDO_CUR
11 POWERGOOD
LDO_GATE
LDO_OUT
12 INV_LDO
V
O2
UDG−02074
Figure 23. Output Voltage Diagram
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ꢀꢁ ꢂ ꢃꢄꢄꢅ
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
AUTO SKIP MODE EFFICIENCY
PWM MODE EFFICIENCY
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
100
80
100
80
VIN = 8 V
VIN = 20 V
VIN = 12 V
VIN = 8 V
VIN = 12 V
60
60
40
20
40
20
VIN = 20 V
f
= 300 kHz,
OSC
V
1 = 1.8 V
V 1 = 1.8 V
O
O
0
0
0.01
0.1
1
10
0.01
0.1
1
10
Output Current − A
Output Current − A
Figure 24
Figure 25
SBRC OUTPUT LINE REGULATION
LDO OUTPUT LINE REGULATION
1.802
1.801
1.492
1.491
I
1 = 6 A
O
= 1.8 V
LDO_IN
2 = 3 A
VO1 = V
I
O
1.800
1.799
1.798
1.490
1.489
1.488
5
10
15
20
15
5
10
15
Input Voltage − V
−
20
15
Input Voltage − V
−
V
IN
V
IN
Figure 26
Figure 27
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ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢅ
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
SBRC OUTPUT LOAD REGULATION
LDO OUTPUT LOAD REGULATION
1.510
1.505
1.500
1.810
1.805
1.800
V
1 = V
V
= 12 V
= 1.8 V
LDO_IN
O
IN
1.495
1.795
1.490
1.485
1.790
1.785
1.480
1.780
0.0
0.5
1.0
1.5
2.0
0
1
2
3
4
5
6
Output Current − A
Output Current − A
Figure 28
Figure 29
SBRC OUTPUT VOLTAGE RIPPLE
SBRC OUTPUT VOLTAGE RIPPLE
I
= 0 A
OUT
20 mV/div.
I
20 mV/div.
= 0 A
OUT
4 A
4 A
6 A
6 A
VIN = 4.5 V, V 1 = 1.8 V
O
1 = 1.8 V
VIN = 20 V, V
O
t − time − 1 µs/div.
t − time − 1 µs/div.
Figure 30
Figure 31
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ꢀꢁ ꢂ ꢃꢄꢄꢅ
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
LDO OUTPUT VOLTAGE RIPPLE
LDO OUTPUT VOLTAGE RIPPLE
I
= 0 A
OUT
I
= 0 A
OUT
1 A
1 A
3 A
3 A
= 1.8 V, V
2 = 1.5 V
VIN = 20 V, V
LDO_IN
= 1.8 V, V
2 = 1.5 V
VIN = 8 V, V
O
LDO_IN
O
t − time − 1 µs/div.
t − time − 1 µs/div.
Figure 32
Figure 33
SBRC LOAD TRANSIENT RESPONSE
SBRC LOAD TRANSIENT RESPONSE
V
V
OUT
20 mV/div.
OUT
20 mV/div.
I
I
OUT
2 A/div.
OUT
2 A/div.
0 A
0 A
VIN = 20 V, V
1 = 1.8 V
VIN = 8 V, V 1 = 1.8 V
O
O
m
100 s/div.
t − time − 100 µs/div.
t − time − 100 µs/div.
Figure 34
Figure 35
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ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢅ
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
LDO LOAD TRANSIENT RESPONSE
SBRC-LDO SIMULTANEOUS START-UP
V
OUT
V 1(SBRC)
O
V 2(LDO)
O
I
OUT
1 A/div.
0 A
0 V
I
1 = 4 A, I
2 = 3 A
O
O
VIN = 12 V,
= 1.8 V, V
2 = 1.5 V
VLDO_IN
O
t − time − 1 µs/div.
Figure 37
t − time − 100 µs/div.
Figure 36
SBRC GAIN AND PHASE
LDO GAIN AND PHASE
80
60
40
20
0
240
80
60
40
20
0
240
180
120
60
Phase Margin = 81
Degree
Vo2 = 1.5 V, Io2 = 3 A
Phase Margin = 48Degree
Vo1 = 1.8 V, Io1 = 6 A
180
120
60
Phase
Phase
0
Gain
0
Gain
−60
−120
−20
−40
−60
−120
V
IN
= 12 V
1 k
−20
−40
V
= 1.8 V
LDO_IN
100
10 k
100 k
1 M
100
1 k
10 k
100 k
1 M
Frequency − Hz
Frequency − Hz
Figure 38
Figure 39
32
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ꢀꢁ ꢂ ꢃꢄꢄꢅ
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Table 5. Bill of Materials
Reference
C01A
Qty
1
Description
Manufacturer
Part Number
Capacitor
SP−VCAP, 22 µF, 27 V, 8.3x8.3mm
Ceramic, 4700 pF, 10%, 2.0x1.25mm
Ceramic, 47 pF, 5%, 2.0x1.25mm
Ceramic, 0.01 µF, 2.0x1.25mm
SPCAP, 47 µF, 6.3 V, 7.3x4.3mm
Panasonic
EEFWA27220P
C02, C03
C05
2
1
C04, C07
C09
2
1
Panasonic
EEFCD0J470R
C01B, C06, C11,
C12, C13, C19
6
Ceramic, 0.1 µF, 2.0x1.25mm
C15
1
2
1
2.2 µF, 35 V, 3.2x2.5mm
SPCAP, 150 µF, 2.5 V, 7.4x4.3mm
Ceramic, 10 µF, 25 V
Taiyo-Yuden
Panasonic
GMK325BJ225MN−B
EEFUD0E151R
C16, C17
C24
Taiyo-Yuden
TMK325BJ106MM
C01C, C08, C10,
C14, C25, C26
Removed
Resistor
R01A, R01B, R09
1
1
1
1
2
1
1
2
1
1
10 kΩ, 1%, 2.0x1.25mm
1.2 kΩ, 2.0x1.25mm
18 kΩ, 1%, 2.0x1.25mm
4.7 kΩ, 2.0x1.25mm
100 kΩ, 2.0x1.25mm
6.8 kΩ, 1%, 2.0x1.25mm
820 Ω, 1%, 2.0x1.25mm
22 m, 5%, 2.0x1.25mm
10 kΩ, 2.0x1.25mm
R02
R03
R04
R05, R08
R10
R11
R12A, R12B
Susumu
RL1220T−R022−J
R13
R14
10 Ω, 2.0x1.25mm
R12C, R15A, R15B,
R15C, R16, R22, R24
Removed
Inductor
Diode
L01
1
1
2.8 µH, 12.5X12.5mm
2.5x1.25mm
Removed
Sumida
Hitachi
CEP125−2R8MC−H
HSU119
D01
D02
D03
1
1
1
1
2.6x4.5mm
Rohm
RB160L−40
FDS6612A
FDS6690S*
FD6612A
Nch MOSFET
Q01B
Q02B
Q03A
30 V, SOT−8
30 V, SOT−8
30 V, SOT−8
Fairchild
Q01A, Q02A,
Q03B, Q04
Removed
33
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ꢀ ꢁ ꢂ ꢃ ꢄꢄ ꢅ
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Bill of Materials (continued)
IC
IC01
IC02
1
SSOP−24
TI
TPS5110PW
Removed
Jumper
Header, straight, 2-pin
Jumper, shunt
SW, 7x4.5mm
Header, straight, 3-pin
Jumper, shunt
22−28−4023
15−29−1025
G−12AP
JP01
1
2
Morex
Nikkai
JP02, JP03
22−28−4033
15−29−1025
JP04
1
Morex
Contact
EX5V, EXGND
VIN, VINGND
4
3
MKDS1.5/2−5.08
MKDS1.5/3−5.08
Phoenix
VO1, VO2, VOGND
NOTE: Since the FDS6690S (Q02B) includes an integrated Schottky diode, D02 can be removed.
test setup
+
A
VIN
Power
V
Supply
VINGND
−
+
A
VO1
SBRC
Load
V
−
−
TPS5110
VOGND
EVM
LDO
Load
V
VO2
+
−
A
EXGND
5 V
Power
Supply
V
EX5V
+
Figure 40. Schematic Diagram of the Test Setup
34
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Figure 41. EVM Board Top Layer
35
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Figure 42. EVM Board Second Layer
36
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Figure 43. EVM Board Third Layer
37
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Figure 44. EVM Board Bottom Layer
38
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ꢀꢁ ꢂ ꢃꢄꢄꢅ
SLVS025B − APRIL 2002 − REVISED JULY 2004
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°−ā8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
39
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPS5110PW
TPS5110PWR
TPS5110PWRG4
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
PW
24
24
24
60
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
PW
2000
PREVIEW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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