TPS51200DRCT [TI]
SINK/SOURCE DDR TERMINATION REGULATOR; 漏/源DDR终端稳压器
| 型号： | TPS51200DRCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINK/SOURCE DDR TERMINATION REGULATOR |
| 文件： | 总35页 (文件大小：1260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51200
www.ti.com
SLUS812–FEBRUARY 2008
SINK/SOURCE DDR TERMINATION REGULATOR
1
FEATURES
APPLICATIONS
•
Memory Termination Regulator for DDR,
DDR2, DDR3, and Low Power DDR3/DDR4
2
•
Input Voltage: Supports 2.5-V Rail and 3.3-V
Rail
•
•
Notebook/Desktop/Server
Telecom/Datacom, GSM Base Station,
LCD-TV/PDP-TV, Copier/Printer, Set-Top Box
•
•
VLDOIN Voltage Range: 1.1 V to 3.5 V
Sink/Source Termination Regulator Includes
Droop Compensation
•
Requires Minimum Output Capacitance of
20-µF (typically 3 × 10-µF MLCCs) for Memory
Termination Applications (DDR)
DESCRIPTION
The TPS51200 is a sink/source Double Data Rate
(DDR) termination regulator specifically designed for
low input voltage, low-cost, low-noise systems where
space is a key consideration.
•
•
•
PGOOD to Monitor Output Regulation
EN Input
REFIN Input Allows for Flexible Input Tracking
Either Directly or Through Resistor Divider
The TPS51200 maintains a fast transient response
and only requires a minimum output capacitance of
20 µF. The TPS51200 supports a remote sensing
function and all power requirements for DDR, DDR2,
DDR3, and Low Power DDR3/DDR4 VTT bus
termination.
•
•
•
•
•
Remote Sensing (VOSNS)
±10-mA Buffered Reference (REFOUT)
Built-in Soft Start, UVLO and OCL
Thermal Shutdown
In addition, the TPS51200 provides an open-drain
PGOOD signal to monitor the output regulation and
an EN signal that can be used to discharge VTT
during S3 (suspend to RAM) for DDR applications.
Meets DDR, DDR2 JEDEC Specifications;
Supports DDR3 and Low-Power DDR3/DDR4
VTT Applications
•
SON-10 PowerPAD™Package
The TPS51200 is available in the thermally-efficient
SON-10 PowerPAD package, and is rated both
Green and Pb-free. It is specified from -40°C to
+85°C.
STANDARD DDR APPLICATION
TPS51200
REFIN
VDDQ
1
VIN 10
3.3 VIN
VLDOIN
VTT
2
3
4
5
VLDOIN PGOOD
9
8
7
6
PGOOD
VO
GND
EN
PGND
SLP_S3
VTTREF
VOSNS REFOUT
0.1 mF
UDG-08025
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS51200
www.ti.com
SLUS812–FEBRUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PACKAGE
DEVICE NUMBER
PINS
MEDIUM
MINIMUM
QUANTITY
TPS51200DRCT
TPS51200DRCR
250
–40°C to 85°C
DRC Plastic Small Outline
10
Tape and Reel
3000
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
UNIT
VIN, VLDOIN, VOSNS, REFIN
–0.3 to 3.6
–0.3 to 6.5
–0.3 to 0.3
–0.3 to 3.6
–0.3 to 6.5
–55 to 150
Input voltage range(2)
EN
V
PGND to GND
VO, REFOUT
PGOOD
Output voltage range(2)
Storage temperature
V
Tstg
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
DISSIPATION RATINGS TABLE(1)
DERATING FACTOR
TA = 85°C
TA = 25°C
PACKAGE
POWER RATING
ABOVE TA = 25°C
POWER RATING
10-Pin SON
1.92 W
19 mW/°C
0.79 W
(1) PowerPAD size: 3.0 × 1.9 mm, 4 standard thermal vias. Based on the above environment, junction to thermal pad resistance θJP is
10.24°C/W. Junction to ambient thermal resistance θJA is 52.06°C/W.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
2.375
–0.1
0.5
TYP
MAX
3.500
3.5
UNIT
V
Supply voltages
VIN
EN, VLDOIN, VOSNS
REFIN
1.8
Voltage range
VO, PGOOD
REFOUT
–0.1
–0.1
–0.1
–40
3.5
1.8
PGND
0.1
Operating free-air temperature, TA
85
°C
2
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SLUS812–FEBRUARY 2008
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, VVIN = 3.3 V,VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT
= 3 × 10 µF and circuit shown in Section 1. (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIN
Supply current
TA = 25 °C, VEN = 3.3 V, No Load
0.7
65
1
80
mA
TA = 25 °C, VEN = 0 V, VREFIN = 0, No Load
TA = 25 °C, VEN = 0 V, VREFIN > 0.4 V, No Load
TA = 25 °C, VEN = 3.3 V, No Load
IIN(SDN)
Shutdown current
µA
200
1
400
50
ILDOIN
Supply current ofVLDOIN
µA
µA
ILDOIN(SDN)
INPUT CURRENT
IREFIN
Shutdown current of VLDOIN
TA = 25 °C, VEN = 0 V, No Load
0.1
50
Input current, REFIN
VEN = 3.3 V
1
µA
VO OUTPUT
1.25
0.9
V
mV
V
VREFOUT = 1.25 V (DDR1), IO = 0 A
VREFOUT = 0.9 V (DDR2), IO = 0 A
–15
–15
15
15
VVOSNS
Output DC voltage, VO
mV
V
0.75
VLDOIN = 1.5 V, VREFOUT = 0.75 V (DDR3), IO = 0 A
–2A < IVO < 2A
–15
–25
15
25
mV
Output voltage tolerance to
REFOUT
VVOTOL
mV
IVOSRCL
IVOSNCL
IDSCHRG
VO source vurrent Limit
VO sink current Limit
Discharge current, VO
With reference to REFOUT, VOSNS = 90% × VREFOUT
With reference to REFOUT, VOSNS = 110% × VREFOUT
VREFIN = 0 V, VVO = 0.3 V, VEN = 0 V, TA = 25°C
3
4.5
5.5
25
A
A
Ω
3.5
18
POWERGOOD COMPARATOR
PGOOD window lower threshold with respect to REFOUT
PGOOD window upper threshold with respect to REFOUT
PGOOD hysteresis
–23.5%
17.5%
–20%
20%
5%
–17.5%
23.5%
VTH(PG)
VO PGOOD threshold
TPGSTUPDLY
VPGOODLOW
TPBADDLY
PGOOD startup delay
Output low voltage
PGOOD bad delay
Startup rising edge, VOSNS within 15% of REFOUT
ISINK = 4 mA
2
ms
V
0.4
1
VOSNS is outside of the ±20% PGOOD window
10
µs
VOSNS = VREFIN (PGOOD high impedance),
PGOOD = VIN + 0.2 V
IPGOODLK
Leakage current(1)
µA
REFIN AND REFOUT
VREFIN
REFIN voltage range
0.5
1.8
V
VREFINUVLO
REFIN undervoltage lockout
REFIN rising
360
390
20
420
mV
REFIN undervoltage lockout
hysteresis
VREFINUVHYS
VREFOUT
mV
V
REFOUT voltage
REFIN
–10 mA < IREFOUT < 10 mA, VREFIN = 1.25 V
–10 mA < IREFOUT < 10 mA, VVREFIN = 0.9 V
–10 mA < IREFOUT < 10 mA, VREFIN = 0.75V
–10 mA < IREFOUT < 10 mA, VREFIN = 0.6 V
VREFOUT = 0 V
–15
–15
–15
–15
10
15
15
15
15
mV
REFOUT voltage tolerance to
VREFIN
VREFOUTTOL
IREFOUTSRCL
IREFOUTSNCL
REFOUT source current limit
REFOUT sink current limit
40
40
mA
mA
VREFOUT = 0 V
10
(1) Ensured by design. Not production tested.
Copyright © 2008, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended free-air temperature range, VVIN = 3.3 V,VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT
= 3 × 10 µF and circuit shown in Section 1. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.2
TYP
MAX
UNIT
UVLO / EN LOGIC THRESHOLD
Wake up, TA = 25°C
Hysteresis
Enable
2.3
50
2.375
V
VVINUVVIN
UVLO threshold
mV
VENIH
High-level input voltage
Low-level input voltage
Hysteresis voltage
1.7
VENIL
Enable
0.3
1
V
VENYST
IENLEAK
Enable
0.5
Logic input leakage current
EN, TA = 25°C
–1
µA
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
150
25
TSON
Thermal shutdown threshold(2)
°C
(2) Ensured by design. Not production tested.
4
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SLUS812–FEBRUARY 2008
DEVICE INFORMATION
DRC PACKAGE
TPS51200
(Bottom View)
VOSNS
PGND
VO
5
4
3
2
1
6
7
8
9
REFOUT
EN
GND
VLDOIN
REFIN
PGOOD
10 VIN
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
EN
7
I
For DDR VTT application, connect EN to SLP_S3. For any other application(s), use EN as the ON/OFF
function.
GND
8
4
–
–
O
I
Ground.Signal ground. Connect to negative terminal of the output capacitor.
Power ground output for the LDO
PGND
PGOOD
REFIN
REFOUT
VIN
9
PGOOD output. Indicates regulation.
1
Reference input
6
O
I
Reference output. Connect to GND through 0.1-µF ceramic capacitor.
10
2.5-V or 3.3-V power supply A ceramic decoupling capacitor with a value between 1-µF and 4.7-µF is
required.
VLDOIN
VO
2
3
5
I
O
I
Supply voltage for the LDO
Power output for the LDO
VOSNS
Voltage sense output for the LDO. Connect to positive terminal of the output capacitor or the load.
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SLUS812–FEBRUARY 2008
FUNCTIONAL BLOCK DIAGRAM
2
6
VLDOIN
REFIN
1
+
REFOUT
2.3 V
UVLO
+
VIN 10
Gm
DchgREF
DchgVTT
VOSNS
5
3
VO
+
ENVTT
EN
7
8
Gm
4
9
PGND
REFINOK
GND
PGOOD
+
+
Startup
Delay
UDG-08019
6
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SLUS812–FEBRUARY 2008
DETAILED DESCRIPTION
VO SINK/SOURCE REGULATOR
The TPS51200 is a sink/source tracking termination regulator specifically designed for low input voltage,
low-cost, and low external component count systems where space is a key application parameter. The
TPS51200 integrates a high-performance, low-dropout (LDO) linear regulator that is capable of both sourcing
and sinking current. The LDO regulator employs a fast feedback loop so that small ceramic capacitors can be
used to support the fast load transient response. To achieve tight regulation with minimum effect of trace
resistance, a remote sensing terminal, VOSNS, should be connected to the positive terminal of the output
capacitor(s) as a separate trace from the high current path from VO.
REFERENCE INPUT (REFIN)
The output voltage, VO, is regulated to REFOUT. When REFIN is configured for standard DDR termination
applications, REFIN can be set by an external equivalent ratio voltage divider connected to the memory supply
bus (VDDQ). The TPS51200 supports REFIN voltage from 0.5 V to 1.8 V, making it versatile and ideal for many
types of low-power LDO applications.
REFERENCE OUTPUT (REFOUT)
When it is configured for DDR termination applications, REFOUT generates the DDR VTT reference voltage for
the memory application. It is capable of supporting both a sourcing and sinking load of 10 mA. REFOUT
becomes active when REFIN voltage rises to 0.390 V and VIN is above the UVLO threshold. When REFOUT is
less than 0.375 V, it is disabled and subsequently discharges to GND through an internal 10-kΩ MOSFET.
REFOUT is independent of the EN pin state.
SOFT-START
The soft-start function of the VO pin is achieved via a current clamp. The current clamp allows the output
capacitors to be charged with low and constant current, providing a linear ramp-up of the output voltage. When
VO is outside of the powergood window, the current clamp level is one-half of the full overcurrent limit (OCL)
level. When VO rises or falls within the PGOOD window, the current clamp level switches to the full OCL level.
The soft-start function is completely symmetrical; it works not only from GND to the REFOUT voltage, but also
from VLDOIN to the REFOUT voltage.
EN CONTROL (EN)
When EN is driven high, the TPS51200 VO regulator begins normal operation. When EN is driven low, VO is
discharges to GND through an internal 18-Ω MOSFET. REFOUT remains on when EN is driven low.
POWERGOOD FUNCTION (PGOOD)
The TPS51200 provides an open-drain PGOOD output that goes high when the VO output is within ±20% of
REFOUT. PGOOD de-asserts within 10 µs after the output exceeds the size of the powergood window. During
initial VO startup, PGOOD asserts high 2 ms (typ) after the VO enters power good window. Because PGOOD is
an open-drain output, a 100-kΩ, pull-up resistor between PGOOD and a stable active supply voltage rail is
required.
VO CURRENT PROTECTION
The LDO has a constant overcurrent limit (OCL). Note that the OCL level reduces by one-half when the output
voltage is not within the powergood window. This reduction is a non-latch protection.
VIN UVLO PROTECTION
For VIN undervoltage lockout (UVLO) protection, the TPS51200 monitors VIN voltage. When the VIN voltage is
lower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown is
a non-latch protection.
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SLUS812–FEBRUARY 2008
THERMAL SHUTDOWN
The TPS51200 monitors the its junction temperature. If the device junction temperature exceeds its threshold
value, (typically 150°C), the VO and REFOUT regulators are both shut off, discharged by the internal discharge
MOSFETs. This shutdown is a non-latch protection.
8
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APPLICATION INFORMATION
VIN CAPACITOR
Add a ceramic capacitor, with a value between 1.0-µF and 4.7-µF, placed close to the VIN pin, to stabilize the
bias supply (2.5- V rail or 3.3- V rail) from any parasitic impedance from the supply.
VLDO INPUT CAPACITOR
Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase of
source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-µF (or greater)
ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is
used at VO. In general, use one-half of the COUT value for input.
OUTPUT CAPACITOR
For stable operation, the total capacitance of the VO output terminal must be greater than 20 µF. Attach three,
10-µF ceramic capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent
series inductance (ESL). If the ESR is greater than 2 mΩ, insert an R-C filter between the output and the VOSNS
input to achieve loop stability. The R-C filter time constant should be almost the same as or slightly lower than
the time constant of the output capacitor and its ESR.
Low VIN Applications
TPS51200 can be used in an application system where either a 2.5-V rail or a 3.3-V rail is available. If only a 5-V
rail is available, TPS51100 can be used instead. The TPS51200 minimum input voltage requirement is 2.375 V.
If a 2.5-V rail is used, ensure that the absolute minimum voltage (both DC and transient) at the device pin is be
2.375 V or greater. The voltage tolerance for a 2.5-V rail input is between –5% and 5% accuracy, or better.
S3 and Pseudo-S5 Support
The TPS51200 provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal in
the end application. Both REFOUT and VO are on when EN = high (S0 state). REFOUT is maintained while VO
is turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). When EN = low and
the REFIN voltage is less than 0.390 V, TPS51200 enters pseudo-S5 state. Both VO and REFOUT outputs are
turned off and discharged to GND through internal MOSFETs when pseudo-S5 support is engaged (S4/S5
state). Figure 1 shows a typical startup and shutdown timing diagram for an application that uses S3 and
pseudo-S5 support.
Tracking Startup and Shutdown
The TPS51200 also supports tracking startup and shutdown when EN is tied directly to the system bus and not
used to turn on or turn off the device. During tracking startup, VO follows REFOUT once REFIN voltage is
greater than 0.39 V. REFIN follows the rise of VDDQ rail via a voltage divider. The typical soft-start time for the
VDDQ rail is approximately 3 ms, however it may vary depending on the system configuration. The SS time of
the VO output no longer depends on the OCL setting, but it is a function of the SS time of the VDDQ rail.
PGOOD is asserted 2 ms after VO is within ±20% of REFOUT. During tracking shutdown, VO falls following
REFOUT until REFOUT reaches 0.37 V. Once REFOUT falls below 0.37 V, the internal discharge MOSFETs are
turned on and quickly discharge both REFOUT and VO to GND. PGOOD is deasserted once VO is beyond the
±20% range of REFOUT. Figure 2 shows the typical timing diagram for an application that uses tracking startup
and shutdown.
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SLUS812–FEBRUARY 2008
3.3VIN
V
= 1.5 V
0.390 V
VDDQ
0.370 V
VLDOIN
REFIN
REFOUT
(VTTREF)
EN
(S3_SLP)
V
= 0.75 V
Tss
VO
VO
C
x V
O
O
T
=
SS
I
OOCL
PGOOD
2 ms
UDG-08021
Figure 1. Typical Timing Diagram for S3 and pseudo-S5 Support
3.3VIN
EN
VLDOIN
REFIN
REFOUT
(VTTREF)
t
determined
SS
by the SS time
of VLDOIN
V
= 0.75 V
VO
VO
PGOOD
UDG-08020
2ms
Figure 2. Typical Timing Diagram of Tracking Startup and Shutdown
10
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Output Tolerance Consideration for VTT DIMM Applications
The TPS51200 is specifically designed to power up the memory termination rail (as shown in Figure 3). The DDR
memory termination structure determines the main characteristics of the VTT rail, which is to be able to sink and
source current while maintaining acceptable VTT tolerance. See Figure 4 for typical characteristics for a single
memory cell.
DDR3 240 Pin Socket
VO
TPS51200
10 mF
10 mF
10 mF
UDG-08022
Figure 3. Typical Application Diagram for DDR3 VTT DIMM using TPS51200
V
V
TT
DDQ
Q1
Q2
25 W
R
S
20 W
Receiver
Ouput
Buffer
(Driver)
V
V
IN
OUT
V
SS
UDG-08023
Figure 4. DDR Physical Signal System Bi-Directional SSTL Signaling
In Figure 4, when Q1 is on and Q2 is off:
•
•
Current flows from VDDQ via the termination resistor to VTT
VTT sinks current
In Figure 4, when Q2 is on and Q1 is off:
•
•
Current flows from VTT via the termination resistor to GND
VTT sources current
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Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the
tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR
JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003).
VTTREF – 40 mV < VTT < VTTREF + 40 mV, for both dc and ac conditions
The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning.
The TPS51200 ensures the regulator output voltage to be:
VTTREF –25 mV < VTT < VTTREF + 25mV, for both DC and AC conditions and –2 A < IVTT < 2 A
The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to
DDR, DDR2, DDR3 and Low Power DDR3/DDR4 applications (see Table 1 for detailed information). To meet the
stability requirement, a minimum output capacitance of 20 µF is needed. Considering the actual tolerance on the
MLCC capacitors, three 10-µF ceramic capacitors are sufficient to meet the above requirement.
Table 1. DDR, DDR2, DDR3 and LP DDR3 Termination Technology and Their Differences
Low Power
DDR
DDR2
DR3
DDR3
FSB Data Rates
Termination
200, 266, 333 and 400 MHz 400, 533, 677 and 800 MHz
800, 1066, 1330 and 1600 MHz
Same as DDR3
On-die termination for data group. On-die termination for data group.
VTT termination for address,
command and control signals
Motherboard termination to
VTT for all signals
VTT termination for address,
command and control signals
Same as DDR3
Same as DDR3
Not as demanding
Not as demanding
Only 34 signals (address,
command, control) tied to
VTT
Only 34 signals (address,
command, control) tied to
VTT
Max source/sink transient
currents of up to 2.6A to
2.9A
•
•
Termination
Current Demand
•
ODT handles data signals
•
ODT handles data signals
Less than 1A of burst current
Less than 1A of burst current
2.5V Core and I/O 1.25V
VTT
1.2V Core and
I/O 0.6V VTT
Voltage Level
1.8V Core and I/O 0.9V VTT
1.5V Core and I/O 0.75V VTT
The TPS51200 is designed as a Gm driven LDO. The voltage droop between the reference input and the output
regulator is determined by the transconductance and output current of the device. The typical Gm is 250 S at 2 A
and changes with respect to the load in order to conserve the quiescent current (that is, the Gm is very low at no
load condition). The Gm LDO regulator is a single pole system. Its unity gain bandwidth for the voltage loop is
only determined by the output capacitance, as a result of the bandwidth nature of the Gm (see Equation 1) .
Gm
F
=
UGBW
2´ p´ C
OUT
(1)
where
•
•
•
FUGBW is the unity gain bandwidth
Gm is transconductance
COUT is the output capacitance
There are two limitations to this type of regulator when it comes to the output bulk capacitor requirement. In order
to maintain stablility, the zero location contributed by the ESR of the output capacitors should be greater than the
-3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in the
design. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order to
prevent the gain peaking effect around the Gm –3-dB point because of the large ESL, the output capacitor and
parasitic inductance of the VO trace.
12
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Figure 5. Bode Plot for a Typical DDR3 Configuration
Figure 5 shows the bode plot simulation for a typical DDR3 configuration of the TPS51200, where:
•
•
•
•
•
•
•
VIN = 3.3 V
VVLDOIN = 1.5 V
VVO = 0.75 V
IIO = 2 A
3 × 10-µF capacitors included
ESR = 2.5 mΩ
ESL = 800 pH
The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52°. The 0-dB level is crossed, the
gain peaks because of the ESL effect. However, the peaking is kept well below 0 dB.
Figure 6 shows the load regulation and Figure 7 shows the transient response for a typical DDR3 configuration.
When the regulator is subjected to ±1.5-A load step and release, the output voltage measurement shows no
difference between the dc and ac conditions.
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OUTPUT VOLTAGE
vs
OUTPUT CURRENT
790
V
= 3.3 V
IN
0°C
780
770
760
750
740
730
25°C
-40°C
DDR3
-40°C
0°C
720
710
700
85°C
25°C
85°C
-3
-2
-1
0
1
– Output Current – A
2
3
I
OUT
Figure 6. DC Regulaltion
Figure 7. Transient
LDO Design Guidelines
The minimum input to output voltage difference (headroom) decides the lowest usable supply voltage Gm-driven
to drive a certain load. For TPS51200, a minimum of 300 mV (VLDOINMIIN – VOMAX) is needed in order to
support a Gm driven sourcing current of 2 A based on a design of VIN = 3.3 V and COUT = 3 × 10µF. Because the
TPS51200 is essentially a Gm driven LDO, its impedance characteristics are both a function of the 1/Gm and
RDS(on) of the sourcing MOSFET (see Figure 8). The current inflection point of the design is between 2 A and 3 A.
When ISRC is less than the inflection point, the LDO is considered to be operating in the Gm region; when ISRC is
greater than the inflection point but less than the overcurrent limit point, the LDO is operating in the RDS(on)
region. The maximum sourcing RDS(on) is 0.144 Ω with VIN = 3.0 V and TJ = 125°C.
14
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1/Gm
Inflection
Point
1/R
DS(on)
(between
2 A and 3 A)
Overcurrent
Limit
I
- Source Current - A
SRC
UDG-08026
Figure 8. TPS51200 Impedance Characteristics
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SLUS812–FEBRUARY 2008
THERMAL DESIGN
Because the TPS51200 is a linear regulator, the VO current flows in both source and sink directions, thereby
dissipating power from the device. When the device is sourcing current, the voltage difference between VLDOIN
and VO times IO (IIO) current becomes the power dissipation as shown in Equation 2.
P
=
V
(
- V
x I
)
O _SRC
DISS _SRC
VLDOIN
VO
(2)
In this case, if VLDOIN is connected to an alternative power supply lower than the VDDQ voltage, overall power
loss can be reduced. For the sink phase, VO voltage is applied across the internal LDO regulator, and the power
dissipation, PDISS_SNK can be calculated by Equation 3.
P
= V ´ I
VO O _SNK
DISS _SNK
(3)
Because the device does not sink and source current at the same time and the IO current may vary rapidly with
time, the actual power dissipation should be the time average of the above dissipations over the thermal
relaxation duration of the system. Another source of power consumption is the current used for the internal
current control circuitry from the VIN supply and the VLDOIN supply. This can be estimated as 5 mW or less
during normal operatiing conditions. This power must be effectively dissipated from the package.
Maximum power dissipation allowed by the package is calculated by Equation 4.
PPKG = [TJ(MAX) – TA(MAX)]/ θJA
T
J(max) ´ TA(max)
(
=
)
PPKG
qJA
(4)
where
•
•
•
TJ(MAX) is +125°C
TA(MAX) is the maximum ambient temperature in the system
θJA is the thermal resistance from junction to ambient
The thermal performance of an LDO is greatly depends on the printed circuit board (PCB) layout. The TPS51200
is housed in a thermally-enhanced PowerPAD™ package that has an exposed die pad underneath the body. For
improved thermal performance, this die pad must be attached to ground via thermal land on the PCB. This
ground trace acts as a both a heatsink and heatspreader. The typical thermal resistance, θJA, 52.06°C/W, is
achieved based on a land pattern of 3 mm × 1.9 mm with four vias (0.33-mm via diameter, the standard thermal
via size) without air flow (see Figure 9).
Land Pad
3 mm x 1.9 mm
Exposed Thermal
Die Pad,
2.48 mm x 1.74 mm
UDG-08018
Figure 9. Recommend Land Pad Pattern for TPS51200
To further improve the thermal performance of this device, using a larger than recommended thermal land as
well as increasing the number of vias helps lower the thermal resistance from junction to thermal pad. The typical
thermal resistance from junction to thermal pad, θJP, is 10.24°C/W (based on the recommend land pad and four
standard thermal vias).
16
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SLUS812–FEBRUARY 2008
For further information regarding the PowerPAD™ package and the recommended board layout, refer to the
PowerPAD™ package application note (SLMA002). This document is available at www.ti.com.
LAYOUT CONSIDERATIONS
Consider the following points before starting the TPS51200 layout design.
•
•
•
The input bypass capacitor for VLDOIN should be placed as close as possible to the pin with short and wide
connections.
The output capacitor for VO should be placed close to the pin with short and wide connection in order to
avoid additional ESR and/or ESL trace inductance.
VOSNS should be connected to the positive node of VO output capacitor(s) as a separate trace from the high
current power line. This configuration is strongly recommended to avoid additional ESR and/or ESL. If
sensing the voltage at the point of the load is required, it is recommended to attach the output capacitor(s) at
that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between the
GND pin and the output capacitor(s).
•
•
Consider adding low-pass filter at VOSNS if the ESR of the VO output capacitor(s) is larger than 2 mΩ.
REFIN can be connected separately from VLDOIN. Remember that this sensing potential is the reference
voltage of REFOUT. Avoid any noise-generating lines.
•
•
The negative node of the VO output capacitor(s) and the REFOUT capacitor should be tied together by
avoiding common impedance to the high current path of the VO source/sink current.
The GND and PGND pins should be connected to the thermal land underneath the die pad with multiple vias
connecting to the internal system ground planes (for better result, use at least two internal ground planes).
Use as many vias as possible to reduce the impedance between PGND/GND and the system ground plane.
Also, place bulk caps close to the DIMM load point, route the VOSNS to the DIMM load sense point.
•
•
In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly
to the package’s thermal pad. The wide traces of the component and the side copper connected to the
thermal land pad help to dissipate heat. Numerous vias 0,33 mm in diameter connected from the thermal land
to the internal/solder side ground plane(s) should also be used to help dissipation.
Please consult the TPS51200-EVM User's Guide (SLUUxxx) for detailed layout recommendations.
Copyright © 2008, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS
For Figure 10 through Figure 24, 3 × 10-µF MLCCs (0805) are used on the output.
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.30
940
V
= 3.3 V
V
= 3.3 V
IN
IN
25°C
25°C
930
920
1.28
1.26
910
900
-40°C
1.24
0°C
-40°C
0°C
1.22
890
880
DDR2
DDR
-40°C
0°C
25°C
85°C
-40°C
0°C
25°C
85°C
1.20
1.18
85°C
85°C
1
870
-3
-2
-1
0
1
– Output Current – A
2
3
-3
-2
-1
0
2
3
I
I
– Output Current – A
OUT
OUT
Figure 10.
Figure 11.
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
790
780
770
760
750
740
730
670
650
630
610
85°C
V
= 3.3 V
V
= 3.3 V
IN
IN
0°C
25°C
25°C
-40°C
0°C
-40°C
590
DDR3
DDR3
720
710
700
-40°C
0°C
25°C
85°C
-40°C
0°C
25°C
85°C
85°C
570
550
-3
-2
-1
0
1
– Output Current – A
2
3
-3
-2
-1
0
1
– Output Current – A
2
3
I
I
OUT
OUT
Figure 12.
Figure 13.
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SLUS812–FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)
For Figure 10 through Figure 24, 3 × 10-µF MLCCs (0805) are used on the output.
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
1.00
0.95
0.90
0.85
V
= 2.5 V
V
= 2.5 V
-40°C
IN
IN
25°C
0.80
85°C
DDR2
-40°C
0°C
25°C
&
0°C
DDR
-40°C
0°C
25°C
85°C
85°C
-40°C
0.75
0.70
0°C
25°C
85°C
0.90
-3
-2
-1
0
– Output Current – A
1
2
3
-3
-2
-1
0
1
2
3
I
I
– Output Current – A
OUT
OUT
Figure 14.
Figure 15.
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
800
750
700
650
750
700
650
V
= 2.5 V
V
= 2.5 V
IN
IN
85°C
85°C
-40°C
0°C
25°C
600
550
-40°C
25°C
LP DDR3
DDR3
-40°C
0°C
-40°C
0°C
25°C
85°C
0°C
25°C
85°C
500
-3
-2
-1
0
– Output Current – A
1
2
3
-3
-2
-1
0
1
2
3
I
I
– Output Current – A
OUT
OUT
Figure 16.
Figure 17.
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SLUS812–FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)
For Figure 10 through Figure 24, 3 × 10-µF MLCCs (0805) are used on the output.
REFOUT VOLTAGE
vs
REFOUT CURRENT
REFOUT VOLTAGE
vs
REFOUT CURRENT
1.255
1.254
1.253
1.252
1.251
1.250
1.249
1.248
1.247
905
904
903
902
901
900
899
898
897
25°C
25°C
-40°C
-40°C
DDR
LP DDR3
-40°C
25°C
85°C
-40°C
25°C
85°C
85°C
85°C
-15
-10
-5
0
– Output Current – mA
5
10
15
-15
-10
I
-5
0
5
10
15
I
– Output Current – mA
REFOUT
REFOUT
Figure 18.
Figure 19.
REFOUT VOLTAGE
vs
REFOUT CURRENT
REFOUT VOLTAGE
vs
REFOUT CURRENT
605
604
603
602
601
600
599
598
598
755
754
753
752
751
750
749
748
747
25°C
25°C
-40°C
DDR3
-40°C
LP DDR3
-40°C
25°C
85°C
-40°C
25°C
85°C
85°C
85°C
-15
-10
I
-5
0
5
– Output Current – mA
10
15
-15
-10
-5
0
– Output Current – mA
5
REFOUT
I
REFOUT
Figure 20.
Figure 21.
20
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TYPICAL CHARACTERISTICS (continued)
For Figure 10 through Figure 24, 3 × 10-µF MLCCs (0805) are used on the output.
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
GAIN AND PHASE
vs
FREQUENCY
70
60
200
150
100
1.8
1.6
1.4
1.2
1.0
0.8
0.6
1.25 V
0.90 V
Phase
50
40
0.6 V
50
30
20
10
0
Gain
0.75 V
(V)
-50
-100
-150
-200
0
-10
V
DDR2
Gain
Phase
OUT
0.4
0.2
0
0.60
0.75
0.90
1.25
-20
-30
1 k
10 k
100 k
f – Frequency - Hz
1 M
10 M
0
0.5
1.0
1.5
2.0
2.5
– Output Current – A
3.0
3.5
I
OUT
Figure 22.
Figure 23.
GAIN AND PHASE
vs
FREQUENCY
60
50
40
200
150
100
Phase
30
20
50
0
10
0
Gain
-50
-100
-150
-10
DDR3
Gain
Phase
-20
-30
-200
1 k
10 k
100 k
f – Frequency - Hz
1 M
10 M
Figure 24.
Copyright © 2008, Texas Instruments Incorporated
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SLUS812–FEBRUARY 2008
DESIGN EXAMPLES
Design Example 1
This design example describes a 3.3-VIN, DDR2 Configuration
R1
10 kW
TPS51200
REFIN
1
2
VIN 10
3.3 VIN
V
= V
V
= 1.8 V
= 1.8 V
VDDQ
R2
10 kW
C4
1000 pF
R3
100 kW
C6
4.7 mF
VLDOIN PGOOD
9
PGOOD
V
VLDOIN
VDDQ
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
= 0.9 V
VTT
C1
C2
C3
10 mF 10 mF 10 mF
PGND
SLP_S3
VTTREF
VOSNS REFOUT
C5
0.1 mF
UDG-08028
Figure 25. 3.3-VIN, DDR2 Configuration
Design Example 1 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
10 kΩ
R3
100 kΩ
C1, C2, C3
C4
10 µF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 µF
C6
4.7 µF, 6.3 V
10 µF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
22
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Design Example 2
This design example describes a 3.3-VIN, DDR3 Configuration
R1
10 kW
TPS51200
REFIN
1
2
VIN 10
3.3 VIN
V
= V
V
= 1.5 V
= 1.5 V
VDDQ
R2
10 kW
C4
1000 pF
R3
100 kW
C6
4.7 mF
VLDOIN PGOOD
9
PGOOD
V
VLDOIN
VDDQ
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
= 0.75 V
VTT
C1
C2
C3
10 mF 10 mF 10 mF
PGND
SLP_S3
VTTREF
VOSNS REFOUT
C5
0.1 mF
UDG-08029
Figure 26. 3.3-VIN, DDR3 Configuration
Design Example 2 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
R3
10 kΩ
100 kΩ
C1, C2, C3
C4
10 µF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 µF
C6
4.7 µF, 6.3 V
10 µF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
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Design Example 3
This design example describes a 2.5-VIN, DDR3 Configuration
R1
10 kW
TPS51200
REFIN
1
2
VIN 10
2.5 VIN
V
= V
V
= 1.5 V
= 1.5 V
VDDQ
VDDQ
R2
10 kW
C4
1000 pF
R3
100 kW
C6
4.7 mF
VLDOIN PGOOD
9
PGOOD
V
VLDOIN
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
= 0.75 V
VTT
C1
C2
C3
10 mF 10 mF 10 mF
PGND
SLP_S3
VTTREF
VOSNS REFOUT
C5
0.1 mF
UDG-08030
Figure 27. 2.5-VIN, DDR3 Configuration
Design Example 3 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
R3
10 kΩ
100 kΩ
C1, C2, C3
C4
10 µF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 µF
C6
4.7 µF, 6.3 V
10 µF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
24
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Design Example 4
This design example describes a 3.3-VIN, LP DDR3 Configuration
R1
10 kW
TPS51200
REFIN
1
2
VIN 10
3.3 VIN
V
= V
V
= 1.2 V
= 1.2 V
VDDQ
VDDQ
R2
10 kW
C4
1000 pF
R3
100 kW
C6
4.7 mF
VLDOIN PGOOD
9
PGOOD
V
VLDOIN
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
= 0.6 V
VTT
C1
C2
C3
10 mF 10 mF 10 mF
PGND
SLP_S3
VTTREF
VOSNS REFOUT
C5
0.1 mF
UDG-08031
Figure 28. 3.3-VIN, LP DDR3 Configuration
Design Example 4 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
Resistor
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
R3
10 kΩ
100 kΩ
C1, C2, C3
C4
10 µF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 µF
C6
4.7 µF, 6.3 V
10 µF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
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Design Example 5
This design example describes a 3.3-VIN, DDR3 Tracking Configuration
R1
10 kW
TPS51200
1
2
REFIN
VIN 10
3.3 VIN
V
= V
V
= 1.5 V
= 1.5 V
VDDQ
R2
10 kW
C4
1000 pF
R3 C6
100 kW 4.7 mF
VLDOIN PGOOD
9
PGOOD
V
VLDOIN
VDDQ
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
= 0.75 V
VTT
C1
C2
C3
10 mF 10 mF 10 mF
PGND
VOSNS REFOUT
VTTREF
C5
0.1 mF
UDG-08032
Figure 29. 3.3-VIN, DDR3 Tracking Configuration
Design Example 5 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
R3
10 kΩ
Resistor
100 kΩ
C1, C2, C3
C4
10 µF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 µF
C6
4.7 µF, 6.3 V
10 µF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
26
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SLUS812–FEBRUARY 2008
Design Example 6
This design example describes a 3.3-VIN, LDO Configuration.
R1
10 kW
TPS51200
REFIN
2.5 V
1
2
VIN 10
3.3 VIN
R2 C4
3.86 kW 1000 pF
R3
100 kW
C6
4.7 mF
VLDOIN PGOOD
9
PGOOD
V
= V
= 2.5 V
VLDOIN
VLDOREF
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
V
= 1.8 V
VLDO
C1
C2
C3
10 mF 10 mF 10 mF
PGND
ENABLE
REFOUT
VOSNS REFOUT
C5
0.1 mF
UDG-08033
Figure 30. 3.3-VIN, LDO Configuration
Design Example 6 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
SPECIFICATION
PART NUMBER
MANUFACTURER
R1
10 kΩ
R2
R3
Resistor
3.86 kΩ
100 kΩ
C1, C2, C3
C4
10 µF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
Capacitor
0.1 µF
C6
4.7 µF, 6.3 V
10 µF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
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SLUS812–FEBRUARY 2008
Design Example 7
This design example describes a 3.3-VIN, DDR3 Configuration with LFP.
R1
10 kW
TPS51200
REFIN
1
2
VIN 10
3.3 VIN
V
= V
V
= 1.5 V
= 1.5 V
VDDQ
VDDQ
R2
10 kW
C4
1000 pF
R3
100 kW
C6
4.7 mF
VLDOIN PGOOD
9
PGOOD
V
VLDOIN
C7
10 mF
C8
10 mF
3
4
5
VO
GND
EN
8
7
6
= 0.75 V
VTT
(1)
R4
C1
C2
C3
10 mF 10 mF 10 mF
PGND
SLP_S3
VTTREF
VOSNS REFOUT
C5
0.1 mF
(1)
C9
UDG-08034
Figure 31. 3.3-VIN, DDR3 Configuration with LFP
Design Example 7 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
SPECIFICATION
PART NUMBER
MANUFACTURER
R1, R2
R3
10 kΩ
Resistor
100 kΩ
(1)
R4
C1, C2, C3
C4
10 µF, 6.3 V
1000 pF
GRM21BR70J106KE76L
Murata
C5
0.1 µF
Capacitor
C6
4.7 µF, 6.3 V
10 µF, 6.3 V
GRM21BR60J475KA11L
GRM21BR70J106KE76L
Murata
Murata
C7, C8
C9(1)
(1) The values of R4 and C9 should be chosen to reduce the parasitic effect of the trace (between VO and the output MLCCs) and the
output capacitors (ESR and ESL).
28
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS51200
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2008
PACKAGING INFORMATION
Orderable Device
TPS51200DRCR
TPS51200DRCRG4
TPS51200DRCT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SON
DRC
10
10
10
10
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
SON
SON
DRC
DRC
DRC
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS51200DRCTG4
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS51200DRCR
TPS51200DRCT
SON
SON
DRC
DRC
10
10
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS51200DRCR
TPS51200DRCT
SON
SON
DRC
DRC
10
10
3000
250
346.0
190.5
346.0
212.7
29.0
31.8
Pack Materials-Page 2
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