TPS51215A [TI]
具有 2 位 VID 的 3V 至 28V 输入、单相 D-CAP2 控制器;
| 型号： | TPS51215A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 2 位 VID 的 3V 至 28V 输入、单相 D-CAP2 控制器 控制器 |
| 文件： | 总32页 (文件大小：1716K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS51215A
SLUSDW9A –JUNE 2020–REVISED JUNE 2020
TM
TPS51215A Single Phase, D-CAP2 Controller with 2-Bit VID Control
and Low Power Mode
1 Features
3 Description
The TPS51215A is
a single-phase, D-CAP2™
1
•
Differential voltage feedback
synchronous buck controller with a 2-bit VID input
supporting and three other independent
•
•
•
DC compensation for accurate regulation
Wide input voltage range: 3 V to 28 V
0
V
externally programmable output voltage levels, where
full external programmability of the voltage level, step
setting and voltage-change slew rate is desired. It is
used for Intel IMVP8/9 applications where multiple
voltage levels are desired.
Flexible, 2-bit VID supports output voltage from
0.5-V to 2.0-V and 0-V VOUT
•
D-CAP2™ mode at 600kHz for Ultra-Low/Low
ESR Output Capacitor
The TPS51215A supports all POS/SPCAP and/or all
ceramic MLCC output capacitor options in
applications where remote sense is a requirement.
Tight DC load regulation is achieved through external
programmable integrator capacitor. The TPS51215A
provides full protection suite, including OVP, OCL, 5-
V UVLO and thermal shutdown. It supports the
conversion voltage up to 28 V, and output voltages
adjustable from 0.5 V to 2 V.
•
•
4700 ppm/°C, low-side RDS(on) current sensing
Programmable soft-start time and output voltage
transition time
•
•
•
•
•
•
Built-in output discharge
Power good output
Integrated boost switch
Built-in OVP/UVP/OCP
Thermal shutdown (non-latched)
3-mm × 3-mm, 20-Pin, QFN (RUK) package
The TPS51215A is available in the 3 mm × 3 mm,
QFN, 0.4-mm pitch package and is specified from
–40°C to 125°C.
2 Applications
Device Information(1)
•
•
•
Notebook computers
Desktop computers
Industrial PC
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS51215A
WQFN (20)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VIN
TRIP
VSNS
GSNS
GND
SLEW
MODE
V5IN
DRVH
SW
V3
V2
V1
V0
Vout
TPS51215A
BST
DRVL
VREF PGOOD VID0
VID1
EN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS51215A
SLUSDW9A –JUNE 2020–REVISED JUNE 2020
www.ti.com
Table of Contents
7.4 D-CAP2 Control Mode ............................................ 14
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Applications ................................................ 15
Power Supply Recommendations...................... 23
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 8
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
8
9
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
11 Device and Documentation Support ................. 25
11.1 Device Support .................................................... 25
11.2 Receiving Notification of Documentation Updates 25
11.3 Community Resources.......................................... 25
11.4 Trademarks........................................................... 25
11.5 Electrostatic Discharge Caution............................ 25
11.6 Glossary................................................................ 25
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
12.1 Package Option Addendum .................................. 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
June 2020
A
initial release
2
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SLUSDW9A –JUNE 2020–REVISED JUNE 2020
5 Pin Configuration and Functions
RUK Package
20-Pin WQFN
Top View
20
19
18
17
16
1
2
3
4
5
15
14
13
12
11
GSNS
V3
V5IN
DRVL
TPS51215A
Thermal Pad
V2
DRVH
SW
V1
V0
BST
6
7
8
9
10
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
I
Supply input for high-side MOSFET driver (bootstrap terminal). Connect a capacitor from this pin to the SW pin. Internally
connected to V5IN via the bootstrap MOSFET switch.
BST
11
DRVH
DRVL
EN
13
14
10
17
O
O
I
High-side MOSFET gate driver output.
Synchronous low-side MOSFET gate driver output.
Enable input for the device. Support 3.3-V logic
GND
I
Combined AGND and PGND point. The positive on-resistance current sensing input.
Voltage sense return tied directly to GND sense point of the load. Tie to GND with a 10-Ω resistor to close feedback if
remote sensing is used. Short to GND if remote sense is not used.
GSNS
1
I
MODE
PGOOD
SLEW
SW
16
7
I
connect to V5IN
O
PGOOD output. Connect pull-up resistor.
19
12
18
5
I
Program the startup using 4.5 µA and voltage transition time using 45 µA from an external capacitor via current source.
High-side MOSFET gate driver return. The RDS(on) current sensing input (–).
Connect resistor to GND to set OCL at VTRIP/8. Output 10 µA current at room temperature, TC = 4700ppm/°C.
Voltage need to be set to 0V, corresponding to 00
I/O
TRIP
V0
I
I
I
I
I
I
V1
4
Voltage set-point programming resistor input, corresponding to 01
Voltage set-point programming resistor input, corresponding to 10
Voltage set-point programming resistor input, corresponding to 11
5-V power supply input for internal circuits and MOSFET gate drivers
V2
3
V3
2
V5IN
15
Logic input for set-point voltage selector. Use in conjunction with VID1 pin to select among four set-point reference voltages.
Support 1-V and 3.3-V logic.
VID0
8
I
Logic input for set-point voltage selector. Use in conjunction with VID0 pin to select among four set-point reference voltages.
Support 1-V and 3.3-V logic.
VID1
9
6
I
O
I
VREF
VSNS
2 V, 300-µA voltage reference. Bypass to GND with a 1-µF ceramic capacitor.
Voltage sense return tied directly to the load voltage sense point. Tie to VOUT with a 10-Ω resistor to close feedback if
remote sensing is used.
20
—
Thermal Pad
—
Connect directly to system GND plane with multiple vias.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–2
MAX
36
UNIT
BST
6
BST(3)
transient < 20 ns
transient < 20 ns
6.5
30
–5
SW
–5
32
Input voltage range(2)
V
EN, TRIP, MODE, VID1, VID0
–0.3
–0.3
–0.3
–0.35
–0.3
–5
5.5
5.3
3.6
0.35
0.3
36
V5IN
SLEW, VSNS
GSNS
GND
DRVH
–0.3
–2
6
DRVH(3)
transient < 20 ns
6.5
6
Output voltage range(2)
–0.3
–2
V
DRVL
transient < 20 ns
6.5
6
PGOOD
–0.3
–0.3
–40
–55
VREF, V0, V1, V2, V3
3.6
150
150
Junction temperature, TJ
Storage temperature, TSTG
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
5.25
33.5
5.5
UNIT
Supply voltage
V5IN
V
BST
BST(1)
–0.1
–0.1
–3
SW
28
SW(2)
–4.5
–0.1
–0.1
–0.3
–0.1
–3
28
Input voltage range
V
EN, TRIP, MODE, VID1, VID0
5.5
SLEW, VSNS
GSNS
3.5
0.3
GND
0.1
DRVH
33.5
33.5
5.5
DRVH(2)
DRVH(1)
–4.5
–0.1
–0.1
–1.5
–0.1
–0.1
–40
Output voltage range
5.5
V
DRVL
transient < 20 ns
5.5
PGOOD
5.5
VREF, V0, V1, V2, V3
3.5
Operating free-air temperature, TJ
125
°C
(1) Voltage values are with respect to the SW terminal.
(2) This voltage should be applied for less than 30% of the repetitive period.
6.4 Thermal Information
TPS51215A
RUK (WQFN)
20 PINS
94.1
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
58.1
64.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
31.8
ψJB
58.0
RθJC(bot)
5.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
Over recommended free-air temperature range, VIN = 12 V, V5IN = 5V, TJ = -40°C to 125°C, typical values are at TJ = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input Voltage Range
V5IN Supply Current
VIN
3
28
V
No load, VEN=3.3V,Vout ≠0, Non
Switching, VMODE=5V
610
µA
IV5IN
V5IN Stand-by Current
V5IN Shutdown Current
No load, VEN=3.3V, Vout=0
No load, VEN=0V
250
1
µA
µA
IV5INSDN
UVLO
Wake up V5IN voltage
Shut down V5IN voltage
Hysteresis V5IN voltage
4.4
4
4.6
V
V
VV5IN_UVLO
V5IN Under-Voltage Lockout
3.8
400
mV
VREF VOLTAGE
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Electrical Characteristics (continued)
Over recommended free-air temperature range, VIN = 12 V, V5IN = 5V, TJ = -40°C to 125°C, typical values are at TJ = 25°C
(unless otherwise noted)
PARAMETER
Output Voltage
TEST CONDITIONS
IVREF = 30 µA, w/r/t GSNS
MIN
TYP
MAX
UNIT
V
VVREF
2
0 µA ≤IVREF ≤ 30 µA, 0°C ≤TJ ≤ 85°C
–0.8
–1
0.8
1
%
VVREFTOL
IVREFOCL
Output Voltage Tolerance
Current Limit
0 µA ≤IVREF ≤ 300 µA, -40°C ≤TJ ≤
125°C
%
VVREF-GSNS = 1.7V
0.4
1
mA
DUTY CYCLE and FREQUENCY CONTROL
VIN = 12 V, VVSNS = 1.8 V, VMODE
=5V
FSW
Switching Frequency (1)
600
kHz
TON(MIN)
Minimum On-time
Minimum Off-time
DRVH rising to falling
DRVH falling to rising
40
ns
ns
TOFF(MIN)
DRIVERS
320
Source, IDRVH = 50 mA
Sink, IDRVH = 50 mA
Source, IDRVL = 50 mA
Sink, IDRVL = 50 mA
DRVH-off to DRVL-on
DRVL-off to DRVH-on
1.5
0.6
0.9
0.4
14
Ω
Ω
RDRVH
RDRVL
tD
High-side Driver Resistance
Ligh-side Driver Resistance
Dead Time
Ω
Ω
ns
ns
21
SOFTSTART AND SLEWRATE
During Soft Start
ISLEW
4.5
45
µA
µA
During Vout Dynamic Scaling
POWER GOOD
PG from low to high
PG from high to low
VOUT falling (fault)
VOUT rising (good)
VOUT rising (fault)
VOUT falling (good)
VPGOOD =0.5V
1
0.2
84
ms
us
%
TPGDLY
PG Deglitch Time
PG Threshold
92
%
VPGTH
116
108
6
%
%
IPGMAX
IPGLK
PG Sink Current
PG Leak Current
mA
uA
VPGOOD =5.5V
1
CURRENT LIMIT
ITRIP
TRIP source current
TJ = 25°C, VTRIP = 0.4 V
9
10
11
µA
ppm/C
V
TRIP source current temperature
coefficient(1)
TCTRIP
VTRIP
4700
VTRIP Voltage Range
0.2
360
188
20
3
390
212
30
VTRIP = 3.0V
VTRIP = 1.6V
VTRIP = 0.2V
VTRIP = 3.0V
VTRIP = 1.6V
VTRIP = 0.2V
375
200
VOCL
Current Limit Threshold
mV
mV
25
–390
–212
–30
–375
–200
–25
–360
–188
–20
VNOCL
Negative Current Limit Threshold
LOGIC THRESHOLD
VEN(ON)
VEN(OFF)
VEN(HSYS)
IEN
EN Threshold High-level
1.5
V
V
EN Threshold Low-level
EN Hysteresis
0.5
1
250
mV
uA
V
EN Leakage Current
VIDx Threshold High-level
–1
VVIDx(HI)
0.9
6
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Electrical Characteristics (continued)
Over recommended free-air temperature range, VIN = 12 V, V5IN = 5V, TJ = -40°C to 125°C, typical values are at TJ = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.3
1
UNIT
V
VVIDx(LI)
IVIDx
VIDx Threshold Low-level
VIDx Leakage Current
–1
uA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
OVP Trip Threshold
OVP Deglitch Time
UVP Trip Threshold
UVP Deglitch Time
118
65
120
0.2
68
1
123
70
%
us
%
TOVPDLY
VUVP
TUVPDLY
ms
VOUT VOLTAGE
VSLEWCLP SLEW Clamp Voltage
gM
VREFIN = 1.1 V
1.012
1.188
V
Error Amplifier Transconductance
VSNS Input Current
VREFIN = 1.1 V
60
20
12
us
ISNS
VVSNS = 1.1 V
uA
mA
IVSNSDIS
VSNS Discharge Current
EN=0, VVSNS=0.5V,VMODE = 5V
OUTPUT DISCHARGE
RDIS
Discharge Resistance
TJ=25°C, VVOUT =0.5V, VEN=0V
42
Ω
Thermal protection
TOTP
OTP Trip Threshold
OTP Hysteresis
140
10
°C
°C
TOTPHSY
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6.6 Typical Characteristics
16
70
60
50
40
30
20
10
0
Vout Dynamic Scaling
Soft Start Phase
14
12
10
8
6
-40
-10
20
50
80
110
140
-40
-10
20
50
80
110
140
Tj - Junction Temperature (èC)
Tj - Junction Temperature (èC)
Figure 1. Trip Current Vs Temperature
Figure 2. Slew Current Vs Temperature
2.1
700
600
500
400
300
200
100
0
2.06
2.02
1.98
1.94
1.9
VIN=5.4V, VOUT=1.8V
VIN=12.6V, VOUT=1.8V
VIN=19.5V, VOUT=1.8V
-40
-10
20
50
80
110
140
0
2
4
6
8
10
I-Load (A)
12
14
16
18
20
Tj - Junction Temperature (èC)
FSWv
Figure 3. VREF Voltage Vs Temperature, IVREF=0A
Figure 4. Switching frequency Vs Loading Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VVIN=7.4V, VOUT=1.8V
VVIN=12.6V, VOUT=1.8V
VVIN=19.5V, VOUT=1.8V
VVIN=7.4V, VOUT=1.65V
VVIN=12.6V, VOUT=1.65V
VVIN=19.5V, VOUT=1.65V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
I-Load (A)
I-Load (A)
EFFv
EFFv
Figure 5. Efficiency Curve, Vout=1.8V
Figure 6. Efficiency Curve, Vout=1.65V
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7 Detailed Description
7.1 Overview
TPS51215A is a synchronous step-down controller which can operate from 3 V to 28 V input voltage (VIN). The
proprietary D-CAP2TM mode enables low external component count, ease of design, optimization of the power
rail for cost, size and efficiency. TPS51215A is able to adapt to both low equivalent series resistance (ESR)
output capacitors such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors.
The TPS51215A needs an external 5V supply to power the internal control circuitry. The undervoltage lockout
(UVLO) circuit monitors the V5IN pin voltage to protect the internal circuitry from low input voltages. TPS51215A
operates in fixed 600kHz switching frequency.
The TPS51215A supports 2-bits VID and Low Power Mode(LPM) to dynamically change the Vout voltage to
satisfy the Intel IMVP8/9 applications — VCCIN_AUX, VCCIO_0, VCCIO_1_2 applications.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Switch Mode Power Supply Control
The TPS51215A is a high performance, single-synchronous step-down controller with differential voltage
feedback. It realizes accurate regulation at the specific load point over wide load range.
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Feature Description (continued)
The TPS51215A is using D-CAP2 mode which do not require complex external compensation networks and can
minimize the external components counts. An adaptive on-time control scheme is used to achieve pseudo-
constant frequency. The TPS51215A adjusts the on-time (tON) to be inversely proportional to the input voltage
(VIN) and proportional to the SMPS output voltage (VOUT). The switching frequency remains nearly constant over
the variation of input voltage at the steady-state condition.
7.3.2 VREF, V0, V1, V2, V3 and Output Voltage
The device provides a 2.0-V, accurate voltage reference from the VREF pin. This output has a 300-µA current
sourcing capability to drive V1, V2 and V3 input voltages through a voltage divider circuit as shown in Figure 7. If
higher overall system accuracy is required, the sum of total resistance (R1+R2+R3+R4+R5) from VREF to GND
should be designed to be more than 67 kΩ. A MLCC capacitor with a value of 0.1-µF or larger should be placed
close to the VREF pin.
The device also provides 2-bit VID flexible output voltage control. Fixed 0V output voltage and up to three
voltage levels can be programmed externally by a voltage divider circuit. Fixed 0V output voltage corresponds to
VID 00, V1 corresponds to VID 01, V2 corresponds to VID 10 and V3 corresponds to VID 11. It is not necessary
to match the voltage set point (VSET1, VSET2 or VSET3 ) to any particular V1, V2 or V3 input. Assignment of the
input voltage is entirely dependent on the user requirement, which makes the device very easy and flexible to
use.
The device can also be configured to provide 1-bit VID flexible output voltage operation. In the applications
where fewer than four input voltage levels are needed, the remaining input voltage pins cannot be left floating.
VREF 2 V
R1
TPS51215A
V3
VSET1
11
R2
V2
VSET2
10
R3
V1
VSET3
01
R4
V0
VSET4
00
R5
VID0 VID1
Figure 7. Setting the Output Voltage
7.3.3 Soft-Start and Power Good
Prior to asserting EN high, the power stage conversion voltage and V5IN voltage should be ready. When EN is
asserted high, TPS51215A provides soft start to suppress in-rush current during start-up. The soft start action is
achieved by an internal SLEW current of 4.5 µA (typ) sourcing into a external MLCC capacitor connected from
SLEW pin to GND.
Use Equation 1 to determine the soft-start timing.
V
OUT
t
= C
´
SS
SLEW
I
SLEW
where
•
•
•
CSLEW is the soft start capacitance
VOUT is the output voltage
ISLEW is the internal 4.5-µA current source
(1)
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Feature Description (continued)
The TPS51215A has a open-drain PowerGood output pin that indicates the Vout voltage is within the target
range. The target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms
delay for assertion from low to high, and ±16% (typ) and 0.2-µs delay for de-assertion from high to low during
operation.
7.3.4 SLEW and VID Function
In addition to providing soft start function, SLEW is also used to program the VID transition time. TPS51215A
supports 2-bit VID and 1-bit VID operations. VID0 and VID1 works with 1.05-V logic level signals with capability
of supporting up to 3.3-V logic high.
V0 V1 V2 V3
VID0
00
01
10
11
VID1
I1(1)
+
gM
I2(2)
VSNS
SLEW
UDG-11206
(1) I1: Enable during VID transitioning, 45 µA.
(2) I2: Soft start, 4.5 µA.
Figure 8. VID Configuration
During VID transition:
•
SLEW current is increased to 45 µA. Based on the VID transition time of the system, the amount of the SLEW
capacitance can be calculated to meet such requirement. The minimum SLEW capacitance can be supported
by the device is 2nF.
where
•
•
ISLEW is 45 µA, dV is the voltage change during VID transition
dt is the required transition time
(2)
•
•
FCCM (forced continuous conduction mode) operation is used regardless of the load level. In the meantime,
the overcurrent level is temporality increased to 125% times the normal OCL level to prevent false OC trip
during fast SLEW up transition. Power good, UVP and OVP functions are all blanked as well. All normal
functions are resumed 16 internal clock cycles (64 µs) after VID transition is completed.
Additional SLEW CLAMP is implemented. If severe output short occurs (either to GND or to some other high
voltage rails in the system), SLEW is engaged into SLEW CLAMP, approximately 50 mV above or below the
output voltage reference point. After 32 internal clockcycles, the CLAMP is engaged, UVP and OVP functions
are activated to disable the controller at fault.
•
•
If VID 00 is selected, part will enter low power mode where the DRVL and DRVH will be stop switching and
Vout will decay to 0V. At mean time, the PGOOD pin still keeps high. The Vout transition time can be
calculated by Equation 2
VID is fixed to 11 internally until soft-start end which means that Vout ramp to V3 in soft start period.
Figure 10 showed the power up sequence
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Feature Description (continued)
11
11
V3
00
VID
V3
Decay
Vout
Figure 9. Low Power Mode Enter and Exit
VIN
V5IN
EN
V3
V2
500uS
VOUT
VID
Forced to 11
VID=10
SS_END
Figure 10. Power up Sequence
7.3.5 MODE Pin Configuration
MODE pin should be connected to V5IN pin.
7.3.6 Light-Load Operation
In auto-skip mode, the TPS51215A SMPS control logic automatically reduces its switching frequency to improve
light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent negative
inductor current by turning off the low-side MOSFET. Equation 3 shows the boundary load condition of this skip
mode and continuous conduction operation.
V
- V
(
OUT ) V
1
IN
OUT
I
=
´
´
LOAD(LL)
2´L
V
f
SW
X
IN
(3)
7.3.7 Out-of-Bound Operation
When the output voltage rises to 8% above the target value, the out-of-bound operation starts. During the out-of-
bound condition, the controller operates in forced PWM-only mode. Turning on the low-side MOSFET beyond the
zero inductor current quickly discharges the output capacitor. During this operation, the cycle-by-cycle negative
overcurrent limit is also valid. Once the output voltage returns to within regulation range, the controller resumes
to auto-skip mode.
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Feature Description (continued)
7.3.8 Current Sensing and Overcurrent Protection
In order to provide both cost effective solution and good accuracy, TPS51215A supports MOSFET RDS(on)
sensing. For RDS(on) sensing scheme, TRIP pin should be connected to GND through the trip voltage setting
resistor, RTRIP. In this scheme, TRIP terminal sources 10µA of ITRIP current (at TJ = 25°C) and the trip level is set
to 1/8 of the voltage across the RTRIP. The inductor current is monitored by the voltage between the GND pin and
the SW pin so that the SW pin is connected to the drain terminal of the low-side MOSFET. ITRIP has a
4700ppm/°C temperature slope to compensate the temperature dependency of the RDS(on). GND is used as the
positive current sensing node so that GND should be connected to the sense resistor or the source terminal of
the low-side MOSFET.
TPS51215A has cycle-by-cycle overcurrent limiting protection. The inductor current is monitored during the off-
state and the controller maintains the off-state when the inductor current is larger than the overcurrent trip level.
The overcurrent trip level, VOCTRIP, is determined by Equation 4.
I
æ
ö
TRIP
VOCTRIP = RTRIP
´
ç
÷
8
è
ø
(4)
Because the comparison is made during the off-state, VOCTRIP sets the valley level of the inductor current. The
load current OCL level, IOCL, can be calculated by considering the inductor ripple current.
Overcurrent limiting using RDS(on) sensing is shown in Equation 5.
æ
ç
ö
÷
æ
ç
ö
÷
I
VOCTRIP
VOCTRIP
V
IN - VOUT
VOUT
1
2
IND(ripple)
IOCL
=
+
=
+
´
´
ç
÷
ç
÷
RDS on
2
RDS on
LX
fSW ´ V
IN
( )
( )
è
ø
è
ø
where
•
IIND(ripple) is inductor ripple current
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down.
7.3.9 Overvoltage and Undervoltage Protection
The TPS51215A sets the overvoltage protection (OVP) when VSNS voltage reaches a level 20% (typ) higher
than the target voltage. When an OV event is detected, the controller changes the output target voltage to 0 V.
This usually turns off DRVH and forces DRVL to be on. When the inductor current begins to flow through the
low-side MOSFET and reaches the negative OCL, DRVL is turned off and DRVH is turned on, for a minimum on-
time.
After the minimum on-time expires, DRVH is turned off and DRVL is turned on again. This action minimizes the
output node undershoot due to LC resonance. When the VSNS reaches 0 V, the driver output is latched as
DRVH off, DRVL on.
The undervoltage protection (UVP) latch is set when the VSNS voltage remains lower than 68% (typ) of the
REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DRVH low and DRVL low and
discharges the VOUT. UVP detection function is enabled after 1.2 ms of SMPS operation to ensure startup.
To release the OVP and UVP latches, toggle EN or adjust the V5IN voltage down and up beyond the
undervoltage lockout threshold.
7.3.10 V5IN Undervoltage Lockout Protection
TPS51215A has a 5-V supply undervoltage lockout protection (UVLO) threshold. When the V5IN voltage is lower
than UVLO threshold voltage, typically 4.0 V, VOUT is shut off. This is a non-latch protection.
7.3.11 Thermal Shutdown
TPS51215A includes an internal temperature monitor. If the temperature exceeds the threshold value, 140°C
(typ), VOUT is shut off. The state of VOUT is open at thermal shutdown. This is a non-latch protection and the
operation is restarted with soft-start sequence when the device temperature is reduced by 10°C (typ).
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7.4 D-CAP2 Control Mode
Figure 11 shows a simplified model of D-CAP2 mode architecture in the TPS51215A.
VIN
CC1
VSNS
SW
DH
RC1
CC2
RC2
SLEW
LX
C1
Control
Logic
and
G
VOUT
–
–
PWM
Comparator
Driver
DL
+
V3
+
ESR
RLOAD
COUT
VREF
R1
+
2.0 V
R2
TPS51215A
UDG-11262
Figure 11. Simplified D-CAP2 Mode Architecture
When TPS51215A operates in D-CAP2 mode, it uses an internal phase compensation network (RC1, RC2, CC1
and CC2 and G) to work with very low ESR output capacitors such as multi-layer ceramic capacitors (MLCC) and
POSCAP. The role of such network is to sense and scale the ripple component of the inductor current
information and then use it in conjunction with the voltage feedback to achieve loop stability of the converter.
The switching frequency used for D-CAP2 mode is 600 kHz and it is generally recommended to have a unity
gain crossover (f0) of 1/4 of the switching frequency, which is approximately 150 kHz for the purpose of this
application.
Given the range of the recommended unity gain frequency, the power stage design is flexible, as long as
Equation 6 is true.
1
1
£
´ f
0
10
2´ p´ L
´ C
OUT
OUT
(6)
When TPS51215A is configured in D-CAP2 mode, the overall loop response is dominated by the internal phase
compensation network. The compensation network is designed to have two identical zeros at 7.7 kHz in the
frequency domain, which serves the purpose of splitting the L-C double pole into one low frequency pole (same
as the L-C double pole frequency) and one high-frequency pole (greater than the unity gain crossover
frequency).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This section describes two different applications for the TPS51215A controller. Design 1 is a 2-Bit VID ICC(max)
=
30A, application for VCCIN_AUX application in Intel IMVP9 platform. Design 2 is a 1-Bit VID ICC(max) =10A, for
VCCIO_1_2 in Intel RocketLake-S platform.
8.2 Typical Applications
VIN
TRIP
VSNS
GSNS
GND
SLEW
MODE
V5IN
DRVH
SW
V3
V2
V1
V0
Vout
TPS51215A
BST
DRVL
VREF PGOOD VID0
VID1
EN
Figure 12. Typical 2-Bit VID Application
8.2.1 Design Requirements
The Step One: Determine the Specifications section and the Step Two: Determine System Parameters section
itemize the system agent rail application requirements.
8.2.2 Detailed Design Procedure
The simplified design procedure creates VCCIN-AUX rail for IMVP9 Intel platform application using the
TPS51215A controller.
8.2.2.1 Step One: Determine the Specifications
•
•
•
•
•
•
V00 = 0 V
V01 = 1.1 V
V10 = 1.65 V
V11 = 1.8 V
ICC(max) = 30 A
IDYN(max) = 12 A
8.2.2.2 Step Two: Determine System Parameters
The input voltage range and operating frequency are of primary interest.
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Typical Applications (continued)
In this example:
•
•
5.5 V ≤ VIN ≤ 20 V
fSW = 600 kHz
8.2.2.3 Step Three: Determine Inductor Value and Choose Inductor
Smaller values of inductor have better transient performance but higher ripple and lower efficiency. Higher values
have the opposite characteristics. It is common practice to limit the ripple current to 25% to 50% of the maximum
current. In this example, use 25%:
IP-P = 30 A × 0.4 = 12 A
At fSW = 600 kHz with a 20-V input and a 1.8-V output:
1.8 V
1
20 V -1.8 V ´
( )
´
V
(
- V ´ T
)
V
(
- V ´D ´ T
)
20 V 600kHz
12 A
OUT
IN
ON
OUT
IN
L =
=
=
I
I
P-P
P-P
(7)
For this application, a 0.22-µH, 1.15-mΩ inductor from Cyntec with part number CMLE063T-R22MS is used.
8.2.2.4 Step Four: Set the Output Voltages
Set the output voltage levels. for V0, V1, V2 and V3 pins ).
•
•
•
•
VID 00, V0 = VSET1 = 0 V
VID 10, V2 = VSET2 = 1.1 V
VID 01, V1 = VSET3 = 1.65 V
VID 11, V3 = VSET4 = 1.8 V
The resistor value:
•
•
•
•
•
•
VREF = 2 V
R1 = 20 kΩ
R2 = 15 kΩ
R3 = 54.9 kΩ
R4 = 110 kΩ
R5 = 0Ω
VREF 2 V
R1
TPS51215A
VSET4
V3
V2
R2
R3
R4
R5
VSET3
VSET2
V1
V0
VSET1
VID0
VID1
Figure 13. Setting the Output Voltage
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Typical Applications (continued)
8.2.2.5 Step Five: Calculate SLEW Capacitance
SLEW can be used to program the soft-start time and voltage transition timing. During soft-start operation, the
current source used to program the SLEW rate is 4.5 µA (nominal). During VID transition, the current source is
switched to a higher current of 45 µA.
In this design example, the requirement is to complete VID_00 to VID_11 transition within 120 µs, calculate the
SLEW capacitance based on Equation 8.
dT
120 ms
C
= I´
= 45 mA ´
= 3nF
SLEW
dV
1.8 V
(8)
For VOUT = 1.8 V, the soft start timing based on CSLEW is 1.2 ms.
The slower slew rate is desired to minimize large inductor current perturbation during startup and voltage
transition, thus reducing the possibility of acoustic noise.
8.2.2.6 Step Six
TPS51215A uses a low-side on-resistance (RDS(on) ) sensing scheme. The TRIP pin sources 10 µA of current and
the trip level is set to 1/8 of the voltage across the TRIP resistor (RTRIP ). The overcurrent trip level is determined
by RTRIP × (ITRIP /8). Because the comparison is done during the off state, the trip voltage sets the valley current.
The load current can be calculated by considering the inductor ripple current.
æ
ö
÷
÷
ø
æ
ö
V
- V
V
OUT
(
)
(
SW IN
)
IN
OUT
8´ I
-
´
´R
DS on
ç
ç
ç
÷
÷
OCL
( )
ç
è
2´Lx
f
(
´ V
(
)
)
è
ø
R
=
TRIP
I
TRIP
-
where
•
•
•
•
•
•
VIN is the input voltage
VOUT is the output voltage
fSW is the switching frequency (600 kHz)
RDS(on) is the low-side FET on resistance
ITRIP is the trip current, 10 µA (nominal)
Lx is the output inductance
(9)
8.2.2.7 Step Seven: Determine the Output Capacitance
The switching frequency for D-CAP2 mode is 600 kHz and it is generally recommend to have a unity gain
crossover (f0) of 1/4 of the switching frequency, which is approximately 150kHz for the purpose of this
application.
Given the range of the recommended unity gain frequency, the power stage design is flexible, as long as the LC
double pole frequency is less than 10% of f0.
1
1
f
=
£
´ f = 9kHz Û 12kHz
0
LC
10
2p L
´ C
OUT
OUT
(10)
As long as the LC double pole frequency is designed to be less than 1/10 of f0, the internal compensation
network provides sufficient phase boost at the unity gain crossover frequency in order for the converter to be
stable with enough margin.
When the ESR frequency of the output bulk capacitor is in the vicinity of the unity gain crossover frequency of
the loop, additional phase boost is achieved. This applies to POSCAP and/or SPCAP output capacitors.
When the ESR frequency of the output capacitor is beyond the unity gain crossover frequency of the loop, no
additional phase boost is achieved. This applies to low/ultra low ESR output capacitors, such as MLCCs.
Equation 11 and Equation 12 can be used to estimate the amount of capacitance needed for a given dynamic
load step/release. Note that there are other factors that may impact the amount of output capacitance for a
specific design, such as ripple and stability. Equation 11 and Equation 12 are used only to estimate the transient
requirement, the result should be used in conjuction with other factors of the design to determine the necessary
output capacitance for the application.
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Typical Applications (continued)
æ
ç
ç
è
ö
÷
÷
ø
2
V
´ t
SW
OUT
L ´ DI
´
+ t
MIN(off)
(
)
LOAD(max)
V
IN(min)
C
=
OUT(min_under)
æ
ç
ç
è
ö
÷
÷
ø
æ
ç
ç
è
ö
÷
÷
ø
V
- V
IN(min)
OUT
2´ DV
´
´ t
- t
´ V
OUT
LOAD(insert)
SW
MIN(off)
V
IN(min)
(11)
(12)
2
)
LOUT ´ DI
(
LOAD(max)
COUT(min_over)
=
2´ DVLOAD(release) ´ VOUT
Equation 11 and Equation 12 calculate the minimum COUT for meeting the transient requirement, which is 480 µF
assuming ±7.5% voltage allowance for load step and release.
8.2.2.8 Step Eight: Select Decoupling and Peripheral Components
For the TPS51215A, peripheral capacitors use the following minimum values of ceramic capacitance. X5R or
better temperature coefficient is recommended. Tighter tolerances and higher voltage ratings are always
appropriate.
•
•
•
•
V5IN decoupling ≥2.2 µF, ≥ 6.3 V
VREF decoupling 0.22 µF to 1 µF, ≥ 4 V
Bootstrap capacitors ≥ 0.1 µF, ≥ 10 V
Pull-up resistors on PGOOD, 100 kΩ
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Typical Applications (continued)
8.2.3 Application Examples
8.2.3.1 Design 1: 2-Bit VID ICC(max) = 30 A, DCAP2 600-kHz Application for VCCIN_AUX in Intel TigerLake
platform
GSNS
0
2.7n
34.8k
2.2u
VSNS SLEW
GSNS
TRIP
GND
MODE
V5IN
V5IN
VIN
20k
0
0
VREF
V3
V2
V1
V0
DRVL
DRVH
SW
VSNS
15k
Q1
0
LOUT
TPS51215A
0.1uF
54.9k
110k
VOUT
0.1u
COUT_BULK + COUT_MLCC
VREF
PGOOD VID0
VID1 EN BST
Q2
0
VREF
100 k
VID0
PGOOD
VID1 EN
Figure 14. Application Circuit for Design 1
Table 1. VID Table for Design 1
OUTPUT VOLTAGE
(V)
VID1
VID0
0
0
1
1
0
1
0
1
0
1.1
1.65
1.8
Table 2. List of Materials for Design 1
REFERENCE
DESIGNATOR
PART
NUMBER
QTY
SPECIFICATION
MANUFACTURER
CIN (not shown)
6
1
10 µF, 25 V
TDK
Panasonic
Murata
C3216X5R1V106M160AB
6TPF220M5L
COUT_BULK
COUT_MLCC
LOUT
220 µF, 6.3 V, 5 mΩ
22 µF, 6.3 V
12
1
GRM21BR60J226ME39L
CMLE063T-R22MS-68
CSD87355Q5D
0.22 µH, 38 A, 1.15 mΩ
30 V, 45A
Cyntec
Q1 Q2
1
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8.2.3.2 Design 2: 2-Bit VID, ICC(max) = 10 A, for VCCIO_1_2 in Intel RocketLake - S platform
GSNS
0
2.7n
15k
2.2u
VSNS SLEW
GSNS
TRIP
GND
MODE
V5IN
V5IN
VIN
100k
0
0
VREF
V3
V2
V1
V0
DRVL
DRVH
SW
VSNS
50k
50k
Q1
0
LOUT
TPS51215A
0.1 …F
VOUT
COUT_MLCC
m
0.1
VREF
PGOOD VID0
VID1 EN BST
Q2
0
VREF
100 k
LPM
PGOOD
EN
Figure 15. Application Circuit for Design 2
Table 3. VID Table for Design 2
OUTPUT VOLTAGE
(V)
VID1
VID0
0
0
1
1
0
1
0
1
0
Not Used
Not Used
1.0
Table 4. List of Materials for Design 2
REFERENCE
DESIGNATOR
PART
NUMBER
QTY
SPECIFICATION
MANUFACTURER
CIN (not shown)
COUT_MLCC
LOUT
3
6
1
1
10 µF, 25 V
TDK
Murata
C3216X5R1V106M160AB
GRM21BR60J226ME39L
CMLE063T-R47MS-68
CSD87355Q5D
22 µF, 6.3 V
0.47 µH, 25 A,2.9 mΩ
30 V, 45A
Cyntec
Q1 Q2
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8.2.4 Application Curves of Design 1
Vout=2V/div
Vout=2V/div
EN=5V/div
EN=5V/div
SW=10V/div
SW=10V/div
IL=10A/div
IL=10A/div
400us/div
80us/div
Figure 16. Start Up Relative to EN Rising
Figure 17. Shut Down Relative to EN Falling
Vout=20mV/div, AC
Vout=20mV/div, AC
SW=10V/div
SW=10V/div
IL=5A/div
IL=5A/div
4us/div
2us/div
Figure 18. Steady State IOUT = 1 A
Figure 19. Steady State IOUT = 10 A
Vout=500mV/div
Vout=500mV/div
VID=5V/div
VID=5V/div
SW=10V/div
SW=10V/div
IL=10A/div
IL=10A/div
20us/div
20us/div
Figure 20. VID Transient, VID = 01 to 11, VOUT = 1.1 V to 1.8
V
Figure 21. VID Transient, VID = 11 to 01, VOUT = 1.8 V to 1.1
V
Vout=500mV/div
Vout=500mV/div
VID1,0=5V/div
VID1,0=5V/div
PGOOD=5V/div
PGOOD=5V/div
IL=10A/div
IL=10A/div
200us/div
200us/div
Figure 22. Low Power Mode Exit VOUT = 0 V to 1.8 V
Figure 23. Low Power Mode Enter VOUT = 1.8 V to 0 V
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Vout=100mV/div, 1.8V offset
Vout=100mV/div, 1.8V offset
IL=10A/div
IL=10A/div
4ms/div
20ms/div
Figure 25. Load Transient, IOUT = 16 A to 30 A, Tr = Tf = 1
µs
Figure 24. Load Transient, IOUT = 0 A to 16 A, Tr = Tf = 1 µs
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9 Power Supply Recommendations
The TPS51215A is intended to be powered by a well regulated dc voltage. and input voltage is 3 V to 28 V. Input
supply must be appropriate for th desired output current. If the input voltage supply is located for from the part,
come additional input buck capacitance is recommended. Typical value is 50uF and 0.1uF Vin capacitor is
needed.
•
•
VIN is the power of input for buck, V5IN is power supply for internal control logic.
EN is high before VIN has the power input, V5IN power supply must be provided after or same time with VIN,
otherwise the output will be latched, this latch can be recovered by toggling the EN pin or re-power up the
V5IN
•
EN is low before VIN and V5IN have the power input, then there is no power supply input sequence
requirement
10 Layout
10.1 Layout Guidelines
Certain issues must be considered before designing a layout using the TPS51215A.
•
•
•
VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed on one
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the
small signal traces from noisy power lines.
All sensitive analog traces and components such as VSNS, SLEW, MODE, V0, V1, V2, V3, VREF and TRIP
should be placed away from high-voltage switching nodes such as SW, DH, DL or BST to avoid coupling.
Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and components. Need
to placed close to the part and minimized length of routing trace.
The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
–
–
–
Loop #1. The most important loop to minimize the area of is the path from the VIN capacitor(s) through the
high and low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of
the VIN capacitor(s) and the source of the low-side MOSFET at ground as close as possible. (Refer to loop
#1 of Figure 26)
Loop #2. The second important loop is the path from the low-side MOSFET through inductor and VOUT
capacitor(s), and back to source of the low-side MOSFET through ground. Connect source of the low-side
MOSFET and negative node of VOUT capacitor(s) at ground as close as possible. (Refer to loop #2 of
Figure 26)
Loop #3. The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-
side MOSFET, high current flows from V5 capacitor through gate driver and the low-side MOSFET, and
back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current
flows from gate of the low-side MOSFET through the gate driver and PGND, and back to source of the
low-side MOSFET through ground. Connect negative node of V5 capacitor, source of the low-side
MOSFET and PGND at ground as close as possible. (Refer to loop #3 of Figure 26)
•
VSNS can be connected directly to the output voltage sense point at the load device or the bulk capacitor at
the converter side. For additional noise filtering, insert a 10-Ω, 1-nF, R-C filter between the sense point and
the VSNS pin. Connect GSNS to ground return point at the load device or the general ground plane/layer.
VSNS and GSNS can be used for the purpose of remote sensing across the load device, however, care must
be taken to minimize the routing trace to prevent excess noise injection to the sense lines.
•
•
Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5
mm (20 mils) diameter along this trace.
•
•
The PCB trace defined as SW node, which connects to the source of the switching MOSFET, the drain of the
rectifying MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.
In order to effectively remove heat from the package, prepare the thermal land and solder to the package
Copyright © 2020, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: TPS51215A
TPS51215A
SLUSDW9A –JUNE 2020–REVISED JUNE 2020
www.ti.com
Layout Guidelines (continued)
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps to dissipate heat
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side ground
plane(s) should be used to help dissipation.
VREF
TPS51215A
V3
VIN
V2
0.1 µF
V1
V5IN
Controller
VOUT
#1
V0
2.2 µF
#2
GSNS
VSNS
GSNS
DRVL
#3
VSNS
PwrPad GND
SLEW
3 nF
TRIP
MODE
Figure 26. DC/DC Converter Ground System
24
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Product Folder Links: TPS51215A
TPS51215A
www.ti.com
SLUSDW9A –JUNE 2020–REVISED JUNE 2020
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
D-CAP2, E2E are trademarks of Texas Instruments.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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25
Product Folder Links: TPS51215A
PACKAGE OPTION ADDENDUM
www.ti.com
3-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS51215ARUKR
ACTIVE
WQFN
RUK
20
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
51215A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51215ARUKR
WQFN
RUK
20
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RUK 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS51215ARUKR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RUK0020B
WQFN - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
0.5
0.3
PIN 1 INDEX AREA
3.1
2.9
0.25
0.15
DETAIL
OPTIONAL TERMINAL
TYPICAL
DIMENSION A
OPTION 01
OPTION 02
(0.1)
(0.2)
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
(DIM A) TYP
OPT 02 SHOWN
1.7 0.05
6
10
EXPOSED
THERMAL PAD
16X 0.4
5
11
21
SYMM
4X
1.6
1
15
SEE TERMINAL
DETAIL
0.25
20X
0.15
0.1
C A
B
20
16
PIN 1 ID
SYMM
0.05
(OPTIONAL)
0.5
0.3
20X
4222676/A 02/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RUK0020B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.7)
SYMM
20
16
20X (0.6)
1
15
20X (0.2)
(0.6)
TYP
21
SYMM
(2.8)
16X (0.4)
5
11
(R0.05)
TYP
(
0.2) TYP
VIA
6
10
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222676/A 02/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RUK0020B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.47) TYP
16
(R0.05) TYP
20
20X (0.6)
1
15
21
20X (0.2)
(0.47)
TYP
SYMM
(2.8)
16X (0.4)
11
5
METAL
TYP
6
10
4X ( 0.75)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 21:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222676/A 02/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
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will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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