TPS51216-EP [TI]
增强型产品完整 DDR2、DDR3 和 DDR3L 存储器电源解决方案同步降压控制器;
| 型号： | TPS51216-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品完整 DDR2、DDR3 和 DDR3L 存储器电源解决方案同步降压控制器 双倍数据速率 控制器 存储 |
| 文件： | 总37页 (文件大小：1979K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51216-EP
ZHCSQC2A –NOVEMBER 2015 –REVISED JULY 2022
TPS51216-EP 具有同步降压控制器、2A LDO 和缓冲基准的完整DDR2、DDR3
和DDR3L 存储器电源解决方案
1 特性
3 说明
• 同步降压控制器(VDDQ)
TPS51216-EP 以最少总成本和最小空间为 DDR2、
DDR3 和 DDR3L 存储器系统提供完整的电源。它将同
步降压稳压器控制器 (VDDQ) 与 2A 灌电流/拉电流跟
踪 LDO (VTT) 和缓冲低噪声基准 (VTTREF) 相集成。
TPS51216-EP 采用 D-CAP™ 模式与 300kHz/400kHz
频率相结合，以实现易用性和快速瞬态响应。VTTREF
跟踪VDDQ/2 的精度优于 0.8%。能够提供 2A 灌电流/
拉电流峰值电流功能的 VTT 只需 10μF 的陶瓷电容
器。此外，还提供专用的LDO 电源输入。
– 转换电压范围：3 至28 V
– 输出电压范围：0.7 至1.8 V
– 0.8% VREF 精度
– D-CAP™ 模式，可实现快速瞬态响应
– 可选300kHz/400kHz 开关频率
– 自动跳过功能优化了轻负载和重负载时的效率
– 支持S4/S5 状态下的软关闭
– OCL/OVP/UVP/UVLO 保护
– 电源正常输出
TPS51216-EP 提供丰富、实用的功能以及出色的电源
性能。它支持灵活功率级控制，将 VTT 置于高阻抗状
态（处于 S3）并在 S4/S5 状态下对 VDDQ、VTT 和
VTTREF 进行放电（软关闭）。
• 2A LDO (VTT)、缓冲基准(VTTREF)
– 2A（峰值）灌电流和拉电流
– 只需10μF 陶瓷输出电容
– 经缓冲的低噪声10mA VTTREF 输出
– 0.8% VTTREF，20mV VTT 精度
– 在S3 下支持高阻抗，在S4/S5 下支持软关闭
• 热关断
器件信息
器件型号(1)
封装尺寸（标称值）
封装
TPS51216-EP
WQFN (20)
3.00mm × 3.00mm
• 20 引脚3mm × 3mm WQFN 封装
• 支持国防、航天和医疗应用
– 受控基线
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
VIN
– 一个组装/测试基地
– 一个制造基地
– 支持军用（-55°C 至125°C）温度范围，1
– 延长了产品生命周期
– 延长了产品变更通知
5VIN
TPS51216
PGND
VBST 15
12 V5IN
VDDQ
DRVH 14
S3
S5
17 S3
16 S5
SW 13
PGND
– 产品可追溯性
DRVL 11
PGND 10
6
8
7
VREF
2 应用
PGOOD 20
Powergood
REFIN
GND
VDDQSNS
VLDOIN
VTT
9
2
3
1
• DDR2/DDR3/DDR3L 存储器电源
• SSTL_18、SSTL_15、SSTL_135 和HSTL 终端
VTT
19 MODE
18 TRIP
VTTSNS
VTTGND
VTTREF
4
5
VTTREF
PGND
AGND
UDG-10138
AGND
应用示意图
1
提供额外的温度范围- 请联系工厂
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSCA7
TPS51216-EP
ZHCSQC2A –NOVEMBER 2015 –REVISED JULY 2022
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................19
9 Application and Implementation..................................20
9.1 Application Information............................................. 20
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................26
11 Layout...........................................................................27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 28
12 Device and Documentation Support..........................29
12.1 接收文档更新通知................................................... 29
12.2 支持资源..................................................................29
12.3 Trademarks.............................................................29
12.4 Electrostatic Discharge Caution..............................29
12.5 术语表..................................................................... 29
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 Typical Characteristics.............................................. 11
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................16
8.3 Feature Description...................................................16
Information.................................................................... 29
4 Revision History
Changes from Revision * (November 2015) to Revision A (July 2022)
Page
• 更新了整个文档中的表格、图和交叉引用的编号格式.........................................................................................1
• Updated resistor numbers in Equation 7 to match description......................................................................... 24
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5 说明（续）
它还提供具有低侧MOSFET RDS(on) 检测功能的可编程OCL、OVP/UVP/UVLO 以及热关断保护。
TPS51216-EP 采用20 引脚3mm × 3mm WQFN 封装，额定结温为-55°C 至125°C。
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6 Pin Configuration and Functions
20
19
18
17
16
1
2
3
4
5
15
14
13
12
11
VTTSNS
VLDOIN
VTT
VBST
DRVH
SW
Thermal Pad
VTTGND
VTTREF
V5IN
DRVL
6
7
8
9
10
图6-1. RUK Package 20-Pin WQFN Top View
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
DRVH
DRVL
GND
NO.
14
11
7
O
O
High-side MOSFET gate driver output.
Low-side MOSFET gate driver output.
Signal ground.
—
MODE
PGND
PGOOD
19
10
20
I
Connect resistor to GND to configure switching frequency and discharge mode. (See 表8-2.)
Gate driver power ground. RDS(on) current sensing input (+).
—
O
Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.
Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for
stable operation.
REFIN
8
I
SW
S3
13
17
16
I/O
High-side MOSFET gate driver return. RDS(on) current sensing input (–).
S3 signal input. (See 表8-1.)
I
I
S5
S5 signal input. (See 表8-1.)
Connect resistor to GND to set OCL at VTRIP / 8. Output 10-μA current at room temperature, TC = 4700
ppm/°C.
TRIP
18
I
VBST
15
9
I
I
High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin.
VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF.
Power supply input for VTT LDO. Connect VDDQ in typical application.
1.8-V reference output.
VDDQSNS
VLDOIN
VREF
2
I
6
O
O
VTT
3
VTT 2-A LDO output. Need to connect 10 μF or larger capacitance for stability.
Power ground for VTT LDO.
VTTGND
VTTREF
VTTSNS
V5IN
4
—
O
I
5
Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability.
VTT output voltage feedback.
1
12
I
5-V power supply input for internal circuits and MOSFET gate drivers.
Thermal
pad
Connect to GND
—
—
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–5
MAX
36
6
UNIT
VBST
VBST(3)
SW
30
3.6
3.6
0.3
6
Input voltage(2)
VLDOIN, VDDQSNS, REFIN
VTTSNS
V
–0.3
–0.3
–0.3
–0.3
–5
PGND, VTTGND
V5IN, S3, S5, TRIP, MODE
DRVH
36
6
DRVH(3)
–0.3
–2.5
–0.3
–0.3
–0.3
–2.5
–0.3
–55
–55
DRVH(3) (duty cycle < 1%)
VTTREF, VREF
VTT
6
3.6
3.6
6
Output voltage(2)
V
DRVL
DRVL (duty cycle < 1%)
PGOOD
6
6
Junction temperature, TJ
Storage temperature, Tstg
135
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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MAX UNIT
7.3 Recommended Operating Conditions
MIN
4.5
NOM
Supply voltage
V5IN
5.5
33.5
5.5
28
V
VBST
–0.1
–0.1
-3
VBST(2)
SW
SW(1)
28
–4.5
–0.1
–0.1
–0.1
–0.1
–3
Input voltage range
V
VLDOIN, VDDQSNS, REFIN
VTTSNS
3.5
3.5
0.1
5.5
33.5
5.5
33.5
3.5
3.5
5.5
5.5
125
PGND, VTTGND
S3, S5, TRIP, MODE
DRVH
DRVH(2)
–0.1
–4.5
–0.1
–0.1
–0.1
–0.1
–55
DRVH(1)
VTTREF, VREF
VTT
Output voltage range
V
DRVL
PGOOD
TJ
Operating junction temperature
°C
(1) This voltage should be applied for less than 30% of the repetitive period.
(2) Voltage values are with respect to the SW terminal.
7.4 Thermal Information
TPS51216-EP
RUK (WQFN)
20 PINS
94.1
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
58.1
64.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
31.8
ψJT
58.0
ψJB
RθJC(bot)
5.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
TJ = –55°C to 125°C, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE = 0 V, VS3 = VS5 = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
SUPPLY CURRENT
IV5IN(S0)
V5IN supply current, in S0
V5IN supply current, in S3
V5IN shutdown current
TJ = 25°C, No load, VS3 = VS5 = 5 V
TJ = 25°C, No load, VS3 = 0 V, VS5 = 5 V
TJ = 25°C, No load, VS3 = VS5 = 0 V
TJ = 25°C, No load, VS3 = VS5 = 5 V
TJ = 25°C, No load, VS3 = 0 V, VS5 = 5 V
TJ = 25°C, No load, VS3 = VS5 = 0 V
590
500
μA
μA
IV5IN(S3)
IV5INSDN
1
5
5
5
μA
μA
μA
μA
IVLDOIN(S0)
IVLDOIN(S3)
IVLDOINSDN
VREF OUTPUT
VLDOIN supply current, in S0
VLDOIN supply current, in S3
VLDOIN shutdown current
1.8000
IVREF = 30 μA, TJ = 25°C
VVREF
Output voltage
Current limit
V
1.7820
0.4
1.8180
0 μA ≤IVREF <300 μA, TJ = –55°C to 125°C
VVREF = 1.7 V
IVREFOCL
0.8
mA
VTTREF OUTPUT
VVTTREF
Output voltage
VVDDQSNS/2
V
49.2%
49%
10
50.8%
51%
|IVTTREF| <100 μA, 1.2 V ≤VVDDQSNS ≤1.8 V
|IVTTREF| <10 mA, 1.2 V ≤VVDDQSNS ≤1.8 V
VVDDQSNS = 1.8 V, VVTTREF= 0 V
VVTTREF
Output voltage tolerance to VVDDQ
IVTTREFOCLSRC
IVTTREFOCLSNK
IVTTREFDIS
Source current limit
Sink current limit
18
17
mA
mA
mA
VVDDQSNS = 1.8 V, VVTTREF = 1.8 V
10
VTTREF discharge current
TJ = 25°C, VS3 = VS5 = 0 V, VVTTREF = 0.5 V
0.8
1.3
VTT OUTPUT
VVTT
Output voltage
VVTTREF
V
|IVTT| ≤10 mA, 1.2 V ≤VVDDQSNS ≤1.8 V, IVTTREF
0 A
=
20
–20
30
40
|IVTT| ≤1 A, 1.2 ≤VVDDQSNS ≤1.8 V, IVTTREF = 0 A
–30
–40
VVTTTOL
Output voltage tolerance to VTTREF
mV
|IVTT| ≤2 A, 1.4 V ≤VVDDQSNS ≤1.8 V, IVTTREF = 0 A
|IVTT| ≤1.5 A, 1.2 V ≤VVDDQSNS ≤1.4 V, IVTTREF = 0
A
40
–40
VVDDQSNS = 1.8 V, VVTT = VVTTSNS = 0.7 V,
IVTTREF = 0 A
IVTTOCLSRC
IVTTOCLSNK
Source current limit
Sink current limit
2
2
3
3
A
VVDDQSNS = 1.8V, VVTT = VVTTSNS = 1.1 V, IVTTREF = 0
A
IVTTLK
Leakage current
TJ = 25°C , VS3 = 0 V, VS5 = 5 V, VVTT = VVTTREF
VS3 = 5 V, VS5 = 5 V, VVTTSNS = VVTTREF
VS3 = 0 V, VS5 = 5 V, VVTTSNS = VVTTREF
5
0.5
1
IVTTSNSBIAS
IVTTSNSLK
VTTSNS input bias current
VTTSNS leakage current
0.0
0
–0.5
–1
μA
TJ = 25°C, VS3 = VS5 = 0 V, VVDDQSNS = 1.8 V,
VVTT = 0.5 V, IVTTREF = 0 A
IVTTDIS
VTT Discharge current
7.8
mA
VDDQ OUTPUT
VVDDQSNS
VDDQ sense voltage
VREFIN
VDDQSNS regulation voltage
tolerance to REFIN
VVDDQSNSTOL
TJ = 25°C
3
mV
–3
IVDDQSNS
IREFIN
VDDQSNS input current
REFIN input current
VVDDQSNS = 1.8 V
VREFIN = 1.8 V
39
μA
μA
0.0
0.1
–0.1
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, MODE pin pulled
down to GND through 47 kΩ(Non-tracking)
IVDDQDIS
VDDQ discharge current
VLDOIN discharge current
12
mA
A
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, MODE pin pulled
down to GND through 100 kΩ(Non-tracking)
IVLDOINDIS
1.2
SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY
300
400
VIN = 5 V, VVDDQSNS = 1.8 V, RMODE = 100 kΩ
VIN = 5 V, VVDDQSNS = 1.8 V, RMODE = 200 kΩ
VDDQ switching frequency
kHz
ƒSW
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7.5 Electrical Characteristics (continued)
TJ = –55°C to 125°C, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE = 0 V, VS3 = VS5 = 5 V (unless otherwise
noted)
PARAMETER
Minimum on time
Minimum off time
TEST CONDITION
DRVH rising to falling1
MIN
TYP
60
MAX UNIT
tON(min)
ns
tOFF(min)
DRVH falling to rising
200
320
450
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7.5 Electrical Characteristics (continued)
TJ = –55°C to 125°C, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE = 0 V, VS3 = VS5 = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VDDQ MOSFET DRIVER
1.6
0.6
0.9
0.5
10
3.0
1.5
Source, IDRVH = –50 mA
RDRVH
RDRVL
tDEAD
DRVH resistance
DRVL resistance
Dead time
Sink, IDRVH = 50 mA
Source, IDRVL = –50 mA
Sink, IDRVL = 50 mA
DRVH-off to DRVL-on
DRVL-off to DRVH-on
Ω
2.0
1.2
ns
20
INTERNAL BOOT STRAP SW
VFBST
Forward voltage
VV5IN-VBST, TJ = 25°C, IF = 10 mA
0.1
0.2
1.5
V
IVBSTLK
VBST leakage current
TJ = 25°C, VVBST = 33 V, VSW = 28 V
0.01
μA
LOGIC THRESHOLD
IMODE
MODE source current
14
580
15
600
16
620
μA
MODE 0
MODE 1
MODE 2
MODE 3
829
854
879
VTHMODE
MODE threshold voltage
mV
1202
1760
1232
1800
1262
1840
0.5
VIL
S3/S5 low-level voltage
S3/S5 high-level voltage
S3/S5 hysteresis voltage
S3/S5 input leak current
VIH
1.8
V
VIHYST
VILK
0.25
0
1
–1
μA
SOFT START
Internal soft-start time, CVREF = 0.1 μF,
S5 rising to VVDDQSNS > 0.99 × VREFIN
tSS
VDDQ soft-start time
1.1
ms
PGOOD COMPARATOR
PGOOD in from higher
106%
90%
114%
82%
3
108%
92%
116%
84%
5.9
110%
94%
PGOOD in from lower
VTHPG
VDDQ PGOOD threshold
PGOOD out to higher
118%
86%
PGOOD out to lower
IPG
PGOOD sink current
PGOOD delay time
PGOOD start-up delay
VPGOOD = 0.5 V
mA
ms
ns
Delay for PGOOD in
0.8
1
1.2
11
tPGDLY
Delay for PGOOD out, with 100 mV over drive
CVREF = 0.1 μF, S5 rising to PGOOD rising
330
2.5
tPGSSDLY
ms
PROTECTIONS
ITRIP
TRIP source current
TJ = 25°C, VTRIP = 0.4 V
9
10
μA
TRIP source current temperature
coefficient1
ppm/°
C
TCITRIP
VTRIP
4700
VTRIP voltage range
0.2
360
3
390
V
VTRIP = 3.0 V
VTRIP = 1.6 V
VTRIP = 0.2 V
VTRIP = 3.0 V
VTRIP = 1.6 V
VTRIP = 0.2 V
375
200
VOCL
Current limit threshold
190
210
mV
20
25
30
–390
–210
–30
–375
–200
–25
0
–360
–190
–20
VOCLN
Negative current limit threshold
mV
VZC
Zero cross detection offset
mV
V
Wake-up
4.2
3.7
4.4
4.5
4.1
VUVLO
V5IN UVLO threshold voltage
Shutdown
3.9
VOVP
VDDQ OVP threshold voltage
VDDQ OVP propagation delay
OVP detect voltage
With 100 mV over drive
118%
120%
430
122%
tOVPDLY
ns
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7.5 Electrical Characteristics (continued)
TJ = –55°C to 125°C, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE = 0 V, VS3 = VS5 = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITION
UVP detect voltage
MIN
TYP
68%
1
MAX UNIT
VUVP
VDDQ UVP threshold voltage
VDDQ UVP delay
66%
70%
ms
tUVPDLY
tUVPENDLY
VOOB
VDDQ UVP enable delay
OOB threshold voltage
1.2
ms
108%
THERMAL SHUTDOWN
Shutdown temperature1
Hysteresis1
140
10
TSDN Thermal shutdown threshold
°C
1. Ensured by design. Not production tested.
1M
Electromigration fail mode
100k
10k
1k
100
80
90
100
110
120
130
140
150
160
D008
Continuous Junction Temperature (°C)
A. See data sheet for absolute maximum and minimum recommended operating conditions.
B. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
C. Enhanced plastic product disclaimer applies.
图7-1. TPS51216-EP Derating Chart
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7.6 Typical Characteristics
1000
10
8
800
600
400
200
0
6
4
2
0
-55
-55
-25
5
35
65
Junction Temperature (°C)
95
125
-25
5
35
65
Junction Temperature (°C)
95
125
D001
D002
图7-2. V5IN Supply Current vs Junction Temperature
图7-3. V5IN Shutdown Current vs Junction Temperature
10
16
14
12
10
8
8
6
4
2
0
6
4
-55
-25
5
Junction Temperature (°C)
35
65
95
125
-55
-25
5
Junction Temperature (°C)
35
65
95
125
D003
D004
图7-4. VLDOIN Supply Current vs Junction Temperature
图7-5. Current Sense Current vs Junction Temperature
150%
140%
15
UVP
OVP
130%
120%
110%
100%
90%
12
9
6
80%
70%
3
60%
50%
0
-55
-55
-25
5
35
65
Junction Temperature (°C)
95
125
-25
5
35
65
Junction Temperature (°C)
95
125
D005
D006
图7-6. OVP/UVP Threshold vs Junction Temperature
图7-7. VDDQSNS Discharge Current vs Junction Temperature
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7.6 Typical Characteristics (continued)
10
800
700
600
500
400
300
200
RMODE = 100 kΩ
IVDDQ = 10 A
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
8
6
4
2
0
6
8
10
12
14
16
18
20
22
-55
-25
5
35
65
Junction Temperature (°C)
95
125
Input Voltage (V)
D007
图7-9. Switching Frequency vs Input Voltage
图7-8. VTT Discharge Current vs Junction Temperature
800
800
RMODE = 200 kΩ
IVDDQ = 10 A
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
RMODE = 100 kΩ
VIN = 12 V
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
700
600
500
400
300
200
100
0
700
600
500
400
300
200
6
8
10
12
14
16
18
20
22
0
2
4
6
8
10
12
14
16
18
20
Input Voltage (V)
VDDQ Output Current (A)
图7-10. Switching Frequency vs Input Voltage
图7-11. Switching Frequency vs Load Current
800
1.55
RMODE = 200 kΩ
VIN = 12 V
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
RMODE = 200 kΩ
VIN = 12 V
1.54
1.53
1.52
1.51
1.50
1.49
1.48
1.47
1.46
1.45
700
600
500
400
300
200
100
0
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
VDDQ Output Current (A)
VDDQ Output Current (A)
图7-12. Switching Frequency vs Load Current
图7-13. Load Regulation
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7.6 Typical Characteristics (continued)
1.55
0.770
0.765
0.760
0.755
0.750
0.745
0.740
0.735
0.730
RMODE = 200 kΩ
IVDDQ = 0 A
IVDDQ = 20 A
1.54
1.53
1.52
1.51
1.50
1.49
1.48
1.47
1.46
1.45
VVDDQ = 1.5 V
−5
6
8
10
12
14
16
18
20
22
−10
0
5
10
Input Voltage (V)
VTTREF Current (mA)
图7-14. Line Regulation
图7-15. VTTREF Load Regulation
0.695
0.690
0.685
0.680
0.675
0.670
0.665
0.660
0.655
0.650
0.620
0.615
0.610
0.605
0.600
0.595
0.590
0.585
0.580
VVDDQ = 1.35 V
−5
VVDDQ = 1.2 V
−10
0
5
10
−10
−5
0
5
10
VTTREF Current (mA)
VTTREF Current (mA)
图7-16. VTTREF Load Regulation
图7-17. VTTREF Load Regulation
0.790
0.715
0.705
0.695
0.685
0.675
0.665
0.655
0.645
0.635
0.780
0.770
0.760
0.750
0.740
0.730
0.720
0.710
VVDDQ = 1.5 V
VVDDQ = 1.35 V
−2.0 −1.5 −1.0 −0.5
0.0
0.5
1.0
1.5
2.0
−2.0 −1.5 −1.0 −0.5
0.0
0.5
1.0
1.5
2.0
VTT Current (V)
VTT Current (V)
图7-18. VTT Load Regulation
图7-19. VTT Load Regulation
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7.6 Typical Characteristics (continued)
0.640
0.630
0.620
0.610
0.600
0.590
0.580
100
90
80
70
60
50
40
30
20
10
0
VIN = 20 V
VIN = 12 V
VIN = 8 V
VVDDQ = 1.5 V
RMODE = 200 kΩ
0.570
VVDDQ = 1.2 V
0.560
−2.0 −1.5 −1.0 −0.5
0.0
0.5
1.0
1.5
2.0
0.001
0.01
0.1
1
10
100
VTT Current (V)
VDDQ Output Current (A)
图7-20. VTT Load Regulation
图7-22. 1.5-V Load Transient Response
图7-24. 1.5-V Startup Waveforms
图7-21. Efficiency
图7-23. VTT Load Transient Response
图7-25. 1.5-V Startup Waveforms (0.5-V Pre-Biased)
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7.6 Typical Characteristics (continued)
图7-27. 1.5-V Soft-Stop Waveforms (Non-Tracking Discharge)
图7-26. 1.5-V Soft-Stop Waveforms (Tracking Discharge)
80
60
180
135
90
80
60
180
135
90
40
40
20
45
20
45
0
0
0
0
−20
−40
−60
−80
−45
−90
−135
−180
−20
−40
−60
−80
−45
−90
−135
−180
Gain
Phase
Gain
Phase
IVTT = −1 A
IVTT = 1 A
10000
100000
1000000
10000000
10000
100000
1000000
10000000
Frequency (Hz)
Frequency (Hz)
图7-28. VTT Bode Plot (Sink)
图7-29. VTT Bode Plot (Source)
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8 Detailed Description
8.1 Overview
TPS51216-EP provides complete Power Supply Solution for DDR2, DDR3 and DDR3L memory system.
8.2 Functional Block Diagram
UV
OV
20 PGOOD
V
+8/16 %
+
+
+
+
V
–32%
+20%
REFIN
REFIN
REFIN
Delay
V
V
–8/16 %
REFIN
15 mA
Control Logic
REFIN
VREF
8
6
UVP
OVP
On-Time
Discharge Type
Selection
19 MODE
Reference
Soft-Start
PWM
+
+
VBST
15
VDDQSNS
9
14 DRVH
13 SW
10 mA
8 R
TRIP 18
S5 16
OC
+
+
XCON
t
ON
R
One-
Shot
7 R
S3 17
NOC
+
GND
7
12 V5IN
R
11 DRVL
+
ZC
VTT Discharge
VDDQ
Discharge
V5OK VTTREF Discharge
10 PGND
VTTREF
5
2
3
4
VLDOIN
+
+
4.4 V/3.9 V
+
+
+
VTT
VTTSNS
1
VTTGND
TPS51216
UDG-10135
8.3 Feature Description
8.3.1 VDDQ Switch Mode Power Supply Control
TPS51216-EP supports D-CAP mode which does not require complex external compensation networks and is
suitable for designs with small external components counts. The D-CAP mode provides fast transient response
with appropriate amount of equivalent series resistance (ESR) on the output capacitors. An adaptive on-time
control scheme is used to achieve pseudo-constant frequency. The TPS51216-EP adjusts the on-time (tON) to be
inversely proportional to the input voltage (VIN) and proportional to the output voltage (VDDQ). This makes a
switching frequency fairy constant over the variation of input voltage at the steady state condition.
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8.3.2 VREF and REFIN, VDDQ Output Voltage
The part provides a 1.8-V, ±0.8% accurate, voltage reference from VREF. This output has a 300-μA (max)
current capability to drive the REFIN input voltage through a voltage divider circuit. A capacitor with a value of
0.1-μF or larger should be attached close to the VREF terminal.
The VDDQ switch-mode power supply (SMPS) output voltage is defined by REFIN voltage, within the range
between 0.7 V and 1.8 V, programmed by the resister-divider connected between VREF and GND. (See 节
9.2.2.2.) A few nano farads of capacitance from REFIN to GND is recommended for stable operation.
8.3.3 Soft-Start and Powergood
TPS51216-EP provides integrated VDDQ soft-start functions to suppress in-rush current at start-up. The soft-
start is achieved by controlling internal reference voltage ramping up. 图 8-1 shows the start-up waveforms. The
switching regulator waits for 400μs after S5 assertion. The MODE pin voltage is read in this period. A typical
VDDQ ramp up duration is 700μs.
TPS51216-EP has a powergood open-drain output that indicates the VDDQ voltage is within the target range.
The target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay
for assertion (low to high), and ±16% (typ) and 330-ns delay for de-assertion (high to low) during running. The
PGOOD comparator is enabled 1.1 ms after VREF is raised high and the start-up delay is 2.5 ms. Note that the
time constant which is composed of the REFIN capacitor and a resistor divider needs to be short enough to
reach the target value before PGOOD comparator enabled.
S5
VREF
VDDQ
PGOOD
400 ms
700 ms
1.4 ms
UDG-10137
图8-1. Typical Start-up Waveforms
8.3.4 Power State Control
The TPS51216-EP has two input pins, S3 and S5, to provide simple control scheme of power state. All of VDDQ,
VTTREF and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ and
VTTREF voltages are kept on while VTT is turned off and left at high impedance state (high-Z). The VTT output
floats and does not sink or source current in this state. In S4/S5 states (S3=S5=low), all of the three outputs are
turned off and discharged to GND according to the discharge mode selected by MODE pin. Each state code
represents as follow; S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF.
(See 表8-1)
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表8-1. S3/S5 Power State Control
STATE
S0
S3
HI
S5
HI
VREF
VDDQ
VTTREF
ON
VTT
ON
ON
ON
S3
LO
LO
HI
ON
ON
ON
OFF (high-Z)
OFF (discharge)
S4/S5
LO
OFF
OFF (discharge)
OFF (discharge)
8.3.5 Discharge Control
In S4/S5 state, VDDQ, VTT, and VTTREF outputs are discharged based on the respective discharge mode
selected above. The tracking discharge mode discharges VDDQ output through the internal VTT regulator
transistors enabling quick discharge operation. The VTT output maintains tracking of the VTTREF voltage in this
mode. (Refer to 图 7-26.) After 4 ms of tracking discharge operation, the mode changes to non-tracking
discharge. The VDDQ output must be connected to the VLDOIN pin in this mode. The non-tracking mode
discharges the VDDQ and VTT pins using internal MOSFETs that are connected to corresponding output
terminals. The non-tracking discharge is slow compared with the tracking discharge due to the lower current
capability of these MOSFETs. (Refer to 图7-27.)
8.3.6 VTT Overcurrent Protection
The LDO has an internally fixed constant overcurrent limiting of 3-A (typ) for both sink and source operation.
8.3.7 V5IN Undervoltage Lockout (UVLO) Protection
TPS51216-EP has a 5-V supply UVLO protection threshold. When the V5IN voltage is lower than UVLO
threshold voltage, typically 3.93 V, VDDQ, VTT, and VTTREF are shut off. This is a non-latch protection.
8.3.8 Thermal Shutdown
TPS51216-EP includes an internal temperature monitor. If the temperature exceeds the threshold value, 140°C
(typical), VDDQ, VTT and VTTREF are shut off. The thermal shutdown state of VDDQ is open, VTT and
VTTREF are high impedance (high-Z) respectively, and the discharge functions are disabled. This is a non-latch
protection and the operation is restarted with soft-start sequence when the device temperature is reduced by
10°C (typical).
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8.4 Device Functional Modes
8.4.1 MODE Pin Configuration
The TPS51216-EP reads the MODE pin voltage when the S5 signal is raised high and stores the status in a
register. A 15-μA current is sourced from the MODE pin during this time to read the voltage across the resistor
connected between the pin and GND. 表 8-2 shows resistor values, corresponding switching frequency, and
discharge mode configurations.
表8-2. MODE Selection
RESISTANCE BETWEEN
MODE AND GND (kΩ)
SWITCHING
FREQUENCY (kHz)
MODE NO.
DISCHARGE MODE
3
2
1
0
200
100
68
400
300
300
400
Tracking
Non-tracking
47
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
TPS51216-EP is highly integrated synchronous step-down buck solution. The device is used to convert a higher
DC-DC voltage to lower DC output voltage to provide VDDQ and VTT for various DDR memory power solutions.
9.1.1 D-CAP Mode
图9-1 shows a simplified model of D-CAP mode architecture.
V
IN
VDDQSNS
High-Side
MOSFET
DRVH
9
14
PWM
+
Lx
REFIN
VREF
VDDQ
Control
Logic
and
8
6
ESR
R
LOAD
Driver
R1
Low-Side
MOSFET
DRVL
+
C
11
OUT
1.8 V
R2
UDG-10136
图9-1. Simplified D-CAP Model
The VDDQSNS voltage is compared with REFIN voltage. The PWM comparator creates a set signal to turn on
the high-side MOSFET. The gain and speed of the comparator is high enough to maintain the voltage at the
beginning of each on-cycle (or the end of each off-cycle) to be substantially constant. The DC output voltage
monitored at VDDQ may have line regulation due to ripple amplitude that slightly increases as the input voltage
increase. The D-CAP mode offers flexibility on output inductance and capacitance selections and provides ease-
of-use with a low external component count. However, it requires a sufficient amount of output ripple voltage for
stable operation and good jitter performance.
The requirement for loop stability is simple and is described in 方程式 1. The 0-dB frequency, ƒ0 defined in 方程
式1, is recommended to be lower than 1/3 of the switching frequency to secure proper phase margin.
f
1
SW
f =
£
0
2p´ESR ´C
3
OUT
(1)
where
• ESR is the effective series resistance of the output capacitor
• COUT is the capacitance of the output capacitor
• ƒsw is switching frequency
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Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that
determine jitter performance in D-CAP mode is the down-slope angle of the VDDQSNS ripple voltage. 图 9-2
shows, in the same noise condition, a jitter is improved by making the slope angle larger.
V
VDDQSNS
Slope (1)
Jitter
(2)
Slope (2)
Jitter
20 mV
(1)
V
REFIN
V
+Noise
REFIN
t
t
OFF
UDG-10139
ON
图9-2. Ripple Voltage Slope and Jitter Performance
For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period
as shown in 图9-2 and 方程式2.
V
´ESR
OUT
³ 20mV
f
´L
SW
X
(2)
where
• VOUT is the VDDQ output voltage
• LX is the inductance
9.1.2 Light-Load Operation
In auto-skip mode, the TPS51216-EP SMPS control logic automatically reduces its switching frequency to
improve light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent
negative inductor current by turning off the low-side MOSFET. 方程式 3 shows the boundary load condition of
this skip mode and continuous conduction operation.
V
- V
(
OUT ) V
1
IN
OUT
I
=
´
´
LOAD(LL)
2´L
V
f
SW
X
IN
(3)
9.1.3 VTT and VTTREF
TPS51216-EP integrates two high performance, low-dropout linear regulators, VTT and VTTREF, to provide
complete DDR2/DDR3/DDR3L power solutions. The VTTREF has a 10-mA sink/source current capability, and
tracks ½ of VDDQSNS with ±1% accuracy using an on-chip ½ divider. A 0.22-μF (or larger) ceramic capacitor
must be connected close to the VTTREF terminal for stable operation. The VTT responds quickly to track
VTTREF within ±40 mV at all conditions, and the current capability is 2 A for both sink and source. A 10-μF (or
larger) ceramic capacitor must be connected close to the VTT terminal for stable operation. To achieve tight
regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to
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the positive node of the VTT output capacitors as a separate trace from the high-current line to the VTT pin.
(Refer to 节11.1 for details.)
When VTT is not required in the design, the following treatments are strongly recommended.
• Connect VLDOIN to VDDQ.
• Tie VTTSNS to VTT, and remove capacitors from VTT to float.
• Connect VTTGND to GND.
• Select MODE 0 or MODE 1 shown in 表8-2 (select non-tracking discharge mode).
• Maintain a 0.22-µF capacitor connected at VTTREF.
• Pull down S3 to GND with 1-kΩresistance.
VIN
5VIN
TPS51216
PGND
VBST 15
V5IN
12
VDDQ
DRVH 14
SW 13
17 S3
16 S5
S5
1 kW
DRVL 11
PGND 10
6
8
7
VREF
PGND PGND
PGOOD 20
Powergood
REFIN
GND
VDDQSNS
9
2
3
1
4
5
VLDOIN
VTT
19 MODE
18 TRIP
VTTSNS
VTTGND
VTTREF
0.22 mF
AGND
AGND PGND
PGND
UDG-13089
图9-3. Application Circuit When VTT is not Required
9.1.4 VDDQ Overvoltage and Undervoltage Protection
TPS51216-EP sets the overvoltage protection (OVP) when the VDDQSNS voltage reaches a level 20% (typ)
higher than the REFIN voltage. When an OV event is detected, the controller latches DRVH low and DRVL high.
VTTREF and VTT are turned off and discharged using the non-tracking discharge MOSFETs regardless of the
tracking mode.
The undervoltage protection (UVP) latch is set when the VDDQSNS voltage remains lower than 68% (typ) of the
REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DRVH low and DRVL low and
discharges the VDDQ, VTT, and VTTREF outputs. UVP detection function is enabled after 1.2 ms of SMPS
operation to ensure startup.
To release the OVP and UVP latches, toggle S5 or adjust the V5IN voltage down and up beyond the
undervoltage lockout threshold.
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9.1.5 VDDQ Overcurrent Protection
The VDDQ SMPS has cycle-by-cycle overcurrent limiting protection. The inductor current is monitored during the
off-state using the low-side MOSFET RDS(on) and the controller maintains the off-state while the voltage across
the low-side MOSFET is larger than the overcurrent trip level. The current monitor circuit inputs are PGND and
SW pins so that those should be properly connected to the source and drain terminals of low-side MOSFET. The
overcurrent trip level, VTRIP, is determined by 方程式4.
V
= R
´I
TRIP TRIP
TRIP
(4)
where
• RTRIP is the value of the resistor connected between the TRIP pin and GND
• ITRIP is the current sourced from the TRIP pin. ITRIP is 10 μA typically at room temperature, and has 4700
ppm/°C temperature coefficient to compensate the temperature dependency of the low-side MOSFET
RDS(on)
.
Because the comparison is done during the off-state, VTRIP sets the valley level of the inductor current. The load
current OCL level, IOCL, can be calculated by considering the inductor ripple current as shown in 方程式5.
æ
ç
ö
÷
æ
ç
ö
÷
I
IND ripple
(
V
IN - VOUT
VOUT
VTRIP
VTRIP
)
1
2
IOCL
=
+
=
+
´
´
ç
÷
ç
÷
8´RDS on
2
8´RDS on
LX
fSW ´ V
IN
( )
( )
è
ø
è
ø
(5)
where
• IIND(ripple) is inductor ripple current
In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down.
9.2 Typical Application
V5IN
4.5 V to 5.5 V
R2 200 kW
R1
100 kW
R3 36 kW
S5
S3
AGND
C12
10 mF
V
IN
8 V to 20
21
20
19
18
17
16
C7
0.1 mF
C8
10 mF
C9
10 mF
C10
10 mF
C5
0.1 mF
R6
0 W
PGND
VBST 15
DRVH 14
SW 13
VTT
0.75 V/2 A
1
2
3
VTTSNS
VLDOIN
VTT
R7 0 W
PGND
L1
0.56 mH
Q1
FDMS8680
C1
10 mF
U1
TPS51216RUK
VDDQ
1.5 V/20
VTTGND
4
5
VTTGND
VTTREF
V5IN 12
DRVL 11
Q2
FDMS8670AS
Q3
FDMS8670AS
PGND
C6
1 mF
C11
330 mF
6
7
8
9
10
VTTREF
0.75 V
VDDQ_G
R4
10 kW
R5
49 kW
PGND AGND
C2 C3
0.22 mF 0.1 mF
C4
10 nF
UDG-10165
图9-4. DDR3, 400-kHz Application Circuit, Tracking Discharge
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9.2.1 Design Requirements
See 表9-1 for the design parameters.
表9-1. Design Parameters
VIN
VDDQ
IVDDQ
VTT
IVTT
FSW
8 to 20 V
1.5 V
20 A
0.75 V
2 A
400 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 List of Materials
表9-2. DDR3, 400-kHz Application Circuit, List of Materials
REFERENCE DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
Taiyo Yuden
Panasonic
Panasonic
Fairchild
PART NUMBER
TMK325BJ106MM
EEFSX0D331XE
ETQP4LR56WFC
FDMS8680
C8, C9, C10
C11
3
1
1
1
2
10 µF, 25 V
330 µF, 2V, 6 mΩ
L1
0.56 µH, 21 A, 1.56 mΩ
30 V, 35 A, 8.5 mΩ
30 V, 42 A, 3.5 mΩ
Q1
Q2, Q3
FDMS8670AS
Fairchild
For this example, the bulk output capacitor ESR requirement for D-CAP mode is described in 方程式 6,
whichever is greater.
20mV ´ f
´L
3
SW
ESR ³
or ESR ³
V
2p´ f
´ C
OUT
SW OUT
(6)
9.2.2.2 External Components Selection
The external components selection is simple in D-CAP mode.
1. Determine the value of R4 and R5.
The output voltage is determined by the value of the voltage-divider resistor, R4 and R5, as shown in 图9-4.
R4 is connected between VREF and REFIN pins, and R5 is connected between the REFIN pin and GND.
Setting R4 as 10-kΩis a good starting point. Determine R5 using 方程式7.
(7)
2. Choose the inductor.
The inductance value should be determined to yield a ripple current of approximately ¼ to ½ of maximum
output current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio
and helps stable operation.
V
(
IN
max
(
- V
´ V
)
V
(
IN
max
(
- V
´ V
OUT OUT
OUT
OUT
)
)
)
1
3
L
=
´
=
´
X
I
´ f
V
I
´ f
V
IN
SW
IN
max
(
O
SW
IND ripple
(
max
max
)
)
(
)
(
)
(8)
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The inductor needs a low direct current resistance (DCR) to achieve good efficiency, as well as enough room
above peak inductor current before saturation. The peak inductor current can be estimated in 方程式9.
V
(
IN
max
(
- V
´ V
OUT OUT
)
)
V
1
TRIP
I
=
+
´
IND peak
(
)
8´R
L ´ f
V
IN
X
SW
DS on
max
( )
(
)
(9)
3. Choose the OCL setting resistance, RTRIP
.
Combining 方程式4 and 方程式5, RTRIP can be obtained using 方程式10.
æ
ö
÷
÷
ø
æ
ç
ç
è
ö
÷
÷
ø
V
IN - VOUT
(
)
VOUT
ç
8´ I
-
´
´RDS(on)
ç OCL
2´L
f
(
´ V
IN
(
)
)
X
SW
è
RTRIP
=
ITRIP
(10)
4. Choose the output capacitors.
TI recommends organic semiconductor capacitors or specialty polymer capacitors. Determine ESR to meet
small signal stability and recommended ripple voltage. A quick reference is shown in 方程式11 and 方程式
12.
f
1
SW
£
2p´ESR´ C
3
OUT
(11)
(12)
V
´ESR
OUT
³ 20mV
f
´L
SW
X
9.2.3 Application Curve
图9-5. Output Ripple
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10 Power Supply Recommendations
TPS51216-EP is designed to operate from input voltage supply range of 8 to 20 V. This supply must be well
regulated. The power supply must be well bypassed for proper electrical performance. See 节 11.2 for
recommended bypass capacitor placement.
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11 Layout
11.1 Layout Guidelines
Certain issues must be considered before designing a layout using the TPS51216-EP.
• VIN capacitors, VOUT capacitors, and MOSFETs are the power components and should be placed on one
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the
small signal traces from noisy power lines.
• All sensitive analog traces and components such as VDDQSNS, VTTSNS, MODE, REFIN, VREF, and TRIP
should be placed away from high-voltage switching nodes such as SW, DRVL, DRVH, or VBST to avoid
coupling. Use internal layers as ground planes and shield feedback trace from power traces and components.
• The DC/DC converter has several high-current loops. The area of these loops should be minimized in order
to suppress generating switching noise.
– The most important loop to minimize the area of is the path from the VIN capacitors through the high and
low-side MOSFETs, and back to the capacitors through ground. Connect the negative node of the VIN
capacitors and the source of the low-side MOSFET at ground as close as possible. (Refer to loop number
1 of 图11-1)
– The second important loop is the path from the low-side MOSFET through inductor and VOUT capacitors,
and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET
and negative node of VOUT capacitors at ground as close as possible. (Refer to loop number 2 of 图11-1)
– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side
MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back
to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows
from gate of the low-side MOSFET through the gate driver and PGND, and back to source of the low-side
MOSFET through ground. Connect negative node of V5IN capacitor, source of the low-side MOSFET and
PGND at ground as close as possible. (Refer to loop number 3 of 图11-1)
• Because the TPS51216-EP controls output voltage referring to voltage across VOUT capacitor, VDDQSNS
should be connected to the positive node of VOUT capacitor. In a same manner GND should be connected to
the negative node of VOUT capacitor.
• Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
• Connect the frequency and mode setting resistor from MODE pin to ground, and make the connections as
close as possible to the device. The trace from the MODE pin to the resistor and from the resistor to ground
should avoid coupling to a high-voltage switching node
• Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and vias of at least 0.5
mm (20 mils) diameter along this trace.
• The PCB trace defined as SW node, which connects to the source of the switching MOSFET, the drain of the
rectifying MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.
• VLDOIN should be connected to VDDQ output with short and wide traces. An input bypass capacitor should
be placed as close as possible to the pin with short and wideꢀconnections.
• The output capacitor for VTT should be placed close to the pin with a short and wide connection in order toꢀ
avoid additional ESR and/or ESL of the trace.
• VTTSNS should be connected to the positive node of the VTT output capacitors as a separate trace from the
high-current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed toꢀ
sense the voltage at the point of the load, it is recommended to attach the output capacitors at that point.
Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and
the output capacitors.
• Consider adding a low pass filter (LPF) at VTTSNS in case the ESR of the VTT output capacitors is larger
than 2 mΩ.
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• VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the
reference voltage of VTTREF. Avoid any noise generative lines.
• The negative node of the VTT output capacitors and the VTTREF capacitor should be tied together by
avoidingꢀcommon impedance to high-current path of the VTT source/sink current.
• GND pin node represents the reference potential for VTTREF and VTT outputs. Connect GNDꢀto negative
nodes of VTT capacitors, VTTREF capacitor and VDDQ capacitors with care to avoid additional ESR and/or
ESL. GND and PGND should be connected together at a single point.
• In order to effectively remove heat from the package, prepare the thermal land and solder to the package
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side ground
planes should be used to help dissipation.
CAUTION
Do not connect PGND pin directly to this thermal land underneath the package.
11.2 Layout Example
2
TPS51216
VLDOIN
VIN
VTT
VTT
3
4
10 mF
VTTGND
VTTGND
V5IN
#1
12
V
OUT
VTTREF
MODE
TRIP
1 mF
#2
5
DRVL
PGND
0.22 mF
11
10
19
18
#3
VREF
REFIN GND
8 7
6
0.1 mF
10 nF
UDG-10166
图11-1. DC/DC Converter Ground System
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
D-CAP™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS51216MRUKREP
V62/16601-01XE
ACTIVE
ACTIVE
WQFN
WQFN
RUK
RUK
20
20
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 125
-55 to 125
51216M
51216M
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2022
OTHER QUALIFIED VERSIONS OF TPS51216-EP :
Catalog : TPS51216
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51216MRUKREP
WQFN
RUK
20
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RUK 20
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TPS51216MRUKREP
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RUK0020B
WQFN - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
0.5
0.3
PIN 1 INDEX AREA
3.1
2.9
0.25
0.15
DETAIL
OPTIONAL TERMINAL
TYPICAL
DIMENSION A
OPTION 01
OPTION 02
(0.1)
(0.2)
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
(DIM A) TYP
OPT 02 SHOWN
1.7 0.05
6
10
EXPOSED
THERMAL PAD
16X 0.4
5
11
21
SYMM
4X
1.6
1
15
SEE TERMINAL
DETAIL
0.25
20X
0.15
0.1
C A
B
20
16
PIN 1 ID
SYMM
0.05
(OPTIONAL)
0.5
0.3
20X
4222676/A 02/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RUK0020B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.7)
SYMM
20
16
20X (0.6)
1
15
20X (0.2)
(0.6)
TYP
21
SYMM
(2.8)
16X (0.4)
5
11
(R0.05)
TYP
(
0.2) TYP
VIA
6
10
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222676/A 02/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RUK0020B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.47) TYP
16
(R0.05) TYP
20
20X (0.6)
1
15
21
20X (0.2)
(0.47)
TYP
SYMM
(2.8)
16X (0.4)
11
5
METAL
TYP
6
10
4X ( 0.75)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 21:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222676/A 02/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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TI
TPS51217
HIGH PERFORMANCE, SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER FOR NOTEBOOK POWER SUPPLYWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS51217DSCR
HIGH PERFORMANCE, SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER FOR NOTEBOOK POWER SUPPLYWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS51217DSCT
HIGH PERFORMANCE, SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER FOR NOTEBOOK POWER SUPPLYWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS51218
HIGH PERFORMANCE, SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER FOR NOTEBOOK POWER SUPPLYWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS51218DSCR
HIGH PERFORMANCE, SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER FOR NOTEBOOK POWER SUPPLYWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS51218DSCT
HIGH PERFORMANCE, SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER FOR NOTEBOOK POWER SUPPLYWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS51218_16
HIGH PERFORMANCE, SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER FOR NOTEBOOK POWER SUPPLYWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS51219
High Performance, Single-Synchronous Step-Down Controller with Differential Voltage FeedbackWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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