TPS51222 [TI]
Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller; 固定频率， 99 ％占空比峰值电流模式笔记本系统功率控制器
| 型号： | TPS51222 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller |
| 文件： | 总42页 (文件大小：1033K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51222
www.ti.com ............................................................................................................................................................................................... SLUS908–JANUARY 2009
Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller
1
FEATURES
2
•
•
•
Input Voltage Range: 4.5 V to 32 V
APPLICATIONS
•
Notebook Computer System and I/O Bus
Output Voltage Range: 1 V to 12 V
•
Point of Load in LCD TV, MFP
Selectable Light Load Operation
(Continuous / Auto Skip / Out-Of-Audio™ Skip)
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Programmable Droop Compensation
Voltage Servo Adjustable Soft Start
200-kHz to 1-MHz Fixed-Frequency PWM
Current Mode Architecture
The TPS51222 is a dual synchronous buck regulator
controller with two LDOs. It is optimized for 5-V/3.3-V
system controller, enabling designers to cost
effectively complete 2-cell to 4-cell notebook system
power supply. The TPS51222 supports high
efficiency, fast transient response, and 99% duty
cycle operation. It supports supply input voltage
ranging from 4.5 V to 32 V, and output voltages from
1 V to 12 V. Peak current mode supports stability
operation with lower ESR capacitor and output
accuracy. The high duty cycle (99%) operation and
the wide input/output voltage range supports flexible
design for small mobile PCs and a wide variety of
other applications. The fixed frequency can be
adjusted from 200 kHz to 1 MHz by a resistor, and
each channel runs 180° out-of-phase. The TPS51222
can also synchronize to the external clock, and the
interleaving ratio can be adjusted by its duty. The
TPS51222 is available in the 32-pin 5 × 5 QFN
package and is specified from –40°C to 85°C.
180° Phase Shift Between Channels
Resistor or Inductor DCR Current Sensing
Current Monitor Output for Each Channel
Adaptive Zero Crossing Circuit
Powergood Output for Each Channel
OCL/OVP/UVP/UVLO Protections
Thermal Shutdown (Non-Latch)
Output Discharge Function
Integrated Boot Strap MOSFET Switch
QFN-32 (RTV) Package
VBAT
VREG5
5 V/
VBAT
100 mA
VO2
3.3 V
VO1
5 V
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
DRVH1
V5SW
RF
DRVH2 24
VIN 23
VO1
VBAT
EN2
VREG3
3.3 V/
VREG3 22
EN2 21
10 mA
EN1
PGOOD1
SKIPSEL1
EN1
TPS51222RTV
PGOOD1
SKIPSEL1
CSP1
PGOOD2 20
SKIPSEL2 19
CSP2 18
PGOOD2
SKIPSEL2
CSN1
CSN2 17
9
10 11 12 13 14 15 16
EN
IMON1
VO1
IMON2
VO2
UDG-09009
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Out-Of-Audio, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS51222
SLUS908–JANUARY 2009............................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
V5SW
1.25V
4.7V/ 4.5V
EN1 OK
+
+
+
+
4.7V/ 4.5V
VREG3
V5SW OK
VREG5
GND
+
V5OK
THOK
4.2V/ 3.8V
Ready
GND
+
VREF2
150/ 140
Deg-C
1.25V
GND
GND
CLK2
CLK1
OSC
RF
GND
1V +5%/ 10%
+
+
PGOOD1
Delay
1V - 5%/ 10%
1V -30%
+
+
GND
UVP
CLK1
Ready
Fault2
SDN2
OVP
1V +15%
Clamp (+)
Fault1
SDN1
COMP1
VFB1
Ramp
Comp
+
Clamp (-)
+ PWM
VREG5
1V
Enable/
Soft-start
+
+
VFB-AMP
EN1
VREF2
VBST1
DRVH1
SW1
Ramp
Comp
Control
Logic
IMON1
+
Filter
Amp.
Skip
CS-AMP
CSN1
CSP1
+
OCP
XCON
+
VREG5
100mV
DRVL1
AZC
Discharge
Control
GND
GND
N-OCP
+
100mV
VREF2
GND
OOA
Ctrl
GND
SKIPSEL1
Channel-1 Switcher shown
2
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TPS51222
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
TPS51222
–0.3 to 34
–0.3 to 39
–0.3 to 7
–5 to 34
–1 to 13.5
–0.3 to 7
–1 to 7
UNIT
VIN
VBST1, VBST2
VBST1, VBST2(3)
SW1, SW2
(2)
Input voltage range
V
CSN1, CSN2, CSP1, CSP2
EN, EN1, EN2, SKIPSEL1, SKIPSEL2, VFB1, VFB2
V5SW
V5SW (to VREG5)(4)
–7 to 7
DRVH1, DRVH2
–5 to 39
–0.3 to 7
V
V
(3)
DRVH1, DRVH2
Output voltage range(2)
COMP1, COMP2, DRVL1, DRVL2, IMON1, IMON2, PGOOD1,
PGOOD2, RF, VREF2, VREG5
–0.3 to 7
V
VREG3
–0.3 to 3.6
150
V
TJ
Junction temperature
Storage temperature
°C
°C
Tstg
–55 to 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the corresponding SW terminal.
(4) When EN is high and V5SW is grounded, or voltage is applied to V5SW when EN is low.
DISSIPATION RATINGS (2 oz. Trace and Copper Pad with Solder)
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
32-pin RTV
1.7 W
17 mW/°C
0.7 W
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
TYP
MAX
32
6
UNIT
VIN
Supply voltage
V
V5SW
–0.8
–0.1
–4.0
–0.1
–4.0
–0.8
VBST1, VBST2
37
37
6
DRVH1, DRVH2
DRVH1, DRVH2 (wrt SW1, 2)
SW1, SW2
32
13
I/O voltage
V
CSP1, CSP2, CSN1, CSN2
COMP1, COMP2, DRVL1, DRVL2, EN, EN1, EN2, IMON1, IMON2,
PGOOD1, PGOOD2, RF, SKIPSEL1, SKIPSEL2, VFB1, VFB2,
VREF2, VREG5
–0.1
6
VREG3
–0.1
–40
3.5
85
TA
Operating free-air temperature
°C
ORDERING INFORMATION
ORDERABLE PART
TA
-40°C to 85°C
PACKAGE(1)
TRANSPORT MEDIA
QUANTITY
ECO PLAN
NUMBER
TPS51222RTVT
TPS51222RTVR
Tape and Reel
Tape and Reel
250
Plastic Quad Flat Pack
(32-Pin QFN)
Green (RoHS
and no Sb/Br)
3000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2009, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN shutdown current, TA = 25°C,
No Load, EN = 0V, V5SW = 0 V
I(VINSDN)
VIN shutdown current
VIN Standby Current
Vbat Standby Current
V5SW Supply Current
7
80
15
µA
µA
µA
mA
VIN standby current, TA = 25°C, No Load,
EN1 = EN2 = V5SW = 0 V
I(VINSTBY)
I(VBATSTBY)
120
Vbat standby current, TA = 25°C, No Load
500
0.8
SKIPSEL2 = 2V, EN2 = open, EN1 = V5SW = 0V(1)
V5SW current, TA = 25°C, No Load,
ENx = 5V, VFBx = 1.05 V
I(V5SW)
VREF2 OUTPUT
I(VREF2) < ±10 µA, TA = 25°C
1.98
1.97
2.00
2.00
2.02
2.03
V(VREF2)
VREF2 Output Voltage
V
I(VREF2) < ±100 µA, 4.5V < VIN < 32 V
VREG3 OUTPUT
V5SW = 0 V, I(VREG3) = 0 mA, TA = 25°C
3.279
3.135
10
3.313
3.300
15
3.347
3.400
20
V(VREG3)
VREG3 Output Voltage
VREG3 Output Current
V
V5SW = 0 V, 0 mA < I(VREG3) < 10 mA,
5.5 V < VIN < 32 V
I(VREG3)
VREG3 = 3 V
mA
VREG5 OUTPUT
V5SW = 0 V, I(VREG5) = 0 mA, TA = 25°C
4.99
4.90
5.04
5.03
5.09
5.15
V
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA,
6 V < VIN < 32 V
V(VREG5)
VREG5 Output Voltage
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA,
5.5 V < VIN < 32 V
4.50
5.03
5.15
V
V5SW = 0 V, VREG5 = 4.5 V
V5SW = 5 V, VREG5 = 4.5 V
Turning on
100
200
150
300
4.7
200
400
4.8
I(VREG5)
VREG5 Output Current
Switchover Threshold
mA
4.55
0.15
V(THV5SW)
V
Hysteresis
0.20
7.7
0.25
td(V5SW)
Switchover Delay
5V SW Ron
Turning on
ms
R(V5SW)
OUTPUT
I(VREG5) = 100 mA
0.5
Ω
TA = 25°C, No Load
0.9925
0.990
–50
1.000
1.000
1.0075
1.010
50
VFB Regulation Voltage
Tolerance
V(VFB)
V
TA = –40°C to 85°C , No Load
VFBx = 1.05 V, COMPx = 1.8 V, TA = 25°C
I(VFB)
VFB Input Current
nA
R(Dischg)
CSNx Discharge Resistance ENx = 0 V, CSNx = 0.5 V, TA = 25°C
20
40
Ω
VOLTAGE TRANSCONDUCTANCE AMPLIFIER
Gmv
VID
Gain
TA = 25°C
500
µS
Differential Input Voltage
Range
–30
30
mV
TA = 0 to 85°C
27
22
33
33
µA
µA
COMP Maximum Sink
Current
I(COMPSINK)
COMPx = 1.8 V
COMPx = 1.8 V
TA = –40 to 85°C
COMP Maximum Source
Current
I(COMPSRC)
VCOMP
–33
2.22
1.77
–43
2.26
1.81
µA
V
COMP Clamp Voltage
2.18
1.73
COMP Negative Clamp
Voltage
VCOMPN
V
(1) Specified by design. Detail external condition follows application circuit of Figure 52.
4
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TPS51222
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
CURRENT AMPLIFIER
TEST CONDITIONS
CSNx = 5V, TA = 25°C(2)
MIN
TYP
MAX
UNIT
GC
VIC
Gain
1.667
Common mode Input
Voltage Range
0
13
75
V
Differential Input Voltage
Range
VID
TA = 25°C
–75
mV
POWERGOOD
PG in from lower
PG in from higher
PG hysteresis
92.5%
95%
105%
5%
5
97.5%
V(THPG)
PG threshold
102.5%
107.5%
I(PG)
PG sink Current
PGOOD Delay
PGOOD = 0.5 V
Delay for PG in
mA
ms
t(PGDLY)
SOFTSTART
t(SSDYL)
t(SS)
0.8
1
1.2
Soft Start Delay
Soft Start Time
Delay for Soft Start, ENx = Hi to SS-ramp starts
Internal Soft Start
200
960
µs
µs
FREQUENCY AND DUTY CONTROL
f(SW)
Switching Frequency
Rf = 330 kΩ
Lo to Hi
273
0.7
303
1.3
0.2
333
2
kHz
V
V(THRF)
RF Threshold
Hysteresis
V
Sync Input Frequency
Range(2)
f(SYNC)
200
1000
kHz
V(DRVH) = 90% to 10%, No Load, CCM/ OOA(2)
V(DRVH) = 90% to 10%, No Load, Auto-skip
V(DRVH) = 10% to 90%, No Load
DRVH-off to DRVL-on
120
160
290
30
40
1
ns
ns
ns
ns
ns
V
tONmin
tOFFmin
tD
Minimum On Time
Minimum Off Time
Dead time
250
400
50
10
30
DRVL-off to DRVH-on
70
(2)
V(DTH)
V(DTL)
DRVH-off threshold
DRVL-off threshold
DRVH to GND
DRVL to GND(2)
1
V
CURRENT SENSE
TA = 0 to 85°C
56
55
55
54
60
60
60
60
5
65
68
67
72
2 V< VCSNx < 12.6 V
TA = –40 to 85°C
TA = 0 to 85°C
TA = –40 to 85°C
Positive
V(OCL)
Current limit threshold
mV
0.95 V < VCSNx < 12.6 V
Auto-Zero cross adjustable
offset range
VZCAJ
0.95 V < VCSNx < 12.6 V, Auto-skip
0.95 V < VCSNx < 12.6 V, OOA
0.95 V < VCSNx < 12.6 V
mV
mV
Negative
–5
Zero cross detection
comparator Offset
V(ZC)
–4
0
4
TA = 0 to 85°C
–50
–49
–60
–60
–73
–77
Negative current limit
threshold
V(OCLN-LV)
TA = –40 to 85°C
(2) Specified by design.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
OUTPUT DRIVERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Source, V(VBST-DRVH) = 0.1 V
1.7
1
5
3
4
2
R(DRVH)
DRVH resistance
DRVL resistance
Ω
Ω
Sink, V(DRVH-SW) = 0.1 V
Source, V(VREG5-DRVL) = 0.1 V
Sink, V(DRVL-GND) = 0.1 V
1.3
0.7
R(DRVL)
CURRENT MONITOR
GIMON Current monitor gain
50
VCSPx–VCSNx = 60 mV, 0.95 V < VCSNx < 12.6 V,
TA = 25°C
VIMON
Current monitor output
2.75
3.00
3.25
200
V
VCSPx–VCSNx = 0 mV, 0.95 V < VCSNx < 12.6 V,
TA = 25°C
VIMON-OFF
Current monitor output offset
–200
mV
UVP, OVP AND UVLO
V(OVP)
OVP Trip Threshold
OVP detect
UVP detect
110%
115%
1.5
120%
t(OVPDLY)
V(UVP)
OVP Prop Delay
UVP Trip Threshold
UVP Delay
µs
65%
0.8
1.7
75
70%
1
73%
1.2
t(UVPDLY)
ms
V
Wake up
Hysteresis
Wake up
Hysteresis
Wake up
Hysteresis
1.8
1.9
V(UVREF2)
V(UVREG3)
V(UVREG5)
VREF2 UVLO Threshold
VREG3 UVLO Threshold
VREG5 UVLO Threshold
100
3.1
125
3.2
mV
3
V
0.10
4.1
0.35
0.15
4.2
0.20
4.3
V
V
0.40
0.44
INTERFACE AND LOGIC THRESHOLD
Wake up
Hysteresis
Wake up
Hysteresis
0.8
0.1
1
0.2
1.2
0.3
V(EN)
EN Threshold
V
0.45
0.1
0.50
0.2
0.55
0.3
V(EN12)
EN1/EN2 Threshold
V
V
EN1/EN2 SS Start
Threshold
V(EN12SS)
SS-ramp start threshold at external soft start
1
(3)
V(EN12SSEND)
I(EN12)
EN1/EN2 SS End Threshold SS-End threshold at external soft start
2
2
V
EN1/EN2 Source Current
VEN1/EN2 = 0V
Continuous
1.6
2.4
1.5
2.1
3.4
µA
Auto Skip
1.9
3.2
SKIPSEL1/SKIPSEL2
Setting Voltage
V(SKIPSEL)
V
OOA Skip (min 1/8 Fsw)
OOA Skip (min 1/16 Fsw)
SKIPSELx = 0 V
SKIPSELx = 5 V
3.8
–0.5
–0.5
0.5
0.5
I(SKIPSEL)
SKIPSEL Input Current
µA
BOOT STRAP SW
V(FBST) Forward Voltage
I(BSTLK) VBST Leakage Current
THERMAL SHUTDOWN
VVREG5-VBST, IF = 10 mA, TA = 25°C
VVBST = 37 V, VSW = 32 V
0.10
0.01
0.20
1.5
V
µA
Shutdown temperature(3)
Hysteresis(3)
150
10
T(SDN)
Thermal SDN Threshold
°C
(3) Specified by design.
6
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DEVICE INFORMATION
PINOUT
RTV PACKAGE
(TOP VIEW)
DRVH1
V5SW
1
2
3
4
5
6
7
8
24
23
22
21
20
19
DRVH2
VIN
RF
VREG3
EN2
TPS51122
EN1
PGOOD1
SKIPSEL1
CSP1
PGOOD2
SKIPSEL2
CSP2
18
17
CSN2
CSN1
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
COMP1
COMP2
CSN1
NO.
10
15
8
Loop compensation pin for current mode (error amplifier output). Connect R (and C if required) from this pin
to VREF2 for proper loop compensation with current mode operation.
I
I
Current sense comparator inputs (–). See the current sensing scheme section. Used as power supply for the
current sense circuit for 5 V or higher output voltage setting. Also, used for output discharge terminal.
CSN2
17
7
CSP1
Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should
be used to extract voltage drop across DCR. 0.1-µF is a good value to start the design. See the current
sensing scheme section for more details.
I/O
O
CSP2
18
DRVH1
DRVH2
DRVL1
DRVL2
1
High-side MOSFET gate driver outputs. Source 1.7 Ω, sink 1.0 Ω, SW-node referenced floating driver. Drive
voltage corresponds to VBST to SW voltage.
24
30
27
O
I
Low-side MOSFET gate driver outputs. Source 1.3 Ω, sink 0.7 Ω, and GND referenced driver.
VREF2 and VREG5 linear regulators enable pin. When turning on, apply greater than 1.2 V and less than 6
V. Connect to GND to disable.
EN
12
EN1
4
Channel 1 and channel 2 SMPS Enable Pins. When turning on, apply greater than 0.55 V and less than 6 V.
Connect to GND to disable. Adjustable soft-start capacitance to be attached here.
I
EN2
21
28
11
14
5
GND
–
Ground
IMON1
IMON2
O
Current monitor outputs for channel 1 and channel 2. Adding an RC filter is recommended.
PGOOD1
PGOOD2
Powergood window comparator outputs for channel 1 and channel 2. The recommended applied voltage
should be less than 6 V, and the recommended pull-up resistance value is from 100 kΩ to 1 MΩ.
O
20
Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for
synchronization.
RF
3
I/O
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PIN FUNCTIONS (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
SKIPSEL1
6
Skip mode selection pin.
GND: Continuous conduction mode
VREF2: Auto Skip
I
SKIPSEL2
19
VREG3: OOA Auto Skip, maximum 7 skips (suitable for fsw < 400kHz)
VREG5: OOA Auto Skip, maximum 15 skips (suitable for equal to or greater than 400kHz)
SW2
SW1
25
32
I/O
I
High-side MOSFET gate driver returns.
VREG5 switchover power supply input pin. When EN1 is high, PGOOD1 indicates GOOD and V5SW
voltage is higher than 4.8 V, switch-over function is enabled.
Note: When switch-over is enabled, VREG5 output voltage is approximately equal to the V5SW input
voltage.
V5SW
2
VBST1
VBST2
31
26
Supply inputs for high-side N-channel FET driver (boot strap terminal). Connect a capacitor (0.1-µF or
greater is recommended) from this pin to respective SW terminal. Additional SB diode from VREG5 to this
pin is an optional.
I
I
VFB1
VFB2
VIN
9
SMPS voltage feedback Inputs. Connect the feedback resistors divider, and should be referred to (signal)
GND.
16
23
13
I
Supply input for 5-V and 3.3-V linear regulator. Typically connected to VBAT.
VREF2
O
2-V reference output. Bypass to (signal) GND with 0.22-µF of ceramic capacitance.
Always alive 3.3 V, 10 mA low dropout linear regulator output. Bypass to (signal) GND with more than 1-µF
ceramic capacitance. Runs from VIN supply or from VREG5 when it is switched over to V5SW input.
VREG3
VREG5
22
O
O
5-V, 100-mA low dropout linear regulator output. Bypass to (power) GND using a 10-µF ceramic capacitor.
Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN. Switches over to V5SW
when 4.8 V or above is provided.
29
Note: When switch-over (see above V5SW) is enabled, VREG5 output voltage is approximately equal to
V5SW input voltage.
8
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TYPICAL CHARACTERISTICS
INPUT VOLTAGE SHUTDOWN CURRENT
INPUT VOLTAGE SHUTDOWN CURRENT
vs
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
15
12
15
12
V = 12 V
I
T
= 25°C
A
9
6
9
6
3
0
3
0
-50
0
50
100
150
5
10
15
20
25
30
V – Input Voltage – V
I
T
– Junction Temperature – °C
J
Figure 1.
Figure 2.
INPUT VOLTAGE STANDBY CURRENT
INPUT VOLTAGE STANDBY CURRENT
vs
vs
JUNCTION TEMPERATURE
INPUT VOLTAGE
150
120
150
120
T
= 25°C
V = 12 V
I
A
90
60
90
60
30
0
30
0
-50
0
50
100
150
5
10
15
20
25
30
T
– Junction Temperature – °C
V – Input Voltage – V
I
J
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
NO LOAD BATTERY CURRENT
NO LOAD BATTERY CURRENT
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
EN = on
EN1 = off
EN2 = on
EN = on
EN1 = on
EN2 = on
5
10
15
20
25
5
10
15
20
25
V – Input Voltage – V
I
V – Input Voltage – V
I
Figure 5.
Figure 6.
BATTERY CURRENT
vs
INPUT VOLTAGE
VREF2 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.02
2.01
2.00
1.99
1.98
EN = on
EN1 = on
EN2 = off
V = 12 V
I
5
10
15
20
25
–100
–50
0
50
100
V – Input Voltage – V
I
I
– VREF2 Output Current – mA
VREF2
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
VREG3 OUTPUT VOLTAGE
vs
VREG5 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
3.40
3.35
3.3
5.10
5.05
5.00
4.95
4.90
V = 12 V
V = 12 V
I
I
3.25
3.20
0
20
40
60
80
100
0
I
2
4
6
8
10
I
– 5-V Linear Regulator Output Current – mA
– 3.3-V Linear Regulator Output Current – mA
REG5
REG3
Figure 9.
Figure 10.
SWITCHING FREQUENCY
vs
JUNCTION TEMPERATURE
FORWARD VOLTAGE OF BOOST SW
vs
JUNCTION TEMPERATURE
330
320
0.25
0.20
R
= 330 kW
RF
310
300
0.15
0.10
290
280
270
0.05
0
-50
0
50
100
150
-50
0
50
100
150
T
– Junction Temperature – °C
T
– Junction Temperature – °C
J
J
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
OVP/UVP THRESHOLD VOLTAGE
vs
VBST LEAKAGE CURRENT
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
150
130
1.5
1.2
OVP
UVP
110
90
0.9
0.6
70
50
0.3
0
-50
0
50
100
150
-50
0
50
100
150
T
– Junction Temperature – °C
T
– Junction Temperature – °C
J
J
Figure 13.
Figure 14.
CURRENT LIMIT THRESHOLD
vs
JUNCTION TEMPERATURE
5-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
66
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
Auto-Skip Mode
= 330 kHz
V
(V)
CSN
f
SW
1
5
64
62
12
60
58
I
(A)
O
0
4
8
56
54
-50
0
50
100
150
4.5
5.0
5.5
6.0
6.5
7.0
T
– Junction Temperature – °C
V – Input Voltage – V
I
J
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
3.3-V OUTPUT VOLTAGE
vs
5-V EFFICIENCY
vs
OUTPUT CURRENT
INPUT VOLTAGE
3.40
3.35
3.30
3.25
3.20
100
80
Auto-Skip
Auto-Skip Mode
= 330 kHz
f
SW
60
40
CCM
OOA
I
(A)
O
Current Mode
20
0
0
4
8
V = 12 V
I
R
= 18 kW
GV
0.001
0.01
0.1
1
10
4.5
5.0
5.5
6.0
6.5
7.0
V – Input Voltage – V
I
I
– 5-V Output Current – A
O1
Figure 17.
Figure 18.
5-V EFFICIENCY
vs
OUTPUT CURRENT
3.3-V EFFICIENCY
vs
OUTPUT CURRENT
100
90
100
80
V = 8 V
I
Auto-Skip
V = 12 V
I
V = 20 V
I
60
40
20
CCM
80
70
OOA
V = 12 V
I
Current Mode
Auto-Skip
Current Mode
60
50
R
= 12 kW
GV
5.0-V SMPS: ON
R
= 18 kW
GV
0
0.001
0.001
0.01
0.1
1
10
0.01
0.1
1
10
I
– 3.3-V Output Current – A
I
– 5-V Output Current – A
O2
O1
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
3.3-V EFFICIENCY
vs
OUTPUT CURRENT
5-V SWITCHING FREQUENCY
vs
OUTPUT CURRENT
400
350
300
250
200
150
100
50
100
90
CCM
V = 8 V
I
V = 12 V
V = 20 V
I
I
80
70
60
V = 12 V
OOA
I
Current Mode
50
40
R
= 12 kW
GV
5.0-V SMPS: ON
Auto-Skip
0
0.001
0.001
0.01
0.1
1
10
0.01
0.1
1
10
I
– 3.3-V Output Current – A
I
– 5-V Output Current – A
O2
O1
Figure 21.
Figure 22.
3.3-V SWITCHING FREQUENCY
5-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
vs
OUTPUT CURRENT
400
350
300
250
200
150
100
50
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
CCM
Auto-Skip
OOA
CCM
OOA
V = 12 V
I
Current Mode
R
= 18 kW
GV
Auto-Skip
0
0.001
0.01
0.1
1
10
0
1
2
3
4
5
6
7
8
I
– 3.3-V Output Current – A
I
– 5-V Output Current – A
O2
O1
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
3.3-V OUTPUT VOLTAGE
vs
5-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
Auto-Skip
and
OOA
Auto-Skip
and
OOA
CCM
CCM
V = 12 V
I
Current Mode
(Non-droop)
V = 12 V
I
Current Mode
R
= 1 kW
GV
C = 1.8 nF
R
= 12 kW
GV
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
I
– 3.3-V Output Current – A
I
– 5-V Output Current – A
O1
O2
Figure 25.
Figure 26.
3.3-V OUTPUT VOLTAGE
vs
5.0-V BODE-PLOT – GAIN AND PHASE
vs
OUTPUT CURRENT
FREQUENCY
80
60
180
135
90
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
Phase
Auto-Skip
and
OOA
40
20
45
Gain
0
0
–20
–40
–60
–80
45
CCM
–90
–135
–180
V = 12 V
I
Current Mode
V
= 5.0 V
O
V = 12 V
I
(Non-droop)
I
= 8 A
O
R
= 9.1 kW
GV
C = 1.8 nF
100
1 k
10 k
100 k
1 M
f – Frequency – Hz
0
1
2
3
4
5
6
7
8
I
– 3.3-V Output Current – A
O2
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
3.3-V BODE-PLOT – GAIN AND PHASE
vs
FREQUENCY
5.0-V SWITCH-OVER WAVEFORMS
80
60
180
135
90
Phase
40
VREG5 (100 mV/div)
20
45
Gain
0
0
VO1 (100 mV/div)
–20
–40
–60
–80
45
–90
–135
–180
V
= 3.3 V
O
V = 12 V
I
2 ms/div
I
= 8 A
O
100
1 k
10 k
100 k
1 M
f – Frequency – Hz
Figure 29.
Figure 30.
CURRENT MONITOR VOLTAGE
vs
OUTPUT CURRENT
3.0
2.5
2.0
V
IMON1
1.5
1.0
V
IMON2
0.5
0
0
2
4
6
8
10
12
I
– Output Current – A
OUTx
Figure 31.
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TYPICAL CHARACTERISTICS
5.0-V START-UP WAVEFORMS
3.3-V START-UP WAVEFORMS
EN2 (5V/div)
EN1 (5V/div)
Vout1 (2V/div)
Vout2 (2V/div)
PGOOD2 (5V/div)
1msec/div
PGOOD1 (5V/div)
1msec/div
Figure 32.
5.0-V SOFT-STOP WAVEFORMS
Figure 33.
3.3-V SOFT-STOP WAVEFORMS
EN2 (5V/div)
EN1 (5V/div)
Vout1 (2V/div)
Vout2 (2V/div)
PGOOD2 (5V/div)
PGOOD1 (5V/div)
1msec/div
1msec/div
Figure 34.
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
5.0-V LOAD TRANSIENT RESPONSE
3.3-V LOAD TRANSIENT RESPONSE
VI =12V, Auto-skip
VI=12V, Auto-skip
VO1 (100mV/div)
VO2 (100mV/div)
SW1 (10V/div)
SW2 (10V/div)
IO1 (5A/div)
100 ms/div
IO2 (5A/div)
100 ms/div
Figure 36.
Figure 37.
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DETAILED DESCRIPTION
ENABLE AND SOFT START
When EN is Low, the TPS51222 is in the shutdown state. Only the 3.3-V LDO stays alive, and consumes 7 µA
(typically). When EN becomes High, the TPS51222 is in the standby state. The 2-V reference and the 5-V LDO
become enabled, and consume about 80 µA with no load condition, and are ready to turn on SMPS channels.
Each SMPS channel is turned on when ENx becomes High. After ENx is set to high, the TPS51222 begins the
softstart sequence, and ramps up the output voltage from zero to the target voltage in 0.96 ms. However, if a
slower soft-start is required, an external capacitor can be tied from the ENx pin to GND. In this case, the
TPS51222 charges the external capacitor with the integrated 2-µA current source. An approximate external
soft-start time would be tEX-SS = CEX / IEN12, which means the time from ENx = 1 V to ENx = 2 V. The recommend
capacitance is more than 2.2 nF.
1) Internal
Soft-start
EN1
Vout1
200ms
960ms
EN1<2V
EN1>1V
2) External
Soft-start
EN1
External
Soft-start
time
Vout1
Figure 38. Enable and Soft-start Timing
Table 1. Enable Logic States
EN
GND
Hi
EN1
EN2
VREG3
ON
VREF2
Off
VREG5
Off
CH1
Off
CH2
Off
Don’t Care
Don’t Care
Lo
Hi
Lo
Hi
Lo
Lo
Hi
Hi
ON
ON
ON
Off
Off
Hi
ON
ON
ON
ON
Off
Off
Hi
ON
ON
ON
ON
ON
Hi
ON
ON
ON
ON
3.3-V, 10-mA LDO (VREG3)
A 3.3-V, 10-mA, linear regulator is integrated in the TPS51222. This LDO services some of the analog circuit in
the device and provides a handy standby supply for 3.3-V Always On voltage in the notebook system. Apply a
2.2-µF (at least 1-µF), high quality X5R or X7R ceramic capacitor from VREG3 to (signal) GND in adjacent to the
device.
2-V, 100-µA Sink/Source Reference (VREF2)
This voltage is used for the reference of the loop compensation network. Apply a 0.22-µF (at least 0.1-µF),
high-quality X5R or X7R ceramic capacitor from VREF2 to (signal) GND in adjacent to the device.
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5.0-V, 100-mA LDO (VREG5)
A 5.0-V, 100-mA, linear regulator is integrated in the TPS51222. This LDO services the main analog supply rail
and provides the current for gate drivers until switch-over function becomes enable. Apply a 10-µF (at least
4.7-µF), high-quality X5R or X7R ceramic capacitor from VREG5 to (power) GND in adjacent to the device.
VREG5 SWITCHOVER
When EN1 is high, PGOOD1 indicates GOOD and a voltage of more than 4.8 V is applied to V5SW, the internal
5V-LDO is shut off and the VREG5 is shorted to V5SW by an internal MOSFET after an 7.7-ms delay. When the
V5SW voltage becomes lower than 4.65 V, EN1 becomes low, or PGOOD1 indicates BAD, the internal switch is
turned off, and the internal 5V-LDO resumes immediately.
BASIC PWM OPERATIONS
The main control loop of the SMPS is designed as a fixed frequency, peak current mode, pulse width modulation
(PWM) controller. It achieves stable operation with any type of output capacitors, including low ESR capacitor(s)
such as ceramic or specialty polymer capacitors.
The current mode scheme uses the output voltage information and the inductor current information to regulate
the output voltage. The output voltage information is sensed by VFBx pin. The signal is compared with the
internal 1-V reference and the voltage difference is amplified by a transconductance amplifier (VFB-AMP). The
inductor current information is sensed by CSPx and CSNx pins. The voltage difference is amplified by another
transconductance amplifier (CS-AMP). The output of the VFB-AMP indicates the target peak inductor current. If
the output voltage decreases, the TPS51222 increases the target inductor current to raise the output voltage.
Alternatively, if the output voltage rises, the TPS51222 decreases the target inductor current to reduce the output
voltage.
At the beginning of each clock cycle, the high-side MOSFET is turned on, or becomes ‘ON’ state. The high-side
MOSFET is turned off, or becomes OFF state, after the inductor current becomes the target value which is
determined by the combination value of the output of the VFB-AMP and a ramp compensation signal. The ramp
compensation signal is used to prevent sub-harmonic oscillation of the inductor current control loop. The
high-side MOSFET is turned on again at the next clock cycle. By repeating the operation in this manner, the
controller regulates the output voltage. The synchronous low-side or the rectifying MOSFET is turned on each
OFF state to keep the conduction loss minimum.
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PWM FREQUENCY CONTROL
The TPS51222 has a fixed frequency control scheme with 180° phase shift. The switching frequency can be
determined by an external resistor which is connected between RF pin and GND, and can be calculated using
Equation 1.
5
1 × 10
f
kHz =
ù
û
é
sw
ë
RF kΩ
é
ù
û
ë
(1)
TPS51222 can also synchronize to more than 2.5 V amplitude external clock by applying the signal to the RF
pin. The set timing of channel 1 initiates at the raising edge (1.3 V typ) of the clock and channel 2 initiates at the
falling edge (1.1 V typ). Therefore, the 50% duty signal makes both channels 180° phase shift.
1000
900
800
700
600
500
400
300
200
100
0
100
200
300
400
500
RF - Resistance - kW
Figure 39. Switching Frequency vs RF
LIGHT LOAD OPERATION
The TPS51222 automatically reduces switching frequency at light load conditions to maintain high efficiency if
Auto Skip or Out-of-Audio™ mode is selected by SKIPSELx. This reduction of frequency is achieved by skipping
pulses. As the output current decreases from heavy load condition, the inductor current is also reduced and
eventually comes to the point that its peak reaches a predetermined current, ILL(PEAK), which indicates the
boundary between heavy-load condditions and light-load conditions. Once the top MOSFET is turned on, the
TPS51222 does not allow it to be turned off until it reaches ILL(PEAK). This eventually causes an overvoltage
condition to the output and pulse skipping. From the next pulse after zero-crossing is detected, ILL(PEAK) is limited
by the ramp-down signal ILL(PEAK)RAMP, which starts from 25% of the overcurrent limit setting (IOCL(PEAK): (see the
Current Protection section) toward 5% of IOCL(PEAK) over one switching cycle to prevent causing large ripple. The
transition load point to the light load operation ILL(DC) can be calculated in Equation 2.
I
LL(DC) + ILL(PEAK) * 0.5 IIND(RIPPLE)
(2)
(V - V
) × V
OUT
1
IN
OUT
I
=
×
IND(RIPPLE)
L × f
V
SW
IN
(3)
where
•
fSW is the PWM switching frequency which is determined by RF resistor setting or external clock
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I
= 0.2 - 0.13´ t ´ f
´ t ´I
)
SW
OCL PEAK
(
LL(PEAK)RAMP
ON
(
)
(4)
Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it
decreases almost proportionally to the output current from the ILL(DC), as described in Equation 2; while
maintaining the switching synchronization with the clock. Due to the synchronization, the switching waveform in
boundary load condition (close to ILL(DC)) appears as a sub-harmonic oscillation; however, it is the intended
operation.
If SKIPSELx is tied to GND, the TPS51222 works on a constant frequency of fSW regardless its load current.
Inductor
Current
ILL(PEAK)
ILL(DC)
IIND(RIPPLE)
0
Time
Figure 40. Boundary Between Pulse Skipping and CCM
20% of I
I
Ramp Signal
LL(PEAK)
OCL
I
at
LL(PEAK)
Light Load
7% of I
OCL
t
ON
1/f
SW
t – Time
Figure 41. Inductor Current Limit at Pulse Skipping
Table 2. Skip Mode Selection
SKIPSELx
GND
VREF2
VREG3
VREG5
OOA Skip (maximum 7
skips, for <400 kHz)
OOA Skip (maximum 15 skips, for
equal to or greater than 400kHz)
OPERATING MODE
Continuous Conduction
Auto Skip
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OUT OF AUDIO SKIP OPERATION
Out-Of-Audio™ (OOA) light-load mode is a unique control feature that keeps the switching frequency above
acoustic audible frequencies toward virtually no load condition while maintaining state-of-the-art high conversion
efficiency. When OOA is selected, the switching frequency is kept higher than audible frequency range in any
load condition. The TPS51222 automatically reduced switching frequency at light-load conditions. The OOA
control circuit monitors the states of both MOSFETs and forces an ON state if the predetermined number of
pulses are skipped. The high-side MOSFET is turned on before the output voltage declines down to the target
value, so that eventually an overvoltage condition is caused. The OOA control circuit detects this overvoltage
condition and begins modulating the skip-mode on time to keep the output voltage.
The TPS51222 supports a wide-switching frequency range, therefore, the OOA skip mode has two selections.
See Table 2. When the 300-kHz switching frequency is selected, a maximum of seven (7) skips (SKIPSEL=3.3
V) makes the lowest frequency at 37.5 kHz. If a 15-skip maximum is chosen, it becomes 18.8 kHz, hence the
maximum 7 skip is suitable for less than 400 kHz, and the maximum 15 skip is 400 kHz or greater.
99% DUTY CYCLE OPERATION
In a low-dropout condition such as 5-V input to 5-V output, the basic control loop attempts to maintain 100% of
the high-side MOSFET ON. However, with the N-channel MOSFET used for the top switch, it is not possible to
use the 100% on-cycle to charge the boot strap capacitor. TPS51222 detects the 100% ON condition and
asserts the OFF state at the appropriate time.
HIGH-SIDE DRIVER
The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which is 1.7Ω for VBSTx to DRVHx, and 1Ω for DRVHx to SWx. When
configured as a floating driver, 5 V of bias voltage is delivered from VREG5 supply. The instantaneous drive
current is supplied by the flying capacitor between VBSTx and SWx pins. The average drive current is equal to
the gate charge at Vgs = 5V times switching frequency. This gate drive current as well as the low-side gate drive
current times 5 V makes the driving power which needs to be dissipated mainly from TPS51222 package. A
dead time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET
on, and low-side MOSFET off to high-side MOSFET on.
LOW-SIDE DRIVER
The low-side driver is designed to drive high-current low-RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which are 1.3Ω for VREG5 to DRVLx and 0.7Ω for DRVLx to GND. The
5-V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by an input
capacitor connected between VREG5 and GND. The average drive current is also calculated by the gate charge
at Vgs = 5 V times switching frequency.
CURRENT SENSING SCHEME
In order to provide both good accuracy and cost effective solution, the TPS51222 supports external resistor
sensing and inductor DCR sensing. An RC network with high quality X5R or X7R ceramic capacitor should be
used to extract voltage drop across DCR. 0.1µF is a good value to start the design. CSPx and CSNx should be
connected to positive and negative terminal of the sensing device respectively. The output signal of the internal
current amplifier becomes 100 mV at the OCL setting point. This means that the current sensing amplifier
normalize the current information signal based on the OCL setting. Attaching a RC network recommended even
with a resistor sensing scheme to get an accurate current sensing; see the External Components Selection
session for detailed configurations.
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ADAPTIVE ZERO CROSSING
TPS51222 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the ZC comparator and delay time of the ZC detection circuit. It prevents
SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too early
detection. As a result, better light load efficiency is delivered.
CURRENT PROTECTION
TPS51222 has cycle-by-cycle overcurrent limiting control. If the inductor current becomes larger than the
overcurrent trip level, TPS51222 turns off high-side MOSFET, turns on low-side MOSFET and waits for the next
clock cycle.
IOCL(PEAK) sets peak level of the inductor current. Thus, the dc load current at overcurrent threshold, IOCL(DC), can
be calculated as follows;
I
OCL(DC) + IOCL(PEAK) * 0.5 IIND(RIPPLE)
(5)
V
OCL
I
+
OCL(PEAK)
R
SENSE
(6)
where
•
•
RSENSE is resistance of current sensing device
V(OCL) is the overcurrent trip threshold voltage
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down, and it ultimately crosses the undervoltage protection threshold and shutdown.
POWERGOOD
The TPS51222 has powergood output for both switcher channels. The powergood function is activated after
softstart has finished. If the output voltage becomes within ±5% of the target value, internal comparators detect
power good state and the powergood signal becomes high after 1ms internal delay. If the output voltage goes
outside of ±10% of the target value, the powergood signal becomes low after 1.5µs internal delay. Apply voltage
should be less than 6V and the recommended pull-up resistance value is from 100kΩ to 1MΩ.
OUTPUT DISCHARGE CONTROL
The TPS51222 discharges output when ENx is low. The TPS51222 discharges outputs using an internal
MOSFET which is connected to CSNx and GND. The current capability of these MOSFETs is limited to
discharge the output capacitor slowly. If ENx becomes high during discharge, MOSFETs are turning off, and
some output voltage remains. SMPS changes over to soft-start. The PWM initiates after the target voltage
overtakes the remaining output voltage.
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OVERVOLTAGE/UNDERVOLTAGE PROTECTION
TPS51222 monitors the output voltage to detect overvoltage and undervoltage. When the output voltage
becomes 15% higher than the target value, the OVP comparator output goes high and the circuit latches as the
high-side MOSFET driver OFF and the low-side MOSFET driver ON, and shuts off another channel.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After 1 ms, TPS51222 latches OFF both high-side and
low-side MOSFETs, and shuts off another channel. This UVP function is enabled after soft-start has completed.
The procedure for restarting from these protection states is:
1. toggle EN
2. toggle EN1 and EN2 or
3. once hit UVLO
UVLO PROTECTION
The TPS51222 has undervoltage lockout protections (UVLO) for VREG5, VREG3 and VREF2. When the voltage
is lower than UVLO threshold voltage, TPS51222 shuts off each output as shown inTable 3. This is non-latch
protection.
Table 3. UVLO Protection
CH1/ CH2
VREG5
—
VREG3
On
VREF2
On
VREG5 UVLO
VREG3 UVLO
VREF2 UVLO
Off
Off
Off
Off
—
Off
Off
On
—
THERMAL SHUTDOWN
The TPS51222 monitors the device temperature. If the temperature exceeds the threshold value, TPS51222
shuts off both SMPS and 5V-LDO, and decreases the VREG3 current limitation to 5 mA (typically). This is
non-latch protection.
CURRENT MONITOR
TPS51222 monitors the output current as the voltage difference between CSPx and CSNx terminal. The
transconductance amplifier (CS-AMP) amplifies this differential voltage by 50 times and sends out from IMONx
thermal. Adding RC filter is recommended.
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APPLICATION INFORMATION
EXTERNAL COMPONENTS SELECTION
A buck converter using the TPS51222 consists of linear circuits and a switching modulator. Figure 42 shows the
basic scheme.
Voltage divider
VIN
Switching Modulator
Ramp
comp.
R1
DRVH
Lx
VFB
+
Gmv
Rs
PWM
+
Control
logic
&
+
R2
+
DRVL
Driver
1.0V
ESR
Co
RL
COMP
VREF
Gmc
CSP
Rgv
Cc
Rgc
+
+
CSN
2.0V
Error Amplifier
Figure 42. Simplified Current Mode Functional Blocks
The external components can be selected by following manner.
1. Determine output voltage dividing resistors (R1 and R2: shown in Figure 42) using the next equation
R1 + ǒV
Ǔ
* 1.0 R2
OUT
(7)
2. Determine switching frequency. Higher frequency allows smaller output capacitances, however, degrade
efficiency due to increase of switching loss. Frequency setting resistor for RF-pin can be calculated by;
1 105
ƒsw [kHz]
RF[kW] +
(8)
3. Choose the inductor. The inductance value should be determined to give the ripple current of
approximately 25% to 50% of maximum output current. Recommended ripple current rate is about 30% to
40% at the typical input voltage condition, next equation uses 33%.
(V
- VOUT ) × VOUT
1
IN(TYP)
L =
×
0.33 x IOUT(MAX) x fSW
V
IN(TYP)
(9)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation.
4. Determine the sensing resistor.
Determine the sensing resistor using next equation. IOCL(PEAK) should be approximately 1.5 × IOUT(MAX) to
1.7 × IOUT(MAX)
.
VOCL
IOCL(PEAK)
RSENSE
+
(10)
5. Determine Rgv. Rgv should be determined from preferable droop compensation value and is given by next
equation based on the typical number of Gmv = 500µS.
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I
OUT(MAX)
1
Rgv + 0.1
V
OUT
I
Gmv Vdroop
OCL(PEAK)
(11)
(12)
IOUT(MAX)
VOUT[V]
Rgv[kW] + 200
IOCL(PEAK) Vdroop[mV]
If no-droop is preferred, attach a series RC network circuit instead of single resistor. Series resistance is
determined using Equation 12 . Series capacitance can be arbitrarily chosen to meet the RC time constant,
but should be kept under 1/10 of fo.
6. Determine output capacitance Co to achieve a stable operation using the next equation. The 0 dB frequency,
fo, should be kept under 1/3 of the switching frequency.
Gmv Rgv ƒsw
5
1
ƒ0 + IOCL(PEAK)
t
p
3
VOUT
Co
(13)
(14)
Gmv Rgv
ƒsw
15
p
1
Co u
IOCL(PEAK)
VOUT
7. Calculate Cc. The purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. If
ceramic capacitor(s) is used, there is no need for Cc. If a combination of different capacitors is used, attach a
RC network circuit instead of single capacitance to cancel zeros and poles caused by the output capacitors.
With single capacitance, Cc is given in Equation 15.
ESR
Rgv
Cc + Co
(15)
8. Choose MOSFETs Generally, the on resistance affects efficiency at high load conditions as conduction loss.
For a low output voltage application, the duty ratio is not high enough so that the on resistance of high-side
MOSFET does not affect efficiency; however, switching speed (tr and tf) affects efficiency as switching loss.
As for low-side MOSFET, the switching loss is usually not a main portion of the total loss.
RESISTOR CURRENT SENSING
For more accurate current sensing with an external resistor, the following technique is recommended. Adding an
RC filter to cancel the parasitic inductance of resistor, this filter value is calculated using Equation 16.
Lx
Rs
Cx Rx +
(16)
This equation means time-constant of Cx and Rx should match the one of Lx (ESL) and Rs.
VIN
Ex-resistor
Lx(ESL)
Rs
DRVH
L
Control
logic
&
DRVL
Driver
Co
CSP
CSN
+
Cx
Rx
Figure 43. External Resistor Current Sensing
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INDUCTOR DCR CURRENT SENSING
To use inductor DCR as current sensing resistor (Rs), the configuration needs to change as below. However, the
equation that must be satisfied is the same as the one for the resistor sensing.
VIN
Inductor
DRVH
Lx
Rs(DCR)
Control
logic
&
DRVL
Driver
Co
Rx
CSP
+
Cx
CSN
Figure 44. Inductor DCR Current Sensing
VIN
Inductor
DRVH
Lx
Rs(DCR)
Control
logic
&
DRVL
Driver
Co
Rx
CSP
+
Cx
Rc
CSN
Figure 45. Inductor DCR Current Sensing With Voltage Divider
TPS51222 has a fixed V(OCL) point (60 mV). In order to adjust for DCR, a voltage divider can be configured a
described in Figure 45.
For Rx, Rc and Cx can be calculated as shown below, and overcurrent limitation value can be calculated as
follows:
Lx
Cx ´ Rx P Rc
(
=
)
Rs
(17)
(18)
Rx ) Rc
1
Rs
I
OCL(PEAK) + VOCL
Rc
Figure 46 shows the compensation technique for the temperature drifts of the inductor DCR value. This scheme
assumes the temperature rise at the thermistor (RNTC) is directly proportional to the temperature rise at the
inductor.
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Inductor
Lx
Rs(DCR)
RNTC
Rx
Rc1
Rc2
CO
CSP
+
Cx
CSN
Figure 46. Inductor DCR Current Sensing With Temperature Compensate
LAYOUT CONSIDERATIONS
Certain points must be considered before starting a PCB layout work using the TPS51222.
Placement
•
•
•
•
•
Place RC network for CSP1 and CSP2 close to the device pins.
Place bypass capacitors for VREG5, VREG3 and VREF2 close to the device pins.
Place frequency-setting resistor close to the device pin.
Place the compensation circuits for COMP1 and COMP2 close to the device pins.
Place the voltage setting resistors close to the device pins.
Routing (sensitive analog portion)
• Use separate traces for; see Figure 47
–
–
–
Output voltage sensing from current sensing (negative-side)
Output voltage sensing from V5SW input (when VOUT = 5V)
Current sensing (positive-side) from switch-node
V5SW
R1
VFB
R2
H-FET
Inductor
Vout
SW
Cout
L-FET
R
CSP
CSN
C
Figure 47. Sensing Trace Routings
•
Use Kelvin sensing traces from the solder pads of the current sensing device (inductor or resistor) to current
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sensing comparator inputs (CSPx and CSNx). (See Figure 48)
Current sensing
Device
RC network
next to IC
Figure 48. Current Sensing Traces
•
•
•
Use small copper space for VFBx. These are short and narrow traces to avoid noise coupling
Connect VFB resistor trace to the positive node of the output capacitor.
Use signal GND for VREF2 and VREG3 capacitors, RF and VFB resistors, and the other sensitive analog
components. Placing a signal GND plane (underneath the IC, and fully covered peripheral components) on
the internal layer for shielding purpose is recommended. (See Figure 49)
•
Use a thermal land for PowerPAD™. Five or more vias, with 0.33-mm (13-mils) diameter connected from the
thermal land to the internal GND plane, should be used to help dissipation. Do NOT connect the GND-pin to
this thermal land on the surface layer, underneath the package.
Routing (power portion)
•
•
•
•
Use wider/shorter traces of DRVL for low-side gate drivers to reduce stray inductance.
Use the parallel traces of SW and DRVH for high-side MOSFET gate drive, and keep them away from DRVL.
Connect SW trace to source terminal of the high-side MOSFET.
Use power GND for VREG5, VIN and VOUT capacitors and low-side MOSFETs. Power GND and signal GND
should be connected near the device GND terminal. (See Figure 49)
0W resistor
GND
#28
GND-pin
To inner
Power-GND
layer
To inner
Signal-GND
plane
Inner Signal-GND plane
Figure 49. GND Layout Example
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APPLICATION CIRCUITS
2 W S
2 B F V
2 T S B V
2 L V R D
D N G
2 P M O C
2 N O M I
2 F E R V
N E
5 G E R V
1 L V R D
1 T S B V
1 W S
1 N O M I
1 P M O C
1 B F V
Figure 50. Current Mode, DCR Sensing, 5.0-V/8-A, 3.3-V/8-A, 330-kHz
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Table 4. Current Mode, DCR Sensing, 5.0-V/8-A, 3.3-V/8-A, 330-kHz
SYMBOL
C11
SPECIFICATION
MANUFACTURER
Sanyo
PART NUMBER
6TPE330MIL
2 × 330 µF, 6.3 V, 18 mΩ
2 × 10 µF, 25 V
C12
Murata
GRM32DR71E106K
4TPE470MFL
C21
470 µF, 4.0V, 15 mΩ
2 × 10 µF, 25 V
Sanyo
C22
Murata
GRM32DR71E106K
FDV1040-3R3M
FDV1040-3R3M
FDMS8692
L1
3.3 µH, 10.7 A, 10.5 mΩ
3.3 µH, 10.7 A, 10.5 mΩ
30-V, 12 A, 10.5 mΩ
30 V, 18 A, 5.4 mΩ
TOKO
L2
TOKO
Q11, Q21
Q12, Q22
Fairchild
Fairchild
FDMS8672AS
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2 W S
2 B F V
2 T S B V
2 L V R D
D N G
2 P M O C
2 N O M I
2 F E R V
N E
5 G E R V
1 L V R D
1 T S B V
1 W S
1 N O M I
1 P M O C
1 B F V
Figure 51. Current Mode (Non-Droop), DCR Sensing, 5.0-V/8-A, 3.3-V/8-A, 330-kHz
Table 5. Current Mode (Non-droop), DCR Sensing, 5.0-V/8-A, 3.3-V/8-A, 330-kHz
SYMBOL
SPECIFICATION
MANUFACTURER
PART NUMBER
C11
2 x 330 µF, 6.3 V 18 mΩ
Sanyo
6TPE330MIL
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Table 5. Current Mode (Non-droop), DCR Sensing, 5.0-V/8-A, 3.3-V/8-A, 330-kHz (continued)
SYMBOL
C12
SPECIFICATION
MANUFACTURER
Murata
PART NUMBER
GRM32DR71E106K
4TPE470MFL
2 x 10 µF, 25 V
C21
470 µF, 4.0V, 15 mΩ
2 x 10 µF, 25 V
Sanyo
C22
Murata
GRM32DR71E106K
FDV1040-3R3M
FDV1040-3R3M
FDMS8692
L1
3.3 µH, 10.7 A, 10.5 mΩ
3.3 µH, 10.7 A, 10.5 mΩ
30-V, 12-A, 10.5 mΩ
30-V, 18-A, 5.4 mΩ
TOKO
L2
TOKO
Q11, Q21
Q12, Q22
Fairchild
Fairchild
FDMS8672AS
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2 W S
2 B F V
2 T S B V
2 L V R D
D N G
2 P M O C
2 N O M I
2 F E R V
N E
5 G E R V
1 L V R D
1 T S B V
1 W S
1 N O M I
1 P M O C
1 B F V
Figure 52. Current Mode, DCR Sensing, 5.0-V/5-A, 3.3-V/5-A, 300-kHz
Table 6. Current Mode, DCR Sensing, 5.0-V/5-A, 3.3-V/5-A, 300-kHz
SYMBOL
SPECIFICATION
MANUFACTURER
PART NUMBER
C11
2 × 120 µF, 6.3V, 15 mΩ
Panasonic
EEFCX0J121R
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Table 6. Current Mode, DCR Sensing, 5.0-V/5-A, 3.3-V/5-A, 300-kHz (continued)
SYMBOL
C12
SPECIFICATION
MANUFACTURER
Murata
PART NUMBER
GRM32DR71E106K
EEFCX0G221R
GRM32DR71E106K
CEP125-4R0MC-H
CEP125-4R0MC-H
IRF7821
2 × 10 µF, 25 V
C21
2 × 220 µF, 4.0 V, 15 mΩ
2 × 10 µF, 25 V
Panasonic
Murata
C22
L1
4.0 µH, 10.3 A, 6.6 mΩ
4.0 µH, 10.3 A, 6.6 mΩ
30 V, 13.6 A, 9.5 mΩ
30 V, 13.8 A, 5.8 mΩ
Sumida
Sumida
IR
L2
Q11, Q21
Q12, Q22
IR
IRF8113
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PACKAGE MATERIALS INFORMATION
www.ti.com
28-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51222RTVR
TPS51222RTVR
TPS51222RTVT
TPS51222RTVT
WQFN
WQFN
WQFN
WQFN
RTV
RTV
RTV
RTV
32
32
32
32
3000
3000
250
330.0
330.0
180.0
180.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
1.5
1.5
1.5
1.5
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS51222RTVR
TPS51222RTVR
TPS51222RTVT
TPS51222RTVT
WQFN
WQFN
WQFN
WQFN
RTV
RTV
RTV
RTV
32
32
32
32
3000
3000
250
367.0
367.0
210.0
210.0
367.0
367.0
185.0
185.0
35.0
35.0
35.0
35.0
250
Pack Materials-Page 2
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